CA2011935A1 - Dual-path computer interconnect system with four-ported packet memory control - Google Patents

Abstract

DUAL-PATH COMPUTER INTERCONNECT SYSTEM
WITH FOUR-PORTED PACKET MEMORY CONTROL

ABSTRACT OF THE DISCLOSURE
A computer interconnect system uses packet data transmission over serial links connecting nodes of a network. The serial links provide simultaneous dual paths for transmit/receive. An adapter couples a CPU or the like at a node to the serial link. The adapter includes a packet memory for temporarily storing transmit packets and receive packets, along with a port processor for executing the protocol.
Packets of data are transferred between the system bus of the CPU and the packetmemory by a pair of data movers, one for read and one for write. The packet memory is accessed upon demand by the serial link, the port processor and the data movers, using interleaved cycles. To accommodate this access upon demand withoutrequest/grant cycles, parking registers are provided to store read or write data until a later cycle, and the data rate on the packet memory port is high enough to allow ample time for simultaneous use of both channels as well as packet processing and moving to and from the CPU.

Description

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DUAL-PATH COMPUTER INTERCONNECI SYSTEM
WITH FOUR-PORTED PACKET MEMORY CONTROL

BACKGROUND OF THE INVENTION

This invention relates to computer interconnect systems, and more particularly to a packet communication system employing dual serial data paths between computer nodes.

In U.S. Patents 4,777,595, 4,560,985, 4,49Q785, and in copending applications Ser. No. 109,503, 110,009 and 110,51~, filed October 16, 1987, all assigned to Digital Equipment Corporation, assignee oE this invention, computer interconnect systemsare shown of the type employing packet data transEer using serial paths. These types of computer interconnect systems have heen commercially used Eor processors and bulk memory facilities o~ the VAX architecture, and provide versatile systems o~ high performance and reliability. However, with increasing demands for additional functions, compatibility with a wide variety of computer equipment, higher speed, ~15 lower cost, iarger networks and higher reliability ~both o~ data and hardware), Eurther development oE thîs type oE interconnect system is imperative.

The likelihood of completing a packet transFer initiated by a given node in a network of this type is dependent upon whether a serial data channel is Eree, i.e., nat being used for another transEer, and whether the destination node itself is free and ready to receive the packet. This lilcelihood can be increased by having more than one serial data channel interconnecting the nodes. Also, having more than one serial data channel makes possible the simultaneous reception and/or transmission 2 ~ 3 ~

on more th~n one channel at the same time. While some prior packet communica-tions systems of the type mentioned above have included two transmission channels Eor each node, these have been ~or the purpose oE redundancy rather than simultaneous use, and so the net maximum data rates are not improved1 even though the reliability is enhanced.

Simultaneous data transmission and/or reception has been provided over serial data linlcs by merely repiica~ing all of the port har~war~ associated with a serial port or communications adapter. This is no~ only more expensive, occupies more space and consumes more power, but also the ports must be separately addres~ed by the host computer. That is, i~ is preferable that the multiple simultaneous paths be transparent to the host cornpute~.
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When a packet data stream is being transmitted or received by a node in a system oE this type, the data handling circuit~ used by the node to deliver the data stream ~o the transmitter, or accept the incoming data stream from the receiver,must be able to execute the transfer without any possibility of a stall or delay due to a bus request not being granted, or the like. Any stall during reception or ;j~ transmission means the packet must be discarded and resent. Since it is not known when packe~s are going to be received at a nade, a received packet must be quickly ? ~ mo~/ed from ~he rçceiver to the host computer since another packet may be , 20 Eollowing immediately.
., , It is a principal object of this invention to provide an improved computer interconnect system, particularly one which allows increased per~ormance by simultaneous use of dual paths between nodes. Another object is to provide an improved high~speed computer interconnect systenn in which a greater probability of ,, "

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gaining use of a transmission path from one node to another is achieved, yet thecomponent parts o~ the system are not needlessly duplicated. A further object is eO
provide a dual-path packet data communication system allowing simultaneous transmission and/or reception by these paths, in which use oE one or the other oE the S dual paths is nevertheless transparent to the host computer. An additional object is to provide a packet data transmission and reception system suitable for handling high-performance dual simultaneous operation v~a two or more serial channels.
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~ SIJMMARY OF THE IN~ENTlC)N
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In accordance with one embodiment of the inven~ion, a computer isltercorl-` ~ 10 nect system employs packet data transfer by dual paths which may be simultaneously active. The nodes or computers are connected by these serial data paths in a star-type network thraugh a central hub. The central hub may be capable of detecting addresses in the packets and establishing a pa~h from a source node to a destination node. A packet ~uffer is used for temporarily storing packets to be transmitted or packets being received. By usin~ a wide-word (e.g., 32-bit) access port to the packet bu~fer, with converters Eor changing to or Erom bit-serial in accessing this port, the ;~ data rate of the high-speed serial paths can be accommodated with interleaved ' access cycles for this packet buffer Priority is given to access cycles for the data .!',~ to or Erom the serial paths in allocating access to the packet buEEer, so there need by no stalls in delivering data at the bit rate oE the serial links. The task of moving .; data to or Erom the CPU is given secondary priority in the schedule oE access to the ~: packet buEEer, but even so there is ample time to locally process packets and move them out of the packet buEfer to accommodate new incoming data packets. A local processor usually accesses the packet bufEer, in addition to the serial paths and the !: .
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data move functi~n, and the access cycles Eor this local processor are interleaved with the other necessary accesses, hut at a lower priority than the serial path access.
For example, the local processor may be used to checlc the header of a packet where addresses, command fields, and other definition information are located; this S information is checked while the packet is still in the packet buffer to determine whether or not to move the packet to the host processor. All of these types oE
access are scheduled without the necessity Eor the usual requestlgrant arbitration: the senal paths are given unconditional access when they request ilt, bu~ cannot access more oEten than every other cycle, while the local processor is given a fLxed-delay ~; 10 access which always allows an intervening cycle iE the serial path also needs access.
llle local processor also cannot make back-to-back accesses to the packet buffer.
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The task of moving data to or ~rom the host computer uses cysles not occupied by .'r, the other two Eunctions. The cycle time oE ~he packet buffer must therefore be . "
~s East enough accommodate all oE these competing functions. To allow the data '~:, 15 movers and the local processor to access the packet bu~fer in this manner without a request/grant arbitration of the classic type, the data being transEerred is conditionally buEfered or parked to allow intervening cycles before the trans~er is implemented.
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BRIEF DESCRIPTION OF THE DRAWINGS
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The n~vel Eea~ures believed characteristic oE the invention are set forth in theappended slaims. The invention itself, however, as well as other f~atures and ad-vantages thereof, will be best understood by reEerenc~ to a detailed description of a specific embodiment which follo~s, when read in conjunction with the accompany-ing drawings, wherein:
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Figure 1 is an electrical diagrarn in block Eorm o~ a dual-path computer interconnect system which may use the features of the invention;
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Figure 2 is a diagram oE a packet Eormat which may be used in the computer interconnect system of Figure l;

Pigure 3 is an electrical diagram in block form of one oE the adapters 11 used in the computer interconnect system of Figure l;

Figure 4 is an electrical diagram in block Eorm o~ the memory control ~: circuit~y 35 used in the device of Figure 3;
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., Figure 5 is a timing diagram o~ events vs. time Eor packet bu~fer access cycles in the system of Figure 1-4; ;~

Figure 6 is an electrical diagram of the logic circuitry oE the zone manager . in the system of Figures 1-4;

. Figure 7 is a logic Elow chart o~ the states executed by the zone manager o~
Figure 6 in the memory controller 35 oE Figure 4;

~i,r~ 15 Figure 8 is an electrical diagram in block form of an active hub used in the , system of Figure 1;
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Figure 9 is an electrical schernatic diagram oE a passive hub used in the system oE Figure 1~ in another embodiment;
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2 ~ 3 5 Figure 10 is an electrical diagram of an abort-transmit circuit used in the system of Figures 1-9 according to one embodiment of the invention; and Figure 11 is a timing diagram showing events vs. time for packet transmission operations in the systems of Figures 1-10.

S DETAILED DESCRIPTION OF SPECIFIC EMBODIMENT ~:

Referling to Figure 1, a packet-type computer Interconnect system employ~ng dual paths Eor simultaneous ~ransmit and/or receive, implementing featurcs of the invention, is illustrated according to one embodiment having a number of CPUs 10or similar processor-type devices which are capable oE generating and receivlng messages. The nodes or CPUs 1U could be disk controllers, high speed printer Eacilities, or other resources o~ this type, as well as high-performance data pro~essors.
Each one of the CPUs 10 is coupled to a communications adapter 1I by a system bus 12. In the case where the CPUs 10 employ the ~AX architecture standard, for example, the busses 12 can include the same 64-bit multiplexed address/data bus and control bus which the VAX CPU uses for accessing main memo~y and other such local resources. In this computer interconnect system, there can be a large number of these CPUs 10, several hundred or even several thousand, three ~eing shown for ~: simplicity. Each one o~ the communications adapters 11 is connected to dual communication paths comprising two serial links A and B, where each channel or lin~ A has a serial receiw line 13 and a serial transmit line 14, and each link B has a serial receive ~ine 15 and a serial transmit line 16. All of the serial links A are connected to a cGntral hub or distribution nodo 17, and all of the serial links B aro ., 7 . ,, ' :: . .... . - . .... . .......... .
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cormectcd to a hub 18. The hubs 17 and 18 can be active interconnect mechanisms, in which case they Eunction as cross-bar switches, rnaking a direct connection between a particular one oE the adapters 11 and another one as requested by an address in the message packet transmitted on one of the serial links A o~ B.

S The Eormat of the message packets 20 transrnitted and received on the dual path serial links A or B is set Eorth in Figure 2 and in U.S. Pat. 47777,595, assi~ned to Digital Equipment Corporation. The packet 20 includes a sync portion 21, a header and information portion 22, and a trailer 23. The sync portion and trailer are added by the communications adapter 11, while the header and information packet 22 is generated in the host computer or CPU 10 Eor a node. The header and information partion 22 comprises an integral number of bytes ~rom about ~en in length up to, in an example embodimen~, about 4,100 bytes. Each byte of the packet 20 is transmitted bit-serially on the links A or B, using Manchester coding.
The transrnission rate on a serial link A or ~ is, for example, 70 Mbi~/sec, i.e., 114.28-nsec per byte. The sync portion 21 includes a fixed nurnber such as sevenone-byte bit-sync characters (e.g., 55h~X) Eollowed by a one-byte charac~er sync (e.g., 96~ and ~unctions to allow the recei~ing adapter 11 to recognize the beginning of an incoming message and to regenerate a clock synched on the bit and charac~er boundaries. The trailer 23 includes first a 32-bit CRC generated by the source node and used by the receiver node to calculate a function of all oE the bits in the header and inEormation portion 22 ~o ~heck the integrity oE the received data; the trailer 23 also ends with a number of trailer characters which mereiy Eunction to designate the end o~ a message packet. The packets 20 are transmitted asynchronously on the links A and B, separated by intervals where no carrier is present on the wire link.

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Thc header and information portion 22 oE the packet 20 of Figure 2 includes a type or command field 24 specifying what t~pe of message is being transmitted,followed by a length field 25 speci~ing the length oE the message expressed as the number of bytes~ An address field 26 specifies the destination address to which the S CPU 10 (of ~he source node) requests the data be sen" and this destination address is repeated in a second field 27 containing the complement o~ the same address, for reliability purposes. The source address (the address oE the node sending the data) is contained in a field 28. These addresses may be absolute addresses, or aliases, depending upon the soEtware used. The size o~ the address fields detennines the number of nodes that can be uniquely addressed in a network: a one-byte address field can address 256 nodes. These Eields 24 to 28 constitu~e the "header" of the packet. Following the addresses in the packet 20 is the data field 29, which may be from zero to 4089 bytes in length. An acknowledge packet is o~ the same format as the packet 20 of Figure 2, but it has a zero-length data field 29, and it has no length field 25; the type ~leld 24 o~ an acknowledge packet has a certain code Eor a positive acknowledge and another code for a negative acknowledge or NAK.

The medium used to convey the data packets 20 along the serial linlcs A and B a~ illustrated in Figure 1 is pairs of coa~ial lines 13 and 14, or 15 and 16. That is, four coaxial cables connect to each node (two for each channel). It is understood, however, ~hat other media such as ~lber optics or twisted-pair cabling, could be used instead. Likewise, she network may include bridges to other networks, and may use interconnect arrangements other than the crossbar switch mentioned.

In the dual path computer interconnect system o~ Figure 1, any one of the CPUs lO may be simultaneously transmitting packets 20 to two different semote CPUs via the hub 17 or 18, or it may be simultaneously receiving two different :
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packets 20 Erom two remote CPUs 10, or it may be transmitting a packet 20 on link A and receiving a packet 20 on link B, or vice versa. Thus, when a CPU 10 sends a message packet 20 to the hub 17 or 18 ~or Eorwarding to a particular remote CPU
10, the probability oE a serial link A or B Eor the addressed CPU being free to S receive is much higher than if only one path was present. IE a message packet 20 is sent out by a CPU 10 on a link A or B, and the hub 17 or 18 finds that no path is Eree to the addressed remote CPU 10, then the packet 20 is discarded and mustbe resent; when an adapter 11 is transmitting on outgoing line 14 or 16, this adapter is at the same time detecting the carrier on its incoming receive line 13 or 15, and the active hub sends a "Elow control" signal on this receive line 13 or 15 when the packet 20 cannot be sent on to the remote CPU addressed by this packet. Thus, the transmission oE the packet 20 can be aborted beEore completion. If a cormection is made by the active hub 17 or 18 to the intended remote CPU 10, so that the packet 20 transmitted by a given CPU 10 is sent on to the addressed destination via the active hub 17 or 18, then an acknowledge packet is sent baclc by this remoteCPU and is directed to the given CPU via the receive line 13 or 15.

The circuitry in the active hub 17 may pèrEorm the function of detecting the presence of a transmitted packet 20 on any of the lines 14 or 16 by det~cting the header 21, determining the destination address Erom the Eields 26 and 27, checking to see if the addressed destination node has a Eree link A or B, and, if so, making the connection to send the packet to that node. The links A and B are interchange-able from the standpoint of the CPUs 10. The reason Eor having two serial links A and B instead o~ one is to increase the probability that one will be free, and so to decrease the average delay time or number of retries needed. At any given time, there can be several completed connec~ions between pairs of nodes through the hub 17 or 18. The hub 17 or 18 may be constructed in the manner disclosed in :. , -.

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copending U.S. p~tent applications Ser. Nos. 109,503, 110,009 and 110,513, filedOctober 16, 1987, assigned to Digital Equipment Corporation, incorporated hereinby reEerence, or as explained below in reEerence to Figures 7 and 8.

The adapter 11 is shown in more detail in Figure 3. A wire interface circuit 30 provides the connection to the transmit and receive wires 13, 14, 15 and 16 of the serial links A and B. At the other end, a b~s in~erface circuit 31 couples the bus 12 to the adapter circuitry; the bus 12 includes a 64-bit multiplexed address/data bus 1~a and a control bus 12b. This bus 12 is also used by the CPU 10 to access main memory, Eor example, and various other resources, so the adapter 11 must share use of this bus. Two DMA-type circuits 32 and 33 called data movers A and B are used to move data between the ~a~a bus 12a (~r~a interEace 31) and a packet bu~fer memory 34, using a memor~ controller 35. The A data mover 32 is used to transEer blocks of data ~rom the CPU 10 to the packet buffer 34, and the B data mover 33 is used to transEer blocks of data in the other direction, from packet buEfer 34 to the CPU 10. The data movers 32 and 33 each contain a buEfer holdingfour 64-bit doublewords, so the accesses to bus 12 and packet buffer can be separately timed. A por~ processor 36 defines the internal operation of the adapter 11 under cantrol a~ a program stored in a program memory 37 haYing EPROM and RAM portions. The memory control circuit 35 functions to a~bitrate and direct the transfer o~ outgoing and incoming data packets, storing these temporarily in thepacket buf~er 34 as will be expiained.

The packet buffer 34 is a RAM functioning as a temporary store ~or packets oE data received Erom either of the A or B receive lines 13 or 15, then such packets are moved from the packet bu~fer to the CPU 10 or its main memo~y by data mover B and data bus 12a; similarly the packet buf~er 34 ~unctions as a temporary store Il :
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2 ~ 3 5 Eor packet~ which are going to be transmitted by either oE the A or B transmit lines 14 or 16, in which case the packets are sent from the CPU 10 to the packet buffer via data bus 12a and data mover A. The packet buffer 34 is connected to the memo~y controller 35 by a 32-bit data bus 40 and a 13-bit addr~ss bus 41, along with control lines 42. The size oE the packet bufEer 34 in the example embodiment is 8K
longwords, where a longword is 32-bits, i.e., two 16-bit words or four bytes. Data is transferred ~rom the wire interface circuit 30 to the memo~y controller 35 (and thus to the packet bu~fer) by a byte-wide receive data bus 43 for the channel A data receive line 13, or trans~erred by a byte-wide receive data bus 44 for channel B data receive linç 15. Likewise, transmit data is transEerred in paraliel to the wire interface circuit 30 via transmit data busses 45 or 46 Eor the channel A or channel B transmit lines 14 or 16, respectively.

The wire interface circuit 30 includes parailel-to-serial converters 47 Eor outgoing data, and serial-to-parallel converters 48 Eor incoming data, for each oE the A and B channels. Similarly, each outgoing path includes a binary-to-Manchester code conver~er 50, and each incoming receive-data path includes a Manchester-to-binary code converter 51. A clock is recovered from an incoming signal ~r each channel A or B using clock detector circuits 52. One example of Manchester-to-binary decoder an~ clock detector circuitry suitable for use in this wire interface circuit 30 is shown in 'U.S. Patent 45592,072~ assigned to Digital Equipment Corporation, incorporated herein by re~erence. The outgoing transmit packets on lines 13 and 15 are clocked by a local 70-Mbit/sec clock oscillator apptied ~o the converters 47 and coders 50. Control of the wire interface circuit 30 is by ` commands applied from the memory control circuit through a control bus 53 to a controller 54, operating as a state machine. A detector 55 Eor each channel functions to detect the presencç of a carrier on the receive lines 13 or 15, and to :`
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provide a carr`ier-detect signal to the controller 54, and also (after enabled by the controller 54) to detect the presence o~ the character sync field Eollowing the bit sync characters oE the packet 20. Thus, an incoming packet first causes the carrier detect signal to be sent to the controller 54, then, if the controller 54 sends an S enable signal to the detector 55, the character sync byte causes a sync signal to be sent to the controller 54, at which time the controller 5~, would command the serial-to-parallel regis~er 48 to start clocking in the data bits at the clock rate determined by the recovered clock ~rom clock detector 52. A~ter eight clocks (8-bits), a byte o~ data is loaded to bus 43 or 44 ~or transEer to the memory controller 35, where Eour of these bytes are accumulalted before writing a 32-bit longword to the packet buffer 34. Since the data rate on the line 13 or 15 is, e.g., 70-Mbit/sec (114.28 nsec/byte), the write operation to the packet buf~er 34 need only be at a rate of (32~114.28)/8 or once every 456 nsec; the cycle time for a read or write to packet bufEer 34 v~a busses 40-42 is only about one-eighth this amount (e.g., 64 nsec/cycle), and so there is amble time for accessing the packet buEEer Eor other functions. That is, access cycles on the bus 40 needed to serv~ce reception of a packet on one channel is about every seventh or eighth cycle. Outgoing packets are similarly treated; 32-bit lon~words are read ~rom the packet buEfer via busses 40^42, then sent (byte or nibble at a time) to one oE the converters 47 via a bus 45 or 46, then clocked out through binary-to-Manchester coders 50 at a 70-Mbit/sec (14.285 nsec,~bit) rate using a local clock instead of a recovered clock. Simultaneous reception (andlor ~ransmission), using both channels A and B, requires only about one~fourth of the available access cycles on the packet bufEer bus 40 to transEer data to or from tlle wire interEace 30.

The operation of the memory controller 35, wire interface 30, and data movers 32 and 33, is controlled by the port processor 36, which may comprise a : .
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commercially-available high-speed RlSC-type microprocessor, or may be especiallytailored to ~he particular protocol or application of the network. This processor 36 accesses its program memory 37 by an address bus 56, a data bus 57 and a cont~olbus 58. Also, a local memory 59 is accessed by an internal data bus 60 which allo is used by the processor 36 to write or read various control or status registers in the memory controller 35. The local memo~ 59 merely functions to store some temporarily-used or variable addresses or node characteristics as may be required;
this memory is addressed only 'oy the processor 36 via address bus 61. The procçssor 36 sends or recei~es control or command signals to or Erom the memory controller35 and a controller 62 for the data movers by a control bus 63. The port processor 36 accesses various address and control registers in the memory controller 35 by the data bus 60 and a 6-bit address bus 67, along w~th the control bus 63. The controller 62, when activated by commands from the processor 36, memory controller 35 and/or Erom CPU 10 via control bus 64 (i.e., from system control bus 12b), ac-tivates the selected data mover 3~ or 33 execute a DMA transEer of Eour doublewords (a block of four 64-bit segments oE data) using the 64-bit data bus 65 on one side or the 32-bit data bus 66 on the other side going to the memory controller 35. Thus, one function of the data rnover A is to convert a 64-bit wide data write from the bus 12a to two 32-bit transfers into the packet buffer 34 via bus 66; similarly, data mover B accepts two 32-bit longwords from packet buEfer 34 via bus 66 and sends one 64-bit doubleword to bus 12a via bus 65. These transfers are done in groups of four, or 4x64 bits (4x8 or 32-bytes), with a wait period in between;
this is to avoid tying up the CPU bus 10 for lengthy periods, and is more than sufficient to keep the packet buffer 34 replenished with transmit data or depleted oE receive data so long as a block move is done on average once for every eight 32-bit packet buEfer accesses.

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Referring to Figure 4, the construction oE the memory control circuitly 35 is shown in more detail. This circuitly controls access to the packet buE~er data bus 40, the packet buf~er address bus 41, the port internal bus 60, and the data mover bus 66, as well as the transmit and receive busses 43, 44, 45 and 46 The packet S buffer 34 is ported to Eour difEerent functional elements, all four oE which must have access to the packet buf~er These Eour functional elements are (1) the wire interface for transmit and receive data, (2) the data mover A Eor moving in transmit data from the CPU 10, (3) the data mo~er B for moving ou~ received packets to the CPU 10, snd (4) the port processor 36 Eor checking addresses and otherwise manipulating the transmit and receive data while it is in the packet buEfer. Thus the address bus 41 ~or the packet buffer is driven by a multiplexer 70 ha~ng Eour inputs for these ~our ~unctions. Address counters 71, 72 and 73 ~or three oE these pro~ide inputs 74, 75 and 76 to the multiplexer 70. The counter 71 holds the packet bufEer address used by the data mover B for sending data to the CPU 10, and counter 72 holds the packet buffer address Eor the data m~ver A Eor data being sent to the packet buffer Erom the CPU 10. The countes 73 holds the address being used by the port processor 36 for accessing the packet buEEer Eor writç or read. Each one of these counters is automatically incremented each cycle for repeated reads or writes to adjacent locations Eor block moves, Eor examplç. The address counters 71~
72, and 73 are written to by the port processor 36 via an input bus 77, using the address bus 67 for selection; similarly, these address counters may be read by the port processor via multiplexer 78 receiving inputs 79 from the busses 74, 75 and 76 as before (selected by address bus 67), with the output o~ this rnultiple~er 78 being coupled via selectors 80 and 81 to the port data bus 60. The other address inputfor the bus 41 via multiplexer 70 is by an input 83 Erom a pair oE address registers 84 and 85 in a transmit/receive controller 86, and these addrçss registers also may be written to by the processor 36 via post bus 60 and the same internal bus 87 used . .
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2 ~ 3 5 to write to the addre3 registers 71-73, or read from by the processor 36 via bus 88, multiple~er 78 and selectors 81 and 82, using the address bus 67 for selection.

Also seen in Figure 4 is a memory map 89 oE the packet buEfer, where the 8K longwords of storage is shown divided into Zone 1 and Zone 2 Eor receive data, and a transmit zone ~r packets o~ data awaiting transmit. Each one of the Zones 1 and 2 may be 2K longwords in size. The counter register 71 always addresses the transmit zone, and the counter registers 72, 84 and 85 address the Zone 1 and Zone 2 areas of the memoty map 89. The zone marlager circuitry described below controls the way receive data is wri~ten ~o these zones.

The memory controller circuitry o~ Figure 4 defines the pathways between the data mover bus 66 and the packet buffer bus 40. Data in 3~-bit iongwords ~rom ~he four by 64-bit buEfer in the data mover A is applied ~o a bu~fer re~ister 90 where each 32-bit longword may be parked ~r a cycle beEore being applied via bus 91 and multiplexer 92 to the data bus 40 to be written to the packet bufEer. In a similar manner, data from the packet buffer on the bus ~,0 may be held in parking registers 93 or 94 which have inputs ~rom bus 95 and have outputs 96 and 97 to the port internal bus 60 or the data mover bus 66. The output 96 from the parlcing register 93 for pasket bufEer data is coupled to the bus 60 via selectors 81 and 82.
Data going to the data mover E~ via bus 66 is coupled to a bus 98 by selector 99which receives one input from the parlcing register g4 via bus 97 and receives its other input from a parking register 100 functioning to hold a 32-bit longword oEdata from the bus 87 being sent to data mover B i~ the ~us 66 is busy.

The packet buEEer bus 40 of Figure 4 san supp3y data to the parking registers 93 and 94 for the port bus or data mol~ers, and supplies data via bus 95 ~o the . . .
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transrn~t busses 45 and 46 going to the wire interface circuitry 30. Since the busses 40 and ~5 are 32-bit busses, this data is buE~ered in couplers 101 and 102 to provide byte or nibble width instead of 32-bit wide data; the busses 40 and 95 have a cycle time Eour or eight times shorter than the busses 45 and 46 (and about 32-times S shorter than the time required to transEer 32-bits o~ data on wires 14 and 16). The incoming data on busses 43 and 44 is likewise bufEered irl couplers 103 and 104 to change from byte-wide to 3~-bit w~de, and then connected by selector 105 and bus106 to the rnultiplexer 92. Thus, in a given machine cycle oE the processor 36 or bus cycle of the packet buEfer 34, the packet bu~fer can deliver a 32-bit longword of data to ~1) a coupler 101 or 102, or (2) the register 93 for delivery this cycle or the next to the processor 36 via bus 60, or (3) the register 94 for delivery in this cycle or the ne~t to the data mover B via bus 66; or, alternatively, the packet bu~fer can receive (for write) a 32-bit longword ~rom (1) the coupler 103 or 104, or (2) the data mover A via bus 66 and input 91, or (3) the processor 36 v~a bus 60 and bus 87, all via multiplexer 92.
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The ar~itration and control of which of the sources or destinations of data is used in any given cycle is determined in an arbitration and control circuit 108 in the memory controller circuit~y oE Figure 4, ~unctioning to supply the packet memory 34 with addresses via selector 70 and bus 41 and with read or write controls via bus 42, and to establish a data path between the bus 40 and the other elements as just described. To this end, the control 108 applies control signals (not shown) to each oE the selectors 70, 78, 81, 82 92, 99, and 105 in machine cycles where these devices are used, and to load or read the various registers or busses. The control 108 also triggers the incrementing oE the counter registers 71-73 or 84 and 85 during sequen-tial reads or writes, i.e., block moves.

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2 ~ 3 5 Wllen a data trans~er Erom the packet bufEer 34 and the CPU 10 via data mover B is needed, as when a packet has been received and stored in the packet buEEer, the port processor 36 executes a routine which first loads the beginningaddress oE this packet into the register 71 (and thus begins a fetch of the addressed data from ~he packet buffer to the park register 94), and then control is trans~erred to the arbitrate and controt circuit 108 and mover control 62 by commands issuedon bus 63. The control 62 receives a "read mover bu~er ready" command which is asserted on a line of bus 6~ from control 108, and when the mover B is ready (mover B must request bus access via control bus 64 to gain use oE the CPU data bus 12a), ie asserts a "read mover transfer GO" command via bus 63 to the mernory controller circuitry 108, which then clears the ~read mover buffer read~,r" cornmand and places the 32-bit longword Eetched Erom the p;~cket bu~Eer onto the bus 66 Yia path 95, 94, ~7 99, 98 in Figure 4. IE the bus 66 is busy or the GfO signal is not asserted yet, this data can be held in the park register 94. The address register 71 is incremented by the control 108 and the "ready" and "GO" sequence begins again.
The mover A assembles eight longwords transferred in this manner and stores themin its internal four ~y 64-bit buEfer, then when ~his internal buffer is Eull attempts an eight-longword write to the CPU 10, usually by DMA to the main memoty oE the CPU, and when it has been given access to the CPU bus and completed the write it can then assert GO again. Since the processor 36 keeps track oE start and endaddresses of the packets, it has also loaded a count register in ~he control 108 so that the sequence wil~ end when this count is reached, i.e., ~he entire recei~ed data packe~ has been trans~erred.

When a transfer from the CPU 10 to the packet bu~Eer 34 via the write mover A is needed, as when the CPU 10 has a massage to send, the CPU 10 will first write a command longword to an internal register in mover A via bus 65, then . .

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the control 62 decodes this command it asserts a request via bus 63, in response to which the port processor 36 begins a data move by loading a PB start address to the register 72 that is suitable ~or a new packet, then trans~ers control to the controller 108. The controller 108 asserts a "write mover buffcr ready" signal on bus 63'tocontroller 62 indicating that the data can be sent on bus 66. When the control 62 detects a vacant bus cycle by arbitrating the bus 66 ~or register trans~ers and packet buffer transEers, it places the first 32-bit longword oE the data onto the bus 66 and asserts a "write mover transfer GO" signal, causing the controller 108 to ~ake data from the bus 66 through park register 90 and write it to the addressed location defined by register 72, via bus 91 and selector 92. IE the bus 40 is busy, the data is held in the park register until ~he next free bus cycle. When the write has been executed, the ~ontrol 108 asser~s the "write mover buf~er ready~ signal again via bus 63 to control 62, and the cycle repeats.

ReEerring to Figure 5, a timing diagram of access cycles for the packet bu~Eer bus 40, 41, 42 is illustrated ~or various conditions. The access cycles are in this example 64-nsec in length, during each o~ which a write or read may be made to the packet buffer 34. Access to the packet buE~er 34 by the port p~ocessor 36 and the wire inter~ace 30 is of higher priority than that o~ the data mover control 62 as just described. That is, if either of the port processor 36 or the wire interface request access to the packet buf~er during a cycle-1 of Figure 5, the data movers are stalied by negating the "reacly" signals from control 108 to control 62 mentioned above.-, lhe result is that the accçss time for either the port processor or the wire intcrface ', is fixed and predictable. The transmit and receive data rates as indicated above are ` such that even if both serial paths A and B are in use the amount o~ data to be transferred via busses 43-46 will occupy only about one-quarter o~ the access cycles available on the bus 40, and these will be non-adjacent cycles (the wire interface ,-~ 19 , .
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never ma~es back-to-back requests in two sequential cycles), so iE the bus 40 is busy in one cycle for a wire interface transEer it will be free the next. Thus the wire interface can keep up with the serial data stream on the channels A and B, and the code executed by the port processor 36 receives return oE memory data in a S deterministic fashion; the processor 36 is also restricted to making a bus 40 request at a maximum oE every other cycle, i.e., no back-to-back requests are allowed.

The arbitrator and control 108 apportions the mems)ry bus 40 cycles to the processor 36 and the wire inter~ce controllers 86, 54, using the parking registers to avoid the necessity for any request/grant protocol. It appears to the wire interEace controls 86, 54 that a request ~or a write memory access is honored immediately, and the same is true for the port processor 36; the data from either of these sources is accepted by the memory controller 108 which de~ermir~es if the data is retired (written to memory 34) or parked. The requests are always accepted upon demand, even iE both the processor 36 and the controller 86 make a write request in the same cycle. "Read packet buffer" reguests are also honored immediately, with therequest Erom the w~re interface control 86 being executed in the cycle following the request and the data being returned to the couplers 101 or 102 in the next cycle;
the processor 36 has its read request accepted without delay, and9 although the mernory fetch via bus 40 Eor this processor read request may occur in either the next or the subsequent cycle, the read data is always returned on the third cycle Eollowing the request, as it is held in the park register 93 so the processor 36 can always expect the return data at a Eixed delay. In the event the memoty controller honors a write request Erom both the controller 86 and the processor 36 in the same cycle, it parks the data for the processor in the parking register 109 and retires the data Erom the wire interface couplers 103 or 104 in the frst memory cycle then retires the processor data ~rom parking register 109 in the next cycle, leaving the controller ~;

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108 ready to accept two more requests. In the event that either the processor 36or the wire interface controls 86, 54 make a solitary write request. then their data is retired in the first cyc!e9 leaving the subsequent cyc~e available for ~he other port if needed. r S The parking registers 90 and 94 are ~Ised in the data m~ver interface as mentioned above, in conjunction with the priorities oE ~he wir~ interface and processor. The "write movcr transEer GO" si~nal sent by the control 62 acts as apacket buEfer request and indicates that write data is being sent to the memory controller 35 via bus 66; this data on bus 66 is either written into the packet buEEer v~a path 91 under control of the controller 108 (if no processor or wire interface request is pending), or will be held in ~he parking register 90, so no data is lost, there is no resend needed, nor is a "bus request, bus grant" arbitration needed after the "ready" signal has indicated that the register 90 is ~ree. The loading of the read mover address register 71 by ~he port processor 36 is the command to the controller 108 to begin a read mover sequence for accessing the packet buf~er. When a cycleEor the packet buffer ;s given to the read mover sequence, the controller 108 prefetches the data ~rom the packet bu~fer addressed by the register 71 and loads it into the parking register 94. When the mover B is ready to receive this data, the control 62 send the "read mover transfer GO" signal which acts as another request.
~a "grant" signal in ~he conventional sense is sent by ~he memory controller. The data being requested by the mover control 62 with the "read mover transEer GO"
signal has already been stored in the parking register 90 before this request from the control 62. The controller 108 causes the data in parking register 90 to be placed onto bus 66 when this "GO" signal is received ~om control 62, and this signal also acts as another packet buffer request which is arbitrated and another long~vord of data Erom the mover B is prefetched iE the packet buEfer bus is Eree this cycle. As .`. .
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2~11 935 this "ready"r'GO" handsha~e progresses, the controller 108 attempts to keep the write mover parking register 90 empty and the read mover parking register 94 Euil, while using the processor parking register 109 to resolve request conflicts between the processor 36 and the wirè in~erface control 86, 54.

S As seen in the memory map 89 o~ Figure 4, the receive portion oE the packet buffer 34 has two zones where receive data is written, and these zones are managed by the controller 108 in a manner which will be represented by the logical depiction oE the same circuitry in Figure 6. The purpose o~ this zone management is to provide temporary storage of the received data in the packet buEfer 34 even though two se~ial data stream p~cket~ o~ variable size may be arriving at the same time.
Thi~ management technique avoids the prior technique o~ reserving areas o~ ~xèd size, which would reduce the capacity to handle packets even though the buEfer was not fully utilized. Because each incoming packet 20, whether large or small, con~ains the same beginning fields 24-28 and C~.C, small packets may have as much or moredescriptive information as data field 29. Thus in small packets, the descriptive-to data ratio may be considered high while in larger packets it is srnaller; a small packet utili~es not only space (was~ed i~ fL~ed areas are allocated) but processor time as well, since the packet must be accessed to examine it and introduce whatever part of the protocol is place~ ;n ~he responsibility oE the port processor. A fixed allocation as mentioned increases the likelihood the packet buffer capacity will be reached so that further incoming data cannot be accepted and must be NAKed and resent later; this double handling wastes computer time.

Accordingly, the purpose of the packet buEEer management technique .~ irnplemented with the logic oE Figure 6 is to accomrnodate incoming data packets 20 25 with less likelihood o~ the buffer 34 being filled and unable to accept mure, even ,~

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though thcrc m~y be two simultaneous incoming packets, and even though the packets are o~ variable size. The order oE receipt is preserved, regardless oE whether channel A or B handled the data, or whether zone l or zone 2 stored the data.
This must be accomplished at the high data rates of the serial links A and B, i.e., S 70-Mbit/sec.

lhe half of the packet bufEer 34 used for recei~e data (4K longwords) provides up to six~y-four variable-size buffers ~or packets, available on a demand basis by a zone select arrangement, maintaining sequentiality even though the packets are arriving overlapped. The delivery sequencing is done w`ith respect to successful packet termina~ion times regardless of the packet start times, the packet lengths, or the path A or B on which the packets are received. Mult;ple, elasticrecei~e-data buffers are thus provided to enhance the ability of the adapter 1I to process packets at high speed.

Referring to Figure 6, packet memory 34 is considered to have two receive-data ~ones 1 and 2" and the incoming data from the couplers 103 and 104 is allocated to one or the other zone according to a receiver crossbar 110 which ismerely a flip flop in the controller 86 designating which one of the registers 84, 85 is used in association with which coupler 103, 104 input as selected by the selector 105. The crossbar 110 is toggled periodically i~ the detectors 5~ indicate to the controller 86 that both lines 13 and 15 are silent (no carrier). Thus, neither path A or pa~h B is favored ~or using eithcr zone, and pre~erably the zones will fillappro~mately equally. Paths 40-1 and 40-2 are schematically shown ~or writing tozones 1 and 2 (as if sepa~ate and simultaneous), although it is understood that physically the bus 40 is shared and writing is interleaved if two packets are being received simultaneously. Two address registers 111, 112 are included in the con-" ~ ," ,~
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troUer 86 and Eunction as the head pointers for zone 1 and for zone 2. Th registers 84 and 85 used to address the two zones are counters which may be incremented by increment circuits 113. Tail pointers 114 Eor each zone are included as will be explained. Compare circuits 115 and 116 also included in the control~86 S produce outputs 117 or 118 when the content o~ the address registers 84 or 85 have reached a value equal to the tail pointers 114. The two head pointer registers 111, 112 and two tail pointer registers 114 may be written to (or read) by the port processor 36 using the busses 60, 63 and 67; indeed the logic o~ Figure 6 may beperformed by code e~ecuted by the port processor, alth<~ugh speed is enhanced byusing fixed logic in the controller 86.

Data packets may arrive from external sources on lines 13 or 15 at any time, and may be on path A or E,. Assume packet-1 arrives on path A and is connected by the crossbar 110 to zone 1. When the receive process is started by receipt oE a character sync as mentioned above, resulting in a control "sync-A" Erom controller 54 to controller 86, the zone 1 header pointer is copied from register 111 to register 84 where it is used as the address register pointing to the next empty longword in the packet buEfer 34 via mul~iplexer 70 and bus 41 (depicted as address input 41 1 in Figure 6). Register 84 is incremented each time a longword is wri~ten to the packet buffer 34. If the receive process is termina~ed successfully (no ~RC errors, length equals Eeld 25, etc.) then the contents oE register 84 is copied to head pointer register 111 after all longwords of the packet have been written to the packet buEfer.
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If a second paclcet 20 comes in from path B while the Frst packet is in progress, then it is fed to zone 2. The head pointer 112 is copied to counter register 85, which is used to address the longwords of packe~ buEfer wne 2 via address input 41-2 as the register 85 is incremented ~or each write; upon successful ~, , ., .

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completion the register 85 points to the address next after this stored packet and is copied to the head pointer register 112. If a packet terminates unsuccessEully due to a CRC error, Eor example, then the head pointer register 111 or 112 is left unmodified and the next packet will write over the bad data just written to the S packet buEEer. Following receipt of a packet Erom one path, iE the other path is not currently active, then the controller 86 switches the receiver crossbar 110 to swap the connections between path and zone. During silence on both receive lines 13 and 15, the crossbar continuously switches the path-to-zone connection back and Eorth until a packet reception on either path is detected. Upon detection of an incoming packet, the crossbar is leEt in whatever position it happened to be in at the time.
This is done to distribute paclcets evenly between the two zones in cases where one of the paths A or B is repea~edly active and the other silent. UpOIl successEul completion o~ any packet, the controller 86 asserts a zone-don~ signal Z1-done or Z2-done to a zone-done monitor 119 implemented either in hardware in the control86 or in software in the port processor and its local rnemory 59. A 64-bit deep,single-bit-wide register Eile 120 Eunctions as the zone-select Eile. A 6-bit 1-oE-64 write-pointer register 121 points to one loca~ion (one bit) of this file 120, and likewise a 1-of-64 read-pointer register 122 points to one location of this ~le 120.
The zone-done monitor I19 writes via input 123 a zero Eor zone-l done or a one for zone-2 done at the address pointed to by the write-pointer 121, every time a Z1-done or a Z2-done signal is received, and increments the write-pointer register 121 so it points to the next free one-bit slot of the file 120. The contents of the write-and read-pointers 121 and 122 are continuously monitored by two compare circuits123 and 124, where an "equal" output 125 is produced iE the pointers 121 and 122are equal, or a "not-equal" output 126 is produced iE the pointers 121 and 122 are - not equal. If the not-equal output 126 is produced, then an interrupt is asserted to the port processor 36 indicating that there is at least one packet in the packet buEEer ..
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201 193~
34 that requires service. Upon receipt of this interrupt, the port processor 36 e~ecutes a register read operation via bus 60 to retrieve the zone-select output 127 ~rom the zone-select file 120, this output being a one-bit value at the locationpointed to by the read-pointer 122, telling the processor 3S whether to fetch d~ta Erom zone~1 or zone-2 of the packet buEfer. This read ~rom output 127 also causes the read-pointer 122 to be incremented by an input 128 such tha~ the next ently in the zone-select file 120 is pointed to. This arrangement causes the packets to be serviced by the port processor 36 in the order received. The routine executed bythe port processor 36 when this interrup~ can be serviced causes it to access the header of the new packet in the selected zone in the packet buffer to retrieve this data for checking or processing. When this packet has been checked or processed,then fo~warded on to the CPU 10 via the data mover B ~as this can be done under the priority se~ by Lhe arbitrator and contro3ler 108), the port processor then adds the packet length (which it retrieved from the rleld 25 of ~he packet 20) to the head address (which it maintains in local memory 59 matched with the head pointers 111 and 113). The port processor 36 then writes this new address into the tail pointer 114, releasing the space back to the zone manager logic to be used again as needed.
If, during receipt of a packet, the value of the register 84 or 85 being used at the time reaches the value oE the corresponding tail pointer register 114, as indicated by output 117 or 118 from compare circuit 115 or 116, then a NAlC is sent to the control 86 via lines 129 or 130 and the writing of this paclcet to the packet buEfer zone is stupped and the packet is NAKed (nega~ive acknowledged) so it would haveto be resent later. Similarly, iE the write-pointer 121 reaches the same value as the read-poin~er 122, then all sixty-four slots Eor packets have been used (the portprocessor is not keeping up with packet receipt by checking and initiating data mover operations) and so the packet must be NAKed, so the output 125 ~rom equal detector 123 is (~ ed with the outputs 117 and 118 in gates 131 and 132, so either ., . . ~ -, . :, . . . :
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of the~e overfiow conditions produces a NAK. As packet buffer space is released by the port processor 36 back to the zone manager logic, the tail pointers 114 lead the address counter ~egisters 84 and 85 and so new packets are transferred into the packet buffer 34 and made available for service by the port processor. This S zone management technique allows temporary store o~ variable-length packets with longword granularity in a dual receive path system. The total number oE buffers (sixty-four in th;s e~arnple) is set by the size oE the zone select ~lle 120 and/or the size of the packet buffer 34 used for the zones. In the 4K long~vords allocated in ~his e~ample, the average packet size is 64 ~ongwords (256 bytes~. By using a larger packet buEfer 34 and a larger file 120, the capacity cl~uld be increased as needed.

Referring to Figure 7, a logic flow chart is shown Eor operation of the zone managemen~ function impiemented by the circuitry of Figure 6. The first step is an idle loop, depicted in blocks 134 and 135, where the crossbar 110 is switched each cycle iE neither path A or path B is receiving a packet, i.e., the control 86 checks to see iE either of the channels has completed the sequence mentioned above of carrier detect, enable, character sync. I~ either A or E~ does, a Sync-A or Sync-B
signal is sent by control 54 to control 85. Either one causes the crossbar to be left in whatever condition it is in, and the state of block 136 to be entered, which ioads the head pointer 111 or 112 to be loaded to the counter 84 or 85, then a loop isentered to write the contents of 32-bit register 103 or 104 to ~he packet buffer 34 via bus 40, at state 137, increment the counter register 84 or 85, then check to see if the receive-data signal is still valid at decision point 138; if yes, the loop is re-executed, if no, the complete packet has been loaded to the packet buffer and the ne~t decision point 139 is whether or not packet is good, so iE the CRC check Eails then the entire loop begins again via path 140 IE CRC check passes, then the comparator 125 is checked at decision point 141 to see i~ the zone selector file 120 ., .

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is full, and if so the packet is discarded and the entire loop restarted via path 140.
If the file 120 is not Eull then the steps oE block 142 are performed to complete a valid packet load; the counter 84 or 85 is loaded to the head pointer 111 or 112, the zone-done pointer 11~ writes to the zone select ~lle 120 to indicate which z~ne S received the packet, and the write pointer 121 is incremented. llle last step 143 is to signal an interrupt to the port processor 36, which will be serviced as access cycles are available. Aftes the interrupt is signalled, the enlire loop is started again via path 140, whether the interrupt is serviced immediately or not. The zones thus start to fill with packets, and the port processor tries to keep up in selvicing the stored packets then initiating mover B operations to send the packets on to the CPU 10.The zones in the packet bu~fer act as two separate circular buf~ers, since the head pointers uill each roll over to begin at the lowest address after reaching theirmaximum address values. The zone select Eile 120 acts as a historical silo oE the order of completion oE packet receipts, so that the port processor serv~ces them and of~-loads them in order, even though an set of packets ~rom a single source (consti~uting a sequence which is expected by ~he CPU to be in order) might havebeen routed partly to zone-1 and partly to zone-2 indiscriminately.

I~eferring to ~igure 8, the active hub 17 is shown in more detail. The transmit and receive lines from each host CPU or node 10 are connected to corresponding receive and transmit inputs 145 and 146, respectively for the hub.Note that there are two hubs, a hub 17 for all oE ths A channels and a hub 18 Eor all of the B channels. Each receive input 145 (which is the transmit line 14 or 16 of the node) is connected to a Manchester-to-binary decoder 147, and clock recovery circuit 148 and carrier and sync detect circuits 149 are included just as in the wire interface 30 of Figure 3, then a serial to parallel converter 148 produces byte-width data on a bus 149. A con~rol processor 150 receives lhe carrier detect and sync : ~ .. ,.~ : . ~ :. . . :, , .
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~'011935 detect signals, then accepts the ~lelds 24-28 oE the incoming packet in order todeterrnine what the destination address is, and attempt to route the packet in real time to the destination node. The ~lUb does not store packets for later routing when the destination node might become ~ree, but instead routes the incoming packet S immediately or else discards it. The incomin~ data is coupled by the bus 149 to a switch matrix 151, which is connected by at least two junctors 152 and 153 to all of the other channels of the hub 17. The switch matrixes 151 are corltrolled by thecentral controller 150 via bus 154 and ~unction as a crossbar switch to (in eFfect) connect the input 145 from the source node for the packet to the output 146 of the addressed destination node, and at the same time connect ~he input 145 oE the destination node to the output 145 oE the source node so the Acknowledge packet can be sent back as soon as the packet has been received. The controller 150 candetect if the destination node is busy (by checking for carrier~ and iE so the packet is discarded. A Elow control signal is available at a source 155 for sending outthrough a parallel-to-serial converter 156 and a binary-to-Manchester coder 157 to the transmit output 146 (and ~hus to the receive line 13). A selector 15~ under sontrol of the controller 150 determines whether the output 146 is to be from Elow control source 155 or is to be packet data from a bus 159 from the switch matrix.
Flow control is sent i~ the destination channel is busy, or if the junctors 152 and 153 are both busy; with two junctors only two messages can be routed at one time, somore traEEic can be handled by having additional junctors. The controller 150 can store the source and destination addresses Eor a packet that had to be discarded so this source node has a priority for a time after the destination becomes Eree iE the source resends.

A network with a small number of nodes can operate with a passive hub 17 or 18 instead of the active hub of Figure 8. A passive hub may be merely a star , .
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2~1 1935 connection as seen in Figure 9. All o~ the transmit lines 14 Erom all of the nodes are connected to primary windings 160 o~ a trans~ormer, and all oE the receive lines 13 going to all oE the nodes are connected to seconda~y windings 161. The nodes operate on the basis of carrier-sense multiple access with collision detect (CSM~/-S CD), whereby a node with a packet to send first senses its receive line 13 to see if a carrier is present and if so it is known that the hub is busy and so the node waits until the carrier is not present. That is, only one node may be sending and one node receiving at any time. If two nodes simultaneously sense no carrier and start to send, each node w~ll be reading the incoming packet on its input line 13 and noise will be detected instead of its own outgoing packet; in this case bo~h nodes will stop sending the packet, wait a random eime (or prioritized time in~erval ~ccording to U.S. Pat. 4,560,985) and resend, with the probability bein~ high that one of these nodes will begin before the o~her so another collision is avoided.

In a system using the active hub oE Figure 8, the probability of the destination node being ~ree and the switch matrix 151 being free to make the connection is acceptable under moderate traffic and a reasonable number o~ nodeson line. Thus, when a source node 10 sends a packet 20 there is no precheck on availability, but instead if no carrier is detected on the receive line then the packet is trànsrnitted. The source node 10 waits a predetermined timeout period after the end of the trailer of the packet 20 is transmitted, and if an acknowledge packet has no~ been recei~ed then it is assuD~ed that the paclcet was not received by the destination node 10. Or, if an acknowledge packet 20 is received but it has a NAK
type in field 24, then it is known that the pacKet was recei~ed but it could not be buf~ered. In either oE these e~ents, the source node 10 (by code in executed in the port processor 36 defining the protocol~ begins a resend, which may occur immediately or may be after a priority backoff of the type disclosed in U.S. Pat, li .

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4,560,985. If the switch 151 cannot malce the connection to the destination, either because the switches or junctors lS2, 153 are busy, o~ because the destination node has both of its channels A and B busy with other transmission or reception, the controller 150 activates selector 158 to send the flow control signal back to the node S on its receive line 13 or I5. The ~low control signal is made up of 55ha characte~s, just like the sync characters preceding a packet 20, s~ it appears as the beginning of packet which will have no character sync or data ~lelds. A header time-out circu;t 165 as illustrated in Figure lO is therefore included in the interface control 54. This circuit 165 responds diE~erently for reception conditions vs. transmit conditions.
When no transmit operation is being attempted, the ci~cuit 165 is responsive at input 166 from the sync detect circuit 55 to begin a tim~-out when a carrier is received, then a character sync, a 96h~, is not received within a selected time-out period; in this case a receive-abort signal is asserted on the line 167 to cause the control to quit clocking data into serial-to-parallel converters 48, so the receive Eunction is aborted. This type oE abort would also occur, ~or example, if the destination address was bad (corrupted or not for this node). The mode of operation when transmitting provides important improvement in performance, according to one embodiment.
When a transmit operation is initiated by command to the control 54, an input 168 to the circuit 165 is asserted, and the circuit 165 again responds to the input 166 to begin a time-out when a carrier is detected, then generates an abort-transmit signal on output 169 if a 96ha is not received in the selected time-out period. In either receive or transmit modes, the circuit 165 receives inputs 170 from a decoder 171 responding to contents oE the serial-to-parallel converter 48 for this channel. The circuitry of Figure lO is repeated Eor both channels A and B.

The improved operation provided by the transmit-abort circuit oE Figure 10 is understood in reEerence to Figure 11. Assume that a node-1 (one of the CPUs . - , .

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~0~9~5 10 of Figure 1) begins sending a relatively short packet (e.g., 64-bytes) to node-(another oE the CPUs 10) at time to of Figure 11, and that node-3 also begins a transmission to node-2 o~ a 2K-byte packet at time tl. Also assume that node-2 bas other traEEic on its other channel A or B, or the hub switches are busy, so the node-3 transmission to node-2 cannot go through, and nOw control is returned to node-3 by the hub 17 or 18 beginning at time t2 as soon as this busy condition is recognized by the hub. Without the transmit-abort function, the node-3 will continue transmitting it 2K-byte packet until the end o~ the packet at time t3, even though the entire packet ~s being discarded at the hub 17 or 18. When no acknowledge packet is received by node-3 by the acknowledge timeout, it resends the packet beginning at time t4. Thus, the time t2 to t4 is wasted with a useless transmission, and also this channel oE the node is itsel~ needlessly busy during this period when other traEfic might be waiting. Using the abort-transmit Eunction responsive to Elow control, however, as also illustraLed in Figure 11, the node-3 transmission beginning at t5 will be aborted at t6 as soon as the flow control signal is recognized, then the 2K-byte packet transmission is retried at time t7, when the probabili~ is it will find a ~ree path to node-2 (e.g., the node-1 to node-2 64-byte packet has been completed and acknowledged). In this case, the utilization rates of both port-2 and port-3 are higher, so the overall potential throughput or bandwidth is greater. Nevertheless, this perEormance improvement is compatible with systems using passive hubs, in which case there is no now control and the abort Eunctions do not occur, and with nodes which do not have this improvement in their circuitry (e.g., older, existing installations) in which case flow control is just ignored as in the illustration of Figure 11, tl to t4 situation.

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While this invention has been described with reference to a specific embodi-ment, this description is not meant to be construed in a limiting sense. Variousrnodifications oE the disclosed embodiment, as well as other embodiments oE the invention, will be apparent to persons skilled in the art upon reference to thisS description. I~ is there~ore contemplated that the appended claims will cover any such modifilcations or embodiments ar. ~all within the ~rue scope oE the invention.

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Claims (19)

1. A computer interconnect system having a plurality of nodes, each node comprising:
a) a CPU or the like having a system bus;
b) a packet buffer;
c) a data mover for transferring packets of data from said system bus to said packet buffer and transferring packets of data from said packet buffer to said system bus;
d) a serial link for transmitting packets to another node and receiving packets from another node;
e) and packet buffer read/write control means coupled to said serial link and to said data mover; said read/write control means storing packets received by said serial link into said packet buffer and accessing packets from the packet buffer for transmitting on said serial link; said read/write control means providing access to said packet buffer by and said data mover upon demand interleaved with said storing packets and accessing packets.

2. A system according to claim 1 wherein said packet buffer has an input/output port of a data width of at least 32-bit, and said controller couples said serial link to said input/output port by means for converting between 32-bit width and single-bit width.

3. A system according to claim 1 wherein said serial link includes two separate transmit/receive paths.

4. A system according to claim 3 wherein each one of said separate paths can transmit or receive a packet simultaneously with the other one of said paths also transmitting or receiving a packet.

5. A system according to claim 1 wherein each node includes a local processor coupled to access said packet buffer under control of said read/write control means.

6. A system according to claim 1 wherein said control means includes parking registers for holding data transferred by said data mover to said packet buffer or transferred by said packet buffer to said data mover.

7. A system according to claim 6 wherein said packets are transferred in a plurality of words, one word during each of a plurality of read/write cycles of said packet buffer.

8. A system according to claim 5 wherein said serial link and said local processor access said packet buffer in interleaved cycles, said serial link does not access said packet buffer in adjacent cycles, and said port processor does not access said packet buffer in adjacent cycles.

9. A method for packet data communication between a plurality of nodes connected by serial links, each node having a CPU and a packet memory, comprising the steps of:
a) sending a transmit-packet from said CPU of a node to said packet memory by writing a sequence of words to said packet memory during a plurality of firstaccess cycles for the packet memory;

b) transferring said transmit-packet to said serial link for transmitting to another one of the nodes by reading a plurality of words from the packet memory of said node during a plurality of second access cycles for said packet memory;
c) receiving a receive-packet on said serial link and assembling said receive-packet into words for writing to said packet memory of said node during a plurality of third access cycles of said packet memory;
d) accessing said words of said transmit-packet or said receive-packet in said packet memory by processing means during a plurality of fourth access cycles of the packet memory;
e) and sending said receive-packet to said CPU by reading a sequence of words from said packet memory during a plurality of fifth access cycles of the packet memory;
f) at least some of said first, second, third, fourth or fifth access cycles being interleaved.

10. A method according to claim 9 wherein said second access cycles are never consecutive, and wherein said third access cycles are never consecutive.

11. A method according to claim 10 wherein a second access cycle never immediately follows a third access cycle, and a third access cycle never immediately follows a second access cycle.

12. A method according to claim 9 wherein all of said access cycles are executed upon demand, with priority being given to said second and third access cycles, then next priority being given to said fourth access cycles.

13. A method according to claim 12 including the step of temporarily storing said words during sending from said CPU to said packet memory or from said packet memory to said CPU.

14. A method according to claim 9 wherein the period of time of one of said second or third cycles is not more than about one-fourth of the period of time of serial transmitting of one of said words.

15. A method according to claim 14 wherein said words are at least 32-bits wide.

16. A method according to claim 9 wherein said processing means accesses said words in said fourth cycles by requesting a write in a given cycle with the write being executed a number of cycles later determined by whether one of said secondor third cycles is being executed.

17. A method according to claim 16 wherein said processing means accesses said words in said fourth cycles by requesting a read in a given cycle with the data from said read being delivered a fixed number of cycles later regardless of whether one of said second or third cycles is being executed.

18. A method according to claim 17 including the step of parking said data from said read for delivering said fixed number of cycles later.

19. A method according to claim 9 wherein said step of transferring includes serializing said words.