CA2014621A1 - Minimizing the interconnection cost of electronically linked objects - Google Patents

Minimizing the interconnection cost of electronically linked objects

Info

Publication number
CA2014621A1
CA2014621A1 CA2014621A CA2014621A CA2014621A1 CA 2014621 A1 CA2014621 A1 CA 2014621A1 CA 2014621 A CA2014621 A CA 2014621A CA 2014621 A CA2014621 A CA 2014621A CA 2014621 A1 CA2014621 A1 CA 2014621A1
Authority
CA
Canada
Prior art keywords
design
linked objects
electronically linked
partitioning
minimizing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2014621A
Other languages
French (fr)
Other versions
CA2014621C (en
Inventor
James L. Finnerty
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of CA2014621A1 publication Critical patent/CA2014621A1/en
Application granted granted Critical
Publication of CA2014621C publication Critical patent/CA2014621C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement

Abstract

The interconnection costs of electronically linked objects is minimized by the successive partitioning of the initial logic design. The partitioning is based upon the electrical properties of the drivers and loads of the linked objects forming the design. Further, time critical connections are weighted so as to further minimize interconnection cost. A further method refines the result of the successive partitioning by calculating each linked object's contribution to the overall delay of the design. Both the design of device function and timing and the physical realization of the electronically linked objects are solved jointly to make use of the information available from the logical and physical designs.
CA002014621A 1989-06-20 1990-04-17 Minimizing the interconnection cost of electronically linked objects Expired - Fee Related CA2014621C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US369,655 1989-06-20
US07/369,655 US5251147A (en) 1989-06-20 1989-06-20 Minimizing the interconnection cost of electronically linked objects

Publications (2)

Publication Number Publication Date
CA2014621A1 true CA2014621A1 (en) 1990-12-20
CA2014621C CA2014621C (en) 1994-09-13

Family

ID=23456356

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002014621A Expired - Fee Related CA2014621C (en) 1989-06-20 1990-04-17 Minimizing the interconnection cost of electronically linked objects

Country Status (6)

Country Link
US (1) US5251147A (en)
EP (1) EP0403826B1 (en)
JP (1) JPH0334444A (en)
AT (1) ATE158884T1 (en)
CA (1) CA2014621C (en)
DE (1) DE69031513T2 (en)

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Also Published As

Publication number Publication date
EP0403826A3 (en) 1991-10-23
JPH0334444A (en) 1991-02-14
CA2014621C (en) 1994-09-13
US5251147A (en) 1993-10-05
DE69031513D1 (en) 1997-11-06
DE69031513T2 (en) 1998-05-07
EP0403826B1 (en) 1997-10-01
EP0403826A2 (en) 1990-12-27
ATE158884T1 (en) 1997-10-15

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