CA2026224A1 - Apparatus for maintaining consistency in a multiprocess computer system using virtual caching - Google Patents
Apparatus for maintaining consistency in a multiprocess computer system using virtual cachingInfo
- Publication number
- CA2026224A1 CA2026224A1 CA2026224A CA2026224A CA2026224A1 CA 2026224 A1 CA2026224 A1 CA 2026224A1 CA 2026224 A CA2026224 A CA 2026224A CA 2026224 A CA2026224 A CA 2026224A CA 2026224 A1 CA2026224 A1 CA 2026224A1
- Authority
- CA
- Canada
- Prior art keywords
- computer system
- cache
- maintaining consistency
- processor
- main memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
- G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed
Abstract
A computer system including first and second processors, first and second virtually-addressable cache memories each associated with one such processor, a main memory, a bus joining the processors and main memory, first and second apparatus each associated with one such processor for controlling the cache associated with such processor such that information in each cache from the same physical address in main memory resides at the same offset in each cache.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US46122590A | 1990-01-05 | 1990-01-05 | |
US461,225 | 1990-01-05 |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2026224A1 true CA2026224A1 (en) | 1991-07-06 |
CA2026224C CA2026224C (en) | 1995-10-10 |
Family
ID=23831689
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002026224A Expired - Fee Related CA2026224C (en) | 1990-01-05 | 1990-09-26 | Apparatus for maintaining consistency in a multiprocess computer system using virtual caching |
Country Status (6)
Country | Link |
---|---|
US (1) | US5361340A (en) |
JP (1) | JP3493409B2 (en) |
KR (1) | KR930004430B1 (en) |
CA (1) | CA2026224C (en) |
GB (1) | GB2239724B (en) |
HK (1) | HK53994A (en) |
Families Citing this family (52)
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JPH06318174A (en) * | 1992-04-29 | 1994-11-15 | Sun Microsyst Inc | Cache memory system and method for performing cache for subset of data stored in main memory |
JPH06290076A (en) * | 1993-04-05 | 1994-10-18 | Nec Ic Microcomput Syst Ltd | Debugger device |
WO1995009397A1 (en) * | 1993-09-30 | 1995-04-06 | Apple Computer, Inc. | System for decentralized backing store control of virtual memory in a computer |
US5813046A (en) * | 1993-11-09 | 1998-09-22 | GMD--Forschungszentrum Informationstechnik GmbH | Virtually indexable cache memory supporting synonyms |
US5584007A (en) * | 1994-02-09 | 1996-12-10 | Ballard Synergy Corporation | Apparatus and method for discriminating among data to be stored in cache |
US5588129A (en) * | 1994-02-09 | 1996-12-24 | Ballard; Clinton L. | Cache for optical storage device and method for implementing same |
SE515718C2 (en) * | 1994-10-17 | 2001-10-01 | Ericsson Telefon Ab L M | Systems and methods for processing memory data and communication systems |
US6006312A (en) * | 1995-02-27 | 1999-12-21 | Sun Microsystems, Inc. | Cachability attributes of virtual addresses for optimizing performance of virtually and physically indexed caches in maintaining multiply aliased physical addresses |
US5787476A (en) * | 1995-05-05 | 1998-07-28 | Silicon Graphics, Inc. | System and method for maintaining coherency of virtual-to-physical memory translations in a multiprocessor computer |
JPH0926945A (en) * | 1995-07-10 | 1997-01-28 | Toshiba Corp | Information processor |
US5809537A (en) * | 1995-12-08 | 1998-09-15 | International Business Machines Corp. | Method and system for simultaneous processing of snoop and cache operations |
US5787445A (en) * | 1996-03-07 | 1998-07-28 | Norris Communications Corporation | Operating system including improved file management for use in devices utilizing flash memory as main memory |
US6041396A (en) * | 1996-03-14 | 2000-03-21 | Advanced Micro Devices, Inc. | Segment descriptor cache addressed by part of the physical address of the desired descriptor |
US5897664A (en) * | 1996-07-01 | 1999-04-27 | Sun Microsystems, Inc. | Multiprocessor system having mapping table in each node to map global physical addresses to local physical addresses of page copies |
US6199152B1 (en) | 1996-08-22 | 2001-03-06 | Transmeta Corporation | Translated memory protection apparatus for an advanced microprocessor |
US5991819A (en) * | 1996-12-03 | 1999-11-23 | Intel Corporation | Dual-ported memory controller which maintains cache coherency using a memory line status table |
US6069638A (en) * | 1997-06-25 | 2000-05-30 | Micron Electronics, Inc. | System for accelerated graphics port address remapping interface to main memory |
US6249853B1 (en) | 1997-06-25 | 2001-06-19 | Micron Electronics, Inc. | GART and PTES defined by configuration registers |
US6282625B1 (en) | 1997-06-25 | 2001-08-28 | Micron Electronics, Inc. | GART and PTES defined by configuration registers |
CN100392618C (en) * | 1997-08-11 | 2008-06-04 | 全斯美达有限公司 | Translated memory protection apparatus for advanced microprocessor |
CA2283560C (en) * | 1997-08-11 | 2003-12-09 | Transmeta Corporation | Translated memory protection apparatus for an advanced microprocessor |
US6304910B1 (en) * | 1997-09-24 | 2001-10-16 | Emulex Corporation | Communication processor having buffer list modifier control bits |
US6148387A (en) * | 1997-10-09 | 2000-11-14 | Phoenix Technologies, Ltd. | System and method for securely utilizing basic input and output system (BIOS) services |
US6157398A (en) | 1997-12-30 | 2000-12-05 | Micron Technology, Inc. | Method of implementing an accelerated graphics port for a multiple memory controller computer system |
US7071946B2 (en) * | 1997-12-30 | 2006-07-04 | Micron Technology, Inc. | Accelerated graphics port for a multiple memory controller computer system |
US6252612B1 (en) | 1997-12-30 | 2001-06-26 | Micron Electronics, Inc. | Accelerated graphics port for multiple memory controller computer system |
KR19990070788A (en) * | 1998-02-24 | 1999-09-15 | 윤종용 | How to Prevent Arising of Virtual Cache Memory |
US6275872B1 (en) * | 1998-10-20 | 2001-08-14 | Bellsouth Intellectual Property Corporation | Method for performing migration of uninitialized entries from a storage to a repository within an intelligent peripheral in an advanced intelligent network |
US8074055B1 (en) | 1999-01-28 | 2011-12-06 | Ati Technologies Ulc | Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code |
US7065633B1 (en) | 1999-01-28 | 2006-06-20 | Ati International Srl | System for delivering exception raised in first architecture to operating system coded in second architecture in dual architecture CPU |
US6826748B1 (en) | 1999-01-28 | 2004-11-30 | Ati International Srl | Profiling program execution into registers of a computer |
US7013456B1 (en) | 1999-01-28 | 2006-03-14 | Ati International Srl | Profiling execution of computer programs |
US8065504B2 (en) | 1999-01-28 | 2011-11-22 | Ati International Srl | Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processor |
US7111290B1 (en) | 1999-01-28 | 2006-09-19 | Ati International Srl | Profiling program execution to identify frequently-executed portions and to assist binary translation |
US6978462B1 (en) | 1999-01-28 | 2005-12-20 | Ati International Srl | Profiling execution of a sequence of events occuring during a profiled execution interval that matches time-independent selection criteria of events to be profiled |
US7941647B2 (en) | 1999-01-28 | 2011-05-10 | Ati Technologies Ulc | Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination |
US6954923B1 (en) | 1999-01-28 | 2005-10-11 | Ati International Srl | Recording classification of instructions executed by a computer |
US7275246B1 (en) | 1999-01-28 | 2007-09-25 | Ati International Srl | Executing programs for a first computer architecture on a computer of a second architecture |
US8127121B2 (en) | 1999-01-28 | 2012-02-28 | Ati Technologies Ulc | Apparatus for executing programs for a first computer architechture on a computer of a second architechture |
US6779107B1 (en) | 1999-05-28 | 2004-08-17 | Ati International Srl | Computer execution by opportunistic adaptation |
US6549959B1 (en) * | 1999-08-30 | 2003-04-15 | Ati International Srl | Detecting modification to computer memory by a DMA device |
US6469705B1 (en) * | 1999-09-21 | 2002-10-22 | Autodesk Canada Inc. | Cache addressing |
US6934832B1 (en) | 2000-01-18 | 2005-08-23 | Ati International Srl | Exception mechanism for a computer |
US6968469B1 (en) | 2000-06-16 | 2005-11-22 | Transmeta Corporation | System and method for preserving internal processor context when the processor is powered down and restoring the internal processor context when processor is restored |
US7502901B2 (en) * | 2003-03-26 | 2009-03-10 | Panasonic Corporation | Memory replacement mechanism in semiconductor device |
JP4783229B2 (en) * | 2006-07-19 | 2011-09-28 | パナソニック株式会社 | Cache memory system |
JP4821887B2 (en) | 2009-06-08 | 2011-11-24 | 日本電気株式会社 | Coherency control system, coherency control device, and coherency control method |
US8719547B2 (en) * | 2009-09-18 | 2014-05-06 | Intel Corporation | Providing hardware support for shared virtual memory between local and remote physical memory |
KR101355105B1 (en) * | 2012-01-03 | 2014-01-23 | 서울대학교산학협력단 | Shared virtual memory management apparatus for securing cache-coherent |
US9678872B2 (en) * | 2015-01-16 | 2017-06-13 | Oracle International Corporation | Memory paging for processors using physical addresses |
US11550455B2 (en) * | 2016-06-07 | 2023-01-10 | Palo Alto Research Center Incorporated | Localized visual graph filters for complex graph queries |
US10747679B1 (en) * | 2017-12-11 | 2020-08-18 | Amazon Technologies, Inc. | Indexing a memory region |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB232526A (en) * | 1924-09-22 | 1925-04-23 | Progression Sa | Improvements relating to change speed gearing |
US4136385A (en) * | 1977-03-24 | 1979-01-23 | International Business Machines Corporation | Synonym control means for multiple virtual storage systems |
US4400770A (en) * | 1980-11-10 | 1983-08-23 | International Business Machines Corporation | Cache synonym detection and handling means |
US4985829A (en) * | 1984-07-31 | 1991-01-15 | Texas Instruments Incorporated | Cache hierarchy design for use in a memory management unit |
US4785398A (en) * | 1985-12-19 | 1988-11-15 | Honeywell Bull Inc. | Virtual cache system using page level number generating CAM to access other memories for processing requests relating to a page |
US4885680A (en) * | 1986-07-25 | 1989-12-05 | International Business Machines Corporation | Method and apparatus for efficiently handling temporarily cacheable data |
US5091846A (en) * | 1986-10-03 | 1992-02-25 | Intergraph Corporation | Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency |
US5113510A (en) * | 1987-12-22 | 1992-05-12 | Thinking Machines Corporation | Method and apparatus for operating a cache memory in a multi-processor |
US4992930A (en) * | 1988-05-09 | 1991-02-12 | Bull Hn Information Systems Inc. | Synchronous cache memory system incorporating tie-breaker apparatus for maintaining cache coherency using a duplicate directory |
GB8814076D0 (en) * | 1988-06-14 | 1988-07-20 | Int Computers Ltd | Data processing system |
US5097409A (en) * | 1988-06-30 | 1992-03-17 | Wang Laboratories, Inc. | Multi-processor system with cache memories |
US4939641A (en) * | 1988-06-30 | 1990-07-03 | Wang Laboratories, Inc. | Multi-processor system with cache memories |
US5029070A (en) * | 1988-08-25 | 1991-07-02 | Edge Computer Corporation | Coherent cache structures and methods |
US5148533A (en) * | 1989-01-05 | 1992-09-15 | Bull Hn Information Systems Inc. | Apparatus and method for data group coherency in a tightly coupled data processing system with plural execution and data cache units |
US5222224A (en) * | 1989-02-03 | 1993-06-22 | Digital Equipment Corporation | Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system |
-
1990
- 1990-08-24 GB GB9018686A patent/GB2239724B/en not_active Expired - Fee Related
- 1990-09-26 CA CA002026224A patent/CA2026224C/en not_active Expired - Fee Related
- 1990-10-26 KR KR1019900017233A patent/KR930004430B1/en not_active IP Right Cessation
- 1990-11-30 JP JP33700890A patent/JP3493409B2/en not_active Expired - Fee Related
-
1993
- 1993-03-09 US US08/028,766 patent/US5361340A/en not_active Expired - Lifetime
-
1994
- 1994-05-24 HK HK53994A patent/HK53994A/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
GB9018686D0 (en) | 1990-10-10 |
CA2026224C (en) | 1995-10-10 |
JP3493409B2 (en) | 2004-02-03 |
KR930004430B1 (en) | 1993-05-27 |
KR910014814A (en) | 1991-08-31 |
GB2239724A (en) | 1991-07-10 |
HK53994A (en) | 1994-06-03 |
GB2239724B (en) | 1993-11-24 |
JPH03220644A (en) | 1991-09-27 |
US5361340A (en) | 1994-11-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
MKLA | Lapsed |