CA2026741C - Main storage memory cards having single bit set and reset functions - Google Patents
Main storage memory cards having single bit set and reset functionsInfo
- Publication number
- CA2026741C CA2026741C CA002026741A CA2026741A CA2026741C CA 2026741 C CA2026741 C CA 2026741C CA 002026741 A CA002026741 A CA 002026741A CA 2026741 A CA2026741 A CA 2026741A CA 2026741 C CA2026741 C CA 2026741C
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
Abstract
MAIN STORAGE MEMORY CARDS HAVING
SINGLE BIT SET AND RESET FUNCTIONS
ABSTRACT OF THE DISCLOSURE
A data processing network includes multiple processing devices, multiple memory cards of main storage, and a shared interface. Each of the memory cards includes memory arrays, an internal register for temporarily storing a data word read from the arrays, and logic circuitry. When one of the processing devices sends a set or reset command to one of the memory cards, the processor also sends a data mask. A data word to be modified is retrieved from a selected address in the memory arrays and latched into the internal register.
The logic circuitry applies the data mask to a data word in the internal register, to modify the data word according to the data mask, then returns the data word to the selected address in the arrays.
SINGLE BIT SET AND RESET FUNCTIONS
ABSTRACT OF THE DISCLOSURE
A data processing network includes multiple processing devices, multiple memory cards of main storage, and a shared interface. Each of the memory cards includes memory arrays, an internal register for temporarily storing a data word read from the arrays, and logic circuitry. When one of the processing devices sends a set or reset command to one of the memory cards, the processor also sends a data mask. A data word to be modified is retrieved from a selected address in the memory arrays and latched into the internal register.
The logic circuitry applies the data mask to a data word in the internal register, to modify the data word according to the data mask, then returns the data word to the selected address in the arrays.
Description
2~2~7~1 MAIN STORAGE MEMORY CA~DS HAVING
SINGLE BIT SET AND RESET FUNCTIONS
BACKGROUND OF THE INVENTION
The present invention relates to information processing systems including multiple processors linked to multiple memory cards of main storage through a shared intorace, and more particularly to a m~an~ for modifying data stored in main memory, With minlmal impact upon the lnterface.
In recent years and throughout the computer industry, the performance of information processing device~ has improved rapidly, particularly in terms of more rapid performance of data processing operations.
Data processing sy3tems increasingly employ multiple processing devices sharing a common interface for carrying out data tran~mi~sion~ between the processors and main storage which typically i~ composed of multiple memory card~. ImproVements in memory subsystem~ have not Xept pace with the improvements in processors, particularly when configuratlon~ of multlple, parallel proces~ors are con~ldered. Accordlngly, ~y~tem or network architectures have changed to compensate for a main storage which i~ relatively slow as compared to the processing devices. Cache memories and other techniques have been employed, in an attempt to uncouple the processors from the memory cards in main storage.
In connection with modifying data that resides in main storage, the traditiona~ operation involves fetching the data from memory arrays to an internal register in a processor, modifying the data bits as required within the processor, then writing the modified data back into the memory arrays. This operation involves substantial system overhead. For example, the interface to main storage must be arbitrated for and acquired twice, once for a data fetch and once for storing data back into memory. If the interface is shared by multiple processors and by multiple cards of main storage, the time consumed in waiting for access to the interface is Ro9-89-043 2 ~a2~7 4 increased. A processor, upon gaining access to a particular memory card, must wait for the card to access it~ array~ to retrieve the data to be modified.
Techniques to more efficiently modify data in a memory are known. For example, U.S. Patent No. 4,570,222 (Oguchi) discloses a data processing system with an information correcting unction including a dynamic random access memory, a changing unit, a designating unit and a controller. The changing unlt receives data rom the RAM, and a selected portion of the data i~ modiied within the changing unit, ba~ad on input rom the designating unit.
In connection with color graphics displays, U.S.
Patent No. 4,016,544 (Morita et al) discloses a memory write-in control system, including a buer memory or separately storing red, green and blue inormation for each of a multiplicity of dots. Each individual color unit receives a color de~ignating input and a mask input from a write-in control unit which is controlled by a proces~or. I the mask bit is a logical one, the content is modified, while a logical zero in the mask bit leaves the corresponding contents unchanged.
There remains, however, a need to more effectively utilize proces~ing device~, a~ well a~ a data bU~ ~oining multiple proces~ing device~ and main memory.
Therefore, it is an object of the present invention to provide a data processing system in which data in main storage is modified with substantially reduced use o an interface between main storage and multiple processors.
Another object of the invention is to transfer some of the intelligence involved in data modifying operations from the processors to the memory cards of main storage.
Another object is to increase the speed at which data modifying functions, including set and reset, are ~ performed.
- Yet another object is to provide a data processing system in which set and reset functions are performed on selected data in memory arrays, with just one access to the arrays being sufficient for these functions.
Ro9-89-043 3 2 ~ 2 ~ 7 ~1 SUMMARY OF THE INVENTION
To achieve these and other objects, there is provided a data processing system including a processing device configuration for manipulating bit-encoded data, a memory having arrays for storing bit-encoded data as data words with each data word including a plurality of bits, and an interface connected to the processing configuration and to the memory, for transmitting bit-encoded data between the processing conflguration and the memory. The proce~ing configura~ion lncl~de~ a means for genërating a command to ~electlvely modify a designated one of the data words. The processing configuration further includes means for generating addre~s data corresponding to a selected location in the data arrays where the de~ignated data word is stored.
The improvement in this system comprises a mask generating mean~ in the processing device configuration, for generating a data mask corresponding to the designated data word, and for transmitting the data mask to the memory via the interface. A data manipulating means, within the memory, selectively modifies the designated data word according to the data mask after receiving the ma~k and the command. The data manipulating means include~: an inte~mediate da~a retaining means; a latching means, responsive to the command and address data, for locating the designated word in the arrays and transferring the designated word from the selected location to the intermediate data retaining means; a means for receiving the data ma~k and applying the mask to the designated data word when the word is contained in the intermediate data retaining means, to selectively modify the data word; and a write means for transferring the designated data word to the arrays, after the word has been modified.
Preferably, the processing device configuration includes a plurality of processing devices, each adapted to manipulate bit-encoded data and to generate commands.
The memory can include a plurality of memory cards, each card with data arrays for storing bit-encoded data. The interface advantageously includes a data bus for R09-89-043 4 2 0 2 ~ ~ 41 transmission of the data mask, and a command bus for the transmission of the command and the address information.
The data bus and command bus function in parallel, each shared by all of the processing devices and all of the memory cards.
Each of the memory cards can have its own internal register and memory arrays. The internal registers cooperate to provide the intermediate data retaining means.
Each memory card further can include logic circuitry associated with its internal ragister. In re~pon~e to a ~et command, the data word to be modified and the data mask are provided as inputs to an OR logic gate, with the output of the OR gate returned to the data arrays on the card. Responsive to a reset command, the mask i8 firgt inverted, then the inverted mask and data word are provided as inputs to an AND logic gate, with the output of the AND gate returned to the data arrays.
The data words and data masks advantageously have the same predetermined number of bit~. Accordingly there i9 a one-to-one correspondence between each data word and the mask employed in modifying it, enabling rapid modification of the data in a ~ingle read/modify/write cycle, accompli~hed With relatlvely ~traightorward circuitry.
With the internal registers and modifying logic residing on the memory cards, set and reset operations are atomic on the memory cards, in the sense that these operations are handled without any interruption from other commands to the memory card. Performing these operations largely within main storage frees each processor to perform other tasks during virtually all of the time involved in set and reset operations. The number of cycles required for each operation is reduced, as well as the time during which the interface or busses between the processors and main memory are occupied, thus to achieve better system through-put. Finally, once a memory card initiates the modification, it remains dedicated to completing the set or reset function, without interference from interface traffic, array R09-89-043 5 2~S ~1 ini~ialization overhead, or asynchronous memory refresh operations.
IN THE DRAWINGS
For a further appreciation of the above and other objects and advantages, reference is made to the following detailed description of the preferred embodiment and to the drawings, in which:
Figure 1 is a schematic view of an information proce~sing system in whlch a configu~ation of multiple proce~sing device~ i~ a~ociated With main storage, including multiple memory cards, through a shared interface;
Figure 2 is a schematic view of one of the memory cards showing data modification logic;
Figure 3 ls a timing diagram of a conventional data modifying operation;
Figure 4 is a timing diagram similar to that in Figure 3, illustrating data modification according to the present invention;
Figure 5 is a representation of eight-bit data words, illu~trating the ~et function; and Figure 6 i~ ~imilar to Figure 5, and illustrates the re~et unction.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Turning now to the drawings, there is shown in Figure 1 an information processing system 16 for storing and performing selected operations upon bit-encoded data.
The system includes two processing devices, identified at 18 and 20, respectively. An arbitration link 22 joins the two processors, and is used in combination with arbitration logic residing in both processing devices to assign priority to either processor, in terms of access to the interface. It is to be understood that the configuration of processing devices in this network could consist of a sinsle processing device or multiple processing devices in which multiple arbitration links are provided for a point-to-point connection of all processing devices.
R09-89-043 2~2~741 An interface connects the processing devices with main storage, which includes multiple memory cards such as is indicated at 24, 26 and 28. Memory card 24, for example, includes memory arrays 30 for storing bit-encoded data, a buffer 32 for receiving data from the interface and for temporarily containing data for transmission to a selected one of the processing devices.
Memory card 24 also includes an internal register 34 connected to memory array~ 30. Data stored in the memory array~ 1~ loaded into internal regi~ter 34 for temporary intermediate ~torage, during which tlme the data can be modified according to instructions from one o the proces~ing device~.
Memory cards 26 and 28 are similar to memory card 24, including memory arrays 36, a buffer 38 and an internal register 40, and memory arrays 42, an internal register 44 and buffer 46, respectively. Each of these components i~ ~ub~tantially identical to and function~ in the same manner a~ its counterpart~ in the other memory card~.
The interface associating the processors and memory cards includes a data bus 48 and a command/address bus 50, each ~oined to all proce~sors and memory cards, and tran~mitting dat~ independent of and in parallel With the other bu~. Data bu~ 48 tran~mit~ what can conveniently be called working information, i,e. the information in which users of the system have the most interest.
Command/address bus 50 transmits control information, relating to commands to fetch or store particular working data, and address information which identifies the location of particular working data in the memory arrays, or the location to which such data is to be sent.
Command lines 52, one for each processor, transmit command and address information to bus 50, from which one of command lines 54 forwards the information to the appropriate memory card. Command transfers are unidirectional (from a processor to a memory card), the arrows at both ends of command lines 52 indicating that each processing device, while transmitting a command, can inform the remaining processors that the command/address bus is occupied.
Data lines 56 between the processors and bus 48, and data lines 58 between the memory cards and the data bus, accommodate transmissions of working information in both directions. The interface includes further data paths not illustrated in Figure 1, for controlling use of data bus 48, and also may include a commonly shared communication bus for ttatlsmittillcJ status information relatlng to worklng dat~. ~or a ~ur~her Qxplanation of the interface, reference ls madë ~o U.S. Pat~nt No.
5,131,085, issued July 14, 1992, entitled High Performance Shared Main Storage Interface, assigned to the assignee of the present application.
The internal registers in memory cards 24, 26 and 28 are particularly useful in modifying data stored in the respective memory arrays, without transferring data to the processing devices. Circuitry for modifying data is schematically illustrated in Fi~1re 2 for modifying a selected data bit. In this connection, it is to be appreciated that data in system 16 is transmitted and modified in the form of 8 byte data words, corresponding to the capacity of data bus 48. Thus, for any selected data word, the compl~te m~diiGAtion CirGUitry in the memory card would ln~lude ~ub~tantially ldentical logic and multiplexing or each of the remaining data bits of the word, with all bits processed in parallel.
In the figure, proces.sor 18 provides a data mask used in modifying certain data stored in the memory arrays 30 of memory card 24. A latched (as at 59~ output of the arrays is provided as one of the inputs to an AND
logic gate 60, and as an input to an OR logic gate 62.
The other input to the OR gate is the output of buffer 32. The buffer output also is provided to an inverter 64, and the inverted signal provided as the other input of AND gate 60. Outputs of the AND gate and the OR gate are provided to a multiplexer 66, the output of which is latched at 65 returns to memory arrays 30.
Thus, each of the memory cards includes circuitry for retrieving data from the data arrays and loading it R09-89-043 8 2 0 2 ~
into the internal register, receiving and applying the data mask to modify the data when in the internal register, and returning the modified data to the data arrays. A salient advantage of this approach i5 that circuitry for set and reset operations resides largely in the memory cards, rather than in the processor, for a sub~tantial reduction in the number of clock cycles required to perform these operations.
Thls advantage becomes apparent upon comparing the pri~r art approach to modi~ylng data, with a ~et or reset according to the present invention. Conventional t processor-controlled modification of data is illustrated in the timing diagram of Figure 3. A fetch command, including address information corresponding to the location of the requested data in main memory, is sent from the processor to the memory card via the command/addres~ bus during the first clock cycle.
The selected memory card begins to access its memory array~ in the second clock cycle. More particularly, access to the arrays is provided through two control lines, row address strobe (RAS) and column address strobe (CAS). The row address strobe initiates data array access by going active at the beginning o the second clock cycle, whlle the column addres~ ~trobe goas active at the beginning o the third clock cycle. In connection with Figures 3 and 4, it should be noted that the row and column address strobes are shown to go high as they go active, for consistency with the remaining lines, namely processor command, processor data and array data. This is simply a ~atter of convenience in illustration.
Actually, the row and column address strobes are "minus active", going active as the signal switches from the high to the low logic level.
In cycle four, data is read out of the arrays into the memory buffer. During the fifth clock cycle, data is transferred via the data bus to the processor, and the row and column address strobes go inactive. The processor modifies data during clock cycle six.
A store command from the processor during cycle seven is followed in the next cycle by transfer of the R~9-89-043 9 2~2~ 7~1 modified data back to the memory card, along with activation of the row address strobe. The column address strobe goes active during cycle nine and the modified data is returned to the arrays during clock cycles ten-twelve, after which the row address and column address strobes go inactive again. The "M" associated with array data in cycle twelve, refers to a modifying step which is not a set or reset, but rather an arrangement of the data into a form more suitable for ~toring in the arrays as opposed to a form suitable for tran~mission.
Figure 4 i~ a timing dlagram similar to that in Figure 3, showing data modification conducted primarily on the memory card, pursuant to a command from processing devlce 18 to modify certain data at a selected addre~s 68 within memory array 30 of memory card 24. Data bits are modified as parts of 8 byte words. For simplicity in illustration, however, data words having only 8 bits are shown in Figures 5 and 6, in connection with a set operation and a reset operation, respectively.
As seen in Figure 4, proces~or 18 send~ a command to memory card 24 via command/address bus 50. The command is either to "set" or to "re~et" a data word 70 illustrated in Figures 5 and 6. Regardles~ of whether the command was a set or reset command, the processing device provide~ a data mask 72 to mèmory card 24 over data bus 48. The row address strobe becomes active during this cycle.
Figures 5 and 6 show the same 8 bit mask 72, i.e.
with logic "ones" in the third and seventh bit positions, and logic "zeros" in the remaining bit positions. Thus, in connection with a set command the bits of data word 70 in the third and seventh positions will be set to a logical one. For a reset command, these bits will be reset to a logical zero. In both cases, the remaining bits in the data word remain unchanged.
Returning to Figure 4, the column address strobe becomes active at the beginning of the third cycle, and data is read from memory arrays 30 during cycle four. In contrast to Eigure 3, however, data is not read into R09-89-043 lo 2 Q ~ ~ 7 ~1 buffer 32, but rather. latched into internal register 34 of the memory card.
Data word 70 is modified during the fifth clock cycle. In the event that a set command was provided during the second clock cycle, the data word and mask 72 are applied as inputs to OR logic gates such as gate 62.
The output of the OR gates is the modified (in this case set) data word 74. The third and seventh bit positions have been set, i.e. are logical ones. This represents no change or the third bit po~ltion, while th~ ~eventh bit, previously is zero, becomes a one. Th~ ramaining bit po~itions remain the same as for original word 70.
In the event the command in cycle two is a reset command, mask 72 i8 inverted to form an inverted mask 76.
The inverted mask and the data word are then applied to eight AND gates such as gate 60. The output of the AND
gates is the modified (in this case reset) data word 78, in which bits in the third and seventh positions have been reset, changing the bit in the third position in data word 70 to a logical zero, while the seventh bit position remains a logical zero. The other bit positions remain the same.
The modifying operation is completed during the ~ixth cycle, where the modified word i~ writt~n rom internal register 34 back into memory arrays 30, and specifically back to selected address 68.
Thus, the present invention substantially increases the speed of set and reset operations on data in the memory arrays, cutting the number of required clock cycles nearly in half. Ef-ficiency is increased well beyond what this comparison would suggest, however, since these examples assume _hat the processors in each case required no time contending for use of the interface. In any configuration of multiple processors sharing a common interface, the processor involved must contend for use of the interface with main storage. The conventional data modification sequence (Figure 3) requires the processor to gain access to the interface twice, once for fetching data from the memory card, and once for returning modified data. Processor 18 needs access to the R09-89-043 11 2~2~7~1 interface only once, to provide the set or reset command and data mask to memory card 24.
This gives rise to another advantage, in that set and reset operations according to the invention require only half the amount of interface use, specifically one cycle to provide the set or reset command, and one cycle to provide the data mask. The conventional sequence reguires four clock cycles of interface use.
Yet another advantage arises from the faet that the memory array~ are normally inaetlve, and require a predetermined number o clock cycle~ to become eharged or ready or reading data from the arrays or writing data into them. The number o eyeles needed of eourse varies with the nature of the arrays and the eycle time, but adds to the time required for any operation involving aeeess to the arrays. The eonventional data modify sequenee reguire~ aeeess to the memory array~ first to read out data for a return to the processor, and later, after the row address and eolumn address strobes have beeome inaetive, to Write in the modified data. By eontrast, the designated data word in memory eard 24 is modified in a single read/modify/write sequence of three eonseeutive eloek eyele~, with no need to reaetivate the row address ~trobe, Which eontrols aetivation o the memory array~.
A inal advantage, again in eontrast to the eonventional sequenee, is that asynehronous events such as memory refresh do not interfere with data modify operations in the memory cards of network 16. Such events can delay the conventional data modify sequence, particularly if they occur between the fetch command and store command clock cycles. Thus, an information processing network in accordance with the present invention, in which the memory cards of main storage perform set and reset operations responsive to commands and masks from the processing devices, considerably reduces the time and interface usage required for set and reset operations.
SINGLE BIT SET AND RESET FUNCTIONS
BACKGROUND OF THE INVENTION
The present invention relates to information processing systems including multiple processors linked to multiple memory cards of main storage through a shared intorace, and more particularly to a m~an~ for modifying data stored in main memory, With minlmal impact upon the lnterface.
In recent years and throughout the computer industry, the performance of information processing device~ has improved rapidly, particularly in terms of more rapid performance of data processing operations.
Data processing sy3tems increasingly employ multiple processing devices sharing a common interface for carrying out data tran~mi~sion~ between the processors and main storage which typically i~ composed of multiple memory card~. ImproVements in memory subsystem~ have not Xept pace with the improvements in processors, particularly when configuratlon~ of multlple, parallel proces~ors are con~ldered. Accordlngly, ~y~tem or network architectures have changed to compensate for a main storage which i~ relatively slow as compared to the processing devices. Cache memories and other techniques have been employed, in an attempt to uncouple the processors from the memory cards in main storage.
In connection with modifying data that resides in main storage, the traditiona~ operation involves fetching the data from memory arrays to an internal register in a processor, modifying the data bits as required within the processor, then writing the modified data back into the memory arrays. This operation involves substantial system overhead. For example, the interface to main storage must be arbitrated for and acquired twice, once for a data fetch and once for storing data back into memory. If the interface is shared by multiple processors and by multiple cards of main storage, the time consumed in waiting for access to the interface is Ro9-89-043 2 ~a2~7 4 increased. A processor, upon gaining access to a particular memory card, must wait for the card to access it~ array~ to retrieve the data to be modified.
Techniques to more efficiently modify data in a memory are known. For example, U.S. Patent No. 4,570,222 (Oguchi) discloses a data processing system with an information correcting unction including a dynamic random access memory, a changing unit, a designating unit and a controller. The changing unlt receives data rom the RAM, and a selected portion of the data i~ modiied within the changing unit, ba~ad on input rom the designating unit.
In connection with color graphics displays, U.S.
Patent No. 4,016,544 (Morita et al) discloses a memory write-in control system, including a buer memory or separately storing red, green and blue inormation for each of a multiplicity of dots. Each individual color unit receives a color de~ignating input and a mask input from a write-in control unit which is controlled by a proces~or. I the mask bit is a logical one, the content is modified, while a logical zero in the mask bit leaves the corresponding contents unchanged.
There remains, however, a need to more effectively utilize proces~ing device~, a~ well a~ a data bU~ ~oining multiple proces~ing device~ and main memory.
Therefore, it is an object of the present invention to provide a data processing system in which data in main storage is modified with substantially reduced use o an interface between main storage and multiple processors.
Another object of the invention is to transfer some of the intelligence involved in data modifying operations from the processors to the memory cards of main storage.
Another object is to increase the speed at which data modifying functions, including set and reset, are ~ performed.
- Yet another object is to provide a data processing system in which set and reset functions are performed on selected data in memory arrays, with just one access to the arrays being sufficient for these functions.
Ro9-89-043 3 2 ~ 2 ~ 7 ~1 SUMMARY OF THE INVENTION
To achieve these and other objects, there is provided a data processing system including a processing device configuration for manipulating bit-encoded data, a memory having arrays for storing bit-encoded data as data words with each data word including a plurality of bits, and an interface connected to the processing configuration and to the memory, for transmitting bit-encoded data between the processing conflguration and the memory. The proce~ing configura~ion lncl~de~ a means for genërating a command to ~electlvely modify a designated one of the data words. The processing configuration further includes means for generating addre~s data corresponding to a selected location in the data arrays where the de~ignated data word is stored.
The improvement in this system comprises a mask generating mean~ in the processing device configuration, for generating a data mask corresponding to the designated data word, and for transmitting the data mask to the memory via the interface. A data manipulating means, within the memory, selectively modifies the designated data word according to the data mask after receiving the ma~k and the command. The data manipulating means include~: an inte~mediate da~a retaining means; a latching means, responsive to the command and address data, for locating the designated word in the arrays and transferring the designated word from the selected location to the intermediate data retaining means; a means for receiving the data ma~k and applying the mask to the designated data word when the word is contained in the intermediate data retaining means, to selectively modify the data word; and a write means for transferring the designated data word to the arrays, after the word has been modified.
Preferably, the processing device configuration includes a plurality of processing devices, each adapted to manipulate bit-encoded data and to generate commands.
The memory can include a plurality of memory cards, each card with data arrays for storing bit-encoded data. The interface advantageously includes a data bus for R09-89-043 4 2 0 2 ~ ~ 41 transmission of the data mask, and a command bus for the transmission of the command and the address information.
The data bus and command bus function in parallel, each shared by all of the processing devices and all of the memory cards.
Each of the memory cards can have its own internal register and memory arrays. The internal registers cooperate to provide the intermediate data retaining means.
Each memory card further can include logic circuitry associated with its internal ragister. In re~pon~e to a ~et command, the data word to be modified and the data mask are provided as inputs to an OR logic gate, with the output of the OR gate returned to the data arrays on the card. Responsive to a reset command, the mask i8 firgt inverted, then the inverted mask and data word are provided as inputs to an AND logic gate, with the output of the AND gate returned to the data arrays.
The data words and data masks advantageously have the same predetermined number of bit~. Accordingly there i9 a one-to-one correspondence between each data word and the mask employed in modifying it, enabling rapid modification of the data in a ~ingle read/modify/write cycle, accompli~hed With relatlvely ~traightorward circuitry.
With the internal registers and modifying logic residing on the memory cards, set and reset operations are atomic on the memory cards, in the sense that these operations are handled without any interruption from other commands to the memory card. Performing these operations largely within main storage frees each processor to perform other tasks during virtually all of the time involved in set and reset operations. The number of cycles required for each operation is reduced, as well as the time during which the interface or busses between the processors and main memory are occupied, thus to achieve better system through-put. Finally, once a memory card initiates the modification, it remains dedicated to completing the set or reset function, without interference from interface traffic, array R09-89-043 5 2~S ~1 ini~ialization overhead, or asynchronous memory refresh operations.
IN THE DRAWINGS
For a further appreciation of the above and other objects and advantages, reference is made to the following detailed description of the preferred embodiment and to the drawings, in which:
Figure 1 is a schematic view of an information proce~sing system in whlch a configu~ation of multiple proce~sing device~ i~ a~ociated With main storage, including multiple memory cards, through a shared interface;
Figure 2 is a schematic view of one of the memory cards showing data modification logic;
Figure 3 ls a timing diagram of a conventional data modifying operation;
Figure 4 is a timing diagram similar to that in Figure 3, illustrating data modification according to the present invention;
Figure 5 is a representation of eight-bit data words, illu~trating the ~et function; and Figure 6 i~ ~imilar to Figure 5, and illustrates the re~et unction.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Turning now to the drawings, there is shown in Figure 1 an information processing system 16 for storing and performing selected operations upon bit-encoded data.
The system includes two processing devices, identified at 18 and 20, respectively. An arbitration link 22 joins the two processors, and is used in combination with arbitration logic residing in both processing devices to assign priority to either processor, in terms of access to the interface. It is to be understood that the configuration of processing devices in this network could consist of a sinsle processing device or multiple processing devices in which multiple arbitration links are provided for a point-to-point connection of all processing devices.
R09-89-043 2~2~741 An interface connects the processing devices with main storage, which includes multiple memory cards such as is indicated at 24, 26 and 28. Memory card 24, for example, includes memory arrays 30 for storing bit-encoded data, a buffer 32 for receiving data from the interface and for temporarily containing data for transmission to a selected one of the processing devices.
Memory card 24 also includes an internal register 34 connected to memory array~ 30. Data stored in the memory array~ 1~ loaded into internal regi~ter 34 for temporary intermediate ~torage, during which tlme the data can be modified according to instructions from one o the proces~ing device~.
Memory cards 26 and 28 are similar to memory card 24, including memory arrays 36, a buffer 38 and an internal register 40, and memory arrays 42, an internal register 44 and buffer 46, respectively. Each of these components i~ ~ub~tantially identical to and function~ in the same manner a~ its counterpart~ in the other memory card~.
The interface associating the processors and memory cards includes a data bus 48 and a command/address bus 50, each ~oined to all proce~sors and memory cards, and tran~mitting dat~ independent of and in parallel With the other bu~. Data bu~ 48 tran~mit~ what can conveniently be called working information, i,e. the information in which users of the system have the most interest.
Command/address bus 50 transmits control information, relating to commands to fetch or store particular working data, and address information which identifies the location of particular working data in the memory arrays, or the location to which such data is to be sent.
Command lines 52, one for each processor, transmit command and address information to bus 50, from which one of command lines 54 forwards the information to the appropriate memory card. Command transfers are unidirectional (from a processor to a memory card), the arrows at both ends of command lines 52 indicating that each processing device, while transmitting a command, can inform the remaining processors that the command/address bus is occupied.
Data lines 56 between the processors and bus 48, and data lines 58 between the memory cards and the data bus, accommodate transmissions of working information in both directions. The interface includes further data paths not illustrated in Figure 1, for controlling use of data bus 48, and also may include a commonly shared communication bus for ttatlsmittillcJ status information relatlng to worklng dat~. ~or a ~ur~her Qxplanation of the interface, reference ls madë ~o U.S. Pat~nt No.
5,131,085, issued July 14, 1992, entitled High Performance Shared Main Storage Interface, assigned to the assignee of the present application.
The internal registers in memory cards 24, 26 and 28 are particularly useful in modifying data stored in the respective memory arrays, without transferring data to the processing devices. Circuitry for modifying data is schematically illustrated in Fi~1re 2 for modifying a selected data bit. In this connection, it is to be appreciated that data in system 16 is transmitted and modified in the form of 8 byte data words, corresponding to the capacity of data bus 48. Thus, for any selected data word, the compl~te m~diiGAtion CirGUitry in the memory card would ln~lude ~ub~tantially ldentical logic and multiplexing or each of the remaining data bits of the word, with all bits processed in parallel.
In the figure, proces.sor 18 provides a data mask used in modifying certain data stored in the memory arrays 30 of memory card 24. A latched (as at 59~ output of the arrays is provided as one of the inputs to an AND
logic gate 60, and as an input to an OR logic gate 62.
The other input to the OR gate is the output of buffer 32. The buffer output also is provided to an inverter 64, and the inverted signal provided as the other input of AND gate 60. Outputs of the AND gate and the OR gate are provided to a multiplexer 66, the output of which is latched at 65 returns to memory arrays 30.
Thus, each of the memory cards includes circuitry for retrieving data from the data arrays and loading it R09-89-043 8 2 0 2 ~
into the internal register, receiving and applying the data mask to modify the data when in the internal register, and returning the modified data to the data arrays. A salient advantage of this approach i5 that circuitry for set and reset operations resides largely in the memory cards, rather than in the processor, for a sub~tantial reduction in the number of clock cycles required to perform these operations.
Thls advantage becomes apparent upon comparing the pri~r art approach to modi~ylng data, with a ~et or reset according to the present invention. Conventional t processor-controlled modification of data is illustrated in the timing diagram of Figure 3. A fetch command, including address information corresponding to the location of the requested data in main memory, is sent from the processor to the memory card via the command/addres~ bus during the first clock cycle.
The selected memory card begins to access its memory array~ in the second clock cycle. More particularly, access to the arrays is provided through two control lines, row address strobe (RAS) and column address strobe (CAS). The row address strobe initiates data array access by going active at the beginning o the second clock cycle, whlle the column addres~ ~trobe goas active at the beginning o the third clock cycle. In connection with Figures 3 and 4, it should be noted that the row and column address strobes are shown to go high as they go active, for consistency with the remaining lines, namely processor command, processor data and array data. This is simply a ~atter of convenience in illustration.
Actually, the row and column address strobes are "minus active", going active as the signal switches from the high to the low logic level.
In cycle four, data is read out of the arrays into the memory buffer. During the fifth clock cycle, data is transferred via the data bus to the processor, and the row and column address strobes go inactive. The processor modifies data during clock cycle six.
A store command from the processor during cycle seven is followed in the next cycle by transfer of the R~9-89-043 9 2~2~ 7~1 modified data back to the memory card, along with activation of the row address strobe. The column address strobe goes active during cycle nine and the modified data is returned to the arrays during clock cycles ten-twelve, after which the row address and column address strobes go inactive again. The "M" associated with array data in cycle twelve, refers to a modifying step which is not a set or reset, but rather an arrangement of the data into a form more suitable for ~toring in the arrays as opposed to a form suitable for tran~mission.
Figure 4 i~ a timing dlagram similar to that in Figure 3, showing data modification conducted primarily on the memory card, pursuant to a command from processing devlce 18 to modify certain data at a selected addre~s 68 within memory array 30 of memory card 24. Data bits are modified as parts of 8 byte words. For simplicity in illustration, however, data words having only 8 bits are shown in Figures 5 and 6, in connection with a set operation and a reset operation, respectively.
As seen in Figure 4, proces~or 18 send~ a command to memory card 24 via command/address bus 50. The command is either to "set" or to "re~et" a data word 70 illustrated in Figures 5 and 6. Regardles~ of whether the command was a set or reset command, the processing device provide~ a data mask 72 to mèmory card 24 over data bus 48. The row address strobe becomes active during this cycle.
Figures 5 and 6 show the same 8 bit mask 72, i.e.
with logic "ones" in the third and seventh bit positions, and logic "zeros" in the remaining bit positions. Thus, in connection with a set command the bits of data word 70 in the third and seventh positions will be set to a logical one. For a reset command, these bits will be reset to a logical zero. In both cases, the remaining bits in the data word remain unchanged.
Returning to Figure 4, the column address strobe becomes active at the beginning of the third cycle, and data is read from memory arrays 30 during cycle four. In contrast to Eigure 3, however, data is not read into R09-89-043 lo 2 Q ~ ~ 7 ~1 buffer 32, but rather. latched into internal register 34 of the memory card.
Data word 70 is modified during the fifth clock cycle. In the event that a set command was provided during the second clock cycle, the data word and mask 72 are applied as inputs to OR logic gates such as gate 62.
The output of the OR gates is the modified (in this case set) data word 74. The third and seventh bit positions have been set, i.e. are logical ones. This represents no change or the third bit po~ltion, while th~ ~eventh bit, previously is zero, becomes a one. Th~ ramaining bit po~itions remain the same as for original word 70.
In the event the command in cycle two is a reset command, mask 72 i8 inverted to form an inverted mask 76.
The inverted mask and the data word are then applied to eight AND gates such as gate 60. The output of the AND
gates is the modified (in this case reset) data word 78, in which bits in the third and seventh positions have been reset, changing the bit in the third position in data word 70 to a logical zero, while the seventh bit position remains a logical zero. The other bit positions remain the same.
The modifying operation is completed during the ~ixth cycle, where the modified word i~ writt~n rom internal register 34 back into memory arrays 30, and specifically back to selected address 68.
Thus, the present invention substantially increases the speed of set and reset operations on data in the memory arrays, cutting the number of required clock cycles nearly in half. Ef-ficiency is increased well beyond what this comparison would suggest, however, since these examples assume _hat the processors in each case required no time contending for use of the interface. In any configuration of multiple processors sharing a common interface, the processor involved must contend for use of the interface with main storage. The conventional data modification sequence (Figure 3) requires the processor to gain access to the interface twice, once for fetching data from the memory card, and once for returning modified data. Processor 18 needs access to the R09-89-043 11 2~2~7~1 interface only once, to provide the set or reset command and data mask to memory card 24.
This gives rise to another advantage, in that set and reset operations according to the invention require only half the amount of interface use, specifically one cycle to provide the set or reset command, and one cycle to provide the data mask. The conventional sequence reguires four clock cycles of interface use.
Yet another advantage arises from the faet that the memory array~ are normally inaetlve, and require a predetermined number o clock cycle~ to become eharged or ready or reading data from the arrays or writing data into them. The number o eyeles needed of eourse varies with the nature of the arrays and the eycle time, but adds to the time required for any operation involving aeeess to the arrays. The eonventional data modify sequenee reguire~ aeeess to the memory array~ first to read out data for a return to the processor, and later, after the row address and eolumn address strobes have beeome inaetive, to Write in the modified data. By eontrast, the designated data word in memory eard 24 is modified in a single read/modify/write sequence of three eonseeutive eloek eyele~, with no need to reaetivate the row address ~trobe, Which eontrols aetivation o the memory array~.
A inal advantage, again in eontrast to the eonventional sequenee, is that asynehronous events such as memory refresh do not interfere with data modify operations in the memory cards of network 16. Such events can delay the conventional data modify sequence, particularly if they occur between the fetch command and store command clock cycles. Thus, an information processing network in accordance with the present invention, in which the memory cards of main storage perform set and reset operations responsive to commands and masks from the processing devices, considerably reduces the time and interface usage required for set and reset operations.
Claims (15)
1. In a data processing system including a processing device configuration for manipulating bit-encoded data, a memory having arrays for storing bit-encoded data as a plurality of data words, each data word including a plurality of bits, and an interface connected to the processing configuration and to the memory, for transmitting bit-encoded data between the processing configuration and the memory; wherein the processing configuration includes a means for generating a command to selectively modify a designated one of the data words and for generating address data corresponding to a selected location in the data arrays where the designated data word is stored; the improvement comprising:
a mask generating means, in the processing device configuration, for generating a data mask corresponding to the designated data word, and for transmitting the mask to the memory via the interface;
and a data manipulating means, within the memory, for selectively modifying the designated data word according to the mask after receiving the mask and the command, said data manipulating means including:
an intermediate data retaining means;
a latching means, responsive to said command and address data, for locating the designated word in the arrays and transferring the designated word from the selected location to the intermediate data retaining means;
a means for receiving the mask and applying the mask to the designated data word when said word is contained in the intermediate data retaining means, to selectively modify the data word; and a write means for transferring the designated data word to the arrays, after the word has been modified.
a mask generating means, in the processing device configuration, for generating a data mask corresponding to the designated data word, and for transmitting the mask to the memory via the interface;
and a data manipulating means, within the memory, for selectively modifying the designated data word according to the mask after receiving the mask and the command, said data manipulating means including:
an intermediate data retaining means;
a latching means, responsive to said command and address data, for locating the designated word in the arrays and transferring the designated word from the selected location to the intermediate data retaining means;
a means for receiving the mask and applying the mask to the designated data word when said word is contained in the intermediate data retaining means, to selectively modify the data word; and a write means for transferring the designated data word to the arrays, after the word has been modified.
2. The data processing system of Claim 1 wherein:
each of said data words has the same predetermined number of bits.
each of said data words has the same predetermined number of bits.
3. The system of Claim 2 wherein:
said write means returns the modified data word to said selected location.
said write means returns the modified data word to said selected location.
4. The system of Claim 3 wherein:
said processing configuration includes a plurality of processing devices, each said processing device including means for manipulating bit-encoded data and for generating commands, and wherein said memory includes a plurality of memory cards, each of the cards having data arrays for storing bit-encoded data.
said processing configuration includes a plurality of processing devices, each said processing device including means for manipulating bit-encoded data and for generating commands, and wherein said memory includes a plurality of memory cards, each of the cards having data arrays for storing bit-encoded data.
5. The system of Claim 4 wherein:
said interface includes a data bus for transmission of the mask, and a command bus for transmission of the command and the address information, said data bus and command bus being shared in common by all of the processing devices and all of the memory cards.
said interface includes a data bus for transmission of the mask, and a command bus for transmission of the command and the address information, said data bus and command bus being shared in common by all of the processing devices and all of the memory cards.
6. The system of Claim 5 wherein:
each of the memory cards has an internal register, said internal registers cooperating to provide the intermediate data retaining means.
each of the memory cards has an internal register, said internal registers cooperating to provide the intermediate data retaining means.
7. The system of Claim 2 wherein:
each of the masks has said predetermined number of bits.
each of the masks has said predetermined number of bits.
8. The system of Claim 7 wherein:
each of said commands is one of two alternative types of commands, including a set command and a reset command.
each of said commands is one of two alternative types of commands, including a set command and a reset command.
9. The system of Claim 8 wherein:
said memory includes a plurality of memory cards, each memory card having its own ones of said data arrays for storing bit-encoded data and its own internal register, said internal registers cooperating to provide the intermediate data retaining means; and wherein each said card further includes logic circuitry associated with its internal register, for providing the data word to be modified and the mask as inputs to an OR logic gate to carry out said set command, and alternatively for inverting the mask and providing the data word to be modified and the inverted mask as inputs to an AND logic gate.
said memory includes a plurality of memory cards, each memory card having its own ones of said data arrays for storing bit-encoded data and its own internal register, said internal registers cooperating to provide the intermediate data retaining means; and wherein each said card further includes logic circuitry associated with its internal register, for providing the data word to be modified and the mask as inputs to an OR logic gate to carry out said set command, and alternatively for inverting the mask and providing the data word to be modified and the inverted mask as inputs to an AND logic gate.
10. In a data processing system including a configuration of processors for manipulating bit-encoded data, a memory including a main storage means for storing bit-encoded data as pluralities of data words in which each data word includes a plurality of bits, and an interface connected to the processing configuration and the memory for transmitting the bit-encoded data between the configuration and memory;
a process for selectively modifying data stored in the main storage means, including the steps of:
using the processor configuration to generate a modify command for modifying bit-encoded data, address information corresponding to a selected location in the main storage means to designate a certain data word stored at the selected location as the data word to be modified, and a data mask identifying at least one bit in the designated data word to be modified;
transmitting the modify command, address information and data mask to the memory over the interface;
responsive to said command and address information, locating the selected data word and transferring the designated word from the main storage means to an intermediate data retaining means in the memory; and applying the data mask to the designated data word contained in the retaining means, to selectively modify the designated data word according to the content of the data mask.
a process for selectively modifying data stored in the main storage means, including the steps of:
using the processor configuration to generate a modify command for modifying bit-encoded data, address information corresponding to a selected location in the main storage means to designate a certain data word stored at the selected location as the data word to be modified, and a data mask identifying at least one bit in the designated data word to be modified;
transmitting the modify command, address information and data mask to the memory over the interface;
responsive to said command and address information, locating the selected data word and transferring the designated word from the main storage means to an intermediate data retaining means in the memory; and applying the data mask to the designated data word contained in the retaining means, to selectively modify the designated data word according to the content of the data mask.
11. The process of Claim 10 including the further step of:
returning the modified designated data word to the main storage means.
returning the modified designated data word to the main storage means.
12. The process of Claim 11 wherein:
said steps of transferring the designated data word to the intermediate retaining means, applying the mask to the designated data word, and transferring the modified designated word to the main storage means, are all performed during a single read/modify/write cycle.
said steps of transferring the designated data word to the intermediate retaining means, applying the mask to the designated data word, and transferring the modified designated word to the main storage means, are all performed during a single read/modify/write cycle.
13. The process of Claim 11 wherein:
said step of transferring the modified designated data word to the main storage means includes transferring the modified designated data word to the selected location.
said step of transferring the modified designated data word to the main storage means includes transferring the modified designated data word to the selected location.
14. The process of Claim 11 wherein:
said commands are of two kinds including set commands and reset commands; and said step of applying the mask to the designated data word includes the step of providing the designated word and the mask as inputs to an OR logic gate, whenever the command is a set command.
said commands are of two kinds including set commands and reset commands; and said step of applying the mask to the designated data word includes the step of providing the designated word and the mask as inputs to an OR logic gate, whenever the command is a set command.
15. The process of Claim 14 wherein:
said step of applying the mask further includes the steps of inverting the mask to provide an inverse mask, and providing the inverse mask and the designated data word to an AND logic gate, whenever the command is a reset command.
said step of applying the mask further includes the steps of inverting the mask to provide an inverse mask, and providing the inverse mask and the designated data word to an AND logic gate, whenever the command is a reset command.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US450,182 | 1989-12-13 | ||
| US07/450,182 US5167029A (en) | 1989-12-13 | 1989-12-13 | Data processing system and associated process using memory cards having data modify functions utilizing a data mask and an internal register |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2026741A1 CA2026741A1 (en) | 1991-06-14 |
| CA2026741C true CA2026741C (en) | 1994-02-01 |
Family
ID=23787110
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002026741A Expired - Fee Related CA2026741C (en) | 1989-12-13 | 1990-10-02 | Main storage memory cards having single bit set and reset functions |
Country Status (10)
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| US (1) | US5167029A (en) |
| EP (1) | EP0437160B1 (en) |
| JP (1) | JPH03189843A (en) |
| KR (1) | KR940002903B1 (en) |
| CN (1) | CN1017837B (en) |
| AU (1) | AU636680B2 (en) |
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| CA (1) | CA2026741C (en) |
| DE (1) | DE69033416T2 (en) |
| ES (1) | ES2140376T3 (en) |
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| IT1247640B (en) * | 1990-04-26 | 1994-12-28 | St Microelectronics Srl | BOOLEAN OPERATIONS BETWEEN TWO ANY BITS OF TWO ANY REGISTERS |
| US5434970A (en) * | 1991-02-14 | 1995-07-18 | Cray Research, Inc. | System for distributed multiprocessor communication |
| AU7049694A (en) * | 1993-06-14 | 1995-01-03 | Rambus Inc. | Method and apparatus for writing to memory components |
| WO1995010804A1 (en) * | 1993-10-12 | 1995-04-20 | Wang Laboratories, Inc. | Hardware assisted modify count instruction |
| US5499376A (en) * | 1993-12-06 | 1996-03-12 | Cpu Technology, Inc. | High speed mask and logical combination operations for parallel processor units |
| US5692154A (en) * | 1993-12-20 | 1997-11-25 | Compaq Computer Corporation | Circuit for masking a dirty status indication provided by a cache dirty memory under certain conditions so that a cache memory controller properly controls a cache tag memory |
| US6532180B2 (en) | 2001-06-20 | 2003-03-11 | Micron Technology, Inc. | Write data masking for higher speed DRAMs |
| US7016999B1 (en) * | 2002-02-05 | 2006-03-21 | Adaptec, Inc. | Hardware circuit and method for automatically configuring on-the-fly a sub-unit in a SCSI message |
| US6671212B2 (en) * | 2002-02-08 | 2003-12-30 | Ati Technologies Inc. | Method and apparatus for data inversion in memory device |
| US8510569B2 (en) * | 2009-12-16 | 2013-08-13 | Intel Corporation | Providing integrity verification and attestation in a hidden execution environment |
| US8850137B2 (en) * | 2010-10-11 | 2014-09-30 | Cisco Technology, Inc. | Memory subsystem for counter-based and other applications |
| US11537319B2 (en) * | 2019-12-11 | 2022-12-27 | Advanced Micro Devices, Inc. | Content addressable memory with sub-field minimum and maximum clamping |
| CN114579189B (en) * | 2022-05-05 | 2022-09-09 | 深圳云豹智能有限公司 | Single-core and multi-core register data access method, processor and system |
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| JPS559742B2 (en) * | 1974-06-20 | 1980-03-12 | ||
| JPS5671154A (en) * | 1979-11-15 | 1981-06-13 | Nec Corp | Information processing device |
| US4363093A (en) * | 1980-03-10 | 1982-12-07 | International Business Machines Corporation | Processor intercommunication system |
| US4412286A (en) * | 1980-09-25 | 1983-10-25 | Dowd Brendan O | Tightly coupled multiple instruction multiple data computer system |
| US4520439A (en) * | 1981-01-05 | 1985-05-28 | Sperry Corporation | Variable field partial write data merge |
| JPS5960658A (en) * | 1982-09-30 | 1984-04-06 | Fujitsu Ltd | Semiconductor storage device provided with logical function |
| JPS59188764A (en) * | 1983-04-11 | 1984-10-26 | Hitachi Ltd | Memory device |
| US4569016A (en) * | 1983-06-30 | 1986-02-04 | International Business Machines Corporation | Mechanism for implementing one machine cycle executable mask and rotate instructions in a primitive instruction set computing system |
| DE3467549D1 (en) * | 1984-02-06 | 1987-12-23 | Boeing Co | Counterbalanced hinge assembly |
| JPS60189043A (en) * | 1984-03-07 | 1985-09-26 | Fuji Electric Co Ltd | Processor |
| US4663728A (en) * | 1984-06-20 | 1987-05-05 | Weatherford James R | Read/modify/write circuit for computer memory operation |
| JPS61104391A (en) * | 1984-10-23 | 1986-05-22 | Fujitsu Ltd | Semiconductor storage device |
| US4712190A (en) * | 1985-01-25 | 1987-12-08 | Digital Equipment Corporation | Self-timed random access memory chip |
-
1989
- 1989-12-13 US US07/450,182 patent/US5167029A/en not_active Expired - Fee Related
-
1990
- 1990-10-02 CA CA002026741A patent/CA2026741C/en not_active Expired - Fee Related
- 1990-10-31 EP EP90480174A patent/EP0437160B1/en not_active Expired - Lifetime
- 1990-10-31 ES ES90480174T patent/ES2140376T3/en not_active Expired - Lifetime
- 1990-10-31 DE DE69033416T patent/DE69033416T2/en not_active Expired - Fee Related
- 1990-11-07 JP JP2299989A patent/JPH03189843A/en active Pending
- 1990-11-13 AU AU66553/90A patent/AU636680B2/en not_active Ceased
- 1990-11-28 BR BR909006026A patent/BR9006026A/en not_active Application Discontinuation
- 1990-12-07 KR KR9020065A patent/KR940002903B1/en not_active IP Right Cessation
- 1990-12-11 CN CN90109923A patent/CN1017837B/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE69033416D1 (en) | 2000-02-10 |
| CN1017837B (en) | 1992-08-12 |
| CN1052562A (en) | 1991-06-26 |
| DE69033416T2 (en) | 2000-07-06 |
| JPH03189843A (en) | 1991-08-19 |
| AU6655390A (en) | 1991-06-20 |
| CA2026741A1 (en) | 1991-06-14 |
| AU636680B2 (en) | 1993-05-06 |
| EP0437160B1 (en) | 2000-01-05 |
| EP0437160A3 (en) | 1993-01-13 |
| KR940002903B1 (en) | 1994-04-07 |
| US5167029A (en) | 1992-11-24 |
| EP0437160A2 (en) | 1991-07-17 |
| BR9006026A (en) | 1991-09-24 |
| ES2140376T3 (en) | 2000-03-01 |
| KR910012955A (en) | 1991-08-08 |
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