CA2034703A1 - Substrate for packaging a semiconductor device - Google Patents

Substrate for packaging a semiconductor device

Info

Publication number
CA2034703A1
CA2034703A1 CA002034703A CA2034703A CA2034703A1 CA 2034703 A1 CA2034703 A1 CA 2034703A1 CA 002034703 A CA002034703 A CA 002034703A CA 2034703 A CA2034703 A CA 2034703A CA 2034703 A1 CA2034703 A1 CA 2034703A1
Authority
CA
Canada
Prior art keywords
semiconductor device
packaging
substrate
bump
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002034703A
Other languages
French (fr)
Inventor
Masanori Nishiguchi
Atsushi Miki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Masanori Nishiguchi
Atsushi Miki
Sumitomo Electric Industries, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2013417A external-priority patent/JPH03218039A/en
Priority claimed from JP2013412A external-priority patent/JPH03218034A/en
Priority claimed from JP2013413A external-priority patent/JPH03218035A/en
Application filed by Masanori Nishiguchi, Atsushi Miki, Sumitomo Electric Industries, Ltd. filed Critical Masanori Nishiguchi
Publication of CA2034703A1 publication Critical patent/CA2034703A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8012—Aligning
    • H01L2224/80136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/80138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8014—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01061—Promethium [Pm]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0284—Details of three-dimensional rigid printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49139—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/53—Means to assemble or disassemble
    • Y10T29/5313—Means to assemble electrical device
    • Y10T29/53174—Means to fasten electrical component to wiring board, base, or substrate
    • Y10T29/53178—Chip component

Abstract

Abstract of the Disclosure A substrate for packaging a semiconductor device having a bump thereon according to the present invention is characterized by that the substrate has an electrode terminal to which the bump is to be connected, and a recess for receiving at least a top of the bump is formed in the electrode terminal.

Description

s ~

2034~03 1 Title of the Invention SUBSTRATE FOR PACKAGING A SEMICONDUCTOR DEVICE

Back~round of the Invention (Field of the Invention) The present invention relates to a substrate for packaging a semiconductor device such as an IC chip and packaging method.
(Related Background Art~
In packaging a semiconductor device such as an IC, it has been practiced to form a convex bump on an electrode pad o~ the semiconductor device and directly connect the bump to an electrode terminal formed on the substrate.
In the past, the electrode terminal on the substrate has been formed flat. Thus, if the bump on the semiconductor device is not exactly positioned at the material will swell out to a periphery o~ the electrode terminal and may shorten the adjacent electrode terminals.
Further, the higher the interaction density o~ the semiconductor device is, the smaller are the size and pitch o~ the electrode terminals formed on the substrate. As a result, as the integration density goes higher, it is necessary to more precisely position the bump to the electrode terminal.
However, such a high precision positioning requires 2034'^~03 1 a longer time, and the packaging time increases and a high precision and expensive positioning machine is required. As a result, the packaging cost increases.

Summarv of the Invention It is an object of the present invention to shorten the time required $or packaging and reduce the packaging cost.
In order to achieve the above object, in the substrate ~or packaging the semiconductor device of the present invention, a recess ~or receiving at least a top of a bump on the semiconductor device is ~ormed in an electrode terminal on the substrate.
And in the substrate for packaging the semiconductor device of the present invention, a recess for receiving at least a top o~ a bump on the semiconductor device is ~ormed on the surface of the substrate in such a manner that a depth o~ the recess gradually increases as it goes from a periphery to a center, and an electrode terminal to which the bump is to be connected is formed at the center of the recess.
By merely pushing the semiconductor device to the substrate a~ter the coarse positioning, the bump on the semiconductor device can be precisely positioned to -the electrode terminal on the substrate.
Further, in the method ~or packaging the semiconductor device o~ the present invention, some of 203A~03 1 bump electrodes on a semiconductor device are formed higher than the remaining bump electrodes, recesses ~or receiving tops of the some o~ the bump electrodes are formed on a packaging substrate corresponding to the some of the bump electrodes, inserting the tops of the some of the bump electrodes into the recesses to position the semiconductor device to the packaging substrate, and the semiconductor device is packaged to the packaging substrate.
By merely lightly pushing the semiconductor device to the packaging substrate after coarse positioning to assure that the tops of the some of the bump electrodes do not swell out of the recesses formed in the some of the electrode terminals, the bump electrodes on the semiconductor device can be highly precisely positioned to the electrode terminals on the packaging substrate.
Since the height of the some of the bump electrodes which contribute to the positioning iæ higher than that of the remaining bump electrodes, the number of bump electrodes and the number of electrode terminals which contact to each other before the positioning is completed are reduced.
The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way o~ illustration only, and thus are not to be considered as limiting the present invention.

203~703 1 Further scope of applicability o~ the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and speci~ic examples, while indicating preferred embodiments o~ the invention, are given by way o~ illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

Brief DescriPtion of the Drawin~s Fig. lA and lB show a process for connection of a semiconductor device to a packaging substrate according to the ~irst embodiment of the present invention;
Fig. 2 shows a semiconductor device having coarsely positioned to an electrode terminal o~ a substrate according to the ~irst embodiment o~ the present invention ~or packaging the semiconductor device in cross section on the perpendicular direction to the substrate sur~ace;
Fig. 3 shows a structure according to the first embodiment a~ter the packaging in cross section on the perpendicular direction to the substrate surface;
Fig. 4 shows a semiconductor device having coarsely positioned to an electrode terminal of a substrate according to the second embodiment for packaging the semiconductor device in cross section on the ~03~03 1 perpendicular direction to the substrate surface;
Fig. 5 shows a structure according to the second embodiment after the packaging in cross section on the perpendicular direction to the substrate surface;
Fig. 6 shows a semiconductor device having coarsely positioned to electrode terminals of a substrate according to the third embodiment for packaging the semiconductor device in cross section on the perpendicular direction to the substrate surface;
Fig. 7 shows a structure according to the third embodiment after the packaging in cross section on the perpendicular direction to the substrate surface; and Fig. 8 shows an arrangement of bump electrodes in the semiconductor device which can be applied for any of above embodiments.

Description of the Preferred Embodiment The first embodiment of the present invention is now described with reference to Figs. 1 to 3.
As shown in Fig. lA, a plurality of bumps 2 are formed on a semiconductor device 1 to project from the surface thereof.
On the other hand, a plurality of electrode terminals 5 corresponding to the bumps 2 on the semiconductor devices 1 are formed on the substrate 3 to which the semiconductor device 1 is to be packaged (Fig.
lA). The electrode terminal 5 may, for example, be ;~03~703 1 formed in the following manner. First, a recess is formed at an area of the substrate 3 at which the electrode terminal 6 is to be formed. The recess is large enough to receive at least the top (bottom in the drawing) of the bump 2 formed on the semiconductor device 1. The recess is selectively plated to form the electrode terminal 5. The electrode terminal 5 thus formed has the recess 4 for receiving at least the top of the bump 2 on the surface thereof (See Fig. 2 and 3).
It is preferable that a center of the electrode terminal 5 coincides to a deepest (lowest) position of the recess 4.
When the semiconductor device 1 is to be packaged to the substrate 3 thus formed, the bump 2 on the semiconductor device 1 is positioned to the electrode terminal 5 on the substrate by a positioning machine (not shown). This positioning may be coarse to assure that a portion of the bump 2 abuts the metal layer 5 as shown in Fig. 2.
Because if the top of the bump 2 is positioned within a range of the recess 4 of the electrode terminal 5, the bump 2 is guided along the surface of the recess 4 of the electrode terminal 5 as shown in Fig. 3 by lightly pushing the semiconductor device 1 to the substrate 3 after the positioning so that the bump 2 is automatically moved to the center of the electrode terminal 5 and precisely positioned to the electrode ~(~3~703 1 terminal 5. After such precise positioning, the substrate 3 is heated to melt the bump 2 so that the bump 2 is connected to the electrode terminal 5. When the bump 2 is molten, a surface tension of the molten bump material functions to minimize a surface area of the bump material between the electrode pad (not shown) on the semiconductor device 1 at which the bump 2 is formed and the electrode terminal 5 on the substrate 3.
Accordingly, the sur~ace tension functions to minimize the total positional error between the electrode pad on the semiconductor device 1 at which the bump 2 is formed and the electrode terminal 5 on the substrate 3 and the semiconductor device 1 is guided to a position at which the sur~ace tensions o~ the respective bump materials balance. By this sur~ace tension, more precise positioning is automatically attained. Where spare solder is provided to the electrode terminal and it is reflown, the surface tension o~ the molten solder ~unctions in the same manner.
Instead o~ molting the bump 2, insulative bonding agent which contracts when it cures may be ~illed into a gap between the semiconductor device 1 and the substrate 3 and the bump 2 may be pushed to the electrode terminal 5 by a curing contraction ~orce of the bonding agent to electrically connect the bump 2 to the electrode terminal 5.
The second embodiment of the present invention is ~U3~03 1 now described with re~erence to Figs. 4 and 5.
As shown in Fig. lA, a plurality o~ bumps 2 are formed on a semiconductor device 1 to project from the surface thereo~.
On the other hand, a plurality of recesses 4 corresponding to the bumps on the semiconductor device 1 are formed on the substrate 3 on which the semiconductor device 1 is to be packaged, and the electrode terminals 5 are ~ormed at the centers of the recesses 4 (See Figs.
4 and 5). Each o~ the recesses 4 has a dimension which is large enough to receive at least a top (bottom in the drawing) o~ the bump 2 ~ormed on the semiconductor device 1, and a depth o~ the recess gradually increases as it goes ~rom the periphery to the center at which the electrode terminal 5 is ~ormed. The depth o~ the recess 4 may gradually increase continuously from the periphery to the center. The electrode 5 may, ~or example, be formed by selectively plating at the center o~ the recess 4.
When the semiconductor device 1 is to be packaged to the sùbstrate 3 on which the recess 4 and the electrode 5 have been ~ormed, the bump 2 on the semiconductor device 1 is positioned to the electrode terminal on the substrate 3 by a positioning machine (not shown~. This positioning may be coarse positioning which assures that the top of the bump 2 does not swell out of the recess 4 as shown in Fig. 4.

Z03~703 1A size of the bump 2 ~ormed on the semiconductor device 1 was 80 ~m in diameter and approximately 30 ~m in height, and a size o~ the electrode terminal 5 on the substrate 3 was lOO ~m in diameter. The outer diameter of the recess 4 was substantially equal to the diameter o~ the electrode terminal and the depth o~ the recess 4 was approximately 10 ~m. The semiconductor device 1 was packaged on the substrate 3. In this case, a positioning precision required for a positioning machine 10in order to maintain a positioned error between the bump 2 and the electrode terminal 5 a~ter the packaging within +10 ~m was +50 ~m.
On the other hand, the same semiconductor device as that of the above example was packaged on a prior art substrate having a ~lat electrode terminal of the same dimension as that o~ the above example. The precision required ~or the positioning machine was +/- 10~m. The result is shown below.

Present Prior art invention Precision o~
positioning machine +/- 50~m +/- 10~m _ Positional error after packaging +/- 10~m +/- 10~m The third embodiment o~ the present invention is now described with re~erence to Figs 6 to 8.

As shown in Fig. lA, a plurality of bump electrodes ' ~

2~)3~03 1 are formed on a semiconductor device 1 to project therefrom. A height of some bump electrode 2a is higher than that of the remaining bump electrode 2b so that the bump electrode 2a projects more largely from the sur~ace of the semiconductor device 1 than the remaining bump electrode 2b.
On the other hand, a plurality of electrode terminals 5a and 5b are formed on a packaging substrate 3 on which the semiconductor device 1 is packaged, corresponding to the bump electrodes 2a and 2b on the semiconductor device 1. A recess 4 for receiving at least a top of the bump electrode 2a is formed on a surface of the electrode terminal 5a which corresponds to the bump electrode 2a (See Figs. 6 and 7). A depth of the recess 4 gradually increases as it goes from a periphery to a center and it is deepest at the center.
The electrode terminal 5a having such recess 4 may, for example, be formed in the following manner. First, a recess is formed at an area of the packaging substrate 3 at which the electrode terminal 5a is to be ~ormed.
The recess is large enough to receive at least a top (bottom in the drawing) of the bump 2 formed on the semiconductor device 1. The recess is selectively metal-plated or vacuum-deposited to form the electrode terminal 5a. The electrode terminal 5a thus formed has the recess 4 for receiving at least the top o~ the bump electrode 2a, formed there on.

1 When the semiconductor device 1 is to be packaged to the substrate 3 thus $ormed, the bump 2 on the semiconductor device 1 is positioned to the electrode terminal 5 on the substrate by a positioning machine (not shown). This positioning may be coarse to assure that a portion o~ the bump 2 abuts the metal layer 5a as shown in Fig. 6. Because i~ the top o$ the bump 2 is positioned within a range o$ the recess 4 o$ the electrode terminal 5, the bump 2 is guided along the surface o~ the recess 4 o$ the electrode terminal 5 by lightly pushing the semiconductor device 1 to the substrate 3 a$ter the positioning and it is automatically moved toward the center o$ the recess 4.
As shown in Fig. 7, the bump electrode 2a is positioned to the center o$ the electrode terminal 5a and the other bump electrode 2b abuts against the corresponding electrode terminal 5a. And the first abutted bump electrode 2a slides on the packaging substrate 3 while it contacts thereto. Accordingly, the bump electrode 2a contacts to the wiring pattern $ormed on the packaging substrate 3 including the electrode terminals 5a and 6b, and the wiring pattern is damaged by the contact. In order to reduce the damage which the wiring pattern su~$ers from the contact to the bump electrode, in accordance with the present invention, some bump electrode 2a projects more largely $rom the sur$ace o$ the semiconductor device 1 than the other 1 bump electrode 2b. Thus, compared to a case where all bump electrode are formed with the some height, the number of bump electrodes which contact to the wiring pattern before the positioning is completed can be reduced, and the damage which the bump electrode and the wiring pattern suffer from the contact can be reduced.
Accordingly, a total reliability of the bump electrodes 2a and 2b and the electrode terminals 5a and 5b is improved and a yield of packaging is improved.
Further, by selecting the bump electrode 2a which is formed higher than the other bump electrode 2b from a low bump electrode density area such as a corner of the semiconductor device 1 as shown in Fig. 8, a frequency of contact of the bump electrode 2a to the wiring pattern formed on the packaging substrate 3 can be further reduced.
In the present invention, the recess 4 for reGeiving the top of the bump electrode 2a is formed only in the electrode terminal 5a formed on the packaging substrate 3 correspondingly to the bump electrode 2a. By forming the recess 4 only in the limited electrode terminals, the number of electrode terminals having the recesses formed therein can be reduced.
Since the number of electrode terminals 5a which are formed in the recesses of the packaging substrate 3 is limited as described above, a possible area of break of the wiring pattern is reduced.

1 Further, by forming the bump electrode 2a and the electrode terminal 5a which contribute to the positioning as a bump electrode and an electrode terminal for exclusively positioning use which are not connected to the electronic circuit formed on the semiconductor device 3, the other bump electrode 2b and electrode terminal 5b which are connected to the electronic circuit of the semiconductor device and contribute to the exchange of electrical signals with the electronic circuit do not contact to each other until the positioning is completed and the damage due to the contact is prevented. Further, since it is not necessary to form the recesses in the electrode terminal which are connected to the electronic circuit o~ the semiconductor device, a possible area o~ break due to the formation o~ steps disappears from the exchange of the electrical signals with the electronic circuit.
A~ter the positioning of the semiconductor device 1 to the packaging substrate 3, the packaging substrate 3 is heated, spare solder (not shown) applied to the electrode terminals 6a and 5b is reflown and the bump electrodes 2a and 2b and the corresponding electrode terminals 5a and 5b are interconnected. In this case, a surface tension o~ the reflown spare solder acts to gaps between the bump electrodes 2a and 2b and the electrode terminals 5a and 5b and more precise positioning is automatically attained by the action of the surface Z03~7~)3 1 tension. Even if the spare solder is not applied, a same effect may be attained by melting the bump electrodes 2a and 2b by heating them.
In the present embodiment, the recess 4 for receiving the top of the bump electrode 2a is formed in the electrode terminal 5a on the packaging substrate.
Alternatively, a recess for receiving the top of the bump electrode 2a may be formed on the surface of the packaging substrate 3 and an electrode terminal which is formed correspondingly to the bump electrode 2a may be arranged at the center of the recess to attain similar operation and effect.
In accordance with the present invention, a high precision and expensive positioning machine used in the prior art is not required and a relatively inexpensive positioning machine can be used. Further, since the positioning by the positioning machine may be coarse, the positioning time required ~or the positioning by the positioning machine is shorter than that in the prior art which required the precise positioning by the positioning machine. Accordingly, the time and cost ~or the packaging can be reduced.
Further, since the damage of the electrode terminals and the bump electrodes which are formed on the packaging substrate and connected to the electronic circuit of the semiconductor device is reduced, the reliability of the electrode terminal and the bump X03f~703 1 electrodes is improved and the semiconductor device can be packaged on the packaging substrate with high reliability and high yield.
From the invention thus described, it will be obvious that the invention may be varied in many ways.
Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.

Claims (21)

1. A substrate for packaging a semiconductor device having a bump projecting therefrom, characterized by that said substrate has an electrode terminal to which said bump is to be connected, and a recess for receiving at least a top of said bump is formed on a surface of said electrode terminal.
2. A substrate for packaging a semiconductor device according to Claim 1 characterized by that a depth of said recess increases as it goes from a periphery to a center.
3. A substrate for packaging a semiconductor device according to Claim 2 characterized by that the depth of said recess gradually increases stepwise.
4. A substrate for packaging a semiconductor device according to Claim 2 wherein the depth of said recess gradually increases continuously.
5. A substrate for packaging a semiconductor device according to Claim 1 characterized by that a top of said bump is of substantially sphere shape and said recess has a larger radius of curvature than that of said top.
6. A substrate for packaging a semiconductor device having a bump projecting therefrom, characterized by that said substrate has a recess formed on a surface thereof to receive at least a top of said bump, and an electrode terminal to which said bump is to be connected is formed at a center of said recess.
7. A substrate for packaging a semiconductor device according to Claim 6 characterized by that said electrode terminal is formed by selective plating.
8. A packaging structure of a semiconductor device characterized by:
a semiconductor device having a bump formed thereon to project therefrom; and a packaging substrate which has a recess for receiving at least a top of said bump is formed on the surface of a substrate and electrode terminal to which said bump is to be connected is formed at a center of said recess.
9. A packaging structure of a semiconductor device according to Claim 8 characterized by that said electrode terminal is formed by selective plating.
10. A packaging structure of a semiconductor device according to Claim 8 characterized by that a depth of said recess increases as it goes from a periphery to a center.
11. A packaging structure of a semiconductor device according to Claim 10 characterized by that the depth of said recess gradually increases stepwise.
12. A packaging structure of a semiconductor device according to Claim 10 characterized by that the depth of said recess gradually increases continuously.
13. A packaging structure of a semiconductor device characterized by:
A semiconductor device having a plurality of bump formed thereon to project therefrom, some of said bumps projecting more largely than the remaining bumps; and a packaging substrate which has an electrode terminals formed correspondingly to said some of said bumps and having recesses for receiving tops of said some of said bumps.
14. A packaging structure of a semiconductor device according to Claim 13 characterized by that a depth of said recesses increases as it goes from a periphery to a center.
15. A packaging structure of a semiconductor device according to Claim 14 characterized by that the depth of said recesses gradually increases stepwise.
16. A packaging structure of a semiconductor device according to Claim 14 characterized by that the depth of said recess gradually increases continuously.
17. A method for packaging a semiconductor device on a packaging substrate by directly connecting a plurality of bumps projecting from a plurality of electrode terminals on said packaging substrate, comprising the steps of:
forming some of said bumps on said semiconductor device higher than the remaining bumps and forming recesses for receiving tops of said bumps in some of said electrode terminals formed on said packaging substrate correspondingly to said some of said bumps;
inserting the tops of said some of said bumps into said recesses to position said semiconductor device to said packaging substrate; and packaging said semiconductor device to said packaging substrate.
18. A method for packaging a semiconductor device according to Claim 17 characterized by that said some of said bumps are arranged on a low density area.
19. A method for packaging a semiconductor device according to Claim 17 characterized by that said some of said bumps and said some of said electrode terminals are ones for exclusively positioning use.
20. A method for packaging a semiconductor device according to Claim 17 characterized by that instead of forming said recesses in said some of said electrode terminals, recesses for receiving the tops of said some of said bumps to arrange said some of said electrode terminals at centers of the recesses are formed in said packaging substrate.
21. A packaging structure of a semiconductor device characterized by:
a packaging substrate having a bump formed thereon to project therefrom; and a semiconductor device which has a recess for receiving at least a top of said bump is formed on the surface of the semiconductor device and electrode terminal to which said bump is to be connected is formed at a center of said recess.
CA002034703A 1990-01-23 1991-01-22 Substrate for packaging a semiconductor device Abandoned CA2034703A1 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP13417/1990 1990-01-23
JP13413/1990 1990-01-23
JP13412/1990 1990-01-23
JP2013417A JPH03218039A (en) 1990-01-23 1990-01-23 Mounting method of semiconductor element
JP2013412A JPH03218034A (en) 1990-01-23 1990-01-23 Semiconductor mounting board
JP2013413A JPH03218035A (en) 1990-01-23 1990-01-23 Semiconductor element mounting board

Publications (1)

Publication Number Publication Date
CA2034703A1 true CA2034703A1 (en) 1991-07-24

Family

ID=27280241

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002034703A Abandoned CA2034703A1 (en) 1990-01-23 1991-01-22 Substrate for packaging a semiconductor device

Country Status (5)

Country Link
US (1) US5214308A (en)
EP (1) EP0439134A2 (en)
KR (1) KR950001365B1 (en)
AU (1) AU645283B2 (en)
CA (1) CA2034703A1 (en)

Families Citing this family (235)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2673993B2 (en) * 1990-07-02 1997-11-05 日本無線株式会社 Surface acoustic wave device
DE69331876T2 (en) * 1992-01-28 2002-11-28 British Telecomm Alignment of integrated optical components
JP3215424B2 (en) * 1992-03-24 2001-10-09 ユニシス・コーポレイション Integrated circuit module with fine self-alignment characteristics
US5411400A (en) * 1992-09-28 1995-05-02 Motorola, Inc. Interconnect system for a semiconductor chip and a substrate
US5406701A (en) * 1992-10-02 1995-04-18 Irvine Sensors Corporation Fabrication of dense parallel solder bump connections
US5329423A (en) * 1993-04-13 1994-07-12 Scholz Kenneth D Compressive bump-and-socket interconnection scheme for integrated circuits
EP0637070B1 (en) * 1993-07-28 1997-09-24 The Whitaker Corporation Perimeter independent precision locating member for a semiconductor chip and method of making said member
US5435482A (en) * 1994-02-04 1995-07-25 Lsi Logic Corporation Integrated circuit having a coplanar solder ball contact array
US5578869A (en) * 1994-03-29 1996-11-26 Olin Corporation Components for housing an integrated circuit device
US5712192A (en) * 1994-04-26 1998-01-27 International Business Machines Corporation Process for connecting an electrical device to a circuit substrate
US5523628A (en) * 1994-08-05 1996-06-04 Hughes Aircraft Company Apparatus and method for protecting metal bumped integrated circuit chips during processing and for providing mechanical support to interconnected chips
FR2727227B1 (en) * 1994-11-17 1996-12-20 Schlumberger Ind Sa ACTIVE SECURITY DEVICE WITH ELECTRONIC MEMORY
US6826827B1 (en) * 1994-12-29 2004-12-07 Tessera, Inc. Forming conductive posts by selective removal of conductive material
US5573171A (en) * 1995-02-16 1996-11-12 Trw Inc. Method of thin film patterning by reflow
CN1123067C (en) * 1995-05-22 2003-10-01 日立化成工业株式会社 Semiconductor device having a semiconductor chip electrically connected to a wiring substrate
US20020004320A1 (en) * 1995-05-26 2002-01-10 David V. Pedersen Attaratus for socketably receiving interconnection elements of an electronic component
US5598036A (en) * 1995-06-15 1997-01-28 Industrial Technology Research Institute Ball grid array having reduced mechanical stress
JP3310499B2 (en) * 1995-08-01 2002-08-05 富士通株式会社 Semiconductor device
US5810609A (en) * 1995-08-28 1998-09-22 Tessera, Inc. Socket for engaging bump leads on a microelectronic device and methods therefor
DE59611449D1 (en) * 1995-09-08 2007-12-20 Fraunhofer Ges Forschung METHOD AND DEVICE FOR TESTING A CHIP
US5795194A (en) * 1995-09-29 1998-08-18 Berg Technology, Inc. Electrical connector with V-grooves
US6159770A (en) * 1995-11-08 2000-12-12 Fujitsu Limited Method and apparatus for fabricating semiconductor device
US6376921B1 (en) 1995-11-08 2002-04-23 Fujitsu Limited Semiconductor device, method for fabricating the semiconductor device, lead frame and method for producing the lead frame
US6329711B1 (en) 1995-11-08 2001-12-11 Fujitsu Limited Semiconductor device and mounting structure
US6072239A (en) 1995-11-08 2000-06-06 Fujitsu Limited Device having resin package with projections
KR100438256B1 (en) * 1995-12-18 2004-08-25 마츠시타 덴끼 산교 가부시키가이샤 Semiconductor device and manufacturing method
US5660321A (en) * 1996-03-29 1997-08-26 Intel Corporation Method for controlling solder bump height and volume for substrates containing both pad-on and pad-off via contacts
US5726502A (en) * 1996-04-26 1998-03-10 Motorola, Inc. Bumped semiconductor device with alignment features and method for making the same
JP2830852B2 (en) * 1996-08-08 1998-12-02 松下電器産業株式会社 Electronic component mounting method
SE9604678L (en) 1996-12-19 1998-06-20 Ericsson Telefon Ab L M Bumps in grooves for elastic locating
SE516011C2 (en) * 1996-12-19 2001-11-05 Ericsson Telefon Ab L M Tightly packed electrical connectors
SE511425C2 (en) * 1996-12-19 1999-09-27 Ericsson Telefon Ab L M Packing device for integrated circuits
US6406989B1 (en) * 1997-02-21 2002-06-18 Nec Corporation Method of fabricating semiconductor device with bump electrodes
JPH10233413A (en) * 1997-02-21 1998-09-02 Nec Kansai Ltd Semiconductor device and its manufacture and wiring board
US6040618A (en) * 1997-03-06 2000-03-21 Micron Technology, Inc. Multi-chip module employing a carrier substrate with micromachined alignment structures and method of forming
US6246548B1 (en) 1997-03-24 2001-06-12 Maxtor Corporation Mechanically formed standoffs in a circuit interconnect
US5929521A (en) * 1997-03-26 1999-07-27 Micron Technology, Inc. Projected contact structure for bumped semiconductor device and resulting articles and assemblies
JPH1174312A (en) * 1997-08-28 1999-03-16 Mitsubishi Electric Corp Semiconductor device and method for forming solder bump
US6096576A (en) 1997-09-02 2000-08-01 Silicon Light Machines Method of producing an electrical interface to an integrated circuit device having high density I/O count
KR100266637B1 (en) * 1997-11-15 2000-09-15 김영환 Stackable ball grid array semiconductor package and a method thereof
US6046910A (en) * 1998-03-18 2000-04-04 Motorola, Inc. Microelectronic assembly having slidable contacts and method for manufacturing the assembly
SG80587A1 (en) * 1998-03-25 2001-05-22 Texas Instr Singapore Pte Ltd Semiconductor device testing and burn-in methodology
US6040630A (en) 1998-04-13 2000-03-21 Harris Corporation Integrated circuit package for flip chip with alignment preform feature and method of forming same
US6172414B1 (en) * 1998-04-28 2001-01-09 Trw Inc. Apparatus and method for snap-on thermo-compression bonding
US6337509B2 (en) 1998-07-16 2002-01-08 International Business Machines Corporation Fixture for attaching a conformal chip carrier to a flip chip
US6303986B1 (en) 1998-07-29 2001-10-16 Silicon Light Machines Method of and apparatus for sealing an hermetic lid to a semiconductor die
JP3846611B2 (en) * 1998-09-25 2006-11-15 ソニー株式会社 Mounting semiconductor component, mounting structure and mounting method
US6927491B1 (en) * 1998-12-04 2005-08-09 Nec Corporation Back electrode type electronic part and electronic assembly with the same mounted on printed circuit board
US6644982B1 (en) * 1998-12-04 2003-11-11 Formfactor, Inc. Method and apparatus for the transport and tracking of an electronic component
JP2000195984A (en) * 1998-12-24 2000-07-14 Shinko Electric Ind Co Ltd Semiconductor device, its manufacture carrier substrate therefor and its manufacture
US6456099B1 (en) * 1998-12-31 2002-09-24 Formfactor, Inc. Special contact points for accessing internal circuitry of an integrated circuit
US6965166B2 (en) * 1999-02-24 2005-11-15 Rohm Co., Ltd. Semiconductor device of chip-on-chip structure
JP3399518B2 (en) * 1999-03-03 2003-04-21 インターナショナル・ビジネス・マシーンズ・コーポレーション Semiconductor structure and method of manufacturing the same
JP3726998B2 (en) * 1999-04-01 2005-12-14 株式会社村田製作所 Surface wave device
JP4362163B2 (en) * 1999-04-06 2009-11-11 富士通マイクロエレクトロニクス株式会社 Manufacturing method of semiconductor device
US6517359B1 (en) 1999-05-21 2003-02-11 Agilent Technologies, Inc. System and method for mating electrical connections
US6313999B1 (en) 1999-06-10 2001-11-06 Agere Systems Optoelectronics Guardian Corp. Self alignment device for ball grid array devices
US6077766A (en) * 1999-06-25 2000-06-20 International Business Machines Corporation Variable thickness pads on a substrate surface
US6352881B1 (en) 1999-07-22 2002-03-05 National Semiconductor Corporation Method and apparatus for forming an underfill adhesive layer
TW531948B (en) 1999-10-19 2003-05-11 Fci Sa Electrical connector with strain relief
US6805278B1 (en) * 1999-10-19 2004-10-19 Fci America Technology, Inc. Self-centering connector with hold down
JP4464527B2 (en) * 1999-12-24 2010-05-19 大日本印刷株式会社 Semiconductor mounting member and manufacturing method thereof
EP1122567A1 (en) * 2000-02-02 2001-08-08 Corning Incorporated Passive alignement using slanted wall pedestal
US6580165B1 (en) * 2000-11-16 2003-06-17 Fairchild Semiconductor Corporation Flip chip with solder pre-plated leadframe including locating holes
US6707591B2 (en) 2001-04-10 2004-03-16 Silicon Light Machines Angled illumination for a single order light modulator based projection system
US6782205B2 (en) 2001-06-25 2004-08-24 Silicon Light Machines Method and apparatus for dynamic equalization in wavelength division multiplexing
US6747781B2 (en) 2001-06-25 2004-06-08 Silicon Light Machines, Inc. Method, apparatus, and diffuser for reducing laser speckle
US6829092B2 (en) 2001-08-15 2004-12-07 Silicon Light Machines, Inc. Blazed grating light valve
JP2003188507A (en) * 2001-12-18 2003-07-04 Mitsubishi Electric Corp Semiconductor integrated circuit and printed circuit board for mounting the same
US6800238B1 (en) 2002-01-15 2004-10-05 Silicon Light Machines, Inc. Method for domain patterning in low coercive field ferroelectrics
DE10223738B4 (en) * 2002-05-28 2007-09-27 Qimonda Ag Method for connecting integrated circuits
US6767751B2 (en) 2002-05-28 2004-07-27 Silicon Light Machines, Inc. Integrated driver process flow
US6728023B1 (en) 2002-05-28 2004-04-27 Silicon Light Machines Optical device arrays with optimized image resolution
US6822797B1 (en) 2002-05-31 2004-11-23 Silicon Light Machines, Inc. Light modulator structure for producing high-contrast operation using zero-order light
US6829258B1 (en) 2002-06-26 2004-12-07 Silicon Light Machines, Inc. Rapidly tunable external cavity laser
US6813059B2 (en) 2002-06-28 2004-11-02 Silicon Light Machines, Inc. Reduced formation of asperities in contact micro-structures
US6714337B1 (en) 2002-06-28 2004-03-30 Silicon Light Machines Method and device for modulating a light beam and having an improved gamma response
US7423337B1 (en) 2002-08-19 2008-09-09 National Semiconductor Corporation Integrated circuit device package having a support coating for improved reliability during temperature cycling
US6801354B1 (en) 2002-08-20 2004-10-05 Silicon Light Machines, Inc. 2-D diffraction grating for substantially eliminating polarization dependent losses
JP3722137B2 (en) * 2002-08-21 2005-11-30 セイコーエプソン株式会社 Semiconductor device mounting method, semiconductor device mounting structure, electro-optical device, electro-optical device manufacturing method, and electronic apparatus
DE10240461A1 (en) 2002-08-29 2004-03-11 Infineon Technologies Ag Universal housing for an electronic component with a semiconductor chip and method for its production
US6917892B2 (en) * 2002-09-16 2005-07-12 Anritsu Company Single port single connection VNA calibration apparatus
US6791845B2 (en) * 2002-09-26 2004-09-14 Fci Americas Technology, Inc. Surface mounted electrical components
US6712480B1 (en) 2002-09-27 2004-03-30 Silicon Light Machines Controlled curvature of stressed micro-structures
KR100447851B1 (en) * 2002-11-14 2004-09-08 삼성전자주식회사 Wafer level Bonding method of flip-chip manner for semiconductor apparatus in lateral bonded type
US6906598B2 (en) * 2002-12-31 2005-06-14 Mcnc Three dimensional multimode and optical coupling devices
US20040129453A1 (en) * 2003-01-07 2004-07-08 Boggs David W. Electronic substrate with direct inner layer component interconnection
US6900389B2 (en) * 2003-01-10 2005-05-31 Fci Americas Technology, Inc. Cover for ball-grid array connector
US7253510B2 (en) 2003-01-16 2007-08-07 International Business Machines Corporation Ball grid array package construction with raised solder ball pads
US20040147169A1 (en) 2003-01-28 2004-07-29 Allison Jeffrey W. Power connector with safety feature
US7301222B1 (en) 2003-02-12 2007-11-27 National Semiconductor Corporation Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages
US6806997B1 (en) 2003-02-28 2004-10-19 Silicon Light Machines, Inc. Patterned diffractive light modulator ribbon for PDL reduction
US6829077B1 (en) 2003-02-28 2004-12-07 Silicon Light Machines, Inc. Diffractive light modulator with dynamically rotatable diffraction plane
WO2005001933A2 (en) * 2003-06-28 2005-01-06 Infineon Technologies Ag Multichip semi-conductor component and method for the production thereof
US7495179B2 (en) * 2003-10-06 2009-02-24 Tessera, Inc. Components with posts and pads
US7462936B2 (en) 2003-10-06 2008-12-09 Tessera, Inc. Formation of circuitry with modification of feature height
US8641913B2 (en) * 2003-10-06 2014-02-04 Tessera, Inc. Fine pitch microcontacts and method for forming thereof
US7084500B2 (en) * 2003-10-29 2006-08-01 Texas Instruments Incorporated Semiconductor circuit with multiple contact sizes
US7425759B1 (en) * 2003-11-20 2008-09-16 Bridge Semiconductor Corporation Semiconductor chip assembly with bumped terminal and filler
US8207604B2 (en) * 2003-12-30 2012-06-26 Tessera, Inc. Microelectronic package comprising offset conductive posts on compliant layer
US7176043B2 (en) 2003-12-30 2007-02-13 Tessera, Inc. Microelectronic packages and methods therefor
US7709968B2 (en) * 2003-12-30 2010-05-04 Tessera, Inc. Micro pin grid array with pin motion isolation
US7458839B2 (en) 2006-02-21 2008-12-02 Fci Americas Technology, Inc. Electrical connectors having power contacts with alignment and/or restraining features
KR20060118567A (en) 2003-12-31 2006-11-23 에프씨아이 Electrical power contacts and connectors comprising same
US7303941B1 (en) 2004-03-12 2007-12-04 Cisco Technology, Inc. Methods and apparatus for providing a power signal to an area array package
US20050208749A1 (en) * 2004-03-17 2005-09-22 Beckman Michael W Methods for forming electrical connections and resulting devices
US7282375B1 (en) 2004-04-14 2007-10-16 National Semiconductor Corporation Wafer level package design that facilitates trimming and testing
US7109583B2 (en) * 2004-05-06 2006-09-19 Endwave Corporation Mounting with auxiliary bumps
WO2006004671A2 (en) * 2004-06-25 2006-01-12 Tessera, Inc. Microelectronic package structure with spherical contact pins
US7453157B2 (en) * 2004-06-25 2008-11-18 Tessera, Inc. Microelectronic packages and methods therefor
WO2006005643A1 (en) * 2004-07-08 2006-01-19 International Business Machines Corporation Method and system for improving alignment precision of parts in mems
WO2006052616A1 (en) 2004-11-03 2006-05-18 Tessera, Inc. Stacked packaging improvements
TWI237364B (en) * 2004-12-14 2005-08-01 Advanced Semiconductor Eng Flip chip package with anti-floating mechanism
US7476108B2 (en) 2004-12-22 2009-01-13 Fci Americas Technology, Inc. Electrical power connectors with cooling features
US7384289B2 (en) * 2005-01-31 2008-06-10 Fci Americas Technology, Inc. Surface-mount connector
US7939934B2 (en) * 2005-03-16 2011-05-10 Tessera, Inc. Microelectronic packages and methods therefor
US7364945B2 (en) * 2005-03-31 2008-04-29 Stats Chippac Ltd. Method of mounting an integrated circuit package in an encapsulant cavity
US7303427B2 (en) * 2005-04-05 2007-12-04 Fci Americas Technology, Inc. Electrical connector with air-circulation features
US7354800B2 (en) 2005-04-29 2008-04-08 Stats Chippac Ltd. Method of fabricating a stacked integrated circuit package system
US8957511B2 (en) * 2005-08-22 2015-02-17 Madhukar B. Vora Apparatus and methods for high-density chip connectivity
US7745301B2 (en) * 2005-08-22 2010-06-29 Terapede, Llc Methods and apparatus for high-density chip connectivity
US20070045812A1 (en) * 2005-08-31 2007-03-01 Micron Technology, Inc. Microfeature assemblies including interconnect structures and methods for forming such interconnect structures
US8067267B2 (en) * 2005-12-23 2011-11-29 Tessera, Inc. Microelectronic assemblies having very fine pitch stacking
US8058101B2 (en) * 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US7456088B2 (en) 2006-01-04 2008-11-25 Stats Chippac Ltd. Integrated circuit package system including stacked die
US7768125B2 (en) * 2006-01-04 2010-08-03 Stats Chippac Ltd. Multi-chip package system
US7750482B2 (en) * 2006-02-09 2010-07-06 Stats Chippac Ltd. Integrated circuit package system including zero fillet resin
US8704349B2 (en) * 2006-02-14 2014-04-22 Stats Chippac Ltd. Integrated circuit package system with exposed interconnects
US7385299B2 (en) * 2006-02-25 2008-06-10 Stats Chippac Ltd. Stackable integrated circuit package system with multiple interconnect interface
JP2007266111A (en) * 2006-03-27 2007-10-11 Sharp Corp Semiconductor device, laminated semiconductor device using the same, base substrate, and semiconductor device manufacturing method
US7425145B2 (en) * 2006-05-26 2008-09-16 Fci Americas Technology, Inc. Connectors and contacts for transmitting electrical power
US7726982B2 (en) * 2006-06-15 2010-06-01 Fci Americas Technology, Inc. Electrical connectors with air-circulation features
US7652374B2 (en) * 2006-07-31 2010-01-26 Chi Wah Kok Substrate and process for semiconductor flip chip package
US7545029B2 (en) * 2006-08-18 2009-06-09 Tessera, Inc. Stack microelectronic assemblies
US20080150101A1 (en) * 2006-12-20 2008-06-26 Tessera, Inc. Microelectronic packages having improved input/output connections and methods therefor
US7641500B2 (en) 2007-04-04 2010-01-05 Fci Americas Technology, Inc. Power cable connector system
JP5350604B2 (en) * 2007-05-16 2013-11-27 スパンション エルエルシー Semiconductor device and manufacturing method thereof
US7905731B2 (en) 2007-05-21 2011-03-15 Fci Americas Technology, Inc. Electrical connector with stress-distribution features
US7564130B1 (en) * 2007-07-06 2009-07-21 National Semiconductor Corporation Power micro surface-mount device package
KR101388538B1 (en) 2007-09-28 2014-04-23 테세라, 인코포레이티드 Flip chip interconnection with double post
US7762857B2 (en) * 2007-10-01 2010-07-27 Fci Americas Technology, Inc. Power connectors with contact-retention features
US8004070B1 (en) * 2008-04-29 2011-08-23 Wei Chen Wire-free chip module and method
US8062051B2 (en) 2008-07-29 2011-11-22 Fci Americas Technology Llc Electrical communication system having latching and strain relief features
US20100044860A1 (en) * 2008-08-21 2010-02-25 Tessera Interconnect Materials, Inc. Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer
USD640637S1 (en) 2009-01-16 2011-06-28 Fci Americas Technology Llc Vertical electrical connector
USD606497S1 (en) 2009-01-16 2009-12-22 Fci Americas Technology, Inc. Vertical electrical connector
USD610548S1 (en) 2009-01-16 2010-02-23 Fci Americas Technology, Inc. Right-angle electrical connector
USD664096S1 (en) 2009-01-16 2012-07-24 Fci Americas Technology Llc Vertical electrical connector
USD608293S1 (en) 2009-01-16 2010-01-19 Fci Americas Technology, Inc. Vertical electrical connector
US8323049B2 (en) 2009-01-30 2012-12-04 Fci Americas Technology Llc Electrical connector having power contacts
USD619099S1 (en) 2009-01-30 2010-07-06 Fci Americas Technology, Inc. Electrical connector
US8366485B2 (en) 2009-03-19 2013-02-05 Fci Americas Technology Llc Electrical connector having ribbed ground plate
USD618180S1 (en) 2009-04-03 2010-06-22 Fci Americas Technology, Inc. Asymmetrical electrical connector
USD618181S1 (en) 2009-04-03 2010-06-22 Fci Americas Technology, Inc. Asymmetrical electrical connector
US8603862B2 (en) * 2010-05-14 2013-12-10 International Business Machines Corporation Precise-aligned lock-and-key bonding structures
US8330272B2 (en) 2010-07-08 2012-12-11 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US8580607B2 (en) 2010-07-27 2013-11-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
KR101075241B1 (en) 2010-11-15 2011-11-01 테세라, 인코포레이티드 Microelectronic package with terminals on dielectric mass
US8994048B2 (en) * 2010-12-09 2015-03-31 Stats Chippac, Ltd. Semiconductor device and method of forming recesses in substrate for same size or different sized die with vertical integration
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
US20120146206A1 (en) 2010-12-13 2012-06-14 Tessera Research Llc Pin attachment
US9137903B2 (en) 2010-12-21 2015-09-15 Tessera, Inc. Semiconductor chip assembly and method for making same
KR101128063B1 (en) 2011-05-03 2012-04-23 테세라, 인코포레이티드 Package-on-package assembly with wire bonds to encapsulation surface
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US8872318B2 (en) 2011-08-24 2014-10-28 Tessera, Inc. Through interposer wire bond using low CTE interposer with coarse slot apertures
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US20130119532A1 (en) * 2011-11-11 2013-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Bumps for Chip Scale Packaging
EP2624034A1 (en) 2012-01-31 2013-08-07 Fci Dismountable optical coupling device
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
USD727852S1 (en) 2012-04-13 2015-04-28 Fci Americas Technology Llc Ground shield for a right angle electrical connector
USD727268S1 (en) 2012-04-13 2015-04-21 Fci Americas Technology Llc Vertical electrical connector
US8944831B2 (en) 2012-04-13 2015-02-03 Fci Americas Technology Llc Electrical connector having ribbed ground plate with engagement members
US9257778B2 (en) 2012-04-13 2016-02-09 Fci Americas Technology High speed electrical connector
USD718253S1 (en) 2012-04-13 2014-11-25 Fci Americas Technology Llc Electrical cable connector
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9543703B2 (en) 2012-07-11 2017-01-10 Fci Americas Technology Llc Electrical connector with reduced stack height
USD751507S1 (en) 2012-07-11 2016-03-15 Fci Americas Technology Llc Electrical connector
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
CN104662460B (en) * 2012-09-27 2016-11-09 株式会社藤仓 Optical module
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
USD745852S1 (en) 2013-01-25 2015-12-22 Fci Americas Technology Llc Electrical connector
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US9055701B2 (en) * 2013-03-13 2015-06-09 International Business Machines Corporation Method and system for improving alignment precision of parts in MEMS
USD720698S1 (en) 2013-03-15 2015-01-06 Fci Americas Technology Llc Electrical cable connector
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
CN103579012B (en) * 2013-10-24 2016-08-17 天水华天科技股份有限公司 Tape welding spherical array flat-four-side pin-less packaging part production method
US9082753B2 (en) 2013-11-12 2015-07-14 Invensas Corporation Severing bond wire by kinking and twisting
US9087815B2 (en) 2013-11-12 2015-07-21 Invensas Corporation Off substrate kinking of bond wire
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
TWI648563B (en) * 2013-12-03 2019-01-21 光澄科技股份有限公司 Integrated module and forming method thereof
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US20150237732A1 (en) * 2014-02-18 2015-08-20 Qualcomm Incorporated Low-profile package with passive device
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US10032699B1 (en) * 2014-04-28 2018-07-24 Amkor Technology, Inc. Flip chip self-alignment features for substrate and leadframe applications
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
TWI567887B (en) * 2014-06-11 2017-01-21 矽品精密工業股份有限公司 Substrate structure and method of manufacture thereof
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9633971B2 (en) 2015-07-10 2017-04-25 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US11495560B2 (en) 2015-08-10 2022-11-08 X Display Company Technology Limited Chiplets with connection posts
US10468363B2 (en) * 2015-08-10 2019-11-05 X-Celeprint Limited Chiplets with connection posts
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9704822B2 (en) * 2015-11-10 2017-07-11 International Business Machines Corporation Bonding substrates using solder surface tension during solder reflow for three dimensional self-alignment of substrates
US10043779B2 (en) 2015-11-17 2018-08-07 Invensas Corporation Packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
JPWO2018042846A1 (en) * 2016-08-30 2019-06-24 株式会社村田製作所 Electronic device and multilayer ceramic substrate
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US20200045425A1 (en) * 2018-03-07 2020-02-06 USound GmbH Method of manufacturing a mems printed circuit board module and/or sound transducer assembly
CN112204732A (en) * 2018-05-31 2021-01-08 华为技术有限公司 Circuit board and mobile terminal
CN109309069A (en) * 2018-09-19 2019-02-05 深圳市心版图科技有限公司 Welded ball array encapsulates chip and its welding method
JP2022011066A (en) * 2020-06-29 2022-01-17 日本電気株式会社 Quantum device
US20230068329A1 (en) * 2021-08-30 2023-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3436818A (en) * 1965-12-13 1969-04-08 Ibm Method of fabricating a bonded joint
JPS5678356U (en) * 1979-11-12 1981-06-25
FR2541044A1 (en) * 1983-02-21 1984-08-17 Ebauchesfabrik Eta Ag Method for mounting a printed-circuit board on a substrate
US4545610A (en) * 1983-11-25 1985-10-08 International Business Machines Corporation Method for forming elongated solder connections between a semiconductor device and a supporting substrate
US4581680A (en) * 1984-12-31 1986-04-08 Gte Communication Systems Corporation Chip carrier mounting arrangement
JPH07112041B2 (en) * 1986-12-03 1995-11-29 シャープ株式会社 Method for manufacturing semiconductor device
US4937653A (en) * 1988-07-21 1990-06-26 American Telephone And Telegraph Company Semiconductor integrated circuit chip-to-chip interconnection scheme
US4935803A (en) * 1988-09-09 1990-06-19 Motorola, Inc. Self-centering electrode for power devices
CA2034702A1 (en) * 1990-01-23 1991-07-24 Masanori Nishiguchi Method for packaging semiconductor device
AU637874B2 (en) * 1990-01-23 1993-06-10 Sumitomo Electric Industries, Ltd. Substrate for packaging a semiconductor device

Also Published As

Publication number Publication date
EP0439134A2 (en) 1991-07-31
KR950001365B1 (en) 1995-02-17
US5214308A (en) 1993-05-25
AU645283B2 (en) 1994-01-13
EP0439134A3 (en) 1994-02-02
AU6982291A (en) 1991-07-25

Similar Documents

Publication Publication Date Title
CA2034703A1 (en) Substrate for packaging a semiconductor device
US7213331B2 (en) Method for forming stencil
US5367435A (en) Electronic package structure and method of making same
EP1204136B1 (en) Method of fabricating a packaged semiconductor device
US5196726A (en) Substrate for packaging a semiconductor device having particular terminal and bump structure
US5929516A (en) Polymer stud grid array
US5949142A (en) Chip size package and method of manufacturing the same
KR100645415B1 (en) Semiconductor device and manufacturing method
US5866950A (en) Semiconductor package and fabrication method
US6476505B2 (en) Semiconductor device having pads, the intervals of which are adjusted and arranged in semiconductor chip corners
US5657207A (en) Alignment means for integrated circuit chips
US7019221B1 (en) Printed wiring board
US6130478A (en) Polymer stud grid array for microwave circuit arrangements
US20010042924A1 (en) Semiconductor package
US6396155B1 (en) Semiconductor device and method of producing the same
KR100533847B1 (en) Stacked flip chip package using carrier tape
KR20000028944A (en) Semiconductor device to be mounted on main circuit board and process for manufacturing same device
JPH03218039A (en) Mounting method of semiconductor element
US5841188A (en) Tape carrier structure for a tape carrier package
US6518088B1 (en) Polymer stud grid array
KR100246367B1 (en) Semiconductor package and manufacturing method
JPH05267394A (en) Mounting of semiconductor element
JP3174238B2 (en) Semiconductor device and method of manufacturing the same
KR100238197B1 (en) Semiconductor device
KR200278534Y1 (en) Chip size package

Legal Events

Date Code Title Description
EEER Examination request
FZDE Discontinued