CA2036865A1

CA2036865A1 - Interference suppression

Info

Publication number: CA2036865A1
Application number: CA002036865A
Authority: CA
Inventors: Brian J. Long; Michael J. Hynes
Original assignee: Brian J. Long; Michael J. Hynes; Digital Equipment International Limited
Current assignee: Compaq Computer Holding Ltd
Priority date: 1990-03-17
Filing date: 1991-02-21
Publication date: 1991-09-18
Also published as: EP0448881A3; JPH0834764B2; IE910883A1; AU7123791A; GB9006088D0; EP0448881B1; DE69028622T2; EP0448881A2; US5321724A; DE69028622D1; AU636712B2; JPH05250277A

Abstract

ABSTRACT

Interference Suppression System A line driver 12 is coupled by a pair of signal lines 10, 11 to a receiver 13. Preprocessing circuitry 18, for processing signals arriving on the pair of signal lines at the receiver, includes regulating means (Fig. 2) for regulating the potential between the signal lines between predetermined limits and thereby modifying the sensitivity of the system to compensate for changes in line conditions and reject interference when the line driver is powered down. The regulating means comprise: bias means Ql-Q3, Q12 for putting a bias on the signal passing through to the receiver, so as to hold the receiver input away prom the triggering voltage level so that it is not triggered by noise; and bias limiting means Q6-Q7, Q9-Q11 responsive to signals from the driver so as to limit or reduce the effective bias, so that the sensitivity of the system to true signals from the driver is not reduced below a desired level.

Figs. 1, 2

Description

2Q~fi~3 INTERFERENCE SUPPRESSION SYSTEM

The present invention relates to the suppression of interference on signal lines.

In the computer field, there are many situations in which signals have to be transmitted between different units of equipment. One common signaling technique uses DC signaling. This technique is commonly used where the distance between the two units of equipment is in the region of a moire up to around 1000 metros, and the bit rate is not excessively high.

This technique is largely free of interference if a single channel (of say 8 lines in parallel) is operated continuously. However, a problem can arise if the channel is not always in operation but the circuitry at the receiving end is left turned on. Interference can be generated on the channel, and this may be large enough to produce false triggering of the receiving circuitry.

Considering this in more detail, the receiving circuitry often has to be left turned on permanently, since it may not be known when the unit at the transmitting end Jill be in operation and it will not be feasible for the receiving socket to be turned on and off with the transmitting unit. apical examDIQ issue 2036~

microcomputer or workstation coupled to a host computer located elsewhere in a large building. The host computer has to keep its receiving circuitry permanently operating, while the various units to which it is coupled are powered up and powered down at unpredictable times.

The present signaling technique is effective at distances of up to around 1000 m. The signals are carried by a signal line which is referenced to a common return or earth line. The signal line is driven by a driver circuit, and the output impedance of such a driver circuit when powered down is typically high. The voltage on a signal line is therefore largely governed by the receiver circuit when the driver is powered down.
However, variations in the local earth voltage between the two locations will be imposed on the return line at the driver end. Thus such local earth voltage fluctuations will appear between the signal and return lines at the receiver.

Also, it will often happen that the lines of two or more channels (between the same or different units) will run close to each other for substantial distances. There will then be substantial capacitive coupling between the lines of the different channels. Since the output impedance of a powered down driver is high, this can 203~g6~

induce substantial voltages on the lines of a powered down channel. This cross-coupling will thus also appear at the receiver of a powered down channel.

There are various recognized standards for this type of transmission system. These specify, inter alias the sensitivity of the receivers. This sensitivity is such that interference (from either of these causes) can easily cause false triggering of the receivers of a powered down channel. This is clearly undesirable.
Although the receiving unit can be designed to detect such false triggering, e.g. by detecting that it violates system protocols, this makes the system design more complicated, and incurs the overhead of processing these false signals (which are normally treated as attempts at logging into the system).

The main object of the present invention is to provide circuitry for preprocessing signals arriving on a pair of lines at a receiver so as to reject interference appearing when the driver is powered down.

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. .. ...
The invention in its broad form resides in a method and a system comprising a line driver and a receiver coupled by a pair of signal lines, characterized by preprocessing circuitry for processing signals arriving on the pair of signal lines at the receiver, including regulating means for regulating the potential between the signal lines between predetermined limits and including means for modifying the system sensitivity to compensate for changes in line conditions and including means to reject interference when the line driver is powdered down.

In a first embodiment, preferably in the processing circuitry, the regulating means comprises bias means for putting a bias on the signal passing through to the receiver, so as to hold the receiver input away from thy triggering voltage level so that it is not triggered by noise; and bias limiting means responsive to signals from the driver so as to limiter reduce the effective bias, so that the sensitivity ox the system to true signals from the driver is not reduced Boyle a desired level.

In a second embodiment, preferably the processing circuitry comprises a resistor connected between the Tao signal lines; a current regulating circuit including means for feeding a current through the resistor; and, for each signal line, current adjustment means responsive to the conditions on the signal lines or adjusting the current passing through the corresponding end of thy resistor.

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The present preprocessing circuitry in a preferred embodiment puts a bias on the signal passing through to the receiver. This bias has the effect of holding the receiver input away from the triggering voltage level, so that it is not triggered by noise, but the preprocessing circuitry is responsive to signals from the driver so as to limit or reduce the effective bias, so that the sensitivity of the system to true signals from the driver is not reduced below the levels required by the standards mentioned above.

The bias limitation may be achieved by sensing the signal current and adjusting the bias in accordance therewith. Alternatively, the bias limitation may be achieved by sensing the signal voltage and adjusting the bias current in dependence thereon. This voltage control may be supplemented by further voltage sensing means for detecting noise spikes and increasing the bias in the presence of severe noise. The bias current adjustment may be either gradual or switched.

Major features of the invention include the following:
a current regulating circuit including means for feeding a current to one signal line and means for drawing a matching current from the other signal line;

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a resistor connected between the two signal lines to pass said current; and, for each signal line, current adjustment means responsive to the conditions on the signal lines for adjusting the current through the resistor.

The current regulating means may be controlled by current mirror circuitry.

The current regulating circuit may comprise means for producing a constant current and the current adjustment means may then comprise, for each signal line, means for diverting the current away from passage through the resistor. The means for diverting the current away from the resistor may optionally comprise further current mirror circuitry.

Alternatively, the current mirror circuitry controlling the current regulating circuit may include a sociably resistance controlled by logic circuitry forming the current adjustment means.

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The present invention also provides a method of suppressing interference on signal lines in a system comprising a line driver and a receiver coupled by a pair of signal lines characterized in that it comprises the steps of:-preprocessing signals arriving at the pair of signal lines at the receiver by regulating the potential between predetermined limits to modify the sensitivity of the system to compensate for changes in line conditions to reject interference when the line driver is powered down.

grief Description of Drawing Further features and characteristics of the invention will become apparent from the following detailed description of various embodiments thereof, given by way of example and with reference to the drawings, in which:

Fig. 1 is a block diagram of a driver and receiver;

Fig. 2 is a circuit diagram of a current-controlled preprocessing circuit;

Figs. PA and 3B together are a circuit diagram, partially in block form, of a voltage-controlled pro-processing circuit; end 2~3~

Fig. 4 is a circuit diagram of two further current-controlled preprocessing circuits.

Fig. 1 shows a typical signal line 10 and common or return line 11 connecting a driver 12 and a receiver 13.
The receiver 13 is a balanced difference amplifier and trigger circuit, which is responsive to the voltage difference between the lines 10 and 11.

Description of Preferred Embodiments When the driver 12 is powered down, its output impedance to line 10 is high. If a signal line 14 of another channel runs alongside the signal line 10 for a substantial distance, there will be a substantial capacitive coupling 15 between the lines 10 and 14.
Signals on line 14 will therefore be cross-coupled onto l no 10. Line 10 is also coupled to earth via its capacitance to the return line 11, the (high) output resistance of the powered down driver 12, and the input resistance of the receiver 13. The amplitude of the cross-coupled interference will be thus determined by the resulting voltage division.

The input impedance of the receiver 13 presented to the signal line 10 is much smaller than the output resistance of the powered down driver 12. The voltage on line 10 is therefore substantially the earth voltage 203~8~:3 local to the receiver 13 (ignoring cross-coupled interference for the moment). The return line 11, however, is earthed at the driver 12, and its voltage is therefore that of the earth local to the driver 12 (the input impedance presented to the line 11 by the receiver 13 is high relative to the very low resistance to earth at the driver 12). It can easily happen that the local earths at the driver 12 and receiver 13 differ by a few volts, as indicated by the voltage source 17. This will result in a substantial (and possibly varying) voltage appearing at the receiver 13 between the lines 10 and 11.

Both these sources of interference can therefore cause false triggering of the receiver 13.

In the present system, preprocessing circuitry 18 is connected to the lines 10 and 11 immediately in front of the receiver 13. The function of this preprocessing circuitry is to limit interference signals between the lines 10 and 11 to levels below that at which the receiver 13 will trigger, during periods when the driller 12 is powered down. (Of course, the circuitry 18 must not interfere with signals from a powered up driver.) The circuitry 18 is connected to the lines 10 and 11 but, as will be seen, these lines pass through the circuitry 18 to the receiver 13 substantially directly.

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Fig. 2 is a circuit diagram of one form of preprocessing circuitry. The lines 10 and 11 enter at the left-hand side, from the driver 12, and pass through to the right-hand side, continuing on to the receiver 13.
The conditions on these lines are sensed, and the preprocessing circuitry adjusts these conditions to reduce interference signals to below the level at which they can cause triggering of the receiver 13. The circuit can be regarded as consisting of a current reference generating branch Q2-Q8-R8-Q10-Ql~; a regulating branch Ql-Q3-Q6-R3-Q11-Q12 which regulates the voltage between the lines 10 and 11; and two current diverting branches, Q5 Q9 and Q7-Q13. It will be seen that the circuit has, ~i~h`relatively minor exceptions, a symmetry which interchanges the top and bottom; thus transistors Q1 and Q12, for example, are of opposite types (PUP and NUN) but are otherwise matched.

Considering first the current reference generating branch, a reference voltage span Vref and 0 is applied to the bases of NUN transistor Q8 and PUP transistor Q10 having their emitters connected together through a 1.8 ohm resistor R8 as shown. This gives a constant reference current of 150 PA, which therefore also flows through the two further transistors Q2 and Q~4 connected in series with Q8 and Q10.

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The reference voltages Vref and 0 are preferably common to several lines (or channels), particularly if they are implemented on a single chip; this has the advantage that the current in all receivers can be adjusted (and will track each other) by trimming the single signal Vref.

This 150 PA current is mirrored into the regulating branch with amplification. PUP transistor Al and NUN
transistor Ql2 have 4 times the areas of Q2 and Q14.
Accordingly the current in the reference current branch is mirrored into the regulating branch as a current of ~600 MA. This current flows through the S ohm resistor I', so generating a voltage of 3 V across it. The lines 10 and if are connected to thy two sides of R8 via a pair of 500 Ohm resistors Al and R2 as shown.

Transistors Q1 and Q3 are in cascade connection, giving a higher input impedance looking into Q3. This improves the matching of Q3 and Q12, because the input impedance of NUN transistor Ql2 is higher than that of PUP transistor Q3. (If the circuit was implemented by an accurately bipolar technology in which NUN and PUP
transistors were accurately matched, Q3 would not be necessary). Resistors R100, Rl01, R200, and R201 increase the effective impedances of the current mirrors.

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Since the current in the regulating branch is held steady, the voltage difference across R3 is held steady while the voltages at the ends of R3 can move up-and down relatively freely. The voltage between lines 10 and 11 is therefore held steady at a value which holds the input of the receiver constant, thus avoiding any false triggering. (The input voltage at which the receiver output changes is normally close to O v). If the voltage on line 11 is changed by cross-coupled noise from an adjacent line, the voltage on line 10 is changed by substantially the same amount (line 10 having a high impedance at its driver end). The preprocessing circuitry acts as a negative impedance which slightly reduces the total impedance button line 10 and earth.

The operation as so far described is modified by the current diverting branches. The two transistors Q6 and Q7 control a current diversion from resistor R3 at the upper part of the regulating branch, and the two transistors Q9 and Ill perform a similar function for its lower part. The sizes of transistors Q6 and Q11 in the regulating branch are 6 times the areas of Q2 and Q14, and the sizes of Q7 and Q9 are 2 times the areas of Q2 and Q14. Thus there is a 3:1 size ratio between Q6 and Q7, and between Ill and Q9. it no voltage across resistor R4, the current from transistor Al will divide 203~8~

in the ratio 3:1 between transistors Q6 and Q7, so that the current through Q6 will in fact be 450 PA, giving a voltage of 2.25 v across R3.

When the driver 12 is powered on and applies a load to the line (lines 10 and 11), voltages will be developed across the two 500 û resistors I and R2. Considering the current diverting path Q7-Q13, the voltage on line 10 will be applied to the base of transistor Q7, while the voltage on the base of Q6 will differ from that on the base of Q7 by the voltage drop across R1. The load applied to line 10 increases the base voltage on Q7 relative to that on Q6, and so the division of the current from Al between Q6 and Q7 will be changed from its 3:1 ratio.

This current division' is given approximately as -follows. Taking Icky) and Icky) as the actual emitter currents of Q6 and Q7, Is(Q6) and Is(Q7) as their reverse saturation currents, we have Ie(Q6)/Ie(Q7) = Is(Q6)/Is(Q7) . exp(~V/Vt), where V is the voltage difference between the bases of Q6 and Q7 and vet is a constant to = 26 my at a temperature of 300 K). In this equation, the term 2~3~

IstQ6)/Is(Q7) equals the area ratio of Q6 and Q7, which is a constant (3). The voltage difference v is approximately Iline.Rl, where Kline is the current flowing into the line I and Al = 500 Ohm. (The base current from Q7 also makes a contribution to the line current, but this can be ignored as long as the gain of Q7 is high.) The current division ratio is therefore Al if line lo is purely floating, giving a voltage on line lo of about 2.25 V as discussed above. If a signal is applied to line lo resulting in the voltage on line lo rising, then the division ratio also rises, with the current through Q6 rising towards the full current through Al.
If, on the contrary, the voltage on line lo falls, the division ratio also falls. The current through Q6 thus falls towards zero and the biasing effect of the circuit is reduced as the input signal (between lines lo and if) approaches the switching level of around 0 V.

The 5 ohm resistors R4 and R7 operate to limit the reverse base-substrate currents (parasitic diode currents) which flow when the input voltage (on either or both of lines lo and if) is more negative than the negative supply rails. The precise form of protection required depends on the particular form of implementation 2~3~

ox the circuit, and Sweeney implementations (e.g. those using dielectric isolation between transistors, or discrete circuit components) may not require any specific protection. The base currents flowing through R4 and R7 therefore affect the emitter-base voltages of Q6 and Q7.
A more accurate equation for TV is therefore V = Ic(Q6).Rl + Ib(Q6)-R7 - Ib(Q7)-R1-Because of the yearly voltage effect', particularly of the PUP transistors, an active load Q13 is provided at the collector of the current limit transistor Q7. This improves the voltage performance of the circuit by ensuring that the collec~or-emitter voltage of Q7 tracks that of Q6 to within about 3 V. This reduces the dependence of the current limit circuit on collector-emitter voltage differences due to input voltage changes, etc., and makes the circuit less sensitive to early voltage effects on Q7.

There is a corresponding adjustment of the current division between Q9 and Q11 in response to voltage changes on line 11, as a result of the symmetry mentioned above. Two diodes Do and Do are included to prevent 2031~865 reverse base-emitter voltage breakdown on Q9 and Ill when the voltage on line if is more negative than the negative supply rail.

Figs. PA and 3B show a second form of preprocessing circuitry. The major difference from Fig. 2 is that instead of using current diverting branches, the current supplied by the current mirror is varied in dependence on the input signal voltage between lines 10 and 11.
Further, this dependence is switched (rather than varying continuously as the currents in the current diverting branches in Fig. 2 do).

Referring first to Fig. PA,-- this shows a cur en regulating branch QAl-RAt-QA2 and a current reference branch QA3-bloc~=20-QA4. In the current regulating branch, transistor QUEUE corresponds to transistor Al of Fig. 2, resistor RAY to resistor R3, and QUEUE to Ql2. In the current reference branch, QUEUE corresponds to Q2, block 20 to the reference current source Q8-R8-QlO, and QUEUE to Q14.

The reference current source is shown in Fig. 38.
In place of the single path Q8-R8-QlO of Fig. 2, there are three parallel paths QUIRK, QUIRK, and QUIRK. Of these, the first is always on, but the aye second and third are switched, so that the reference current produced by block 20 is switched between three different values (as will be explained, path QUIRK
is forced on if path QUIRK is turned on). Path QUIRK is turned on and off by switching QUEUE on and off by means of a control transistor Hall, and path QUEUE-WRECK is similarly controlled by switching QUEUE on and off by means of a control transistor QUEUE.

The control signals to the block 20 are obtained from the input signal on lines lo and 11 via a control block 21 consisting of a comparator block 22 feeding a logic block 23. Path QUIRK is controlled in dependence on the voltage between lines lo and 11 so that the current produced by block 20 is reduced when a signal appears between them; path QUIRK is controlled in dependence on the detection of a high noise pulse level.

Considering first the path QUIRK, this is controlled by a current control comparator in block 22, which operates at a voltage of about 200 my and controls that current path directly. As long as the voltage between lines 10 and if is above this level, the path QUIRK is turned on. In the quiescent condition, with the driver 13 powered down, the Fig. 3 circuit operates with paths QAS-RA2-QA6 and QUIRK both . fugue 11 turned on (and path Quirkily off) to bias the voltage between lines 10 and 11 to about 1.8 V. This condition remains as long as the noise between lines 10 and if remains low enough not to take the voltage below the 200 my level.

If the signal between lines lo and 11 takes the voltage below 200 my, then the current control comparator output changes, and turns off the path QUIRK. This reduces the current bias, and so effectively increases the sensitivity of the receiver.

The current path Quirkily is a noise control path controlled by two further comparators, a noise start comparator for detecting the start of noise and a noise end comparator for detecting its end, and controlling that current path through respective timers and latching circuits in the logic block 23.

The noise start comparator operates at a level of 0 V. The associated timer in the logic circuitry 23 detects whether the voltage remains below 0 V for a time of less than 5 my. If this condition is satisfied, then it is assumed that the signal is noise rather than a data signal. (Noise spikes resulting from cross-coupling are generally short, because they result prom capacitive 203~6~

coupling and the decay time is usually short). This turns on the current path QUIRK. The increase of current from block 20 increases the bias voltage between the lines 10 and if to about 3.7 V.

The noise end comparator operates at a level of 3 v.
When noise has been detected, the bias voltage between lines lo and if is, as just explained, about 3.7 V. As long as substantial noise remains on the line, the bias voltage is maintained at this elevated level, but once it ends, the bias voltage is reduced to its normal level of 2 V. The noise end comparator detects excursions of the voltage between lines lo and 11 to below 3 V (from the bias level of 3.7 V), and the associated timer detects whether the voltage remains above the 3 V level for 200 my. If this condition is satisfied, it is assumed that the high noise conditions have ended, and the latch which was set by the low noise comparator and timer is cleared, so turning off the path Quirkily.

The logic circuitry 23 also includes an interlock circuit which ensures that if the current path QUERY-QUEUE is turned on, the current path QUIRK is turned on as well.

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Fig. 4 shows a third form of preprocessing circuitry. This operates on broadly the same principles as the circuit of jig. 2, but of course with certain differences. Two slightly different versions are shown, one in which the collectors of QB12 and QB14 are connected to the supply rails (as shown by the broken lines) and the other in which these collectors are connected to the lines 10 and 11 as shown.

As in the Fig. 2 circuit, transistors QB9 and Halo and resistor RB8 set a reference current (200 PA). This current also flows through QB4, and is mirrored into QB3.
The mirrored current of 200 PA therefore divides between QB13 and QB14. If there is no current in RB5, then the base voltages of QB13 and 2814 are equal, and the 200 PA
divides equally between these two transistors. The current through QB13 also flows through Qs6, and is mirrored into QB5. The size of QB5 is chosen to be 4 times that of QB6, so the mirrored current in QB5 is times the current in QB6.

Assume first that the collectors of QB12 and QB14 are connected to the supply rails (broken lines). The current through QB14 then flows direct to the supply rail and plays no useful role. The current through QB13, however, also flows through QB6,` and is thence mirrored 203~8~

into QB5; QB5 is designed to have 4 times the area of Qs6, so the resulting current in Q35 is 400 PA.
Correspondingly, 400 PA flows through QB1. These currents correspond to the currents in Q1-Q3 and Q11-Q12 of the Fig. 2 circuit.

If the voltage on say line 11 varies, then current will flow in RB5. The base voltages of QB13 and QB14 will therefore differ, and the division of the 200 PA
between these two transistors will therefore be changed.
For example, if node 11 goes positive and a current flows into the circuit from that node, then the base of QB13 will be more positive than the base of Qsl4~ QB13 will therefore take less current and QB14 will take more.
This will cause the current in QB6, and hence that in QB5, to fall.

A change of voltage on line lo on the other half of the circuit will have corresponding effects, taking account of course of the fact that the symmetry between the two halves of the circuit involves a sign reversal.

This circuit suffers from the disadvantage that the gain (the change in the current through QBl in response to a change of input voltage) is low. This can be alleviated by connecting the collectors of QBl2 and QB14 203~8~

to the lines lo and if as shown, so what the current flowing through these transistors is fed to the input resistors RBl and RUBS instead of being dumped to the supply rails.

The analysis of this version of the circuit is more difficult. however, it can be seen that when current flows in ABS, the current through QBl3 falls and that through Q814 rises. The current in R~5, however, also flows through QBl4, and thus increases further the current in QBl3. This gives positive feedback, which increases the gain of the circuit, but has the drawback that there is a danger of latching.

The foregoing description has been directed to a particular exemplary embodiment of the invention for the purpose of illustration and explanation only. Louvre, it will be apparent to one skilled in the art that many modifications and changes in the device of the present invention will be possible without departing from the scope of this invention. It is intended that the following claims be interpreted to embrace all such modifications and changes.

Claims

C?IMS

1. A system comprising a line driver (12) and a receiver (13) coupled by a pair of signal lines (10, 11), characterized by preprocessing circuitry (18) for processing signals arriving on the pair of signal lines at the receiver, including regulating means for regulating the potential between the signal lines between predetermined limits and including means for modifying the system sensitivity to compensate for changes in line conditions and including means to reject interference when the line driver is powdered down.

2. A system including preprocessing circuitry according to claim 1, characterized in that the regulating means comprise: bias means (Q1-Q3, Q12) for putting a bias on the signal passing through to the receiver, so as to hold the receiver input away from the triggering voltage level so that it is not triggered by noise; and bias limiting means (Q6-Q7, Q9-Q11) responsive to signals from the driver so as to limit or reduce the effective bias, so that the sensitivity of the system to true signals from the driver is not reduced below a desired level.

3. A system including preprocessing circuitry according to claim 2 characterized in that the bias limiting means comprise means (Fig. 2) for sensing the signal current and adjusting the bias current in accordance therewith.

24 A system including preprocessing circuitry according to claim 2 characterized in that the bias limiting means comprise means (Figs. 3A, 3B) for sensing the signal voltage and adjusting the bias current in accordance therewith.

5. A system including preprocessing circuitry according to claim 4 characterized by further voltage sensing means (21, Fig. 3A) for detecting noise spikes and increasing the bias in the presence of severe noise.

6. A system including preprocessing circuitry according to any of claims 3 to 5 characterized in that the bias current is adjusted continuously (Figs. 2, 4).

7. A system including preprocessing circuitry according to any of claims 3 to 5 characterized in that the bias current is adjusted stepwise (Fig. 3B).

8. A system including preprocessing circuitry according to any previous claim characterized by: a resistor (R3) connected between the two signal lines; a current regulating circuit (Q1-Q3, Q12) including means for feeding a current through the resistor; and, for each signal line, current adjustment means (Q5-Q6; Q9-Q11) responsive to the conditions on the signal lines for adjusting the current passing through the corresponding end of the resistor.

9 A system including preprocessing circuitry according to claim 8 characterized in that the current regulating means are controlled by current mirror circuitry (Q2, Q14).

10. A system including preprocessing circuitry according to either of claims 8 and 9 characterized in that the current regulating circuit comprises means for producing a constant current (Q8-R8-Q10).

11. A system including preprocessing circuitry according to any of claims 8 to 10 characterized in that the current adjustment means comprise, for each signal line, means for diverting the current away from passage through the resistor (Q7, Q9).

12. A system including preprocessing circuitry according to any of claims 8 to 11 characterized in that the means for diverting the current away from the resistor comprise further current mirror circuitry (QB2-QB11. QB6-QB13).

13. A system including circuitry according to any of claims 8 to 12 characterized in that the current mirror circuitry controlling the current regulating circuit includes a switchable resistance (RA2, RA3, RA4) controlled by logic circuitry (23) forming the current adjustment means.

26 1. A method of suppressing interference on signal lines in a system comprising a line driver and a receiver coupled by a pair of signal lines characterized in that it comprises the steps of:
preprocessing signals arriving on the pair of signal lines at the receiver by regulating the potential between the signal lines to be within predetermined limits to modify the sensitivity of the system to compensate for changes in line conditions to reject interference when the line driver is powered down.

15. A method as claimed in claim 14 characterized in that the regulation of the potential is achieved by applying a voltage bias to the signal lines.

16. A method as claimed in claim 14 characterized in that the regulation of the potential is achieved by regulating the current flowing in the signal lines.