CA2037012C - Method for synchronizing interconnected digital equipment - Google Patents
Method for synchronizing interconnected digital equipmentInfo
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- CA2037012C CA2037012C CA002037012A CA2037012A CA2037012C CA 2037012 C CA2037012 C CA 2037012C CA 002037012 A CA002037012 A CA 002037012A CA 2037012 A CA2037012 A CA 2037012A CA 2037012 C CA2037012 C CA 2037012C
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- node
- nodes
- synchronization
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- timing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0679—Clock or time synchronisation in a network by determining clock distribution path in a network
Abstract
Optimized synchronization planning and clock distribution for a network of interconnected digital equipment is achieved by designating a networknode at the highest stratum level as the master clock node, forming a group of all unassigned nodes connected to the assigned node or nodes, selecting subgroup of all nodes from the group wherein the subgroup includes all nodes having the highest stratum level of the group, limiting the subgroup to the nodes which have a desired characteristic when such nodes are included in the subgroup, determining the synchronization performance of each node in the subgroup according to a predetermined criterion, assigning one node from the subgroup as a clock timing receiver wherein the one node exhibits the best performance for nodes in the subgroup, and iterating the method at the forming step. In order to obtain an optimum synchronization plan, it is desirable to repeat the entire method described above for the complete set of nodes which are capable of being designated as a master clock node. When more than one node is capable of being considered as a master clock node, the synchronization planning method is then completed by computing the network synchronization performance for each synchronization plan related to a different designated master clock node and choosing the synchronization plan which offers the best network synchronization performance as computed above.
Description
2Q3701~
METHOD FOR SYNCHRONIZING INTERCONNECTED
DIGITAL EQUIPMENT
Technical Field This invention relates to synchronization of interconnected digital 5 equipment and, more particularly, a method of distributing clock signals in a digital co",-"~ tion network.
Back~round of the Invention Digital co,r""llnic~tion nt;lwolk~ are now appearing in increasingly greater numbers. The digital nelwc.lL.s are as complex as a switched network 10 providing national telecolllll~ ications or as simple as a private data network having several private branch exchange (PBX) equipments interconnected by a Tl.5 line. In the digital network, a master or reference clock provides continuing timing signals to all other clocks in a digital network. This permits all digital equipment on thenetwork to operate from a common time base. Synchronization is made possible by 15 design~ting one or more master clocks as the colllllloll time base and distributing their timing information to all e~luipl~nt in the network. As a result, all int~ ;onnected network e~lui~lllent are expected to operate at a rate related to the rate of the design~ted master clock.
Proper synchronization of digital equipment on the network would be 20 nearly impossible without such clock signals and network performance would beseriously degraded at best. A poorly synchronized network would experience severe synchronization slips and error bursts, both of which adversely affect throughput, quality, and delay performance for data and other traffic and services carried by the digital network.
When two digital co,--",ll.-ication equipments are tr~n~mitting information back and forth to each other at different rates, a slower receiving equipment will not be able to keep pace with the faster tr~nsmitting equipment. As a result, the receiving equipment must drop or discard some of the info~nation in order to keep up with the current information being received. Depending on 30 equipment characteristics, the speed of one of the equipments will be adjusted or synchronized to the speed of the other so that both equipments appear to be operating from the same clock signal. It should be noted that a speed differencecausing a timing loss as small as one second every 300 years is intolerable according to some telecolllmunication network standards.
METHOD FOR SYNCHRONIZING INTERCONNECTED
DIGITAL EQUIPMENT
Technical Field This invention relates to synchronization of interconnected digital 5 equipment and, more particularly, a method of distributing clock signals in a digital co",-"~ tion network.
Back~round of the Invention Digital co,r""llnic~tion nt;lwolk~ are now appearing in increasingly greater numbers. The digital nelwc.lL.s are as complex as a switched network 10 providing national telecolllll~ ications or as simple as a private data network having several private branch exchange (PBX) equipments interconnected by a Tl.5 line. In the digital network, a master or reference clock provides continuing timing signals to all other clocks in a digital network. This permits all digital equipment on thenetwork to operate from a common time base. Synchronization is made possible by 15 design~ting one or more master clocks as the colllllloll time base and distributing their timing information to all e~luipl~nt in the network. As a result, all int~ ;onnected network e~lui~lllent are expected to operate at a rate related to the rate of the design~ted master clock.
Proper synchronization of digital equipment on the network would be 20 nearly impossible without such clock signals and network performance would beseriously degraded at best. A poorly synchronized network would experience severe synchronization slips and error bursts, both of which adversely affect throughput, quality, and delay performance for data and other traffic and services carried by the digital network.
When two digital co,--",ll.-ication equipments are tr~n~mitting information back and forth to each other at different rates, a slower receiving equipment will not be able to keep pace with the faster tr~nsmitting equipment. As a result, the receiving equipment must drop or discard some of the info~nation in order to keep up with the current information being received. Depending on 30 equipment characteristics, the speed of one of the equipments will be adjusted or synchronized to the speed of the other so that both equipments appear to be operating from the same clock signal. It should be noted that a speed differencecausing a timing loss as small as one second every 300 years is intolerable according to some telecolllmunication network standards.
Typical problems resulting from timing or synchronization errors can vary from e~c~nge of incorrect or incomplete information to complete blockage and communication failure of the network. Synchronization errors can also propagate downstream through c~cc~ded equipments as a result of a transient timing phase error. For encrypted data 5 systems, loss or slippage of synchronization can adversely affect security of the network by requiring key retransmission. For facsimile transmission on the digital network,synchronization errors can lead to blurred or even illegible images causing the user to generate a need for facsimile ~ lllission. In digital video services, synchronization errors can cause picture segments to be distorted and blanked for periods extending up to several seconds.
When occurring in industry-specific digital networks, the effect of synchronization errors is further magnified. R~nking networks may lose monetary transaction information; aviation control networks may be impaired in dealing with the volumes of inct~nt~neous flight inforrnation; military and national security can be comprised; hotel, automobile, and airline reservation information may be lost; securities exchange information may include erroneous data; and internal business communications may become flawed, if occurring at all.
To address some of these problem areas, various organizations have ~LL~ d to set standards concerning synchronization and clock precision for networks interconnecting digital equipment. See, for example, American National Standard for Telecommunications --- Synchronization Interface Standards for Digital Networks, ANSI T1. 101-1987. While these standards state the error performance of different clock signals, there is no attempt to teach or suggest the manner in which one should develop and optimize a synchronization plan for an entire network to ensure end-to-end network reliability within the acceptance criteria of the standards.
Summary of the Invention In accordance with one aspect of the invention there is provided a method for planning synchronization clock distribution for a network of inl~-col1.1ected digital equipment wherein each digital equipment is represented as a node interconnected to other nodes by links, the digital equipment characterized by a set of equipment performance parameters and each link characterized by at least one link performance parameter, the method comprising:
assigning one node at the highest stratum level as the master clock node; forming a group of all unassigned nodes connected to the assigned node or nodes; selecting a subgroup of all nodes from the group wherein the subgroup includes all nodes having stratum levels which are equal or highest within the group; limiting the subgroup to nodes which have a desired characteristic when such nodes are included in the subgroup; determining synchronization -performance of each node in the subgroup according to a predett?rmined criterion; assigning - one node from the subgroup as a clock timing receiver wherein the one node exhibits synchronization performance better than synchronization performance for all other nodes in the subgroup; and iterating the method at the forming step until all nodes are assigned as timing receivers.
In order to obtain an optimum synchronization plan, it is desirable to repeat the entire method described above for the complete set of nodes which are capable of being designated as a master clock node. When more than one node is capable of being considered as a master clock node, the synchronization planning method is then completed by computing the network synchronization performance for each synchronization plan related to a di~c~c~l designated master clock node and choosing the synchronization plan which offers the best network synchronization performance as computed above.
Brief De~,_.;plion of the Drawin~
A more complete understanding of the invention may be obtained by reading the following description of a specific illustrative embodiment of the invention in conjunction with the appended drawing in which:
FIG. I is a simplified diagram of a network of interconnected digital equipment;
FIG. 2 shows a flowchart representation of a method for developing an optimized synchronization plan in accordance with the principles of the invention; and FIGS. 3 and 4 show synchlo~ ion plans for the network in FIG. 1 developed in accordance with the principles of the invention with master clocks assigned as nodes A and B, respectively.
Detailed D~_l;~)lion Digital networks are represented as a combination of digital equipment shown as nodes in FIG. I inl~lcollllecled by links shown as lines in FIG. 1. Synchronization performance of a digital network depends on both link and equipment performance. Links are required to transmit timing (clock) information accurately throughout the digital network.
Digital equipment is required to receive the timing (clock) information accurately. In order to ensure that all digital equipment in the network are properly synchronized, plc~ ion of a synchronization plan is almost a necessity.
A synchronization plan describes the flow of timing (clock) information throughout a digital network from one or more master timing sources (master clock nodes) to the r~m~ining equipment in the network. As the size of a digital network ,, grows, pr~al~Lion of a synchro~ aLion plan becomes increasingly more difficult because all possible master timing sources and all possible i~lroll,lalion pathsem~nating from the master timing sources within the network must be considered.
Suboplilllal synchronization plans, that is, plans for which synchronization S pt;lroll-lance is less than optimal such as those developed by prior art adhoc planning methods, are insufficient to ensure maintenance of network synchronization in accordance with the al)prop,iate standard. In digital telecomlllullication nelwolk~, o~limulll synchronization plans, such as those realized in accordance with the principles of the present invention, can permit the digital network to achieve 10 synchronization pt;lro,l"allces which exceed the strict timing requirements required by the standards.
In a network of synchronous digital e~luipment, the purpose of an optimum synchronization plan is to transmit timing information from a master timing source to all e~luiplllel~t in the network in the best possible way. For such a 15 plan, it is necess~ry to choose one or more master timing sources as a common time base of the network. When properly planned, the network will exhibit a minimllm daily time error for all equipment.
In accordance with the principles of this invention, synchronization p~,lr,~ an~e is determined for the network on the basis of a model which 20 inco,~o,~les equipment and link p~,.ro""allce characteristics. On the basis of this model, it is possible to generate an c~li"lum synchronization plan for the digital network.
In our model, each link in the network has associated therewith a p~.rc~ ance parameter specifying the average number of daily transmi~sion errors25 (dte) measured over that link. Daily tran~micsion errors affect the accurate transfer of timing information from one equipment to another. The link perf )rmance p~lle~cl is typically a function of the link length and the media type, for example, fiber, satellite, radio, wire and the like.
Every e~luipn~ll~ has three parameters representing timing performance 30 of the particular equipment within a network. These parameters are the stratum level of the equipl-lelll, its timing reaction to errors in the timing information sent to it, and errors produced by the clock within the particular equipment.
The stratum level refers to four defined levels of clock performance (1 through 4) as defined in standards documents such as the ANSI standard cited above.
35 Smaller stratum level numbers represent more accurate timing performance.
Particularly, a stratum 1 clock occupies the highest level in the synchronization hierarchy and is known as the frequency reference (common time base) for the entire synchronization network. It is a plimal~ frequency standard with a ,~ i",l-.-l accuracy defined to be better than lxlO-ll. A stratum 2 clock occupies the second level in the synchronization hierarchy. This clock must have or must be adjustable 5 to ,--il-i,,.ll.~, accuracy of 1.6xlO-8. A stratum 3 clock occupies the third level in the synchronization hierarchy and has or must be adjustable to have a .~
accuracy of 4.6xlO-6. A stratum 4 clock occupies the fourth level in the synchronization hierarchy and has or must be adjustable to have a minimnm accuracy of 3.2x10-5. Typically, clocks at stratum levels 1, 2 and 3 utilize phase 10 buildout routines to handle clock in~ ions and control residual time error.
The second equi~lllel t pclro...l~nce p&~ e~cl is called time interval error ( l~). TIE is based on the variation of the time delay of a given timing (clock) signal with respect to an ideal timing signal. TIE over a particular period is defined as the dirr.,~cl~ce between the time delay values measured at the end and the 15 beginning of the particular period. l~ is generally expressed in microseconds. This p~llel~ characterizes the ability of e4ui~ ,nt to accurately receive timing (clock) information over a link which may be subject to errors.
The third equiplllent pclrollllance parameter is called propagation (prop). Upon receipt of an error in the timing information, some e4uipllæn~ produce 20 errors on its own outgoing co-,..-~ul-ication links. These errors affect synchronization pclrc,..,~-ce of other e4uiplll~nt which receive timing i~lfc,llllation on the outgoing col~ ullication links. When a particular equiplllcn~ incc,l~ldtes a phase buildout routine which can mask incoming errors, the e4uiplllell~ does not produce or propagate errors. Propagation effect of a particular equipment is measured as the 25 number of errors (typically ranging from 0 to 2) produced for each incoming error seen by the particular equipment.
A nclwol~ of interconnected synchronous digital equipment can be represented by a graph of nodes and links like the one depicted in FIG. 1. Nodes A
through G ~esign~te~l as elements 10 through 16 in the graph represent the 30 synchronous digital equipment in the network. Links 20 through 28 in the graph represent the interconnection of these equipment or nodes. In this network representation, the digital interconnections between the equipment are any medium of co~----~.-l-ications such as wire, fiber, satellite, radio and the like.
Each node and link in FM. 1 are defined by their respective performance 35 parameters.
These parameters are shown in the following tables below:
~037012 NODE STRATUM PROPAGATION TE BUILDOUT
A 2 0 0.07 Y
B 2 0 0.3 Y
D 3 0 0.07 Y
E 3 0 0.65 Y
F 3 0 1.0 Y
and LINK DTE
20 (AB) 10 21 (AD) 5 22 (AE) 20 23 (CD) 4 24 (DE) 3 25 (CF) 3 26 (DG) 7 27 (FG) 4 28 (EG) 12 20 With the network represented as shown in FIG. 1, including the performance parameters of nodes and links, the inventive method determines the master timingsource for the digital network and develops an optimum synchronization plan. Themaster timing source is chosen to operate on its own time base. As the inventivemethod is applied, flow of timing information from the master timing source to other 25 equipment is represented by arrows on the links as shown in FIGs. 3 and 4. Arrows are shown pointing from the timing source equipment to the timing receiving e~lui~
A more detailed explanation of our inventive method for synchronizing interconnected digital equipment proceeds as shown in FIG. 2.
In step 1, instruction box 200 calls for designation of a master clock node. If there are stratum level 1 nodes in the network, then assign all stratum 1 nodes as master nodes. Master nodes which generate the common time base do not have a timing ~ignm~nt If there are no stratum level 1 nodes, then select the node 5 with the best stratum level between levels 2 through 4. If there is more than one node having the highest stratum level between levels 2 through 4, then choose one of them a~ l~ily and call it the master node. The master node is now said to be a~signed Daily time error and daily output error, that is, number of errors produced by the node, of the master node are considered zero. After instruction box 200, 10 control is passed to step 2 at instruction box 202 via line 201.
In step 2, instruction box 202 calls for forming a group of all unassigned nodes connecte~l to the a~igned node, selecting a subgroup of all nodes from thegroup wherein the subgroup includes all nodes having the highest stratum level of the group and limi~ing the subgroup to nodes which have a common desired 15 characteristic. This step requires one to select a subset of nodes which are connected to a master node and select the best stratum level among them. If more than one node has the best stratum level, select all of them. If any of the nodes in the chosen subset produce synchronization il~ailments which affect downstream clocks (i.e.,the particular equiplllent does not incorporate phase buildout), these nodes are to be 20 removed from the chosen subset. If all the nodes in the chosen subset produceahlllellts, the chosen subset is left intact. Control is transferred from instruction box 202 to instruction box 204 via line 203.
In step 3, instruction box 204 calls for de~ ing the synchronization pelrolm~lce of each node in the subgroup according to a predetermined performance 25 criterion and ~signing one node from the subgroup as a clock timing receiver wherein the newly assigned node exhibits the best pelrc,llllance for nodes in the subgroup. At the previous step, a subset of nodes was chosen as possible receiving nodes. Based on whether the nodes produce il~ aillllell~s, that is, whether they do not have phase buildout, the following condition is defined for each node within the 30 chosen subset: COND_l=TRUE, if a receiving node within the chosen subset has phase buildout; COND_l=FALSE, otherwise.
Similarly, for each assigned node connected to a node within the chosen subset (i.e., the possible sources of timing), the following condition is defined:
COND_2=TRUE, if the possible source of timing has phase buildout;
35 COND_2=FALSE, otherwise.
For the chosen nodes and the respective possible sources of timing for which COND_I and COND_2 are true, daily time error of the chosen nodes is calculated as follows:
daily_time_error(receiver) = [dte +daily_output_error(source)]
~ TIE(receiver) +daily +time_error(source) .
S For the chosen nodes for which COND_lis true and the respective possible sources of timing with COND_2is false, daily time error of the chosen nodes is calculated as follows:
daily_time_error(receiver) = [dte + daily_output_error(source)] x TIE(receiver) .
After performing these computations, it is possible to choose the node with the lowest daily time error over the links from an assigned node. This node is assigned as a timing receiver. It will receive timing from an assigned node, such as the master, over the link between them which results in the lowest daily timing error. Since the chosen node has now been assigned timing, an arrow is placed on the link pointing from the source of timing to the chosen node for which timing has been assigned. Control is passed from instruction box 204 to decision box 206 via line 205.
If COND_lis false for the chosen nodes, then calculate the daily output errors produced by the chosen node as follows:
daily_time error(receiver) = [dte+daily_output_error(source)] x prop(receiver).
After this co,l~ a~ion, it is possible to choose the node with the lowest daily output error over the links from an assigned node and assign that node as a timing receiver. Based on the respective possible timing sources for the node assigned as the timing receiver, one can calculate the daily time error as in the first equation, if COND_2is true, or in the second equation, if COND_2is false.
The node assigned as timing receiver will receive timing from an assigned node, such as the master, over the link between them which results in the lowest daily timing error. An arrow is placed on the link pointing from the source of timing to the timing assigned chosen node. Control is transferred from instruction box 204 to decision box 206 via line 205.
In step 4, decision box 206 calls for dele~ g whether all nodes have been ~signç~l as timing receivers. If all nodes have been assigned then control is transferred to decision box 211 via line 207. If all nodes have not been assigned, 5 then control is transferred to instruction box 209 via line 208. If there are nodes which have not been assigned, then it is necessary to select the subset of nodesconnected to nodes which already have assigned timing sources and select the best stratum level among them. This step is similar to step 2 pt;lrc.ll"ed at instruction box 202. If more than one node has the best stratum level, all are selected. If any of the 10 nodes in the chosen subset produces i~ n~s which affect downstream clocks(i.e., do not incorporate phase buildout), these nodes are removed from the chosen subset. If all the nodes in the chosen subset produce in~r~illncnts~ do not remove any nodes from the chosen subset. Control is transferred as described above.
In decision box 211, it is necess~ry to determine whether there are more 15 nodes in the network with the same stratum level as the newly assigned master node.
If such additional nodes exist, then control is transferred to instruction box 200 via line 213. If no such additional nodes exist, then control is transferred to instruction 214 via line 212. When control is transferred from decision box 211 to instruction box 200, it is necessary to select a dirrelt;l-t node to be assigned as the master node.
In step 5, instruction 214 calls for computing the network synchronization pelrollllance for each synchronization plan related to a dirrerellt design~ted master clock node and, thereafter, choosing the synchronization plan which offers the best computed network synchronization performance. After con~idering all the network synchronization plans with the various nodes as possible 25 master, it is necess~ry to calculate the network synchronization performance. This p~Çcllllance is calculated as follows:
net_sync_perf= ~, f(daily_time_error(node), number_of_links(node)) nodes where ~ represents the s...~"~.~lion of the synchronization performance over all the nodes in the network. After computing the network synchronization performance, it 30 is possible to choose the network synchronization plan with the best (i.e., the lowest) network synchronization performance. The timing master for the network will be the master node indicated in that synchronization plan. The flow of synchronization timing inrc,llllalion through the network is indicated by each timing assignment ~03~01~
(arrow direction).
EXAMPLE
To illustrate the above-described method, the teleco~ ications network of FIG. 1 is considered. In this example, there are seven digital equipment S named A through G that are interconnected as shown in FIG. 1. The performance parameters of each e4uiplllent and link have been indicated in the tables above.The method to find the optimal synchronization plan proceeds through several iterations of the method. Each iteration is described in detail below. The number of iterations will be equal to the number of nodes receiving timing. The 10 total number of iterations increases linearly with the number of possible masters.
Iteration I: for Master = Node A
Step 1. The best stratum level of all nodes in the network is 2. There are two nodes with the best stratum levels, namely nodes A and B. Initially, select node A as the master node.
15 Step 2. Nodes B, D, and E are connected to node A. Among these three nodes, node B has the best stratum level. Therefore, node B is selected as the best node among B, D, and E.
Step 3. Since there is only one node selected at Step 3, and since there is only one link between A and B, node B is assigned timing from node A over link AB. The 20 daily timing error of node B is 3 microseconds and its daily output errors is 0.
Therefore, nodes A and B are assigned timing.
Step 4. Nodes D and E are the only unassigned nodes connected to the timing assigned nodes A and B. Since both nodes D and E have the same stratum level, they are both selected as the best nodes. Both nodes D and E have phase buildout25 and do not produce impairments, so they remain in the chosen subset.
Iteration 2: for Master = Node A
Step 3. Calculate the daily time error performance of node D over link AD and ofnode E over link AE as follows:
Node D daily_time_error = (5 + O)X 0.07 = 0.35 Node E daily_time_error_-_(20 + O)X 0.65 = 13.0 Since the pelrollllance of node D is better than node E, node D is assigned the timing source node A over link AD. The daily number of output errors S from node D is zero. Th~lcfol~;, nodes A,B, and D are ~ign~l timing.
Step 4. Nodes C, E, and G are the only unassigned nodes connected to the timing assigned nodes A, B, and D. Node E has the best stratum level and is chosen as the best node.
Iteranon 3: for Master = Node A
10 Step 3. Calculate the daily time error pelrol,llance of node E over links AE and DE
as follows:
Link AE daily_time_error = (20 + 0) x 0.65 - 13.0 Link DE daily_time_error = (3 + O)x 0.65 + 0.35 = 2.3 Since the pelrc,llllallce of node E is better when timing comes from node D over link 15 DE than from node A over link AE, node E is assigned the timing source node Dover link DE. The daily number of output errors from node E is 0. Therefore, nodes A, B, D, and E are assigned timing.
Step 4. Nodes C and G are the only unassigned nodes connected to the timing ~igned nodes A, B, D, and E. They both have the same stratum level and, 20 therefore, are both chosen. Both nodes C and G do not incorporate phase buildout and produce errors, thus they are both chosen.
Iteration 4: for Master = Node A
Step 3. Since both chosen nodes produce impairments, the daily output errors of the nodes are calculated. Calculate the daily output errors of node C over link CD and 25 node G over links DG and EG as follows:
Node C, Link CD daily_output_error = (4 + 0) X 2 = 8 Node G, Link DG daily_output_error = (7 + 0) X 1 = 7 Node G, Link EG daily_output_error = (12 + 0) X 1 = 12 Since the number of daily output errors is lower for node G than node C, node G will S be ~signed timing. Calculate the daily time error of node G over links DG and EG
as follows:
Link DG daily_time_error = (7 + 0) X 100 + 0.35 = 700.35 Link EG daily_time_error = (12 + 0) X 100 + 2.3 = 1202.3 Since the performance of node G is better when timing comes from node D over link 10 DG than from node E over link EG, node G is assigned the timing source node Dover link DG. The daily number of output errors from node G is 7. Therefore, nodes A, B, C, E, and G are assigned timing.
Step 4. Nodes C and F are connected to the assigned nodes D and G. Among these two nodes, node F has the best stratum level. Therefore, node F is selected as the 15 best node.
Iteration S: for Master = Node A
Step 3. Since there is only one node selected at Step 2, and since there is only one link belwe~ll G and F, node F is assigned timing from node G over link FG. The daily timing error of node F is given by Node F daily_time_error = (4 + 7) X 1.0 = 11.0 The daily number of output errors is 0. Therefore, all nodes except C are assigned timing.
Step 4. Since node C is the only node without a timing assignment, it is chosen.
203~012 Iteration 6: for Master = Node A
Step 3. Calculate the daily time error performance of Node C over links CD and CF
as follows:
Link CD daily_time_error = (4 + 0) X 250 + 3.35 = 1000.35 S Link CF daily_time_error = (3 + 0) X 250 + 11.0 = 761.0 Since the p~,.ro~ ance of node C is better when timing comes from node F over link CF than from node D over link CD, node C is assigned the timing source node F
over link CF.
Step 4. All nodes are assigned timing. There is one node, node B, with the same 10 stratum level as node A, which has not been chosen as a possible master node. Go to step 1 and choose node B as the master node.
Iterations for Master = Node B
There will be a total of six (6) iterations for Master = node B. The result of these iterations is shown in FIG. 4.
15 Step 5. When the procedure has been repeated with node B as the master node, all nodes with the best stratum level will have been chosen as a possible master node.
The colllpu~a~ion results which are used to develop the synchronization plans for the digital network of FIG. 1 as shown in FIGs. 3 and 4 are shown in the following tables. The first table is developed using node A as the master; the second 20 table is developed using node B as the master.
DAILY DAILY
NODE TIME ERROR OUTPUT ERROR
B 3.0 0 C 761.0 6 D 0.35 0 E 2.3 0 F 11.0 0 G 700.35 7 5 and DAILY DAILY
NODETIME ERROROUTPUT ERROR
A 0.7 0 B
C 761.7 6 D 1.05 0 E 3.0 0 F 11.7 0 G 701.05 7 15 Step S of the method is used to co~ the network synchronization performance of the two possible plans (one with node A as the timing master and one with node B as the timing master). The nclwolk pc;lrolmallce for the plan using node A as the timing master is better than the one using node B. Thus, the first synchronization plan, with A being the timing master, will be the synchronization plan for the 20 network.
When occurring in industry-specific digital networks, the effect of synchronization errors is further magnified. R~nking networks may lose monetary transaction information; aviation control networks may be impaired in dealing with the volumes of inct~nt~neous flight inforrnation; military and national security can be comprised; hotel, automobile, and airline reservation information may be lost; securities exchange information may include erroneous data; and internal business communications may become flawed, if occurring at all.
To address some of these problem areas, various organizations have ~LL~ d to set standards concerning synchronization and clock precision for networks interconnecting digital equipment. See, for example, American National Standard for Telecommunications --- Synchronization Interface Standards for Digital Networks, ANSI T1. 101-1987. While these standards state the error performance of different clock signals, there is no attempt to teach or suggest the manner in which one should develop and optimize a synchronization plan for an entire network to ensure end-to-end network reliability within the acceptance criteria of the standards.
Summary of the Invention In accordance with one aspect of the invention there is provided a method for planning synchronization clock distribution for a network of inl~-col1.1ected digital equipment wherein each digital equipment is represented as a node interconnected to other nodes by links, the digital equipment characterized by a set of equipment performance parameters and each link characterized by at least one link performance parameter, the method comprising:
assigning one node at the highest stratum level as the master clock node; forming a group of all unassigned nodes connected to the assigned node or nodes; selecting a subgroup of all nodes from the group wherein the subgroup includes all nodes having stratum levels which are equal or highest within the group; limiting the subgroup to nodes which have a desired characteristic when such nodes are included in the subgroup; determining synchronization -performance of each node in the subgroup according to a predett?rmined criterion; assigning - one node from the subgroup as a clock timing receiver wherein the one node exhibits synchronization performance better than synchronization performance for all other nodes in the subgroup; and iterating the method at the forming step until all nodes are assigned as timing receivers.
In order to obtain an optimum synchronization plan, it is desirable to repeat the entire method described above for the complete set of nodes which are capable of being designated as a master clock node. When more than one node is capable of being considered as a master clock node, the synchronization planning method is then completed by computing the network synchronization performance for each synchronization plan related to a di~c~c~l designated master clock node and choosing the synchronization plan which offers the best network synchronization performance as computed above.
Brief De~,_.;plion of the Drawin~
A more complete understanding of the invention may be obtained by reading the following description of a specific illustrative embodiment of the invention in conjunction with the appended drawing in which:
FIG. I is a simplified diagram of a network of interconnected digital equipment;
FIG. 2 shows a flowchart representation of a method for developing an optimized synchronization plan in accordance with the principles of the invention; and FIGS. 3 and 4 show synchlo~ ion plans for the network in FIG. 1 developed in accordance with the principles of the invention with master clocks assigned as nodes A and B, respectively.
Detailed D~_l;~)lion Digital networks are represented as a combination of digital equipment shown as nodes in FIG. I inl~lcollllecled by links shown as lines in FIG. 1. Synchronization performance of a digital network depends on both link and equipment performance. Links are required to transmit timing (clock) information accurately throughout the digital network.
Digital equipment is required to receive the timing (clock) information accurately. In order to ensure that all digital equipment in the network are properly synchronized, plc~ ion of a synchronization plan is almost a necessity.
A synchronization plan describes the flow of timing (clock) information throughout a digital network from one or more master timing sources (master clock nodes) to the r~m~ining equipment in the network. As the size of a digital network ,, grows, pr~al~Lion of a synchro~ aLion plan becomes increasingly more difficult because all possible master timing sources and all possible i~lroll,lalion pathsem~nating from the master timing sources within the network must be considered.
Suboplilllal synchronization plans, that is, plans for which synchronization S pt;lroll-lance is less than optimal such as those developed by prior art adhoc planning methods, are insufficient to ensure maintenance of network synchronization in accordance with the al)prop,iate standard. In digital telecomlllullication nelwolk~, o~limulll synchronization plans, such as those realized in accordance with the principles of the present invention, can permit the digital network to achieve 10 synchronization pt;lro,l"allces which exceed the strict timing requirements required by the standards.
In a network of synchronous digital e~luipment, the purpose of an optimum synchronization plan is to transmit timing information from a master timing source to all e~luiplllel~t in the network in the best possible way. For such a 15 plan, it is necess~ry to choose one or more master timing sources as a common time base of the network. When properly planned, the network will exhibit a minimllm daily time error for all equipment.
In accordance with the principles of this invention, synchronization p~,lr,~ an~e is determined for the network on the basis of a model which 20 inco,~o,~les equipment and link p~,.ro""allce characteristics. On the basis of this model, it is possible to generate an c~li"lum synchronization plan for the digital network.
In our model, each link in the network has associated therewith a p~.rc~ ance parameter specifying the average number of daily transmi~sion errors25 (dte) measured over that link. Daily tran~micsion errors affect the accurate transfer of timing information from one equipment to another. The link perf )rmance p~lle~cl is typically a function of the link length and the media type, for example, fiber, satellite, radio, wire and the like.
Every e~luipn~ll~ has three parameters representing timing performance 30 of the particular equipment within a network. These parameters are the stratum level of the equipl-lelll, its timing reaction to errors in the timing information sent to it, and errors produced by the clock within the particular equipment.
The stratum level refers to four defined levels of clock performance (1 through 4) as defined in standards documents such as the ANSI standard cited above.
35 Smaller stratum level numbers represent more accurate timing performance.
Particularly, a stratum 1 clock occupies the highest level in the synchronization hierarchy and is known as the frequency reference (common time base) for the entire synchronization network. It is a plimal~ frequency standard with a ,~ i",l-.-l accuracy defined to be better than lxlO-ll. A stratum 2 clock occupies the second level in the synchronization hierarchy. This clock must have or must be adjustable 5 to ,--il-i,,.ll.~, accuracy of 1.6xlO-8. A stratum 3 clock occupies the third level in the synchronization hierarchy and has or must be adjustable to have a .~
accuracy of 4.6xlO-6. A stratum 4 clock occupies the fourth level in the synchronization hierarchy and has or must be adjustable to have a minimnm accuracy of 3.2x10-5. Typically, clocks at stratum levels 1, 2 and 3 utilize phase 10 buildout routines to handle clock in~ ions and control residual time error.
The second equi~lllel t pclro...l~nce p&~ e~cl is called time interval error ( l~). TIE is based on the variation of the time delay of a given timing (clock) signal with respect to an ideal timing signal. TIE over a particular period is defined as the dirr.,~cl~ce between the time delay values measured at the end and the 15 beginning of the particular period. l~ is generally expressed in microseconds. This p~llel~ characterizes the ability of e4ui~ ,nt to accurately receive timing (clock) information over a link which may be subject to errors.
The third equiplllent pclrollllance parameter is called propagation (prop). Upon receipt of an error in the timing information, some e4uipllæn~ produce 20 errors on its own outgoing co-,..-~ul-ication links. These errors affect synchronization pclrc,..,~-ce of other e4uiplll~nt which receive timing i~lfc,llllation on the outgoing col~ ullication links. When a particular equiplllcn~ incc,l~ldtes a phase buildout routine which can mask incoming errors, the e4uiplllell~ does not produce or propagate errors. Propagation effect of a particular equipment is measured as the 25 number of errors (typically ranging from 0 to 2) produced for each incoming error seen by the particular equipment.
A nclwol~ of interconnected synchronous digital equipment can be represented by a graph of nodes and links like the one depicted in FIG. 1. Nodes A
through G ~esign~te~l as elements 10 through 16 in the graph represent the 30 synchronous digital equipment in the network. Links 20 through 28 in the graph represent the interconnection of these equipment or nodes. In this network representation, the digital interconnections between the equipment are any medium of co~----~.-l-ications such as wire, fiber, satellite, radio and the like.
Each node and link in FM. 1 are defined by their respective performance 35 parameters.
These parameters are shown in the following tables below:
~037012 NODE STRATUM PROPAGATION TE BUILDOUT
A 2 0 0.07 Y
B 2 0 0.3 Y
D 3 0 0.07 Y
E 3 0 0.65 Y
F 3 0 1.0 Y
and LINK DTE
20 (AB) 10 21 (AD) 5 22 (AE) 20 23 (CD) 4 24 (DE) 3 25 (CF) 3 26 (DG) 7 27 (FG) 4 28 (EG) 12 20 With the network represented as shown in FIG. 1, including the performance parameters of nodes and links, the inventive method determines the master timingsource for the digital network and develops an optimum synchronization plan. Themaster timing source is chosen to operate on its own time base. As the inventivemethod is applied, flow of timing information from the master timing source to other 25 equipment is represented by arrows on the links as shown in FIGs. 3 and 4. Arrows are shown pointing from the timing source equipment to the timing receiving e~lui~
A more detailed explanation of our inventive method for synchronizing interconnected digital equipment proceeds as shown in FIG. 2.
In step 1, instruction box 200 calls for designation of a master clock node. If there are stratum level 1 nodes in the network, then assign all stratum 1 nodes as master nodes. Master nodes which generate the common time base do not have a timing ~ignm~nt If there are no stratum level 1 nodes, then select the node 5 with the best stratum level between levels 2 through 4. If there is more than one node having the highest stratum level between levels 2 through 4, then choose one of them a~ l~ily and call it the master node. The master node is now said to be a~signed Daily time error and daily output error, that is, number of errors produced by the node, of the master node are considered zero. After instruction box 200, 10 control is passed to step 2 at instruction box 202 via line 201.
In step 2, instruction box 202 calls for forming a group of all unassigned nodes connecte~l to the a~igned node, selecting a subgroup of all nodes from thegroup wherein the subgroup includes all nodes having the highest stratum level of the group and limi~ing the subgroup to nodes which have a common desired 15 characteristic. This step requires one to select a subset of nodes which are connected to a master node and select the best stratum level among them. If more than one node has the best stratum level, select all of them. If any of the nodes in the chosen subset produce synchronization il~ailments which affect downstream clocks (i.e.,the particular equiplllent does not incorporate phase buildout), these nodes are to be 20 removed from the chosen subset. If all the nodes in the chosen subset produceahlllellts, the chosen subset is left intact. Control is transferred from instruction box 202 to instruction box 204 via line 203.
In step 3, instruction box 204 calls for de~ ing the synchronization pelrolm~lce of each node in the subgroup according to a predetermined performance 25 criterion and ~signing one node from the subgroup as a clock timing receiver wherein the newly assigned node exhibits the best pelrc,llllance for nodes in the subgroup. At the previous step, a subset of nodes was chosen as possible receiving nodes. Based on whether the nodes produce il~ aillllell~s, that is, whether they do not have phase buildout, the following condition is defined for each node within the 30 chosen subset: COND_l=TRUE, if a receiving node within the chosen subset has phase buildout; COND_l=FALSE, otherwise.
Similarly, for each assigned node connected to a node within the chosen subset (i.e., the possible sources of timing), the following condition is defined:
COND_2=TRUE, if the possible source of timing has phase buildout;
35 COND_2=FALSE, otherwise.
For the chosen nodes and the respective possible sources of timing for which COND_I and COND_2 are true, daily time error of the chosen nodes is calculated as follows:
daily_time_error(receiver) = [dte +daily_output_error(source)]
~ TIE(receiver) +daily +time_error(source) .
S For the chosen nodes for which COND_lis true and the respective possible sources of timing with COND_2is false, daily time error of the chosen nodes is calculated as follows:
daily_time_error(receiver) = [dte + daily_output_error(source)] x TIE(receiver) .
After performing these computations, it is possible to choose the node with the lowest daily time error over the links from an assigned node. This node is assigned as a timing receiver. It will receive timing from an assigned node, such as the master, over the link between them which results in the lowest daily timing error. Since the chosen node has now been assigned timing, an arrow is placed on the link pointing from the source of timing to the chosen node for which timing has been assigned. Control is passed from instruction box 204 to decision box 206 via line 205.
If COND_lis false for the chosen nodes, then calculate the daily output errors produced by the chosen node as follows:
daily_time error(receiver) = [dte+daily_output_error(source)] x prop(receiver).
After this co,l~ a~ion, it is possible to choose the node with the lowest daily output error over the links from an assigned node and assign that node as a timing receiver. Based on the respective possible timing sources for the node assigned as the timing receiver, one can calculate the daily time error as in the first equation, if COND_2is true, or in the second equation, if COND_2is false.
The node assigned as timing receiver will receive timing from an assigned node, such as the master, over the link between them which results in the lowest daily timing error. An arrow is placed on the link pointing from the source of timing to the timing assigned chosen node. Control is transferred from instruction box 204 to decision box 206 via line 205.
In step 4, decision box 206 calls for dele~ g whether all nodes have been ~signç~l as timing receivers. If all nodes have been assigned then control is transferred to decision box 211 via line 207. If all nodes have not been assigned, 5 then control is transferred to instruction box 209 via line 208. If there are nodes which have not been assigned, then it is necessary to select the subset of nodesconnected to nodes which already have assigned timing sources and select the best stratum level among them. This step is similar to step 2 pt;lrc.ll"ed at instruction box 202. If more than one node has the best stratum level, all are selected. If any of the 10 nodes in the chosen subset produces i~ n~s which affect downstream clocks(i.e., do not incorporate phase buildout), these nodes are removed from the chosen subset. If all the nodes in the chosen subset produce in~r~illncnts~ do not remove any nodes from the chosen subset. Control is transferred as described above.
In decision box 211, it is necess~ry to determine whether there are more 15 nodes in the network with the same stratum level as the newly assigned master node.
If such additional nodes exist, then control is transferred to instruction box 200 via line 213. If no such additional nodes exist, then control is transferred to instruction 214 via line 212. When control is transferred from decision box 211 to instruction box 200, it is necessary to select a dirrelt;l-t node to be assigned as the master node.
In step 5, instruction 214 calls for computing the network synchronization pelrollllance for each synchronization plan related to a dirrerellt design~ted master clock node and, thereafter, choosing the synchronization plan which offers the best computed network synchronization performance. After con~idering all the network synchronization plans with the various nodes as possible 25 master, it is necess~ry to calculate the network synchronization performance. This p~Çcllllance is calculated as follows:
net_sync_perf= ~, f(daily_time_error(node), number_of_links(node)) nodes where ~ represents the s...~"~.~lion of the synchronization performance over all the nodes in the network. After computing the network synchronization performance, it 30 is possible to choose the network synchronization plan with the best (i.e., the lowest) network synchronization performance. The timing master for the network will be the master node indicated in that synchronization plan. The flow of synchronization timing inrc,llllalion through the network is indicated by each timing assignment ~03~01~
(arrow direction).
EXAMPLE
To illustrate the above-described method, the teleco~ ications network of FIG. 1 is considered. In this example, there are seven digital equipment S named A through G that are interconnected as shown in FIG. 1. The performance parameters of each e4uiplllent and link have been indicated in the tables above.The method to find the optimal synchronization plan proceeds through several iterations of the method. Each iteration is described in detail below. The number of iterations will be equal to the number of nodes receiving timing. The 10 total number of iterations increases linearly with the number of possible masters.
Iteration I: for Master = Node A
Step 1. The best stratum level of all nodes in the network is 2. There are two nodes with the best stratum levels, namely nodes A and B. Initially, select node A as the master node.
15 Step 2. Nodes B, D, and E are connected to node A. Among these three nodes, node B has the best stratum level. Therefore, node B is selected as the best node among B, D, and E.
Step 3. Since there is only one node selected at Step 3, and since there is only one link between A and B, node B is assigned timing from node A over link AB. The 20 daily timing error of node B is 3 microseconds and its daily output errors is 0.
Therefore, nodes A and B are assigned timing.
Step 4. Nodes D and E are the only unassigned nodes connected to the timing assigned nodes A and B. Since both nodes D and E have the same stratum level, they are both selected as the best nodes. Both nodes D and E have phase buildout25 and do not produce impairments, so they remain in the chosen subset.
Iteration 2: for Master = Node A
Step 3. Calculate the daily time error performance of node D over link AD and ofnode E over link AE as follows:
Node D daily_time_error = (5 + O)X 0.07 = 0.35 Node E daily_time_error_-_(20 + O)X 0.65 = 13.0 Since the pelrollllance of node D is better than node E, node D is assigned the timing source node A over link AD. The daily number of output errors S from node D is zero. Th~lcfol~;, nodes A,B, and D are ~ign~l timing.
Step 4. Nodes C, E, and G are the only unassigned nodes connected to the timing assigned nodes A, B, and D. Node E has the best stratum level and is chosen as the best node.
Iteranon 3: for Master = Node A
10 Step 3. Calculate the daily time error pelrol,llance of node E over links AE and DE
as follows:
Link AE daily_time_error = (20 + 0) x 0.65 - 13.0 Link DE daily_time_error = (3 + O)x 0.65 + 0.35 = 2.3 Since the pelrc,llllallce of node E is better when timing comes from node D over link 15 DE than from node A over link AE, node E is assigned the timing source node Dover link DE. The daily number of output errors from node E is 0. Therefore, nodes A, B, D, and E are assigned timing.
Step 4. Nodes C and G are the only unassigned nodes connected to the timing ~igned nodes A, B, D, and E. They both have the same stratum level and, 20 therefore, are both chosen. Both nodes C and G do not incorporate phase buildout and produce errors, thus they are both chosen.
Iteration 4: for Master = Node A
Step 3. Since both chosen nodes produce impairments, the daily output errors of the nodes are calculated. Calculate the daily output errors of node C over link CD and 25 node G over links DG and EG as follows:
Node C, Link CD daily_output_error = (4 + 0) X 2 = 8 Node G, Link DG daily_output_error = (7 + 0) X 1 = 7 Node G, Link EG daily_output_error = (12 + 0) X 1 = 12 Since the number of daily output errors is lower for node G than node C, node G will S be ~signed timing. Calculate the daily time error of node G over links DG and EG
as follows:
Link DG daily_time_error = (7 + 0) X 100 + 0.35 = 700.35 Link EG daily_time_error = (12 + 0) X 100 + 2.3 = 1202.3 Since the performance of node G is better when timing comes from node D over link 10 DG than from node E over link EG, node G is assigned the timing source node Dover link DG. The daily number of output errors from node G is 7. Therefore, nodes A, B, C, E, and G are assigned timing.
Step 4. Nodes C and F are connected to the assigned nodes D and G. Among these two nodes, node F has the best stratum level. Therefore, node F is selected as the 15 best node.
Iteration S: for Master = Node A
Step 3. Since there is only one node selected at Step 2, and since there is only one link belwe~ll G and F, node F is assigned timing from node G over link FG. The daily timing error of node F is given by Node F daily_time_error = (4 + 7) X 1.0 = 11.0 The daily number of output errors is 0. Therefore, all nodes except C are assigned timing.
Step 4. Since node C is the only node without a timing assignment, it is chosen.
203~012 Iteration 6: for Master = Node A
Step 3. Calculate the daily time error performance of Node C over links CD and CF
as follows:
Link CD daily_time_error = (4 + 0) X 250 + 3.35 = 1000.35 S Link CF daily_time_error = (3 + 0) X 250 + 11.0 = 761.0 Since the p~,.ro~ ance of node C is better when timing comes from node F over link CF than from node D over link CD, node C is assigned the timing source node F
over link CF.
Step 4. All nodes are assigned timing. There is one node, node B, with the same 10 stratum level as node A, which has not been chosen as a possible master node. Go to step 1 and choose node B as the master node.
Iterations for Master = Node B
There will be a total of six (6) iterations for Master = node B. The result of these iterations is shown in FIG. 4.
15 Step 5. When the procedure has been repeated with node B as the master node, all nodes with the best stratum level will have been chosen as a possible master node.
The colllpu~a~ion results which are used to develop the synchronization plans for the digital network of FIG. 1 as shown in FIGs. 3 and 4 are shown in the following tables. The first table is developed using node A as the master; the second 20 table is developed using node B as the master.
DAILY DAILY
NODE TIME ERROR OUTPUT ERROR
B 3.0 0 C 761.0 6 D 0.35 0 E 2.3 0 F 11.0 0 G 700.35 7 5 and DAILY DAILY
NODETIME ERROROUTPUT ERROR
A 0.7 0 B
C 761.7 6 D 1.05 0 E 3.0 0 F 11.7 0 G 701.05 7 15 Step S of the method is used to co~ the network synchronization performance of the two possible plans (one with node A as the timing master and one with node B as the timing master). The nclwolk pc;lrolmallce for the plan using node A as the timing master is better than the one using node B. Thus, the first synchronization plan, with A being the timing master, will be the synchronization plan for the 20 network.
Claims (5)
1. A method for planning synchronization clock distribution for a network of interconnected digital equipment wherein each digital equipment is represented as a node interconnected to other nodes by links, the digital equipment characterized by a set of equipment performance parameters and each link characterized by at least one link performance parameter, the method comprising:
assigning one node at the highest stratum level as the master clock node;
forming a group of all unassigned nodes connected to the assigned node or nodes;
selecting a subgroup of all nodes from the group wherein the subgroup includes all nodes having stratum levels which are equal or highest within the group;
limiting the subgroup to nodes which have a desired characteristic;
determining synchronization performance of each node in the subgroup according to a predetermined criterion;
assigning one node from the subgroup as a clock timing receiver wherein the one node exhibits synchronization performance better than synchronization performance for all other nodes in the subgroup; and iterating the method at the forming step until all nodes are assigned as timing receivers.
assigning one node at the highest stratum level as the master clock node;
forming a group of all unassigned nodes connected to the assigned node or nodes;
selecting a subgroup of all nodes from the group wherein the subgroup includes all nodes having stratum levels which are equal or highest within the group;
limiting the subgroup to nodes which have a desired characteristic;
determining synchronization performance of each node in the subgroup according to a predetermined criterion;
assigning one node from the subgroup as a clock timing receiver wherein the one node exhibits synchronization performance better than synchronization performance for all other nodes in the subgroup; and iterating the method at the forming step until all nodes are assigned as timing receivers.
2. The method as defined in claim 1 further comprising:
assigning a different node having a stratum level equal to the stratum level of the one node as the master clock node and performing the iterating step.
assigning a different node having a stratum level equal to the stratum level of the one node as the master clock node and performing the iterating step.
3. The method as defined in claim 2 further comprising:
computing network synchronization performance for each synchronization plan related to a different assigned master clock node; and choosing the synchronization plan which offers an optimum network sychronization performance.
computing network synchronization performance for each synchronization plan related to a different assigned master clock node; and choosing the synchronization plan which offers an optimum network sychronization performance.
4. The method as defined in claim 1 comprising:
indicating a timing flow along a link into the clock timing receiver after the receiver has been assigned.
indicating a timing flow along a link into the clock timing receiver after the receiver has been assigned.
5. The method as defined in claim 1, wherein the desired characteristic includes the existence of phase buildout for the equipment associated with the node.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/503,205 US5068877A (en) | 1990-04-02 | 1990-04-02 | Method for synchronizing interconnected digital equipment |
| US503,205 | 1990-04-02 |
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| CA2037012A1 CA2037012A1 (en) | 1991-10-03 |
| CA2037012C true CA2037012C (en) | 1996-10-22 |
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| US11922237B1 (en) | 2022-09-12 | 2024-03-05 | Mellanox Technologies, Ltd. | Single-step collective operations |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4142069A (en) * | 1977-06-20 | 1979-02-27 | The United States Of America As Represented By The Secretary Of The Army | Time reference distribution technique |
| US4736393A (en) * | 1986-04-16 | 1988-04-05 | American Telephone And Telegraph Co., At&T Information Systems, Inc. | Distributed timing control for a distributed digital communication system |
| JPH0783360B2 (en) * | 1986-06-27 | 1995-09-06 | 三菱電機株式会社 | Synchronization method |
| JPH01112838A (en) * | 1987-10-26 | 1989-05-01 | Nec Corp | Network clock synchronization system |
| JPH01116862A (en) * | 1987-10-30 | 1989-05-09 | Nec Corp | Clock synchronizing system for multiprocessor system |
| US4939752A (en) * | 1989-05-31 | 1990-07-03 | At&T Company | Distributed timing recovery for a distributed communication system |
| JPH03250829A (en) * | 1990-02-28 | 1991-11-08 | Fujitsu Ltd | Clock topology constitution method for digital synchronous private network |
-
1990
- 1990-04-02 US US07/503,205 patent/US5068877A/en not_active Expired - Lifetime
-
1991
- 1991-02-25 CA CA002037012A patent/CA2037012C/en not_active Expired - Fee Related
- 1991-03-06 AU AU72667/91A patent/AU620755B2/en not_active Ceased
- 1991-03-26 EP EP19910302595 patent/EP0450828A3/en not_active Withdrawn
- 1991-04-01 JP JP3092609A patent/JPH04225647A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| EP0450828A2 (en) | 1991-10-09 |
| AU7266791A (en) | 1991-10-03 |
| EP0450828A3 (en) | 1992-09-23 |
| JPH04225647A (en) | 1992-08-14 |
| US5068877A (en) | 1991-11-26 |
| AU620755B2 (en) | 1992-02-20 |
| CA2037012A1 (en) | 1991-10-03 |
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