CA2041222C - Pulse width modulated self-clocking and self-synchronizing data transmission telephonic switching system - Google Patents
Pulse width modulated self-clocking and self-synchronizing data transmission telephonic switching systemInfo
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- CA2041222C CA2041222C CA002041222A CA2041222A CA2041222C CA 2041222 C CA2041222 C CA 2041222C CA 002041222 A CA002041222 A CA 002041222A CA 2041222 A CA2041222 A CA 2041222A CA 2041222 C CA2041222 C CA 2041222C
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K9/00—Demodulating pulses which have been modulated with a continuously-variable signal
- H03K9/08—Demodulating pulses which have been modulated with a continuously-variable signal of duration- or width-mudulated pulses or of duty-cycle modulated pulses
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4902—Pulse width modulation; Pulse position modulation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/06—Speed or phase control by synchronisation signals the synchronisation signals differing from the information signals in amplitude, polarity or frequency or length
Abstract
Transmissions of synchronous digital data from a master control unit (50A) to a slave, network termination unit (50B) are via a pulse width modulated data stream including pulse width modulated binary code pulses (20, 22) with a pulse width modulated synchronization pulse (24) all of which have a preselected leading edge transition (28) at the same point in each cycle of a master clock signal. A clock signal is derived at the network termination unit (50B) from the received pulse width modulated binary data stream for decoding and for nonself-clocking, synchronous transmissions from the slave, network termination unit (50B) to the master, control unit (50A). The phase synchronization pulse (24) is employed to maintain phase synchronization between the transmission to and from the control unit (50A).
Description
~0~1~22 -BAC~G~OUND 0~ T~E lNv~ ON
This invention gener~lly rel~tes to a switching system for controllin~ communication between transceiving informational sources of a teleco~munications network and, more specifically, to such a system in which timing synchronizational information is encoded directly in the digital information being transceived.
In a modern digital telephonic switching system, audio signals between individual subscriber units are PCM encoded and transceived on a time division multiplexing basis. Circuits know as network termination units have means for interfacing with a group of analog or digital telephone lines and segmenting these lines into corresponding group of channels, or time slots, of a time division multiplexing system. The voice information or digital data on any incoming telephone line of the group is assigned to and is successively ~rovided during corresponding ones of a group of time slots for switching to other transceiving units of the system. The data which is in the plural time slots is then provided to a control unit for switching inEormation from any incoming channel to a selected outgoing channel. These control units also contain central processing elements for controlling this switching operation and also provide a central time base for synchronization of the switching operations.
Thus, it can be appreciated that there are several distinct types of information which must be conveyed between each of the control units and their associated network termination unit. The clock reference from the central time base must be transmitted from the control unit to the network termination unit in order to maintain the network termination unit in frequency synchronization with tne centrol time base of the control unit.
A phase reference must be passed from the control unit to the network termination unit in order to maintain the network termination unit in phase synchroniz~tion with the central time base of the control unit. There, of course, must be a voice or .~
`` . 20412~2 data ~ath from the networ~ termination unit to ~he control unit and vice versa. A control data link must also be provided between the network ~ermination unit and the control unit for both passing messages to the networ~ termination unit to control its oper~tion and, on the otner h nd, to pass messages from the network termination unit to the control in response to commands from the control unit.
If a separate wire were used for each of the above types of inform~tion, six different wires would be required per control unit, network termination unit pair. In a large switching system, even presuming twenty-four channels per network termination unit, the total number of wires, or connections, would be excessive. This fact has become more significant as the size of the individual control and network termination units decreases due to circuit miniaturization which reduces the space available for wire connectors for those units. Accordingly, there is a strongly felt need to reduce the number of wire connections between control and network termination unit pairs to a minimum.
It is, of course, generally known to use time division multiplexing to reduce the number of wires required for coveying different types of information. Referring to Fig. lA, a data encoding scheme commonly referred to as Manchester coding, or bi-phase unipolar encoding is also known in which synchronized information is inherently carried by the data being transmitted, i.e. is self-clocking, so a single wire can simultaneously carry both data and clock information. Binary ones and zeros are represented by negative and positive transitions, and, although a transition occurs once during each cycle, wAether the transition will be positive or negative is indeterminate, thereby requiring detection for ~oth types of transitions for full clock extraction. Moreover, the transitions occur during the middle of the clock period instead of at the beginning of each cycle.
Another scheme known as RZ (return to zero) binary bi2olar coding is also self-clocking. However, it undesirably requires a bipolar voltage source, since binary ones and zeros are 122'~
represented by positive ~nd negative voltage pulses during the start of each cycle which is incompatible with most modern day tel~phonic switching circuitry. A system known as RZ bin ry unipolar coding does not re~uire a bipolar source, but it is only partially self-clocking, since pulses do not occur during each clock cycle. A clock detection for such an RZ data source is shown in U.S. patent 3,894,246 issued July 8, 1973 to Torgrim and assigned to the assignee of this invention. Mo other coding scnemes using a pulse format are known which are self-clocking or which 2rovide for phase synchron zation and, thus any known unipolar data line will have to be accompanied by a companion synchronization line.
SUMMARY OF TH~ lNV~ lON
It is, therefore, the object of the present invention to provide apparatus and methods for synchronous, digital communication in which a digital pulse width modulated encoding scheme is employed which overcomes the disadvantages of using the known self-clocking encoding schemes. Non-self clocking binary signal are pulse width encoded to generate a data stream which is unipolar, capable of providing transitions of predetermined sense (positive, preferably, or negative) and which is completely self-clocking, a pulse width modulated pulse being generated at the beginning of each clock cycle. In its most basic application, binary ones correspond to pulses having one width and binary zeros correspond to positive pulses of another width. In order to obtain phase synchronization, ~s well as timing synchronization, a third pulse of a width differing from the widths of binary ones and binary zeros is generatèd as a phase synchroniz~tion pulse once during each byte or twice during other blocks of data.
Employing the aoove encoding scheme of the invention for data and clock pulses, an adv~ntageous method of communicating in a synchronous digital communicating network is provided which enables full duplex, synchronous communication between any two ter~ina.ion 2oints in the n~twork thcough a single pair oE wire connections without need of additional connections for either clock pulses or phase synchroniz~tion ?ulses. According to this method, a series of digital pulses in nonself-clocking format from one termin3tion ~oint is convetted to the self-clocking format noted above in which binary ones, binary z~sros and phase synchronization pulses are respectively represented by pulses of varying widtns before being transmitted to another termination point. At the other termination point, a clock signal is extracted from the positive transitions of the pulses which occur at the beginning of each clock cycle; this extracted clock signal is then used to decode the pulse width modulated data pulse back to a nonself-clocking format. The synchronization pulses are used to maintain phase synchronization between the termination points.
The objective of the invention is also achieved in part in the application of the above method in switching systems for controlling communication between sources of a telecommunications network of transceiving informational sources. According to one aspect of the inv~ntion, the switching system has a control unit connected with some of the sources and a network termination unit connected with other ones of the sources. The control unit includes means for encoding information from said sources in a serial, pulse width binary format and means for serially transmitting pulse width binary encoded pulses of said encoding information at a preselected transmission bit rate. The network termination unit includes means responsive to the serially transmitted, pulse width binary encoded pulses to extract tnerefrom a clock signal and means responsive to said clock signal for synchronous decoding of the serially transmitted, pulse width binary encoded pulses for provision to said other ones of said sources connected with the network termination unit.
In keeping with another asQect of the invention, the network termination unit also has an encoder for encoding data from the sources connected there~ith into a pulse format and means responsive to the clock signal for transmitting the encoding data 20~1222 to the control unit in Lrequency synchronism with said transmission bit rate.
It is also an ob~ect or the invention to provide a switching system in which synchronization pulses are employed to enable both timing and phase synchronization. In this system, the control unit has means for encoding information from said sources as a series of data pulses, means for generating pulse width encoded synchronization pulses, and means for transmittinq said series of data pulses and pulse width encoded synchronization pulses together on a time division multiplexing basis at a preselected bit rate. The network termination unit has means responsive to at least said pulse width encoded synchronization pulses to derive a clock signal, means responsive to said clock signal for synchronous decoding of the series of data pulses for connection to said other ones of the sources connected with the network termination unit, and means responsive to said pulse width encoded synchronization pulses to control synchronization of the synchronous decoding means of the network termination unit with the encoding means of the control unit.
Prefera~ly, the network termination unit has means for transmitting data from the other ones of the sources connected thereto to the control unit. ThiS includes means responsive to said synchronization pulses for maintaining said data transmitted to the control unit in phase synchronization with the pulse width encoded synchronization pulses from the control unit. A phase synchronization acquisition circuit is provided which includes means associated with said decoding means for generating synchronization pulse receipt signals in response to receipt of said synchronization pulses from the control unit, a counter of said encoding means responsive to said synchronization pulse receipt signals to count clock pulses in phase synchronism with the synchronization pulses, me-ns res?onsive to said counter for generating a synchroniz~tion control signal to indicate when the next synchronization pulse should be received if the counter is in phase synchronism with the synchronization pulses, and means responsive to said synchroniza~ion pulse rec2ipt signal and said synchronization control signal not being generated within a preselected time period of one another for generating an out-of-sync signal. Means responsive to the out-of-sync signal being provided to resynchronize the counter.
Preferably, full duplex synchronous communication is provided between the control unit and the network termination unit. This objective is achieved by providing the control unit with means for encoding information from a series of data pulses, means for decoding information received in a series of data pulses, means for generating synchronization pulses of a preselected width differing from those of the data pulses, and means for transmitting said encoded information and said synchronization pulses together at a preselected bit rate. Similarly, the network termination unit includes means responsive to at least said synchronization pulses to derive a clock signal, means responsive to said clock signal for synchronous encoding and transmission of information from said other one of the sources to the control unit, and means responsive to said synchronization pulses to control phase synchronization of the encoding and transmitting means of said network termination unit with said decoding means of the control unit.
In accordance with an embodiment of the invention, 2s in a telecommunications network of transceiving informational sources, the improvement being a switching interface system for communication between the sources is comprised of a control unit connected with some of the sources including apparatus for encoding information from the sources in a serial, pulse width binary format, and apparatus for serially transmitting pulse width binary encoded pulses of the encoding information at a preselected transmission bit rate; and a network termination unit connected with other ones of the sources including apparatus responsive to the serially transmitted, pulse width binary encoded pulses for extracting therefrom a clock signal, and apparatus responsive to the clock signal for synchronous S decoding of the serially transmitted, pulse width binary encoded pulses for provision to the other ones of the sources connected with the network termination unit.
In accordance with another embodiment, in a telecommunications network of transceiving informational sources, the improvement being a switching interface system for communication between the sources is comprised of a control unit connected with some of the sources including apparatus for encoding information from the sources in a serial, pulse width binary format, and apparatus for serially transmitting pulse width binary encoded pulses of the encoding information at a preselected transmission bit rate; and a network termination unit connected with other ones of the sources including apparatus responsive to the serially transmitted pulse width binary encoded pulses for extracting therefrom a clock signal including apparatus for generating the clock signal at a frequency which is a preselected multiple of the transmission bit rate, and apparatus responsive to the clock signal for synchronous decoding of the serially transmitted, pulse width binary encoded pulses for provision to the other ones of the sources connected with the network termination unit.
In accordance with another embodiment, in a telecommunications network of transceiving informational sources, the improvement being a switching interface system for communication between the sources is comprised of a control unit connected with some of the sources including apparatus for encoding information from the sources in a - 6a -,~
.~ ;
serial, pulse width binary format, apparatus for serially transmitting pulse width binary encoded pulses of the encoding information at a preselected transmission bit rate, and apparatus for periodically inserting phase S synchronization pulses into the serially transmitted pulse width binary encoded pulses to provide phase synchronizational information to a network termination unit;
and the network termination unit connected with other ones of the sources including apparatus responsive to the serially transmitted, pulse width binary encoded pulses to extract therefrom a clock signal, and apparatus responsive to the clock signal for synchronous decoding of the serially transmitted, pulse width binary encoded pulses for provision to the other ones of the sources connected with the network termination unit, apparatus responsive to the phase synchronization pulses to transmit data to the control unit in phase synchronism with the pulse width binary encoded data pulses at the preselected transmission bit rate including a phase synchronization acquisition circuit for generating a synchronization control signal, and apparatus responsive to the synchronization control signal for controlling the synchronous transmission of data to the control unit to maintain the transmission of data to the control unit in synchronization with the synchronization pulses generated thereby.
In accordance with another embodiment, in a telecommunications network of transceiving informational sources, the improvement being a switching interface system for communication between the sources is comprised of a control unit connected with some of the sources including serial, pulse width binary format, apparatus for serially transmitting pulse width binary encoded pulses of the encoding information at a preselected transmission bit rate, -~ 35 -6b -and apparatus for periodically inserting phase synchronization pulses into the serially transmitted pulse width binary encoded pulses to add phase synchronizational information thereto; and a network termination unit S connected with other ones of the sources including apparatus responsive to the serially transmitted, pulse width binary encoded pulses to extract therefrom a clock signal, apparatus responsive to the clock signal for synchronous decoding of the serially transmitted, pulse width binary encoded pulses for provision to the other ones of the sources connected with the network termination unit, and apparatus responsive to the phase synchronization pulses to transmit data to the control unit in phase synchronism with the pulse width binary encoded data pulses at the preselected transmission bit rate including a counter triggered by the clock signal, apparatus responsive to the counter for identifying time division multiplexing channels of the telecommunication network, and apparatus responsive to the binary encoded pulses for maintaining the counter in phase synchronization with the phase synchronization pulses of the control unit.
In accordance with another embodiment, in a telecommunications network of transceiving informational sources, the improvement being a switching interface system 2s for communication between the sources is comprised of a control unit connected with some of the sources including apparatus for encoding information from the sources as a series of data pulses in the serial pulse width binary format, apparatus for generating pulse width encoded synchronization pulses, and apparatus for transmitting the series of data pulses and pulse width encoded synchronization pulses together on a time division multiplexing basis at a preselected bit rate; and a network -r ~ 35 - 6c -~, i termination unit connected with other ones of the sources including apparatus responsive to at least the pulse width encoded synchronization pulses to derive a clock signal, apparatus responsive to the clock signal for synchronous S decoding of the series of pulse width encoded data pulses for connection to the other ones of the sources connected with the network termination unit, and apparatus responsive to the pulse width encoded synchronization pulses to control synchronization of the synchronous decoding apparatus of the network termination unit with the encoding apparatus of the control unit.
In accordance with another embodiment, in a telecommunications network of transceiving informational sources, the improvement being a switching interface system for communication between the sources is comprised of a control unit connected with some of the sources including apparatus for encoding information from the sources as a series of data pulses, apparatus for generating pulse width encoded synchronization pulses, and apparatus for transmitting the series of data pulses and pulse width encoded synchronization pulses together on a time division multiplexing basis at a preselected bit rate; and a network termination unit connected with other ones of the sources including apparatus responsive to at least the pulse width 2s encoded synchronization pulses to derive a clock signal, apparatus responsive to the clock signal for synchronous decoding of the series of data pulses for connection to the other ones of the sources connected with the network termination unit, apparatus for transmitting data from the other ones of the sources connected thereto to the control unit which includes apparatus responsive to the synchronization pulses for maintaining the data transmitted to the control unit in phase synchronization with the pulse 3s - 6d -width encoded synchronization pulses from the control unit including a phase synchronization acquisition circuit responsive to the synchronization pulses received at the network termination unit to develop a synchronization S control signal for controlling the phase synchronization of the encoding apparatus, and apparatus responsive to the pulse width encoded synchronization pulses to control synchronization of the synchronous decoding apparatus of the network termination unit with the encoding apparatus of the control unit.
In accordance with another embodiment in a telecommunications network of informational sources, the improvement being a switching interface system for communication between the sources comprised of a control unit connected with some of the sources including apparatus for binary encoding information from a series of data pulses, apparatus for decoding information received in a series of data pulses, apparatus for generating a series of synchronization pulses of a preselected width differing from width of the data pulses, and apparatus for transmitting the encoded information and the synchronization pulses together at a preselected bit rate; and a network termination unit connected with other ones of the sources including apparatus responsive to at least the synchronization pulses to derive a clock signal, apparatus responsive to the clock signal for synchronous encoding and transmission of information from the other one of the sources to the control unit, and apparatus responsive to the synchronization pulses to control phase synchronization of the encoding and transmitting apparatus of the network termination unit with the decoding apparatus of the control unit.
In accordance with another embodiment, in a telecommunications network of informational sources, the 3s - 6e --improvement being a switching interface system for communication between the sources is comprised of a control unit connected with some of the sources including apparatus for encoding information from a series of data pulses, S apparatus for decoding information received in a series of data pulses, apparatus for generating synchronization pulses of a preselected width differing from width of the data pulses, and apparatus for transmitting the encoded information and the synchronization pulses together at a preselected bit rate; and a network termination unit connected with other ones of the sources including apparatus responsive to at least the synchronization pulses to derive a clock signal, apparatus responsive to the clock signal for synchronous encoding and transmission of information from the other ones of the sources to the control unit, apparatus responsive to the synchronization pulses to control phase synchronization of the encoding and transmitting apparatus of the network termination unit with the decoding apparatus of the control unit, apparatus responsive to the synchronization pulses from the control unit for detecting phase nonsynchronization with the control unit, and apparatus responsive to the nonsynchronization detecting apparatus to alter the timing of the encoding and transmitting apparatus to eliminate the condition of nonsynchronization.
In accordance with another embodiment, in a telecommunications network of informational sources, the improvement being a switching interface system for communication between the sources is comprised of a control unit connected with some of the sources including apparatus for encoding information from a series of data pulses, apparatus for decoding information received in a series of data pulses, apparatus for generating synchronization pulses - 6f -of a preselected width different from width of the data pulses, and apparatus for transmitting the encoded information and the synchronization pulses together at a preselected bit rate; and a network termination unit S connected with other ones of the sources including apparatus responsive to at least the synchronization pulses to derive a clock signal, apparatus responsive to the clock signal for synchronous encoding and transmission of information from the other one of the sources to the control unit, apparatus responsive to the synchronization pulses to control phase synchronization of the encoding and transmitting apparatus of the network termination unit with the decoding apparatus of the control unit, and apparatus responsive to the synchronization pulses from the control unit for transmitting to the control unit an indication of phase nonsynchronization.
In accordance with another embodiment, a method of communication in a synchronous digital data communication network is comprised of the steps of receiving at a controller circuit a stream of binary data pulses in a nonself-clocking format in which clock signals are not carried with the stream of binary data pulses; converting the nonself-clocking data stream to a corresponding self-clocking pulses width modulated binary data stream;
2s transmitting the pulse width modulated binary data stream to a termination unit of the network; extracting a clock signal from the transmitted, binary pulse width modulated data stream received at the termination unit; and employing the extracted clock signal to decode the transmitted, pulse width modulated data stream to a stream of binary data pulses in nonself-clocking format.
In accordance with another embodiment, a method of communication in a synchronous digital data communication - 6g -.
network is comprised of the steps of receiving at a controller circuit a stream of binary data pulses in a nonself-clocking format in which clock signals are not carried with the stream of binary data pulses; converting the nonself-clocking data stream to a corresponding self-clocking pulse width modulated binary data stream;
transmitting the pulse width modulated data stream to a termination unit of the network with preselected transitions at a preselected time during each clock cycle; extracting a clock signal from the transmitted, pulse width modulated data stream received at the termination unit; and employing the extracted clock signal to decode the transmitted, pulse width modulated data stream to a stream of binary data pulses in nonself-clocking format.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing objects and advantageous features will be described and further advantageous features and objects of the invention will be made apparent from the detailed description of the preferred embodiment which will be given with reference to several figures of the drawing, in which:
Fig. lA is a table of prior art comparative waveforms of different encoding schemes including all known self-clocking encoding schemes discussed above in the background section;
Fig. lB is an illustration of the binary code represented by the waveforms of Fig. lA as represented using the binary encoding scheme of the present invention;
Fig. 2 is a table of waveforms which more clearly illustrate 3s - 6h -~1 the preferred ternary encoding scheme of the invention;
Fig. 3 is a block diagram of a telephonic network in which the invention is employed;
Fig. 4A is a block diagram of the digital port circuit of the network of Fig. 3 in which a network link interface circuit of the invention is employed as a network terminal unit;
Fig. 4B is a block diagram of a network shelf controller (NSC) functional block of Fig. 3 in which network link interface circuit of the invention is employed as a control unit;
Fig. 5 is a simplified block diagram of the network link interface circuit operating as a control unit in the NSC circuit of Fig. 4B and the network link interface circuit functioning as a network termination unit in the digital port circuit of Fig.
4A;
Fig. 6A is a circuit diagram of the transmit link encoder section of the network termination unit of Fig. 5;
Fig. 6B is a circuit diagram of the receive link section of the network termination unit of Fig. 5;
Fig. 6C depicts illustrative comparative waveforms of different designated points in the receive link section of Figs.
6A and 6B;
Fig. 6D is a continuation of Fig. 6C;
Fig. 6E is a continuation of Fig. 6D;
Fig. 6F is a continuation of Fig. 6E;
Fig. 7A is a circuit diagram of the transmit link encoder section of the control unit of Fig 5, and is located out of consecutive order on the same page as Fig. 4B;
Fig. 7B is a circuit diagram of the receiver link decoder section of the control unit of Fig. 5;
Fig. 7C depicts comparative waveforms at various designated points in the receiver link decoder section of Fig 7B;
Fig. 7D depicts illustrative comparative waveforms at different designated points in the transmit link encoder section of Fig. 7A and of the receive link decoder in Fig. 7B;
Fig. 8 is a block diagram of a network link interface integrated circuit of Figs. 4A and 4B illustrating the various inputs and outputs of Figs. 4A and 4B;
Fig. 9 is a block diagram of a system configuration in which the networ!c link in~rfac~ circuit of Fig. 8 is variously employed;
Fig. 10 illustrates ~ne signal to v~rious mode pins and master/slave pin of the network link interface circuit o~ Fig. 8 re~uired to achieve different modes of operation required for the dif~erent applications shown in Fig. ~;
Fig. 11 is anot~er functional block diagram of the network link interface circuit to illustrate the various interfaces it has with other elements of the network;
Fig. 12 illustrates the preferred network link format employed with tAe present invention;
Fig. 13 shows the message format employed with the present invention; and Figs. 14 - 43 show the contents of various registers of the network link interface circuit of Fig. 8.
DETAILED DESCRIP~ION
Referring now to the drawing, particularly Figs. lB and 2, the ternary encoding system which enables the many advantageous features of the invention is seen to employ pulses of three different widths. Preferably, the logic zero pulse 20 has the narrowest width, the logic one pulse 22 has the next largest width, approximately twice that of the logic zero pulse 20, and the synchronization, or sync, pulse 24 has the largest width, approximately three times that of the logic zero pulse 20. The entire clock period 26 is preferably four times the width of the logic zero pulse, so that at least one-fourth of the clock period remains without a logic one pulse even when a sync pulse 24 is generated. Unlike other systems shown in Fig. lA, the leading edge of the pulse 20, 22 or 24 coincide with the start of each timing period and the time between the leading edges of successive pulses is always equal to the clock period 2~. Also, a c~de pulse is generated for each ~nd every clock pulse.
Referring now to Fic. 3, t~e invention is employed to interface various elements of a network subsystem 29 which, in turn, is connected with a small business exchange (SBX) bus 30 of a control subsystem, and the elements of a network termination subsystem. Communication of the elements of the subsystem with a central controller and a central memory (not shown) of the telephonic switching system is through means of an SBX bus 30.
The control subsystem of bus 30 is preferably a 68020/68030 microprocessor based multiprocessor, distributed processing system which is capable of either simplex or duplex operation.
The network subsystem 29 consists of a system clock, or CLK, 32 and four interactive switching/control modes (only two shown), each comprising a single stage, non-blocking, 772 channel time slot interchanger, or TSI, 34. Most of these channels (768) are broken down into thirty-two groups of twenty-four channels for interface over high speed serial interfaces known as network links to transition circuits of the network termination subsystem 27. A network shelf controller, or NSC, circuit 36 connected to the TSI 34 has a 68000 microprocessor with two Mbytes of dynamic random access memory (DRAM) to provide processing capability of signaling activity on the 768 channels of each switch mode.
Within the NSC circuit 36, the 768 channel parallel time division multiplexing, or TDM, bus to and from the TSI circuit (not shown) is multiplexed into a thirty-two, twenty-four channel 3.088 MHz serial links, or network links, to and from the network termination subsystem 27. The TSI circuit 34 provides access to higher level processing for itself and the NSC circuit 36 via an SBX interface (not shown) to an SBX circuit residing on the control subsystem secondary bus 30. The central controller memory and central controller are loaded via this secondary bus 30.
The circuits which form the network termination subsystem 27 include a DAS, or digital audio source, 37 for providing tones, announcements and messages; a basic rate line, or BRL, circuit 38; a primary rate interface circuit, or PRI, 40; one or more DSl port circuits 42; and a digital signal processing, or DSP, circuit 44. The BRL circuit 38 provides system access to agent and supervisory consoles, while the PRI circuit 40 provides termination of the twenty-fourth 64 Kbit channel of the TI
digital trunk and also has all the features of a DSl port circuit 42. The DSl port circuit 42 provides digital Tl trunk access ~. 204 1 222 into the system. Pulse code modulation (PCM) channe~Care appropriately formatted and delivered to a DS1 transmit link 46.
Incoming information from the DS1 link 46 are recovered, buffered and delivered to network links for access to the network. The digital signal processing circuit 44 provides three separate TMS
320C25 digital signal processor based circuits for accessing eight of the twenty-four system channels that the DSP circuit 44 accesses over its link into the network. The DSP 44 processor receives functions for multifrequency (MF) and dual tone multi-frequency (DTMF) signals and can also be used for tone meteringfunctions in system diagnostics. As seen, advantageously a linkage 47 of only four wires connects each of the elements of the network termination subsystem 27 with the NSC 36 for a differential system or only two wires in a non-differential system.
The wire linkages 47 are made possible by virtue of use of network link interface, or NLI, integrated circuits 50 of Fig. 8.
As seen in Fig. 9, one or more NLI circuits 50, operating as network termination units 50B, are contained in each of the network termination subsystem elements 37, 38, 40, 42 and 44 and multiple NLI circuits, operating as control units 50A are contained in the NSC circuit 36 of the subsystem 29. Thus, the invention is preferably implemented through means of a single NLI
circuit 50 which, as will be explained in more detail, is capable of operation in different modes depending upon the application in which it is employed. Preferably, the NLI circuit is implemented in a large scale integrated circuit package having the input and output terminals shown in Fig. 8, although separate integrated circuit packages for each of the different modes of operation could be provided in lieu of a single package.
Referring to Fig. 4A for purposes of illustration, the network link interface circuit 50 is shown being used as a network termination unit, or slave, circuit 50B to interface one of the DSl port circuits 42, Fig. 8, with another network link 3s interface circuit 50, Fig. 9, operating as a control unit, or master unit, 50A.
The digital port control (DPC) 42 provides termination for a single DS1 trunk, -i 10 204l~2~
-interfacing lts twenty-four cnannels into the network. The DPC
42 provides for received DSl clock recovery, framing control, bufrering of received PCM and AB(CD) signaling data, as well as DSl line performance monitoring. Through the elastic buffer 53, the received DSl line's PCM and signaling data received on the DSl line 46 is synchronized with the a system clock appearing on line 51A. The data read from the elastic buffer 53 is transmitted on a network link 47 to the network. Information to be delivered to the outgoing DSl line 46 is similarly received from the network on a network link 47. The microprocessor monitors bit-error rate and slip performance of the DSl line, monitors for alarm conditions, controls loopback and other diagnostic facilities, and maintains communication with the control system via a datalink provided in the network link 47.
The received DSl signal from an office repeater bay (ORB), channel service unit (CSU), or galaxy voice circuit (GVC) port interface equipment is transformer-coupled and terminated on the DPC 42, as shown. Similarly, each DSl signal transmitted is transformer-coupled to the line. Three VLSI devices form the core of the DSl interface function of the DPC 50B: the line interface unit 51, the DSl transceiver 52, and the elastic buffer 53. These three VLSI devices are programmable by the DPC
microprocessor 54.
The DPC's line interface unit Sl provides appropriate termination and line driver circuitry for DSl line interface 46, in addition to a programmable line build-out function. The line interface unit 51 also recovers the clock signal on the receive line 46A, presenting this clock and the 1.544 MHz serial data thereon to the DSl transceiver 52 on lines 51A and SlB, respectively. Similarly, the line interface unit 51 will be pro~ided with 1.544MHz serial data by the DSl transceiver 52 on line 52A for transmission on the outbound DSl line 46. The received DSl line clock extracted by the line interface unit 51 may also be output by the DPC 42 for cabling to clock controlling circuitry of the network (not shown) as a reference input.
The DSl transceiver 52 locks on to the framing pattern ` 204 ~ 222 of the receive DSl line 46A and passes each channel of PCM and signaling data to the elastic buEfer 53 device. ~i~ error COUlltS
and alarm conditions of the received DSl line are maintained by the DSl transceiver 52. Similarly, PCM and signaling data to be transmitted on the outbound DSl line 46B are provided by the NLI
50B to the DSl transceiver 52 for framing.
The elastic buffer 53 buffers the received PCM and signaling information for eac~ channel to allow for variations between DSl line and system clocks. This data is read from the buffer by the NLI 50B in synchronism with the system clock. Preferably, the elastic buffer device 53 is programmed to perform signaling integration and freeze functions, if desired.
The NSC 36 encodes the system clock and synchronization signals onto the network link 47 and these signals are decoded by the NLI 50B and its associated phase-locked loop circuitry. The NLI 50B provides the mechanism for connecting the twenty-four channels of PCM and signaling data of the DPC 42 with the network. The NLI 50B also provides the means for the microprocessor 54 to communicate with the microprocessor of the NSC 36 over the 768kbps datalink of the network link 47. In redundant systems, the NLI 50B is connected to an NSC 36 in each network copy.
The DPC 42 contains a 68008 microprocessor 54 is a 68008IC
operating at six MHz. The major function of the microprocessor 54 is to program the DSl interface circuitry of the NLI 50B and to monitor the DSl line 40, reporting error and alarm conditions to the NSC 36. The microprocessor 54 will interact with the NLI
50B for communication with the NSC 36. In such case, the DS1 transceiver 52 will control the facilities data link 51A in ESF
DSl applications. Alternatively, for remote agent applications, the NLI 50~ will control a datalink to remote facility 57B
maintained in one of the 64kDps channels of the DPC 42.
The DPC 42 contains sixty-four kbytes of no wait-state EPROM
55 for boot loading and diagnostic code. The DPC 42 contains 32kbytes of no wait-state RAM 56 which can be optionally expanded to 96kbytes. The RA~ 56 can be write-protected in 8kbyte blocks.
` 21~412~2 Several resisters are also provided in the address space of the microprocessor 54 to allow for control and monitoring of various functions.
The microprocessor 54 can receive interrupts from the NLI 50B, the DSl transceiver 52, the line interface unit 51, the serial communications controller 57, and by a ten microsecond signa developed in the ~LI 5OB.
In order to provide for remote agent capability, the DPC 42 is provided with access to one of the twenty-four sixty-four kbps channels of the DSl line 46 to facilitate 'D' channel control in an ISDN '23B+D' environment. The received sixty-four kbps data is passed by the DSl transceiver 52 through the NLI 50B to a Z8530 serial communications device, or data links 57A and 57B, controlled by the microprocessor 54. The devices 57 will serialize the sixty-four kbps data stream and pass this through the NLI 50B to the DSl transceiver 52 for transmission to the outbound DSl line 46B. At a remote site, another DPC 42 will be present as the source and sink of this 'D' channel information.
The DPC acce~ts redundant -48VDC inputs and contains a DC-to-DC ~ower converter to derive the +5V required for its logic circuits.
Referring now to Fig. 4B, the NLI 50A is seen as used as a master, or control unit, 50A in the NSC 36 for interfacing the network subsystem 29 with elements of the network termination subsystem 27 of Fig. 3. The NSC 36 occupies a mid-level position in the three-tier distributed processing architecture of the switching network. The major role of the NSC 36 is in call processing during which it interacts with a higher order microprocessors of the control system through means of an SBX
interface shared with a TSI 34 with which it is associated. The NSC 36 also interacts with the DAS 37 and DSP 44 in the network termination subsystem 27 through means of network links. AB(CD) signaling bits of lines and trunks and Special-B signaling messages of thin-wire consoles (Special B signaling) are directly controlled by the NSC microprocessor 58. The 'ABS~ IC' ASIC has been developed to facilitate the NSC control of this signaling
This invention gener~lly rel~tes to a switching system for controllin~ communication between transceiving informational sources of a teleco~munications network and, more specifically, to such a system in which timing synchronizational information is encoded directly in the digital information being transceived.
In a modern digital telephonic switching system, audio signals between individual subscriber units are PCM encoded and transceived on a time division multiplexing basis. Circuits know as network termination units have means for interfacing with a group of analog or digital telephone lines and segmenting these lines into corresponding group of channels, or time slots, of a time division multiplexing system. The voice information or digital data on any incoming telephone line of the group is assigned to and is successively ~rovided during corresponding ones of a group of time slots for switching to other transceiving units of the system. The data which is in the plural time slots is then provided to a control unit for switching inEormation from any incoming channel to a selected outgoing channel. These control units also contain central processing elements for controlling this switching operation and also provide a central time base for synchronization of the switching operations.
Thus, it can be appreciated that there are several distinct types of information which must be conveyed between each of the control units and their associated network termination unit. The clock reference from the central time base must be transmitted from the control unit to the network termination unit in order to maintain the network termination unit in frequency synchronization with tne centrol time base of the control unit.
A phase reference must be passed from the control unit to the network termination unit in order to maintain the network termination unit in phase synchroniz~tion with the central time base of the control unit. There, of course, must be a voice or .~
`` . 20412~2 data ~ath from the networ~ termination unit to ~he control unit and vice versa. A control data link must also be provided between the network ~ermination unit and the control unit for both passing messages to the networ~ termination unit to control its oper~tion and, on the otner h nd, to pass messages from the network termination unit to the control in response to commands from the control unit.
If a separate wire were used for each of the above types of inform~tion, six different wires would be required per control unit, network termination unit pair. In a large switching system, even presuming twenty-four channels per network termination unit, the total number of wires, or connections, would be excessive. This fact has become more significant as the size of the individual control and network termination units decreases due to circuit miniaturization which reduces the space available for wire connectors for those units. Accordingly, there is a strongly felt need to reduce the number of wire connections between control and network termination unit pairs to a minimum.
It is, of course, generally known to use time division multiplexing to reduce the number of wires required for coveying different types of information. Referring to Fig. lA, a data encoding scheme commonly referred to as Manchester coding, or bi-phase unipolar encoding is also known in which synchronized information is inherently carried by the data being transmitted, i.e. is self-clocking, so a single wire can simultaneously carry both data and clock information. Binary ones and zeros are represented by negative and positive transitions, and, although a transition occurs once during each cycle, wAether the transition will be positive or negative is indeterminate, thereby requiring detection for ~oth types of transitions for full clock extraction. Moreover, the transitions occur during the middle of the clock period instead of at the beginning of each cycle.
Another scheme known as RZ (return to zero) binary bi2olar coding is also self-clocking. However, it undesirably requires a bipolar voltage source, since binary ones and zeros are 122'~
represented by positive ~nd negative voltage pulses during the start of each cycle which is incompatible with most modern day tel~phonic switching circuitry. A system known as RZ bin ry unipolar coding does not re~uire a bipolar source, but it is only partially self-clocking, since pulses do not occur during each clock cycle. A clock detection for such an RZ data source is shown in U.S. patent 3,894,246 issued July 8, 1973 to Torgrim and assigned to the assignee of this invention. Mo other coding scnemes using a pulse format are known which are self-clocking or which 2rovide for phase synchron zation and, thus any known unipolar data line will have to be accompanied by a companion synchronization line.
SUMMARY OF TH~ lNV~ lON
It is, therefore, the object of the present invention to provide apparatus and methods for synchronous, digital communication in which a digital pulse width modulated encoding scheme is employed which overcomes the disadvantages of using the known self-clocking encoding schemes. Non-self clocking binary signal are pulse width encoded to generate a data stream which is unipolar, capable of providing transitions of predetermined sense (positive, preferably, or negative) and which is completely self-clocking, a pulse width modulated pulse being generated at the beginning of each clock cycle. In its most basic application, binary ones correspond to pulses having one width and binary zeros correspond to positive pulses of another width. In order to obtain phase synchronization, ~s well as timing synchronization, a third pulse of a width differing from the widths of binary ones and binary zeros is generatèd as a phase synchroniz~tion pulse once during each byte or twice during other blocks of data.
Employing the aoove encoding scheme of the invention for data and clock pulses, an adv~ntageous method of communicating in a synchronous digital communicating network is provided which enables full duplex, synchronous communication between any two ter~ina.ion 2oints in the n~twork thcough a single pair oE wire connections without need of additional connections for either clock pulses or phase synchroniz~tion ?ulses. According to this method, a series of digital pulses in nonself-clocking format from one termin3tion ~oint is convetted to the self-clocking format noted above in which binary ones, binary z~sros and phase synchronization pulses are respectively represented by pulses of varying widtns before being transmitted to another termination point. At the other termination point, a clock signal is extracted from the positive transitions of the pulses which occur at the beginning of each clock cycle; this extracted clock signal is then used to decode the pulse width modulated data pulse back to a nonself-clocking format. The synchronization pulses are used to maintain phase synchronization between the termination points.
The objective of the invention is also achieved in part in the application of the above method in switching systems for controlling communication between sources of a telecommunications network of transceiving informational sources. According to one aspect of the inv~ntion, the switching system has a control unit connected with some of the sources and a network termination unit connected with other ones of the sources. The control unit includes means for encoding information from said sources in a serial, pulse width binary format and means for serially transmitting pulse width binary encoded pulses of said encoding information at a preselected transmission bit rate. The network termination unit includes means responsive to the serially transmitted, pulse width binary encoded pulses to extract tnerefrom a clock signal and means responsive to said clock signal for synchronous decoding of the serially transmitted, pulse width binary encoded pulses for provision to said other ones of said sources connected with the network termination unit.
In keeping with another asQect of the invention, the network termination unit also has an encoder for encoding data from the sources connected there~ith into a pulse format and means responsive to the clock signal for transmitting the encoding data 20~1222 to the control unit in Lrequency synchronism with said transmission bit rate.
It is also an ob~ect or the invention to provide a switching system in which synchronization pulses are employed to enable both timing and phase synchronization. In this system, the control unit has means for encoding information from said sources as a series of data pulses, means for generating pulse width encoded synchronization pulses, and means for transmittinq said series of data pulses and pulse width encoded synchronization pulses together on a time division multiplexing basis at a preselected bit rate. The network termination unit has means responsive to at least said pulse width encoded synchronization pulses to derive a clock signal, means responsive to said clock signal for synchronous decoding of the series of data pulses for connection to said other ones of the sources connected with the network termination unit, and means responsive to said pulse width encoded synchronization pulses to control synchronization of the synchronous decoding means of the network termination unit with the encoding means of the control unit.
Prefera~ly, the network termination unit has means for transmitting data from the other ones of the sources connected thereto to the control unit. ThiS includes means responsive to said synchronization pulses for maintaining said data transmitted to the control unit in phase synchronization with the pulse width encoded synchronization pulses from the control unit. A phase synchronization acquisition circuit is provided which includes means associated with said decoding means for generating synchronization pulse receipt signals in response to receipt of said synchronization pulses from the control unit, a counter of said encoding means responsive to said synchronization pulse receipt signals to count clock pulses in phase synchronism with the synchronization pulses, me-ns res?onsive to said counter for generating a synchroniz~tion control signal to indicate when the next synchronization pulse should be received if the counter is in phase synchronism with the synchronization pulses, and means responsive to said synchroniza~ion pulse rec2ipt signal and said synchronization control signal not being generated within a preselected time period of one another for generating an out-of-sync signal. Means responsive to the out-of-sync signal being provided to resynchronize the counter.
Preferably, full duplex synchronous communication is provided between the control unit and the network termination unit. This objective is achieved by providing the control unit with means for encoding information from a series of data pulses, means for decoding information received in a series of data pulses, means for generating synchronization pulses of a preselected width differing from those of the data pulses, and means for transmitting said encoded information and said synchronization pulses together at a preselected bit rate. Similarly, the network termination unit includes means responsive to at least said synchronization pulses to derive a clock signal, means responsive to said clock signal for synchronous encoding and transmission of information from said other one of the sources to the control unit, and means responsive to said synchronization pulses to control phase synchronization of the encoding and transmitting means of said network termination unit with said decoding means of the control unit.
In accordance with an embodiment of the invention, 2s in a telecommunications network of transceiving informational sources, the improvement being a switching interface system for communication between the sources is comprised of a control unit connected with some of the sources including apparatus for encoding information from the sources in a serial, pulse width binary format, and apparatus for serially transmitting pulse width binary encoded pulses of the encoding information at a preselected transmission bit rate; and a network termination unit connected with other ones of the sources including apparatus responsive to the serially transmitted, pulse width binary encoded pulses for extracting therefrom a clock signal, and apparatus responsive to the clock signal for synchronous S decoding of the serially transmitted, pulse width binary encoded pulses for provision to the other ones of the sources connected with the network termination unit.
In accordance with another embodiment, in a telecommunications network of transceiving informational sources, the improvement being a switching interface system for communication between the sources is comprised of a control unit connected with some of the sources including apparatus for encoding information from the sources in a serial, pulse width binary format, and apparatus for serially transmitting pulse width binary encoded pulses of the encoding information at a preselected transmission bit rate; and a network termination unit connected with other ones of the sources including apparatus responsive to the serially transmitted pulse width binary encoded pulses for extracting therefrom a clock signal including apparatus for generating the clock signal at a frequency which is a preselected multiple of the transmission bit rate, and apparatus responsive to the clock signal for synchronous decoding of the serially transmitted, pulse width binary encoded pulses for provision to the other ones of the sources connected with the network termination unit.
In accordance with another embodiment, in a telecommunications network of transceiving informational sources, the improvement being a switching interface system for communication between the sources is comprised of a control unit connected with some of the sources including apparatus for encoding information from the sources in a - 6a -,~
.~ ;
serial, pulse width binary format, apparatus for serially transmitting pulse width binary encoded pulses of the encoding information at a preselected transmission bit rate, and apparatus for periodically inserting phase S synchronization pulses into the serially transmitted pulse width binary encoded pulses to provide phase synchronizational information to a network termination unit;
and the network termination unit connected with other ones of the sources including apparatus responsive to the serially transmitted, pulse width binary encoded pulses to extract therefrom a clock signal, and apparatus responsive to the clock signal for synchronous decoding of the serially transmitted, pulse width binary encoded pulses for provision to the other ones of the sources connected with the network termination unit, apparatus responsive to the phase synchronization pulses to transmit data to the control unit in phase synchronism with the pulse width binary encoded data pulses at the preselected transmission bit rate including a phase synchronization acquisition circuit for generating a synchronization control signal, and apparatus responsive to the synchronization control signal for controlling the synchronous transmission of data to the control unit to maintain the transmission of data to the control unit in synchronization with the synchronization pulses generated thereby.
In accordance with another embodiment, in a telecommunications network of transceiving informational sources, the improvement being a switching interface system for communication between the sources is comprised of a control unit connected with some of the sources including serial, pulse width binary format, apparatus for serially transmitting pulse width binary encoded pulses of the encoding information at a preselected transmission bit rate, -~ 35 -6b -and apparatus for periodically inserting phase synchronization pulses into the serially transmitted pulse width binary encoded pulses to add phase synchronizational information thereto; and a network termination unit S connected with other ones of the sources including apparatus responsive to the serially transmitted, pulse width binary encoded pulses to extract therefrom a clock signal, apparatus responsive to the clock signal for synchronous decoding of the serially transmitted, pulse width binary encoded pulses for provision to the other ones of the sources connected with the network termination unit, and apparatus responsive to the phase synchronization pulses to transmit data to the control unit in phase synchronism with the pulse width binary encoded data pulses at the preselected transmission bit rate including a counter triggered by the clock signal, apparatus responsive to the counter for identifying time division multiplexing channels of the telecommunication network, and apparatus responsive to the binary encoded pulses for maintaining the counter in phase synchronization with the phase synchronization pulses of the control unit.
In accordance with another embodiment, in a telecommunications network of transceiving informational sources, the improvement being a switching interface system 2s for communication between the sources is comprised of a control unit connected with some of the sources including apparatus for encoding information from the sources as a series of data pulses in the serial pulse width binary format, apparatus for generating pulse width encoded synchronization pulses, and apparatus for transmitting the series of data pulses and pulse width encoded synchronization pulses together on a time division multiplexing basis at a preselected bit rate; and a network -r ~ 35 - 6c -~, i termination unit connected with other ones of the sources including apparatus responsive to at least the pulse width encoded synchronization pulses to derive a clock signal, apparatus responsive to the clock signal for synchronous S decoding of the series of pulse width encoded data pulses for connection to the other ones of the sources connected with the network termination unit, and apparatus responsive to the pulse width encoded synchronization pulses to control synchronization of the synchronous decoding apparatus of the network termination unit with the encoding apparatus of the control unit.
In accordance with another embodiment, in a telecommunications network of transceiving informational sources, the improvement being a switching interface system for communication between the sources is comprised of a control unit connected with some of the sources including apparatus for encoding information from the sources as a series of data pulses, apparatus for generating pulse width encoded synchronization pulses, and apparatus for transmitting the series of data pulses and pulse width encoded synchronization pulses together on a time division multiplexing basis at a preselected bit rate; and a network termination unit connected with other ones of the sources including apparatus responsive to at least the pulse width 2s encoded synchronization pulses to derive a clock signal, apparatus responsive to the clock signal for synchronous decoding of the series of data pulses for connection to the other ones of the sources connected with the network termination unit, apparatus for transmitting data from the other ones of the sources connected thereto to the control unit which includes apparatus responsive to the synchronization pulses for maintaining the data transmitted to the control unit in phase synchronization with the pulse 3s - 6d -width encoded synchronization pulses from the control unit including a phase synchronization acquisition circuit responsive to the synchronization pulses received at the network termination unit to develop a synchronization S control signal for controlling the phase synchronization of the encoding apparatus, and apparatus responsive to the pulse width encoded synchronization pulses to control synchronization of the synchronous decoding apparatus of the network termination unit with the encoding apparatus of the control unit.
In accordance with another embodiment in a telecommunications network of informational sources, the improvement being a switching interface system for communication between the sources comprised of a control unit connected with some of the sources including apparatus for binary encoding information from a series of data pulses, apparatus for decoding information received in a series of data pulses, apparatus for generating a series of synchronization pulses of a preselected width differing from width of the data pulses, and apparatus for transmitting the encoded information and the synchronization pulses together at a preselected bit rate; and a network termination unit connected with other ones of the sources including apparatus responsive to at least the synchronization pulses to derive a clock signal, apparatus responsive to the clock signal for synchronous encoding and transmission of information from the other one of the sources to the control unit, and apparatus responsive to the synchronization pulses to control phase synchronization of the encoding and transmitting apparatus of the network termination unit with the decoding apparatus of the control unit.
In accordance with another embodiment, in a telecommunications network of informational sources, the 3s - 6e --improvement being a switching interface system for communication between the sources is comprised of a control unit connected with some of the sources including apparatus for encoding information from a series of data pulses, S apparatus for decoding information received in a series of data pulses, apparatus for generating synchronization pulses of a preselected width differing from width of the data pulses, and apparatus for transmitting the encoded information and the synchronization pulses together at a preselected bit rate; and a network termination unit connected with other ones of the sources including apparatus responsive to at least the synchronization pulses to derive a clock signal, apparatus responsive to the clock signal for synchronous encoding and transmission of information from the other ones of the sources to the control unit, apparatus responsive to the synchronization pulses to control phase synchronization of the encoding and transmitting apparatus of the network termination unit with the decoding apparatus of the control unit, apparatus responsive to the synchronization pulses from the control unit for detecting phase nonsynchronization with the control unit, and apparatus responsive to the nonsynchronization detecting apparatus to alter the timing of the encoding and transmitting apparatus to eliminate the condition of nonsynchronization.
In accordance with another embodiment, in a telecommunications network of informational sources, the improvement being a switching interface system for communication between the sources is comprised of a control unit connected with some of the sources including apparatus for encoding information from a series of data pulses, apparatus for decoding information received in a series of data pulses, apparatus for generating synchronization pulses - 6f -of a preselected width different from width of the data pulses, and apparatus for transmitting the encoded information and the synchronization pulses together at a preselected bit rate; and a network termination unit S connected with other ones of the sources including apparatus responsive to at least the synchronization pulses to derive a clock signal, apparatus responsive to the clock signal for synchronous encoding and transmission of information from the other one of the sources to the control unit, apparatus responsive to the synchronization pulses to control phase synchronization of the encoding and transmitting apparatus of the network termination unit with the decoding apparatus of the control unit, and apparatus responsive to the synchronization pulses from the control unit for transmitting to the control unit an indication of phase nonsynchronization.
In accordance with another embodiment, a method of communication in a synchronous digital data communication network is comprised of the steps of receiving at a controller circuit a stream of binary data pulses in a nonself-clocking format in which clock signals are not carried with the stream of binary data pulses; converting the nonself-clocking data stream to a corresponding self-clocking pulses width modulated binary data stream;
2s transmitting the pulse width modulated binary data stream to a termination unit of the network; extracting a clock signal from the transmitted, binary pulse width modulated data stream received at the termination unit; and employing the extracted clock signal to decode the transmitted, pulse width modulated data stream to a stream of binary data pulses in nonself-clocking format.
In accordance with another embodiment, a method of communication in a synchronous digital data communication - 6g -.
network is comprised of the steps of receiving at a controller circuit a stream of binary data pulses in a nonself-clocking format in which clock signals are not carried with the stream of binary data pulses; converting the nonself-clocking data stream to a corresponding self-clocking pulse width modulated binary data stream;
transmitting the pulse width modulated data stream to a termination unit of the network with preselected transitions at a preselected time during each clock cycle; extracting a clock signal from the transmitted, pulse width modulated data stream received at the termination unit; and employing the extracted clock signal to decode the transmitted, pulse width modulated data stream to a stream of binary data pulses in nonself-clocking format.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing objects and advantageous features will be described and further advantageous features and objects of the invention will be made apparent from the detailed description of the preferred embodiment which will be given with reference to several figures of the drawing, in which:
Fig. lA is a table of prior art comparative waveforms of different encoding schemes including all known self-clocking encoding schemes discussed above in the background section;
Fig. lB is an illustration of the binary code represented by the waveforms of Fig. lA as represented using the binary encoding scheme of the present invention;
Fig. 2 is a table of waveforms which more clearly illustrate 3s - 6h -~1 the preferred ternary encoding scheme of the invention;
Fig. 3 is a block diagram of a telephonic network in which the invention is employed;
Fig. 4A is a block diagram of the digital port circuit of the network of Fig. 3 in which a network link interface circuit of the invention is employed as a network terminal unit;
Fig. 4B is a block diagram of a network shelf controller (NSC) functional block of Fig. 3 in which network link interface circuit of the invention is employed as a control unit;
Fig. 5 is a simplified block diagram of the network link interface circuit operating as a control unit in the NSC circuit of Fig. 4B and the network link interface circuit functioning as a network termination unit in the digital port circuit of Fig.
4A;
Fig. 6A is a circuit diagram of the transmit link encoder section of the network termination unit of Fig. 5;
Fig. 6B is a circuit diagram of the receive link section of the network termination unit of Fig. 5;
Fig. 6C depicts illustrative comparative waveforms of different designated points in the receive link section of Figs.
6A and 6B;
Fig. 6D is a continuation of Fig. 6C;
Fig. 6E is a continuation of Fig. 6D;
Fig. 6F is a continuation of Fig. 6E;
Fig. 7A is a circuit diagram of the transmit link encoder section of the control unit of Fig 5, and is located out of consecutive order on the same page as Fig. 4B;
Fig. 7B is a circuit diagram of the receiver link decoder section of the control unit of Fig. 5;
Fig. 7C depicts comparative waveforms at various designated points in the receiver link decoder section of Fig 7B;
Fig. 7D depicts illustrative comparative waveforms at different designated points in the transmit link encoder section of Fig. 7A and of the receive link decoder in Fig. 7B;
Fig. 8 is a block diagram of a network link interface integrated circuit of Figs. 4A and 4B illustrating the various inputs and outputs of Figs. 4A and 4B;
Fig. 9 is a block diagram of a system configuration in which the networ!c link in~rfac~ circuit of Fig. 8 is variously employed;
Fig. 10 illustrates ~ne signal to v~rious mode pins and master/slave pin of the network link interface circuit o~ Fig. 8 re~uired to achieve different modes of operation required for the dif~erent applications shown in Fig. ~;
Fig. 11 is anot~er functional block diagram of the network link interface circuit to illustrate the various interfaces it has with other elements of the network;
Fig. 12 illustrates the preferred network link format employed with tAe present invention;
Fig. 13 shows the message format employed with the present invention; and Figs. 14 - 43 show the contents of various registers of the network link interface circuit of Fig. 8.
DETAILED DESCRIP~ION
Referring now to the drawing, particularly Figs. lB and 2, the ternary encoding system which enables the many advantageous features of the invention is seen to employ pulses of three different widths. Preferably, the logic zero pulse 20 has the narrowest width, the logic one pulse 22 has the next largest width, approximately twice that of the logic zero pulse 20, and the synchronization, or sync, pulse 24 has the largest width, approximately three times that of the logic zero pulse 20. The entire clock period 26 is preferably four times the width of the logic zero pulse, so that at least one-fourth of the clock period remains without a logic one pulse even when a sync pulse 24 is generated. Unlike other systems shown in Fig. lA, the leading edge of the pulse 20, 22 or 24 coincide with the start of each timing period and the time between the leading edges of successive pulses is always equal to the clock period 2~. Also, a c~de pulse is generated for each ~nd every clock pulse.
Referring now to Fic. 3, t~e invention is employed to interface various elements of a network subsystem 29 which, in turn, is connected with a small business exchange (SBX) bus 30 of a control subsystem, and the elements of a network termination subsystem. Communication of the elements of the subsystem with a central controller and a central memory (not shown) of the telephonic switching system is through means of an SBX bus 30.
The control subsystem of bus 30 is preferably a 68020/68030 microprocessor based multiprocessor, distributed processing system which is capable of either simplex or duplex operation.
The network subsystem 29 consists of a system clock, or CLK, 32 and four interactive switching/control modes (only two shown), each comprising a single stage, non-blocking, 772 channel time slot interchanger, or TSI, 34. Most of these channels (768) are broken down into thirty-two groups of twenty-four channels for interface over high speed serial interfaces known as network links to transition circuits of the network termination subsystem 27. A network shelf controller, or NSC, circuit 36 connected to the TSI 34 has a 68000 microprocessor with two Mbytes of dynamic random access memory (DRAM) to provide processing capability of signaling activity on the 768 channels of each switch mode.
Within the NSC circuit 36, the 768 channel parallel time division multiplexing, or TDM, bus to and from the TSI circuit (not shown) is multiplexed into a thirty-two, twenty-four channel 3.088 MHz serial links, or network links, to and from the network termination subsystem 27. The TSI circuit 34 provides access to higher level processing for itself and the NSC circuit 36 via an SBX interface (not shown) to an SBX circuit residing on the control subsystem secondary bus 30. The central controller memory and central controller are loaded via this secondary bus 30.
The circuits which form the network termination subsystem 27 include a DAS, or digital audio source, 37 for providing tones, announcements and messages; a basic rate line, or BRL, circuit 38; a primary rate interface circuit, or PRI, 40; one or more DSl port circuits 42; and a digital signal processing, or DSP, circuit 44. The BRL circuit 38 provides system access to agent and supervisory consoles, while the PRI circuit 40 provides termination of the twenty-fourth 64 Kbit channel of the TI
digital trunk and also has all the features of a DSl port circuit 42. The DSl port circuit 42 provides digital Tl trunk access ~. 204 1 222 into the system. Pulse code modulation (PCM) channe~Care appropriately formatted and delivered to a DS1 transmit link 46.
Incoming information from the DS1 link 46 are recovered, buffered and delivered to network links for access to the network. The digital signal processing circuit 44 provides three separate TMS
320C25 digital signal processor based circuits for accessing eight of the twenty-four system channels that the DSP circuit 44 accesses over its link into the network. The DSP 44 processor receives functions for multifrequency (MF) and dual tone multi-frequency (DTMF) signals and can also be used for tone meteringfunctions in system diagnostics. As seen, advantageously a linkage 47 of only four wires connects each of the elements of the network termination subsystem 27 with the NSC 36 for a differential system or only two wires in a non-differential system.
The wire linkages 47 are made possible by virtue of use of network link interface, or NLI, integrated circuits 50 of Fig. 8.
As seen in Fig. 9, one or more NLI circuits 50, operating as network termination units 50B, are contained in each of the network termination subsystem elements 37, 38, 40, 42 and 44 and multiple NLI circuits, operating as control units 50A are contained in the NSC circuit 36 of the subsystem 29. Thus, the invention is preferably implemented through means of a single NLI
circuit 50 which, as will be explained in more detail, is capable of operation in different modes depending upon the application in which it is employed. Preferably, the NLI circuit is implemented in a large scale integrated circuit package having the input and output terminals shown in Fig. 8, although separate integrated circuit packages for each of the different modes of operation could be provided in lieu of a single package.
Referring to Fig. 4A for purposes of illustration, the network link interface circuit 50 is shown being used as a network termination unit, or slave, circuit 50B to interface one of the DSl port circuits 42, Fig. 8, with another network link 3s interface circuit 50, Fig. 9, operating as a control unit, or master unit, 50A.
The digital port control (DPC) 42 provides termination for a single DS1 trunk, -i 10 204l~2~
-interfacing lts twenty-four cnannels into the network. The DPC
42 provides for received DSl clock recovery, framing control, bufrering of received PCM and AB(CD) signaling data, as well as DSl line performance monitoring. Through the elastic buffer 53, the received DSl line's PCM and signaling data received on the DSl line 46 is synchronized with the a system clock appearing on line 51A. The data read from the elastic buffer 53 is transmitted on a network link 47 to the network. Information to be delivered to the outgoing DSl line 46 is similarly received from the network on a network link 47. The microprocessor monitors bit-error rate and slip performance of the DSl line, monitors for alarm conditions, controls loopback and other diagnostic facilities, and maintains communication with the control system via a datalink provided in the network link 47.
The received DSl signal from an office repeater bay (ORB), channel service unit (CSU), or galaxy voice circuit (GVC) port interface equipment is transformer-coupled and terminated on the DPC 42, as shown. Similarly, each DSl signal transmitted is transformer-coupled to the line. Three VLSI devices form the core of the DSl interface function of the DPC 50B: the line interface unit 51, the DSl transceiver 52, and the elastic buffer 53. These three VLSI devices are programmable by the DPC
microprocessor 54.
The DPC's line interface unit Sl provides appropriate termination and line driver circuitry for DSl line interface 46, in addition to a programmable line build-out function. The line interface unit 51 also recovers the clock signal on the receive line 46A, presenting this clock and the 1.544 MHz serial data thereon to the DSl transceiver 52 on lines 51A and SlB, respectively. Similarly, the line interface unit 51 will be pro~ided with 1.544MHz serial data by the DSl transceiver 52 on line 52A for transmission on the outbound DSl line 46. The received DSl line clock extracted by the line interface unit 51 may also be output by the DPC 42 for cabling to clock controlling circuitry of the network (not shown) as a reference input.
The DSl transceiver 52 locks on to the framing pattern ` 204 ~ 222 of the receive DSl line 46A and passes each channel of PCM and signaling data to the elastic buEfer 53 device. ~i~ error COUlltS
and alarm conditions of the received DSl line are maintained by the DSl transceiver 52. Similarly, PCM and signaling data to be transmitted on the outbound DSl line 46B are provided by the NLI
50B to the DSl transceiver 52 for framing.
The elastic buffer 53 buffers the received PCM and signaling information for eac~ channel to allow for variations between DSl line and system clocks. This data is read from the buffer by the NLI 50B in synchronism with the system clock. Preferably, the elastic buffer device 53 is programmed to perform signaling integration and freeze functions, if desired.
The NSC 36 encodes the system clock and synchronization signals onto the network link 47 and these signals are decoded by the NLI 50B and its associated phase-locked loop circuitry. The NLI 50B provides the mechanism for connecting the twenty-four channels of PCM and signaling data of the DPC 42 with the network. The NLI 50B also provides the means for the microprocessor 54 to communicate with the microprocessor of the NSC 36 over the 768kbps datalink of the network link 47. In redundant systems, the NLI 50B is connected to an NSC 36 in each network copy.
The DPC 42 contains a 68008 microprocessor 54 is a 68008IC
operating at six MHz. The major function of the microprocessor 54 is to program the DSl interface circuitry of the NLI 50B and to monitor the DSl line 40, reporting error and alarm conditions to the NSC 36. The microprocessor 54 will interact with the NLI
50B for communication with the NSC 36. In such case, the DS1 transceiver 52 will control the facilities data link 51A in ESF
DSl applications. Alternatively, for remote agent applications, the NLI 50~ will control a datalink to remote facility 57B
maintained in one of the 64kDps channels of the DPC 42.
The DPC 42 contains sixty-four kbytes of no wait-state EPROM
55 for boot loading and diagnostic code. The DPC 42 contains 32kbytes of no wait-state RAM 56 which can be optionally expanded to 96kbytes. The RA~ 56 can be write-protected in 8kbyte blocks.
` 21~412~2 Several resisters are also provided in the address space of the microprocessor 54 to allow for control and monitoring of various functions.
The microprocessor 54 can receive interrupts from the NLI 50B, the DSl transceiver 52, the line interface unit 51, the serial communications controller 57, and by a ten microsecond signa developed in the ~LI 5OB.
In order to provide for remote agent capability, the DPC 42 is provided with access to one of the twenty-four sixty-four kbps channels of the DSl line 46 to facilitate 'D' channel control in an ISDN '23B+D' environment. The received sixty-four kbps data is passed by the DSl transceiver 52 through the NLI 50B to a Z8530 serial communications device, or data links 57A and 57B, controlled by the microprocessor 54. The devices 57 will serialize the sixty-four kbps data stream and pass this through the NLI 50B to the DSl transceiver 52 for transmission to the outbound DSl line 46B. At a remote site, another DPC 42 will be present as the source and sink of this 'D' channel information.
The DPC acce~ts redundant -48VDC inputs and contains a DC-to-DC ~ower converter to derive the +5V required for its logic circuits.
Referring now to Fig. 4B, the NLI 50A is seen as used as a master, or control unit, 50A in the NSC 36 for interfacing the network subsystem 29 with elements of the network termination subsystem 27 of Fig. 3. The NSC 36 occupies a mid-level position in the three-tier distributed processing architecture of the switching network. The major role of the NSC 36 is in call processing during which it interacts with a higher order microprocessors of the control system through means of an SBX
interface shared with a TSI 34 with which it is associated. The NSC 36 also interacts with the DAS 37 and DSP 44 in the network termination subsystem 27 through means of network links. AB(CD) signaling bits of lines and trunks and Special-B signaling messages of thin-wire consoles (Special B signaling) are directly controlled by the NSC microprocessor 58. The 'ABS~ IC' ASIC has been developed to facilitate the NSC control of this signaling
- 2~4~
inforn-,ation. The NLI 50A is an ASIC which has been developed to provide communication between the network and network termination elements. The NSC 36 contains thirty-two NLI 50A.
Tne NSC is controlled by a 68000 miccoprocessor 58 operating at lOMHz. The NSC 36 contains 64kbytes of EPRO~ 59 accessible with one wait-state for boot-loading and diagnostic code. The circuit also contains 21~bytes of DRA~ 60 accessible with no wait-states, organized as lMX16. Parity is also kept on byte boundaries throughout the DRAM 60. Software can be down-loaded to this DRAM 60 and then executed. Protection logic 61 allows eight kbyte segments of the DRAM 60 to be write protected, specified as either supervisor or user space, and be restricted from allowing opcode fetches. Any attempt to violate the protection specified for a given DRAM segment will result in a bus error indication to the microprocessor 58.
A 68901 multi-function peripheral 62 is available on the NSC
which contains four eight-bit counters which can be arranged to provide two sixteen-bit counters. A serial port 62A on the peripheral facilitates an off-card communications link. This serial link is employed by the NSC in a control/network channel for communication with a clock in another channel. This serial link is employed in downloading the clock during system initialization and as the means for its intercommunication with the control system microprocessors (not shown). I/O pins on the microprocessor 58 are used as prioritized interrupt inputs and as latches for error indications coming from the memory protection logic 61. The NSC microprocessor 58 can receive interrupts from the SBX interface, from the NLIs 50A, from the serial communication circuitry of the microprocessor 58, and by a ten millisecond signal developed in one of the NLIs 50A.
The NSC/TSI interface to an SBX must respond to control signals and communicate via multiplexed address and data buses.
Several registers are present on the TSI 34 as part of the SBX
interface. The NSC 36 and TSI 34 can be forced to reset by the SBX when a bit in one of these regissterd is toggled. The SBX
can also interrupt the NSC microprocessor 58 by activating - ` 2041~22 certain other bits in these registers. Additionally, a lk word, dùal-port RA~l accessible by tne SBX is present in the TSI 34.
Tnis dual-port RAM is expressly for the purpose of passing control messages and data between tne control system and NSC card microprocessor 58. Althou~h simultaneous access from both directions into this dual-port RAM is possible, data will only be transferred through this memory with a softword-controlIed handshake.
Circuitry on the TSI 34 must also convert between ~BX bus word-oriented parity and NSC/rSI byte-oriented parity.
Each MSC 36 contains an array of thirty-two NLIs 50A. The NLIs 50A bring together the switched PCM and signaling data (to and from the TSI 34), the system clock and sync signals, and a communications link between the NSC 36 and a network termination card microprocessor onto one physical link. There are three interfaces into the NLI array. Each NLI ~OA operates on a twenty-four channel group. For each NLI 50A on an NSC 36, there is an NLI 508 on a network termination circuit with which it is associated.
Network links are employed between the NSC 50 and each network termination circuit. By employing a network link ~or each twenty-four channel group, a maximum ~ailure group size of twenty-four channels is facilitated in duplex systems. In such duplex arrangements, a given network termination circuit will have network links to each of two redundant NSCs 36. The network termination circuit will always transmit to both NSC 3~ copies, but can only be "listening to" one of them at a time.
Minimally, two physical wires would be required for any complete link between the NSC 36 and a network termination circuit: a PCM/signaling data path from the NSC 36 to the network termination circuit and a PCM/signaling data path form the network termination circuit to the NSC 3~. Beyond PCM and signaling patns, each card that resides in the network termination subsystem 27 must also be provided with thre additional elements for proper operation: the system clock, a system synchronization signal, and a path for communication with 2a~4l222 -the network control microprocessors (not shown). While in many systems these three signal paths are provided on physically separ~te wires beyond those reserved for PCM and signaling data.
Advantageously, in the network of Fig. 3, the lines are designed to provide these ~unctions inherently on the same set of wires provided for PCM and signaling data flow. Since only these two wir~os would be required from NSC and network termination connection, a second set of wires is available for the purpose of differtially transmitting each of the signals, thus adding to the reliability of the network links while still keeping the amount of cabling required in to a minimum.
The network link interface integrated circuit, or NLI, 50 is an application-specific integrated circuit designed for controlling the network links as described above. The 3.088 MHz, differential link connecting the NSC 36 to a network termination circuit is referred to as the to port link; that connecting the network termination card to the NSC is called the from-port link.
As the NLIs SOA at the NSC 36 end of a network link have direct access to the system clock provided from the clock, they are said to operate in the "master" timing mode. The NLI 50A .
must derive copy of the system clock from the pulse-width modulation encoded network link that it receives. The network termination circuits NLIs SOB are thus said to operate in "slave~
timing mode. At the network termination circuit, a phase-locked loop is used to recreate the 12.352 MHz system clock from the
inforn-,ation. The NLI 50A is an ASIC which has been developed to provide communication between the network and network termination elements. The NSC 36 contains thirty-two NLI 50A.
Tne NSC is controlled by a 68000 miccoprocessor 58 operating at lOMHz. The NSC 36 contains 64kbytes of EPRO~ 59 accessible with one wait-state for boot-loading and diagnostic code. The circuit also contains 21~bytes of DRA~ 60 accessible with no wait-states, organized as lMX16. Parity is also kept on byte boundaries throughout the DRAM 60. Software can be down-loaded to this DRAM 60 and then executed. Protection logic 61 allows eight kbyte segments of the DRAM 60 to be write protected, specified as either supervisor or user space, and be restricted from allowing opcode fetches. Any attempt to violate the protection specified for a given DRAM segment will result in a bus error indication to the microprocessor 58.
A 68901 multi-function peripheral 62 is available on the NSC
which contains four eight-bit counters which can be arranged to provide two sixteen-bit counters. A serial port 62A on the peripheral facilitates an off-card communications link. This serial link is employed by the NSC in a control/network channel for communication with a clock in another channel. This serial link is employed in downloading the clock during system initialization and as the means for its intercommunication with the control system microprocessors (not shown). I/O pins on the microprocessor 58 are used as prioritized interrupt inputs and as latches for error indications coming from the memory protection logic 61. The NSC microprocessor 58 can receive interrupts from the SBX interface, from the NLIs 50A, from the serial communication circuitry of the microprocessor 58, and by a ten millisecond signal developed in one of the NLIs 50A.
The NSC/TSI interface to an SBX must respond to control signals and communicate via multiplexed address and data buses.
Several registers are present on the TSI 34 as part of the SBX
interface. The NSC 36 and TSI 34 can be forced to reset by the SBX when a bit in one of these regissterd is toggled. The SBX
can also interrupt the NSC microprocessor 58 by activating - ` 2041~22 certain other bits in these registers. Additionally, a lk word, dùal-port RA~l accessible by tne SBX is present in the TSI 34.
Tnis dual-port RAM is expressly for the purpose of passing control messages and data between tne control system and NSC card microprocessor 58. Althou~h simultaneous access from both directions into this dual-port RAM is possible, data will only be transferred through this memory with a softword-controlIed handshake.
Circuitry on the TSI 34 must also convert between ~BX bus word-oriented parity and NSC/rSI byte-oriented parity.
Each MSC 36 contains an array of thirty-two NLIs 50A. The NLIs 50A bring together the switched PCM and signaling data (to and from the TSI 34), the system clock and sync signals, and a communications link between the NSC 36 and a network termination card microprocessor onto one physical link. There are three interfaces into the NLI array. Each NLI ~OA operates on a twenty-four channel group. For each NLI 50A on an NSC 36, there is an NLI 508 on a network termination circuit with which it is associated.
Network links are employed between the NSC 50 and each network termination circuit. By employing a network link ~or each twenty-four channel group, a maximum ~ailure group size of twenty-four channels is facilitated in duplex systems. In such duplex arrangements, a given network termination circuit will have network links to each of two redundant NSCs 36. The network termination circuit will always transmit to both NSC 3~ copies, but can only be "listening to" one of them at a time.
Minimally, two physical wires would be required for any complete link between the NSC 36 and a network termination circuit: a PCM/signaling data path from the NSC 36 to the network termination circuit and a PCM/signaling data path form the network termination circuit to the NSC 3~. Beyond PCM and signaling patns, each card that resides in the network termination subsystem 27 must also be provided with thre additional elements for proper operation: the system clock, a system synchronization signal, and a path for communication with 2a~4l222 -the network control microprocessors (not shown). While in many systems these three signal paths are provided on physically separ~te wires beyond those reserved for PCM and signaling data.
Advantageously, in the network of Fig. 3, the lines are designed to provide these ~unctions inherently on the same set of wires provided for PCM and signaling data flow. Since only these two wir~os would be required from NSC and network termination connection, a second set of wires is available for the purpose of differtially transmitting each of the signals, thus adding to the reliability of the network links while still keeping the amount of cabling required in to a minimum.
The network link interface integrated circuit, or NLI, 50 is an application-specific integrated circuit designed for controlling the network links as described above. The 3.088 MHz, differential link connecting the NSC 36 to a network termination circuit is referred to as the to port link; that connecting the network termination card to the NSC is called the from-port link.
As the NLIs SOA at the NSC 36 end of a network link have direct access to the system clock provided from the clock, they are said to operate in the "master" timing mode. The NLI 50A .
must derive copy of the system clock from the pulse-width modulation encoded network link that it receives. The network termination circuits NLIs SOB are thus said to operate in "slave~
timing mode. At the network termination circuit, a phase-locked loop is used to recreate the 12.352 MHz system clock from the
3.088 MHz timing pulses on its received network link. This clock is used to sa~ple the encoded data on the received network link where 333 Hz system sync pulses, the twenty-four channel PCM and associated signaling data, and a 768 kbps communication channel are multiplexed. Since the network termination circuits clock is, in this fashion, synchronized with the system clock, there is no need for a similar clock recovery scheme on the NSC circuit 50A of decoding its received network link -- the data may merely be sampled by the 12.352 MHz clock provided by the master clock.
There is, however, a thirty foot limitation on the length of network link cabling for this latter point to prevail due to ` 204122:2 phase delays and noise problems associated with longer cables.
Practically speaking, this maximum cable length is not a limiting factor since network and network termination functions can be easily located within the distance of one another.
Each of the ne~work termination circuits has its own form of interface to the NLI 50B for passing twenty-four channel data.
The NLI 50B preferably provided with "moden selection pins in order for the card on which it reside-s to specify the desired twenty-four channel interface required.
Referring now to Fig. 5, an NLI circuit 50 operating as a control unit, or master unit, 50A within an NSC 36 is shown simply connected with another NLI circuit 50 of a DPC 42 which has been preselected to operate as a network termination unit, or slave unit, 50B.
At the NSC 50A, a 12.352 ~Hz frequency reference and a 333 Hz phase reference are provided to the ~LI 50A on lines 80 and 82. Two sets of fixed-modulus counters 63 and 64 are driven by these reference inputs. The 12.352 MHz frequency reference is provided to each of these counters as the clock input; the 333 Hz phase reference is provided to each as the sync (reload) input.
The modulus of the XMT counter 63 is exactly the same as that of the RCV counter 64. Each consists of two stages with the first stage being an eleven bit counter that ranges on successive clock inputs from counts zero to 1543 and a second stage being a five bit counter ranging from zero to twenty-three. The first stage of each c~unter must range from zero through 1543 before the second stage is allowed to increment one time. When the first stage counter reaches count 1543, the next received 12.352 MHz clock input will cause that counter to go to zero. Similarly, when the second stage counter reaches count twenty-three, the next time that the first stage counter is at its maximum value and a 12.352 MHz clock is received, the second stage count will revert to zero. Registers are maintained within the NLI 50A as input to these counters. Figs. 20 and 23 indicate the registers addressable by the microprocessor 58, Fig. ~B, which effect counter operation. Upon the initialization of these registers by 20412~2 -the ~icroprocessor 58, each time that the 333 ~z phase reference input on line 80 is received by the XMT counter 63 and RCV
counter 64, the values from these registers are inserted as the next count or those counters. In this fashion, the microprocessor 58 can specify a phase difference between the XMT
counter 63 and RCV counter 64 simply by specifying a different value in the associated counter load registers for each. This is useful as at the NLI 50B, where there is similarly an XMT counter 65 and a receive counter 66. The modulus of these counters is exactly the same as those on the NSC 50A. The XMT counter 66 and RCV counter 65 of the NLI 50B differ from those on the NLI 50A
only in the way that 12.352 ~Hz clock and 333 Hz sync is applied to them and, potentially, in the counter load register values that their microprocessors of therir associated circuits have set for them once 333 Hz sync is received.
At the NLI 50A, voice and control message data is applied as input to a multiplexer 67 for ultimate transmission to the network termination circuit. Outputs of the X~T counter 63 are used to selet which of these inputs are to be applied to the line encoder 68. A third input to the multiplexer will be anot~er output of the XMT counter 63 indicating that it is time to present a 333 Hz sync signal on the transmitted network link.
The line encoder will act on either the logic zero or logic one data ~rom the voice or control message inputs to produce the encoded logic zero or logic one symbols in Fig. 2. When it receives an input indicating that a sync symbol should be transmitted to the network link, it produces the sync symbol of Fig. 2.
At the network termination end, 50B, the output of the NLI
line encoder 68 is received after propogation through the interconnecting wire 84. ThiS received network link data is passed through a delay network 69 and then input to a divide-by-two circuit 70 such as a toggle flip-flop. Since each symbol received from the network link begins with a low-to-high transition, the received network link, once delayed, is used as the clock input of this toggle flip-Elop 70. The result is a 2~412~2 1.544 MHz clock as input from the divide-by-two circuit 70 which is, in turn applied as input to a phase-locked loop 71 to create a 12.352 MHz clock. A property of this 12.352 ~Hz output from the phase-locked loop 71 is that it is four times higher in frequency than the 3.088 MHz data rate of the r~ceived network link and that every fourth low-to-high edge of this 12.352 MHz clock will lag in phase behind the low-to-high edge beginning each received bit interval of the received network link. The duration of this phase lag is essentially fixed as the duration of the delay block 69.
In this fashion, the 12.352 MHz clock can be used to sample each received network link bit interval four times to discern which of the three symbols was output by the NSC line encoder 68 in a given bit interval. This sampling and decoding of the received bit is the function of the line decoder and demultiplex circuits 72. The 12.352 MHz clock developed by the phase-locked loop 71 is used as the clock input to the RCV counter 65 and XMT
counter 66 at the network termination circuit. When the line decoder and demultiplex circuits 72 identify that a sync input has been received from the incoming network link, this sync indication is applied to the sync (reload) input of the RCV
counter 65 and the XMT counter 66 through means of the phase sync acquisition circuit 73.
Since both the RCV counter 65 and XMT counter 66 operate in a fixed modulus and since the value that they take on when a sync is received is fixed by the microprocessor of the associated network termination circuit by loading the associated counter load registers (Figs. 20 through 23), the phase sync acquisition circuit 73 can compare the current value of each counter against its load register values to predict that a sync symbol should be received as the next input bit from the incoming network link.
Sould either the next bit received from the incoming network link not be a sync symbol, an out-of-sync condition is indicated at the network termination circuit. Should a sync symbol be received ont he incoming network link and it not be predicted by a comparison of either counters current values to its load value, ` 21~41~22 again an out-of-sync condition is indicated t the network termination circuit.
Once the RCV counter 65 and X~IT counter 66 on the network termination initially achieve synchronization with the ~SC 36, they should remain the sync thereafter. In a synchronized condition, the RCV counter 65 will output a signal used to demultiplex the decoded voice and control message data received to appropriate card circuitry from the line decoder and demultiplex circuit 72. Similarly, voice and control message data to be transmitted to the NSC 36 will be presented from other network termination card circuitry to a multiplexer 74 for network link transmission. The XMT counter 66 will provide another input to this multiplexer 74 for insertion during sync bit intervals on the transmitted network link. A XMT counter 66 output will control which bit, whether voice, control message, or sync type, is to be transmitted at a given time.
On the other hand, it is important to note that the transmitted network link data from the network termination NLI
50B is not~pulse-width modulation encoded. This output is strictly logic zero or logic one throughout the 3.088 MHz bit interval. The XMT counter 66 will cause the sync bits to output to the network link to formulate a unique patterns of logic zeroes and logic ones.
The RCV counter 6S on the network termination NLI 50B is clearly fre~uency synchronized to its XMT counter 66. The phase difference between these two counters is controlled by the termination circuits microprocessor by speciEying the value on receiving a sync input. Similarly, the XMT counter 63 at the NSC
36 is clearly frequency synchronized to its RCV counter 64, and the phase difference is controlled by the microprocessor 58 setting of the values when sync is applied. Since the RCV
counter 65 is synchronized to the XMT counter 63 of the NLI 50A
by our pulse-width modulation scheme, the network termination XMT
counter 66 is synchronized to the RCV counter 64. The entire system is thus frequency synchronized and, with appropriate values in all counter's 63-66 load registers, phase synchronized i~ achieved, as well.
For purposes of a illustration, consider the time delay along the path of a bit output by the line encoder 68 of NLI 50A
at the NSC 36, propogating through the network link cable to the network termination circuit DSP 44, propogatinq through the line decoder and demultipl~xer 72, being looped back as input to the transmit multiplexer 74, propogating through the multiplexer and inerconnecting network link cable back to the NSC, and being received at the input latch 75. If the length o the interconnecting cable is limited, with the circuitry of Fig. 5, the round trip interval can be less than one 3.088 MHz bit interval. It is this circuitry and method of Fig. 5 with its inherent synchronization and controlled time delay that allows simple receipt of the non-encoded network link data transmitted from the network termination multiplexer 74 wi~h a latch 75 at the NSC 36. This latch 75 is clocked with a 3.088 MHz signal derived by the NSC RCV counter 64 by simple division of the 12.352 MHz clock that RCV counter 64 receives. The instant which begins a 3.083 MHz output bit interval by the NSC line encoder 68 is the same instant that a bit is sampled and received by its received network link latch 75 The data received by the NSC latch 75 is demultiplexed to go to the appropriate NSC circuitry by a demultiplexer 76 controlled by an output of the RCV counter 64. Further, since the entire system is in synchronization, it is known when to expect sync bits at the NSC end from the network termination end. The farend sync check circuit 77 receives input from the RCV counter 64 to identify those instants when logic one level sync bits should be received from the network termination end and then samples the received network link bits output from the demultiplexer 76. Should the far-end sync check circuit 77 discern that a logic one sync bit was either not received from the network link when it was expected or was received when it was not expected, an indication that the network termination end 50B
is out of sync with respect to the NSC end 50A will result and the NSC microprocessor 58 will be interrupted.
Referring to Figs. 6A and 63, the transmit link section and receive link s~oction of the network termination, or slave, unit 50B are seen. These operate in association with the waveforms shown in Fig. 6C, 6D, 6E and 6F of the drawing.
The circuitry of Fig. 6A is incorporated together with that of Fig. 7A in one integrated circuit. Also, different portions of the circitry in figure 6A (7A) are applicable when the device is employed on the NSC end is a network link interface 50A than would be the case if the device were employed in the network termination end as in an NLI 50B. Similarly, different portions of the circuitry in Fig. 6~(7B) are applicable when the device is employed at the NSC end as a network link interface 50A than would be the case if the device were employed at the network ter~Tination end as an NLI 50B.
It is presumed that the master/slave pin of the NLI 50, Fig. 8, is fixed to logic zero (indicating slave mode) in this application, enabling the appropriate NLI 50B portion of the circuitry of the NLI 50. The NLI receives input from the fixed-modulus XMT counter 66. The XMT counter 66, Fig. 5, consists of two stages with its first stage being an 11 bit counter that ranges on successive clock inputs from counts 0 to 1543 and its second stage a five bit counter ranging from 0 to 23. The first stage of each counter must range from 0 through 1543, and the second stage is a five bit counter ranging from 0 to 23. The first stage of each counter must range from 0 through 1543 before the second stage is allowed to increment one time. When the first stage counter reaches count 1543, the next received clock input will cause that counter to go to zero. Similarlyr when the second stage counter reaches count 23, the next time that the first stage counter is at its maximum value and clock is received, the second stage count will revert to 0. The first stage counter outputs 66~ are labelled I"VAL00 through ICVAL10 on Fig. 6A, but outputs ICVAL02 and ICVAL03 are unused. The second stage counter outputs 66E~ are labelled IFRMCT0 through IFRMCT4 on ` Z041~22 Fig. 6A. The XMT counter 65 is~clocked by the low to high edge of ~n inverted copy of the same 12.352 MHZ clock plus which forced X~T counter 56 outputs to go to a state with ICVALOO, ICVALOl=OO.
Essentially, si~nals at 197 and 198 are NORed togetner to provide a network link bit output lasting one 3.088 MHz period.
If output 195 is low then output 196 is high. r~hen output 195 is high, the data input to the circuit labelled DATA IN will be whatever is transmitted on the network link. If output 196 is high, however, the output will be whatever is also on output 194.
The output 194 signal is the means whereby sync bits are output to the network link from the network termination NLI 50B to the NSC
NLI 50A, with a unique pattern being maintained. Output 194 is equal to the value of output 193 sampled after the output 193 signal has settled from the change in counter state. Similarlly, output 195 is equal to the value of output 192 sampled after the output 192 signal has settled from the change in counter state.
Also, output 196 is the complement of output 195.
The following combinational logic expressions serve to fully describe the operation of the relevant protion of the circuit:
Qut~ut Candition 191=1 only when [ICVALlO-ICVALOO]=OOOOOxxxxxX where X=irrelevant 192=0 only when [ICVAL10-ICVALOO]=OOOOOlllXXX where X=irrelevant 193=0 only when [IFRMCT4-IFRMCTO]=OOOOO
194=0 only when [IFRMCT4-IFRMCTO]=OOOOO when sampled by 12.352 MHz 195=0 only when [ICVAL10-ICVALOO]=OOOOOlllXXX when sampled by 12.352 MHz where X=irrelevant 196=inverse of 19 197=1 only when [IFRMCT4-IFRMCTO]not=OOOOO when sampled by 12.352 MHz AND
[ICVAL10-ICVALOO]=OOOOOlllXXX when sampled by 12.352 MHz where X=don't care 198=1 only when [ICVAL10-ICVALOO]not=OOOOOlllXXX when sampled by 12.352 MHz where X=irrelevant AND
"DATA IN"=0 such that "DATA OUT TO NETI~ORK LINK" takes on the following values:
if [IcvALlo-IcvALoo]=ooooolllxxx when sampled by 12.352 MHz where X=irrelevant, "DATA OUT TO NETWORK LINKn=0 when tIFRMCT4-IFRMCTO]not=OOOOO
when sampled by 12.352 Mhz if [ICVAL10-ICVALOO]not=OOOOOlllXXX when sampled by 12.352 MHz X=don't care, "DATA OUT TO NETWORK LINK"=O when "DATA IN~=O
Referring to Fig. 6B, the network link receiver of the network termination end NLI 50B has the master/slave input at logic zero (indicating slave mode) to enable the appropriate portion of the circuitry. The data is received from two network }inks at the associated network termination circuitry. This is in keeping with a strategy for the switching system has redundant NSC circuits. The circuitry will interact with only one of network link 101 and 102 this is selected by the microprocessor 58 setting a link select bit to chose between data on input 101 or 102 link A or RCVD data from network link B. Whichever network link input is accepted, the data output 104 will be controlled by the decoding circuitry shown and will come from the inverting output of the flip-flop 105 of Fig. 6B. This toggle flip-flop 105 is the divide-by-two circuit 70 of Fig. 5. The multiplexing circuitry shown to select between network link copies and the inherent delay of the toggle flip-flop 105 is represented by the delay circuit 69 of Fig. 5. Since the received network link data arrives at 3.088 MHz, the output of flip-flop 105 is a 1.544 MHz clock signal. This 1.544 MHz clock is applied as input to a phase-locked loop 71 to create the 12.352 MHz phase locked loop signal (FROM PLL) signal shown on Fig. 6B and which is used to clock the XMT counter 66 and RCV
counter 65. The load input signal (CTR SYNC-) to the XMT counter 66 and the RCV counter 65 is developed by the circuitry shown on Fig. 6B and represents the means whereby system synchronizatiion is achieved. The CTR SYNC~ signal is activated by the circuitry depicted in Figure 6B upon recipt of sync 24 symbols in t~ii?
received pulse-wiæth modulation encoded network link data.
The operation of the circuitry in Fig. 6B is illustrated in Figs. 6C through 6F. Fia. 6C depicts the arrival of sync 24 symbols on the received network link and the development of the CTR SYNC- signal to synchronize the switching system. Fias. 6D
throuah 6F indicate the continuation of operation during intervals between received sync 24 symbols for clarity. Noting the labelled points in the circuitry of Fig. 6B, it is seen from Figs. 6C through 6F that:
Line 7 indicates the received network link data. The figure begins with the last portion of a non-sync bit's arrival followed by the arrival of the two consecutive sync 24 symbols. In each bit interval on line 7, the shaded portion represents logic zero and the non-shaded portion represents logic one.
Line 6 represents the T-FF 1.544 MHz output to the phase-locked loop.
Line 1 through 6 represent internal signals of the phase-locked loop, with line 2 indicating the 12.352 MHz clock used by the circuitry in Fig. 6B and line 5 illustrating the phase-locked loop frequency and phase synchronization with the T-FF
output of line 6. The 12.352 MHz clock is used either directly or in inverted form to clock the flip-flop, counter, and shift register stages in the circuitry depicted in Fig. 6B.
Line 8 indicates the Q output of FFl. Each pulse-width modulated bit is sampled four times by FFl in accordance with the high to low transitions of the 12.352 MHz clock. Each pulse-width encoded bit is thus reproduced at the output of FFl with a slight delay from its actual arrival at the network termination circuit. The Q output of FFl is applied as the load input to a synchronous four-bit counter which, in turn, is clocked by the low to high transitions of 12.352 MHz. Whenever a logic zero level is termination card. The Q output of FFl is applied as the load input to a synchronous four-bit counter which, in turn, is clocked by the low-to-high transitions of 12.352MHz. Whenever a logic zero level is apparent on this counter's load input during a low-to-nigh transition of 12.352 MHz, the counter's output becomes [QD-~A]=000. Should the counter's load input be logic one during a low-to-high transition of 12.352 ,~Hz, the counter will increment its count by one.
Line 9 indicates the output of the 4-bit counter during successive 12.352 MHz clock cycles when the network link data received conforms to the pattern of line 7. Note that it is only during those intervals where sync 24 sym~ols are received from the network link that the counter's output reaches the value where sync 24 symbols are received from the network link that the counter's output reaches the value [QD-QA~=0011. Flip-flop FF2A
and FF2B receive their D-inputs directly from this counter's output. FF2A and FF2B are clocked by low-to-high transitions on the inverting output (XQ) of FFl. The low-to-high transition on the inverting ouput of FFl occurs when the delayed and sampled received network link data has reverted from logic one to logic zero, concluding its positive pulse. Flip-flops FF2A and FF2B
and succeeding stages will assess at which of the four sample points taken in the 3.088 MHz bit interval this positive pulse concluded in order to decode the received symbol from amongst the set possible 20,22,24.
Lines 10 to 11 indicate the output of FF2A and FF2B, respectively, when the network link data received conforms to the patterns of line 7. Note from Figure 6B that FF3A and FF3B
receive their D-input from FF2A and FF2B, respectively. -FF3A and FF3B are clocked by the low-to-high transition of the actual received network link data (delayed by the multiplex circuitry) such that their outputs are updated once every 3.088 MHz interval. In a given 3.088 MHz bit interval, the 4-bit counter counts up once for each of the (up to 3) times that the receive network link data sampled by FFl is at logic one, FF2A and FF2B
and then when the actual network link data transitions from logic one to logic zero, the "highest count" that tAe 4-bit counter achieved is latched in FF3A and FF3B.
Lines 12 and 13 indicate tne output of FF3A and FF3B, respectively, when the network link data received conforms to the 204122~
patterns of line 7. Flip-flops 4A and 4B are clocked by the nigh -to-low transitions of the combinational logic which acts on the outputs of FF3A and FF33. The output of FF4A will be the decoded output of each network link bit to the network termination card's circuitry. FF4A will cause a logic one, indicating that a zero symbol 20 was received. F~4A will cause a logic one to be output to the circuit when both the first and second quarters of a received network link bit interval is logic one, indicating that a zero symbol ZO is received. The output of flip-flop FF4B is fed to an eight bit shift register for the purpose of determining the appropriate time to cause a CTR LOAD~signal to the XMT
counter 66 and the RCV counter 65.
Lines 14 and 16 indicate the output of FF4A and FF4B, respectively, when the network link data received conforms to the pattern of line 7.
Line 17 indicates the output of the 8-bit shift register [SR] which receives input from FF4B and is clocked by low-to-high transitions of the 12.352 MHz clock provided by the phase-locked loop.
Line 18 indicates the CTR SY~C~ signal applied to the XMT
counter 66 and the RCV counter 65 to achieve system synchronization. This CTR SYNC- signal is formulated by sampling the output of the depicted combinational logic driven by the SR outputs after a settling period by low-to-high transitions on the 12.352 MHz clock provided by the phase-locked loop.
The remaining lines on Figs. 6C through 6F indicate the outputs of the synchronized XMT counter 66 and RCV counter 65.
Specifically, by comparing lines 20 and 25 it is shown that the 3.088 MHz bit inerval is maintained in phase on both the received and transmitted network link. The timing diagrams represented in Figs. 6C through 6F and in Fig. 7D complement each other.
Together they mesh and fully describe the timing of the switching system and its particular time-division multiplex strategy. The circuitry described in figures 6A and 6B provide the core of this functionality on the network termination end 50B of the network links.
204 ~ 222 Referring to Figs. 7A and 7~, the transmit link encoder section and r-ceive link decoder section of che master control unit 50A are shown. These circuits operate in accordance with the waveform shown in Figs. 7C and 7D.
Referring to Fig. 7A, it is identical to that depicted in Fig. 6A. ~imilarly, the circuitry depicted in Fig. 7B is identical to that depicted in Fig. 6B. This is the case as they ~ave been fabricated in one integrated circuit. Different portions of the circuitry in Fig. 7A(6A) are applicable when the NLI 50 is employed on the NSC end of a network link than would be the case if the NLI 50 were employed on the network termination end 50B. Similarly, different portions of the circuitry in Fig.
7B(6B) are applicable when the NLI 50 is employed on the NSC end of a network link than wou]d be the case if the device were employed at the network termination end. In Fig. 7A, the master/slave pin of the device is fixed to logic one (indicating master mode), enabling the appropriate portion of the circuitry.
The transmitter circuit of Fig. 7A receives input from the fixed-modulus X~T counter 63, Fig. 5. The XMT counter 63 consists of two stages with its first stage being an 11 bit counter that ranges on successive clock input from counts 0 to 1543. The second stage is a five bit ounter ranging from 0 to 23. The first stage of each counter must range from 0 through 1543 bedfore the second stage is allowed to increment one time. When the first stage counter reaches count 23, the next time that the first stage counter outputs are maximum value and clock is received, the second stage count will revert to zero. The first stage counter outputs 169 are referred to as ICVAL00 through ICVAL10. Outputs ICVAL02 and ICVAL03 are unused. The second stage counter outputs 170 are referred to as IFRMCT0 through ~FRMCT4 on Fig. 7A. THe X~T counter 63 is clocked by the low-to-high edge of an inverted copy of the same 12.352 MHz clock in Fig. 5. Further, the data input to the circuit for eventual output to the network link is presented for a full 3.088 MHz interval in phase with the high-to-low edge of the same 12.352 MHz clock pulse which forc~s XMT counter 63 outputs to go to ~ ICVALOO, ICVALOl=OO. 2041222 ~ ssentially, the sisnal at 179 i3 inverted to provide a network link bit output lasting one 3.088MHz period. Note that 173 is e~ual to the value of 178 sampled after the 178 signal nas settled from the change in counter state. The 178 signal is formed by NO~ing tne signal 174, 175, 176, and 177. The 174, 175, 176, and 177 signals each play a role in creating the eventual pulse-width modulated output to the network link. The 174 signal is formulated to insure that the pulse-width modulated output during the first quarter of eacn 3.088 MHz bit interval is a logic one during sync bit times. The 177 signal is formulated to insure that the second quarter of a 3.088MHz bit interval is at logic one during sync bit times. The 176 signal is formulated to insure that the third quarter of a 3.088 MHz bit interval is at logic one during sync bit times. The 175 signal is formulated to cause the second quarter of a 3.088 MHz bit interval to be at logic one during non-sync bit times when the data input (DATA IN) to tne circuit is itself at logic one;
similarly the second quarter of the network link output 3.088 MHz bit interval will be caused to be logic zero when the data input (DATA IN) is itself logic zero during such intervals.
The following combinational logic expressions serve to describe the operation of the relevant portion of the circuit of Fig. 7A:
Qut~ut Condition 171=0 only when [IFRMCT4-IFRMCTO]=OOOOO
172=1 only when [ICVAL10-ICVALOO]=OOOOOXXXXXX where X=irrelevant 173=0 only wnen [ICVAL10-ICVALOO]=OOOOOlllXXX where X=irrelevant 174=1 only when [IcvALlo-IcvALool=xxxxxxxxxoo where X=irrelevant 175=1 only when [ICVAL10-ICVALOO]not=OOOOOlllXXX where X=irrelevant AND
ICVALl=O
AND
"DATA IM"=l 176=1 only wAen 2-412~2 FR.lCTeOOOOO
[ICVAL10-ICVALOO]not=OOOOOlllXXO where X=irrelevant 177=1 only when FR~ICT=OOOOO
AND
[ICVAL10-ICVALOO]not=OOOOOlllXXX where X=irrelevant AND
ICVALl=O
178=NOR(174, 175, 176, 177) 179=178 sampled by 12.352 MHz "DATA ~UTPUT TO NETr~ORK LIN~n=complement of 179 Referring to Fig. 7B, the master/slave pin of the NLI 50A is fixed to logic one (indicating master mode) in this application, enabling the appropriate portion of the circuitry. Data comes in from the network link and passes through the NLI 50A and from its data output to the NSC 36 circuitry. The 12.352 MHz clock and 333 Hz (ISYNC) sync inputs to the ~LI 50 continues through to where the 12 MHz-clock and 333 Hz (SYNC) sync signals which clock and load, respectively, both the NLI X~T counter 63 and RCV
counter 64 to synchronize the switching system.
In Fig. 7B, the data (RCVD DATA FROM NETWORK LINK) at input 150 is, in fact received in a synchronous fashion in accordance with the overall timing control of the switching system. The the input 152 (INPUT DATA MUX CONTROL) will always be set to logic one by the microprocessor of the NSC 36 to enable the path from input 150 to output 153 (DATA OUTPUT TO CARD CIRCUITRY). Since the data received from the network link on the NSC NLI 50B is not encoded, a property of the method employed is realized in that there is no need for any circuitry to perform decoding.
The overall timing control of the switching system has been described in the discussion of Fig. 5. Some critical elements in achieving the described synchronous operation are depicted in Fig. 7B and are illustrated in the timing diagram of Fig. 7C.
Various points on Fig. 7B have been labelled A, B, C, D, E and F
and the timing for each is shown in Fig. 7C. In Fig. 7C, the ~1~412~2 12.352 ~1iz clock and 333 Hz (ISYNC) sync signals provided to the ci~cuit ~re depicted. The nature of those provided signals is that the 12.352 MH7 clock toggles indefinitely. Every 37056 12.352 MHz cycles (with is a thrPe msec interval), tne ISYNC
signal which is normally at logic one transitions to logic zero for an interval lasting two 12.352 MHz cycles with the indicated phase. This pattern of the ISYNC signal similarly continues indefinit~ly. The X~T count~r 63 and RCV counter 64 on the NSC
end of the switching system are clocked by an inverted form of this 12.352 MHz signal (12 MHZ-). The circuitry of Fig. 7B forms the load signal (SYNC) to phase synchronize these two counters from which system timing control is administered through the indicated stages labelled A through F. The timing of Signals A
through F and SYNC are depicted in Fig. 7C relative to the circuit's controlling 12.352 MHz and ISYNC input timing.
Fig. 7D has been provided to indicate the relationship between the circuitry depicted in Figs. 7A and 7B, the XMT
counter 63 and RCV counter 64 of Fig. 5, and the synchronous operation of both the transmitted and received network link data.
Referring to Fig. 7D:
Line 3 indicates the timing of the 12.352 MHz clock input in the circuit of Fig. 7B.
Line 4 indicates the timing of the 333 Hz phase synchronization input to the circuit of ~ig. 7B (ISYNC).
Line 6 indicates the 12MHz- clock input depicted in Fig. 7B
to the XMT counter 63 and RCV counter 64 of Fig. 5 which control the overall timing of the NSC end 50A operation.
Line 7 indicat~s the 333 Hz [SYNC] phase sync input depicted in Fig. 7~ to the XMT counter 63 and RCV counter 64 of Fig. 5 which control the overall timing of the NLI 50A operation Line 10 represents a 3.088 MHz output of the RCV counter 64 which, on its low-to-high transition, is used by the latch 75 indicated in Fig. 5 to sample the received network link data at the NLI 50A.
Line 12 represents a 3.088 MHz output of the XMT counter 63 which, on its low-to-high transition, is used by the line encoder 2041~22 68 indicated in Fig. 5 to begin the network transmission interval of each bit output by the NLI 50A.
Line 13 indicates the timing of network link data received at the NLI 50A by the latch 75 de~icted in Fig. 5. The solid area of that line is where data is insured valid, with all propogation delays settled, by the method employed for the switching system.
Lines 14 through 17 indicates the role of each network link bit received in th~ time-division multiplexed strategy employed in this switching system.
Line 19 indicates the timing of PCM data delivered to the circuitry of Fig. 7A for eventual output to the network link.
Line 21 indicates the role of each network link bit transmitted and its role in the time-division multiplexed strategy employed in this switching system. Each network link bit transmitted is shown to begin with a low-to-high transition of the 3.088 MHz clock indicated on line 12. Pulse-width modulation encoding is enforced on each bit transmitted during these 3.088 MHz intervals.
The timing diagrams represented in Fig. 7D and in Figs. 6C
through 6F complement each other. Together they mesh and fully describe the timing of the switching system and its particular time-division m~ltiplex strategy. The circuitry described in Figs. 7A and 7~ provide the core of this functionality on the NLI 50A.
The NLI 50 of Fig. 8 will generate and control the network links connecting the control subsystem associated with line 30 and network termination shelves, or NSC circuits 36. An NLI 50 will be found on each end of a 3.088MHz network link, with each NLI 50 handling a ~air of links -- one for each direction of transmission. On a given card, the NLI 50 will convert the PCM, signaling, and message information passed to it into a serial stream, add some framing and synchronization bits, and transmit this data in encoded form on a network link. In the other direction, the NLI 50 will perform the line decoding and extract PCM, signaling, and message information to hand off to the appropriate card circuitry. The coding employed for data transmitted on a network link from the control subsystem to the network termination unit will be of a ~ulse width modulation form, with varying length pulses used to represent zeros, ones, and synchronization digits. On the other hand, the coding of network link data sent from the network termination units to the control subsystem will be strictly NR~, Fig. lA. There are several forms in wnich PCM and signaling data may be passed to and from the NLI and separate modes of the device have been defined for each.
Referring again to Fig. 9, each NLI 50 will control twenty-four channels of PCM and signaling data. Since the NSC circuit 36 deals with a 768 channel group, it must have thirty-two NLI
circuits 50 on board to handle all channels it must service. The DAS 37, Fig. 3, supports ninety-six channels and, thus, four NLI
circuits 50 are required per board. The DPC, PRI, BRL, and DSP
circuits each support twenty-four channels, requiring only one NLI circuit 50 per board. In addition to differences in the number of NLI circuits 50 for each of these circuits, there are differences in the way each handles the passing of data to and from its NLI circuit 50 and also in the way the internal timing of each ~LI circuit 50 is controlled. Fig. 9 shows how the NLI
50 will be employed in the system of Fig. 3, and Fig. 10 indicates the mode of device data I/O and internal timing control used on each card. The modes of the NLI 50 I/O are specified by hard-wiring WLI mode select pins A and B 81, Fig. 8. Internal timing control of an NLI 50 is fixed by hard-wiring the NLI
Master/Slave~pin 80, Fig. 8.
The NLI 50 and NSC circuits 36 will operate in Mode 0, specified by wiring both mode select pins A and B 81 to logic 0. In Mode 0, data for network link transmission is presented as eleven parallel bits consisting of eight PCM and three "system" bits.
The three system bits consist of a parity bit, a framing bit, and a superframe-synchronous signaling (SFSS) bit. The same eleven bit parallel format is used for output of data received from a network link. NLI circuits 50 on NSC cards 36 will be provided with a 12.352MHz clock and a 333 Hz synchronizaiton pulse by a system clock. To use these signals for master timinq control, each NLI ;0 should have its Master/Slave pin 80 set to logic one.
NLI circuits 50 on DSl port 42, P~I 40, and BRL 38 will operate in Mode 1, specified by wiring mode pin A as logic 0 and pin B as logic one. In Mode 1, PCM data for network link transmission is presented as a 1.544MHz serial bit stream. The serial PCM stream is organized in frames consisting of twenty-four eight bit samples, with each such set of 192 bits preceeded by a frame bit. Signaling data in Mode 1 is presented as four parallel inputs (A, B, C, and D) to the NLI 50, concurrent in timing with receipt of the eighth bit of each channel's sample on the serial PC~ input stream. In ~ode 1, PCM data received from a network link is output by the NLI 50 in the same 1.544MHz serial format as used for transmission. Signaling data received from the network link will not, however, appear at the NLI pins --this data will replace the least significant bit, or LSB, of the PCM on the serial output stream during the system-defined "signaling framesn. It should be noted that the BRL 38 will not use the signaling bit handling features of the NLI SO. NLI
circuits S0 on data port circuits 42, PRI circuits 40, and BRL
circuits 38 should have their Master/Slave~Pins 80 set to logic zero such that internal timing is controlled by the 12.352MHz clock provided by the NLI circuits phase-locked loop, Fig. 5, (PLL) in conjunction with synchronization information obtained from the received network link.
NLI circuits 50 on DAS circuits 37 will operate in Mode 2, specified by wiring Mode Pin A as logic one and Pin B as logic zero. In Mode 2, PCM data for network link transmission is presented to the NLI 50 as eight parallel PCM bi~s. Likewise, da~a received from a network link will be output from the NLI S0 as eight parallel PCM bits. A-port signaling data will be extracted from the LSB of PCM of each channel on the received link during the system-defined A-port signaling frames and will be stored for eventual reading by the circuits microprocessor. NLI
circuits 50 in DAS circuits 37 should have their Master/Slave~pins -80 set to logic zero such that internal timing is controlled by tne 12.352MHz clock provided by the card's phase-lock~d loop (PL~), Fig. 5, in c~njunction with synchronization information obtained from the received network link.
The NLI circuits 50 on DSP circuits 37 will operate in Mode 3, specified by wiring both mode select pins A and B 81 as logic 1. In Mode 3, PCM data for transmission is presented to the NLI
50 as a 1.536~Hz serial data stream consisting of twenty-four eight bit PCM samples. PCM data received from a network link is also output from the NLI as a 1.536~Hz serial data stream consisting of twenty-four 8 bit PCM samples. A-port signaling data will be extracted from the LSB of PCM of each channel on the received link during the system defined A-signaling frames and wil~ be stored for eventual reading by the circuit's microprocessor. NLI 50 on DSP circuits 37 should have their Master/Slave~pins 80 set to logic zero such that internal timing is controlled by the 12.352MHz clock provided by the circuit's phase-locked loop (PLL), Fig. 5, in conjunction with synchronization information obtained from the received network link.
The NLI 50 performs numerous functions. It converts twenty-four channels of PCM and signaling data into a 3.088MHz serial bit stream and converts a received 3.088MHz serial bit stream into PCM and signaling data. It embeds message information into each transmitted network link using a packet protocol and extracts message information from each received link. It also embeds clock into each transmitted network link through use of pulse-width modulated line coding described above, providing link synchronization by embedding "sync" bits 24 in the serial data stream and extracts clock and sync from each received link. PCM
and signaling data insertion/extraction registers are provided for background testing, and a signaling store with microprocessor access is provided for received A-signaling bits. There is also a ~icroprocessor interface for message information handling and chip control.
Referring to Fig. 11, the NLI 50 has five interfaces: an 204122~
-outbound data interface, the tr~nsmit link interface 82, the receive link interEace 86, an in~ound data interface 88, and a microprocessor interface 90. The outbound data interface 82 ~rovides means for a card to hand off PCM and signaling data to be transmitted on a network link. This data is merged with information specified for transmission by the microprocessor interface 90 and is sent in pulse-width modulation encoded form to the outbound network link by the transmit link interface 84.
In the other direction, data rec~ived form a n~twork link 47 arrives at the receive link interface 86 where PCM and signaling data is extracted and sent to tne inbound data interface 88 for output from the NLI 50. Message information is also extracted from the received network link 47 and is routed to the microprocessor interface 90. The connections between the microprocessor interface 90 and both the receive and transmit interfaces 86 and 84 are made via FIFOs 91.
While there are several formats for data flowing across the NLI inbound and outoound data interfaces 88 and 82, the format of data on each network link 47, whether created by the transmit link interface 84 or received at the receive link interface 86, will always be as indicated in Fig. 12.
The outbound data inter~ace 82 will accept either parallel or serial in~ut for network link transmission. The operation of the outbound data interface 82 is dependent on the strapping of the NLI mode select pins.
As stated previously, each of the thirty-two NLI circuits 50 on the NSC circuit 36 receives parallel data for each of twenty-four channels for network link transmission. This data is obtained from a 768 channel TDM bus. Referring to Fig. 12, each NLI 50 will latcn a set of twenty-four, eleven bit samples at an approximate 192kHz rate. The timing for this latching is derived from counters within the NLI 50 which are driven by the 12.352MHZ
control time base clock, Fig.5, and 333Hz synchronization pulse provided to each element on the ~lSC circuit 36. To identify which set of twenty-four channels of the 768 channel bus are intended for a given circuit, each NLI 50 has a position register loaded witn a value from zero to thirty-one. Eac~
50A on NSC circuit 3~ will have a different value in its position register. The eleven bits handed to each NLI 50A originate at the TSI circuit 34 and consist of eight PCM and three system bits. The theee system bits include a parity bit, a frame bit, and a superframe-synchronous signaling tSFSS) bit. All of these inputs except the S~SS bit are sourced from the switching complex. The SFSS bit is generated by the signaling circuit on the TSI circuit 34 and is passed to the NLI 50A in parallel with the other ten. The parity bit received by the NLI 50A is on the eight PCil and one frame bit generated by the TSI 34, and checking of ttlis parity is performed in the outbound data interface 82, Fig. 11. If a parity error is detected, the appropriate bit of an NLI interrupt status register, Fig. 18, will be set and the DPC circuit's microprocessor will be interrupted. Regardless of the priority check results, the ten remaining data bits are transferred to the transmit link interface 84.
On DPC circuits 42, Fig. 4A, and PRI circuits 40, Figs. 3 and 9, serial PCM and parallel signaling data is received at the outbound data interface 82 for transmission on a network link 47.
The serial stream contains twenty-four channels of PCM data and a frame bit is received at a 1.544MHz rate. A pin 92, Fig. 8, of the NLI 50 has been provided to source a transmit 1.544MHz clock to be used on DPC circui~s 42 and PRI circuits 40 in generating this data stream. An eight k~z transmit sync output pin 100, Fig. 8, has been provided on the NLI 50, so that channel order can be derived on the NLI 50. Timing of each of these clock signals is derived from the received network link synchronization information in conjunction with the 12.352~Hz input to the NLI 50 from tne NLI PLL pin.
The eight bit PCM sample of each channel is extracted from the received serial stream and is converted into parallel form.
The frame bit of the serial stream is latched and passed in parallel with the parallel PCM data of each channel to the transmit link interface 84. The four bits of signaling information received at the outbound data interface 82 represent the A,B,C, and D signaling bics for ~ach channel. 3ased on system-defined superframe timing, the appropriate signaling bit of the four received is selected ~nd sent to the transmit link interface 82 in parallel -~ith the PCM and frame bits. Under microprocessor control, .his signaling data may also be specified to replace the LS~ of outgoina PC~I samples. This type of control is maintained on a channel-by-channel basis through processor specifications for each channel in the transmit signaling control registers, Fig. 5.
Operation of the outbound data interface 82 is comparable on BRL circuits 38, Fig. 9, except that no signaling bits are passed to the NLI 50.
On DAS circuits 37, twenty-four eight bit parallel PCM
samples are presented to the outbound data interface 82 every 125 microseconds for transmission to a network link. The ~LI 50 will supply the DAS 37 with an eight kHz transmit sync output on pin g3 t~ be used with the on board 12.352MHz clock such that the timing and channel order for passing data to the outbound data interface 82 can be derived. The DAS circuit 37, will supply the NLI 50 with data for transmission at a 192kHz rate. This data will, in turn, be transferred to the transmit data interface 84.
On DSP circuits 42, serial PC~ data is received at the outbound data interface 82 for transmission on a network link 47.
The serial stream contains twenty-four channels of PCM data and is received at a 1.536MHz rate. The 1.536MHz transmit clock pin 95 of the NLI 50 has been provided to source the clock to be used on the DSP circuit 44 in generating this data stream. The eight kHz transmit sync pin 93 is also used for determining channel order. The 8 bit PC;~ sample of eacn channel is extracted from the serial stream, converted into parallel form and passed to the transmit link interface 84.
The transmit link interface 84 receives data from the outbound data interface 82 and the microprocessor interface 90.
Sixt~en bit data for link tr3nsmission is formed by combining the (up to) ten bits from tne outbound data interface 82 with four bits from the microprocessor interface 90, generating odd parity on the set, and appending a bit fixed as logic one. Twenty-four such words are formed every 125usec. Two link sync bits are added to these twenty-Eour, sixteen bi. words and the entire block of information is serialized. The setting o~ the NLI's ~laster/Slave~pin 80 determines tne coding employe2 on the outbound 3.083MHz stream. NLI circuits 50 strapped to function as a master 50A employ a pulse-width modulation coding in order for the NLI circuits 50 operatinq as a slave 50B at the far end of the network link to be able to derive a clock from the low-to-high transition which begins each bit interval. N~I circuits 50 which are strapped as a slave 50B output the 3.088M~z stream as simple NRZ, the ones represented as high voltages for the entire bit interval and zeros as low voltages.
The receive link interface 86 receives a 3.088MHz network link and passes the stream immediately through a decoder.
Transitions of data on the received stream are detected in the pulse-width modulation decoder, Fig. 5, and a 3.088MHz clock is derived. This clock is divided by two to form a 1.544M~z signal which, with respect to NLI circuits 50B specified for slave operation by their Master/Slave~pin 80 setting, will be sent out of the NLI 50B to a phase-locked loop circuit, Fig. 5, where 12.352MHz is created and passed back to the NLI 50 for use in deriving all timing. The serial data output of the decoder is clocked into a shift register at a 3.088MHz rate to convert the data into parallel form. Sixteen bit words are formed in this fashion consisting of ten bits bound for the inbound data interface 88, four bits for the microprocessor interface 90, a parity bit on the entire word, and a fixed bit of logic one. An odd parity cllecker is used to verify a properly received data word and, if a parity error is detected, the appropriate bit of the NLI interrupt status register, Fig. 5, will be set and the microprocessor of the NLI circuit 50B will be interrupted. In the 3.088MHz link there are 386 bits transmitted every 125 microseconds. Since only 384 are used for channel data (twenty-four sets of sixteen bit words), two extra bits of link sync information are also rec~ived in the data stream. These bits are . 2041222 routeæ to the counter/-imer circuit 92, Fig. 11, where they are used for acquiring synchronization to the link transmitter.
The inbound data interface 88 receives ten bits from the receive link inter'ace 86 and tr~nsmits this ~ata in either parallel or serial form. The mode select pins on the ~LI 50 are used to selec~ the output mode ror each card.
~ n tne NSC circuit 36, data from each of the thirty-two inbound data interfaces 88 are merged to form a 768 channel TDM
bus. Each NLI master circuit 50A will source a set of twenty-four eleven bit samples at an approximate 192kHz rate. The timing for this latching is derived from counters within the NLI
circuit 50A which are driven by the 12.352MHZ clock and 333Hz synchronization pulse provided to each NLI 50A on the NSC circuit 36 by the clock card 32, Fig. 3. Each NLI circuit 50A has a position register loaded with a value from zero to thirty-one to determine when it should output to this 768 channel bus. r~hen a given NLI circuit 50A is not outputting data, it will keep its outpu. pins in a high impedance state. When a given NLI circuit 50 is outputting data, tne EXG pin 97 of that NLI 50 will generate a low level pulse which is used for special purposes on the NSC circuit 36.
Eleven bits of output are provided by the inbound data interface 88 of each NLI circuit 50, consisting of eight PCM and three system bits. The three system bits include a parity bit, a frame bi~ and a SFSS bit. All of these outputs except the SFSS
bit are sent to the TSI circuit 34, with the parity bit generated on the nine non-SFSS data bits. The SFSS bit is sent to the signaling circuit of the TSI circuit 34 in parallel with the other ten.
In DPC circuits 42 and PRI circuits 40, serial PCM data is output by t~e inbound data interface 88. The serial stream contains twenty-four channels of PCM data and a frame bit and is transmitted at a 1.544MHz rate. The receive 1.544MHz clock pin 92, ~ig. 8, of the NLI nas been provided to be used by DPC 42 and PRI 40 in latc~ing this data stream. A 333Hz receive sync output pin 94 has also been provided such that channel and frame order ~-` " 20~2~
can be derived on these circuits. Timin~ of each of these clock si`~nals is derived from the received network link sync information in conjunction with the 12.352~Hz input from the NLI
phase locked loop circuit.
Signaling information obtained for each channel in the SFSS
bit position on tlle received net~ork link may be inserted into the LSB of each PC~I word output b;~ the inoound data interface 88 in accordance with the system-defined superframe timing. This is selectable on a channel-by-channel basis under micropeocessor control by setting the bit corresponding to a channel in the received link signaling control registers, Figs. 33 - 35.
Operation of the inbound data interface 88 is comparable on BRL
circuits 38, except that no signaling bit information is ever inserted into PC~I samples.
In DAS circuits 37, twenty-four eight bit parallel PCM samples are output by the inbound data interface 88 every 125usec. Each of the four MLI circuits 5~ on the card will be assigned a distinct value in their position register, Fig. 19, to define when each should present parallel output onto a common output bus. When a given device is not passing data from its inbound data interface 88 to this bus, its output pins will remain in a high impedance state. The DAS circuit 37 circuitry will make use of the OSYC pin 98, Fig. 8, of the NLI circuit S0 to determine when output data should be latched from a given NLI circuit 50B.
In DSP circuits 42, serial PCM data is output by the inbound data interface 88. The serial stream contains twenty-four channels of PCM data and is transmitted at a 1.536MHz rate. The 1.536MHz rec2ive clock pin 92 has been provided to source the clock to be used on the DSP circuit 44 in generating this data stream. An 8kHz receive sync pin 100, Fig. 8, and the 1.536MHz and 8kHz pins provided for interaction with the inbound data interface 88 and those provided for interaction with the outbound data interface 82 are distinct. Each set has a different phase than the other. The eight bit PC~ sample of each channel is e~tracted from the serial stream, converted into parallel form and passed to the transmit link interface 84.
2041~2 For channels received by the DSP circuit 42, signaling bits are present in the LSB of PC:~ samples during ~he system-defined signaling frames. A-signaling bits will be captured by the NLI
circui. 50 and s~ored in the receive signaling data registers, Figs. 36 - 38, for reading by the card microprocessor.
The microprocessor interface 90 provides a variety of registers with which the microprocessor can communicate with the NLI circuit 50 and control its function. One major function controlled by the microprocessor interface 90 is associated with passing messages between circuits. This circuit will perform the necessary functions associated with embedding message information into tne 3.088MHz network link transmitted and, conversely, with extracting such information from the received link. The message and associated control information is allocated four out of every sixteen bits on a network link. These information bits are sent using a packet protocol at a 768 kbit/sec rate.
Communications between the control and the network termination units is always initiated from the NSC circuit 36.
'~hen message information needs to be sent to a network card, microprocessor of the NSC 36 will buffer up to 64 bytes -- the first being a byte count -- in an NLI transmit FIFO, through means of writing to a transmit message data register, Fig. 28. Therea~ter, the microprocessor will write a word to th NLI control register, Fig. 17, containing a logic one in the send message bit position. The NLI S0 will "packetize~ the message bytes according to the protocol depicted in Fig. 13, adding flag, status field, and checksum bytes around this information field. Note that during times when no messages are being sent, the NLI circuit 50 will output non-flag characters in the 768kbit/sec field.
The NLI circuit 50 constantly searches for incoming message information by checking for an opening flag in the message field of its received link. Once the opening flag is recognized and the byte count is determined, the NLI circuit 50 will buffer the message bytes in a receive FIFO. A running checksum on the message bytes will be kept as they are receive~ and this will be compared ~o the checksum byte~appended to the incoming message. If the checksum received differs from that calculated, the appropriate bit of an interrupt status register, Fig. 18, will be set and the circuits microprocessor will oe interrupted.
Upon receipt of a valid message, the receive FIFO full bit of the interrupt status register, Fig. 18, will be set and the received status field bits will be interpreted and acted upon.
In the NSC circuit 36, a received message will be detected by polling each interrupt status register, Fig. 18, of the NLI
circuits 50 to see if this receive FIFO full bit is set. The message may then be read out of the NLI circuit 50 through the receive message data register, Fig. 29. The first byte read will be the byte count, and the microprocessor should loop that number of times, re~ding the (up to) sixty-three other message bytes.
The NLI circuit 50 will function in a similar fashion in all other modes with ~he following exceptions. First, on receipt of an inbound message, the circuit's microprocessor will be interrupted along with the indic~tion of receive FIFO full in the ~ILI interrupt status register, Fig. 18. Secondly, on receipt of a message, the receive FIFO will become "locked" such that the message will not be overwritten by a second message to the card.
Obviously, any subsequent messages which are passed while the FIFO remains locked will be lost. The processor must act to unlock the FIFO by altering the appropriate bit of the control register, Fig. 17, upon extracting the current message from the rec~ive FIFO. The FIFO lock mechanism is not available for devices, such as those on the NSC card 36, with master designations on the Master/Slave~pin 80. Finally, no message should be transmitted by an NLI 50 specified to operate in Modes 1 through 3 until a message has been received requesting a response. ~owever, there is nothing in the circuit to restrict sending an unsolicited message.
The NLI circuit 50 will "packetize" messages from the pro~essor using a protocol consisting of adding an opening flag, a status field, and a checksum on all preceeding bytes except the ~3 20412~2 opening flag. The opening flag represents the beginning of a message frame and will always have the value of 7E ~ex (01111110 Binary). The status field is an eight bit field used for sending control information from the ~SC circuit 3~ to network cards --its contents have no meaning on links bound to an NSC 36. The st3tus field bits are used to cause either a reset or a non-maskable interru~t (NMI) to the processor on an NSC circuit 36 or to cause it to switch which bus from which serial information is received. The (up to) sixty-four ~ytes of message information will be transmitted after the status field, with the first byte of the information field always being byte count of that field.
While transmitting this data, a checksum value is calculated.
This checksum byte will be inserted on the link af-er completion OL the information field to provide the far end with a means of checking message integrity.
It should be noted that the byte count beginning the information field may take on the range from zero to sixty-three.
A zero byte count message may be sent, for instance, to simply pass status field information between cards. However, a zero byte count message properly received at a slave device, even with the receive FIFO locked, will be interpreted and acted upon. A
sixty-three byte count message is one with a complet~ly full information field comprising one byte count digit and sixty-three actual data bytes.
The NLI circuit 50 is designed to recognize parity errors on data coming into the NLI circuit 50, as well as generate parity on data leaving the NLI circuit 50. Parity errors can be detected on outbound parallel data from the TSI Mode 0, on received 3.088MHz serial data in all modes or on bytes transferred ,rom either of the two FIFOS maintained within the NLI circuit S0. Odd parity is employed on the 3.088MHz serial links, even parity is employed on the two internal FIFOs, and the type of parity is selected via the control register for Mode 0 TSI data checking and generation. Violations of parity are indicated as to type in the NLI interrupt status register, Fig.
18, and are always accompanied by an interrupt of the circuit's microprocessor. Should the microprocessor wish to mask any of these parity error interru~ts, i~ may do so by setting the corresponding bit of the control register, Fig. 15. Further, should the microproc~ssor wish to cause any or all of ~hese errors to test its own diagnostic software, bits of the control register, ~ig. 14, have also be~n speciEied for this purpose.
Similar to the parity checking, the NLI circuit 50 will always observe the checksum byte associated with each received message. Should the checksum value calculated during message receipt not correspond exactly to that appended to the message, the circuit's microprocessor will receive an interrupt and an indication of such will be placed in the interrupt status register. Such interrupts may be masked or "caused" for diagnostic software checking by setting the appropriate bits of the control register.
Should the NLI 50 ever lose synchronization with the transmitter of its received network link, an indication of such will-be made in the interrupt status register and the circuit's microprocessor will be interrupted. For NLI circuits strapped as a master 50A, the interrupt status register indication will be in the receive link out-of-sync bit location; for NLI circuits 50 strapped as slave units 50B, the interrupt will be indicated in the master clock out-of-sync bit. Further, in NLI circuits 50 operating as a master unit 50A, checks will be made that the internal counters are in step with the synchronization signal provided on a NLI sync input pin 97. Should such synchronization ever be lost, the master clock out-of-sync bit of the interrupt status register, Fig. 18, will be set and the circuit's processor interrupted. Consistent with the handling of other error interrupts, these types may be masked, or ~causedn, for diagnostic software checking by setting the appropriate bits of the control register.
The NLI circuit 50 also provides features for background testing of several system functions. There are registers in each NLI circuit 50 which allow the insertion of a known PCM and signaling pattern in place of the data of one channel to be -output on tne transmit networ~ link. The microprocessor can specify ~n eight bit PC`~ and/or ~ four bit A,B,C, and D si~naling value in ~he transmit insertion data registers, Figs. 26 and 41, and a channel number desianation in tne transmit insertion address register, Fig. 25. ~y setting the enable PC~ insertion bit of the control regis.er, Fig. 16, the microprocessor will cause the ~,B,C and ~ signalinq value to be substituted during -the system defined superframe timing on the SFSS bit for that channel. In this fashion, an NSC 36 can, for a channel out-of-service, send known values on the link to the switching complex and to a signaling circuit of the TSI 34 where action can be taken to check their operation. PCM insertion can take place without signaling insertion and vice versa. There are, similarly, extraction data register, Figs. 39 and 40, and an address register, Fig. 24, in the NLI 50 for latching a given channel's PCM and signaling data as it is received from a network link 47. The insertion and extraction registers can be used ei~her individually or as a pair to monitor a variety of system functions.
The NLI circuit 50 will have a lOmsec output pin for providing each card with a real-time signal for interrupting its processor. This lOmsec signal will be derived from the 12.352MHz clock input to the NLI circuit 50. This interrupt should be acknowledged by reading the clear timer/NMI register of the NLI
circuit 50, Fig. 43, after which the output signal will go inactive until the next interval has elapsed.
The NLI circuit 50 has an output pin for providing DSP
circuits 42 with an interrupt signal for their microprocessor each time A-port signaling bits have been received for all channels on the network link. This 1.5msec signal will be derived from the 12.352MHz clock input to the NLI circuit 50 in accordance witn the system-defined superframe structure. This interrupt should be acknowledged by reading the clear timer/NMI
resister OL the NLI circuit 50, Fig. 43, after which the output si~nal will go inactive until tne next interval has elapsed.
Four pins have been provided on the NLI circuit 50 to 20~1222 accommodate 56 or 54kbps data links. Two pins r~present clock sianals generated oy the ~LI cir~uit 50 for use in transferring 56 or 64kbps data in~o and out of t:~e ~LI circuit. The two clock signals are not in phase. The remaining two pins are the avenues for 56 or ~4kbps data T/O. On the PRI circuit 40, these pins will be used in transferring data between the NLI circuit 50 and a serial communications controller (SCC), which in turn will be connected to the circuit's microprocessor. In this fashion, the processor will be able to receive data from one channel within the NLI circuit 50 and, likewise, source the data bound to that channel. The 56 or 64kbps channel with which the processor can interact will be one of those arriving/departing on the Tl line connected to the circuit. Data link operation must be enabled and 56 or 64kbps operation specified by setting the appropriate bits in the control register, Fig. 16.
A DTAC~ output pin 102, Fig. 8, is provided on each NLI
circuit 50 for use in handshaking during data transEers with a terminal circuit microprocessor.
The registers which compose the microprocessor interface to the NLI are described below and shown in Figs. 14 et seq.
Addresses for each of the registers are given along with their names. These addreses contain five bits and their designation is from A5-Al. On 68000-microprocessor based circuits which employ the NLI circuit 50, it should be expected that the NLI registers will not be at contiguous locations in the processor's address spectrum -- the NLI registers may be placed in either the upper byte only or lower byte only of the processor's data bus. In addition to the address given with each register, there are Read-Only (RO) designations given to the appropriate registers. Any register without an RO designation is read/writeable.
In the control MS register, Fig. 14, of the NLI circuit 50, receive link out-of-sync interrupts cannot be generated for an NLI circuit witn slave designation on its Master/Slave~pin 80;
outbound data parity errors c~n only be caused on NLI circuits 50 strapped for Mode 0 -- the only operating mode where parity flows into the outbound data interface 82.
2~ 22 In the control SS register, Fig. 15, of the ~LI circui. 50, even if a siven interrupt is masked, the status register, ~
lô~ wiil continue to give indications that a given event has occurred. Set.ing bits of .his register simply effects the operation of tne interrupt output pin.
In the concrol TS register, Fia. 16, the IDE bit will be cleared whenever the device goes out of sync and the IDE
bit must be set after the device acguires sync, regar~less of the mode of operation. Bit three will always be read as zero, and it should not be expected to read back from this register exactly what was written to it in all cases. If in Mode 0, the SUFRM bit should be set to select 333Hz sync operation.
In the control LS register, Fig. 17, the receive FIFO lock, will never be activated and can never be set for devices with a master designation on their Master/Slave~pins 80. Bit five will always be read as a zero, ~nd it should not be expected to read back from this register exactly what was wr;tten to it in all cases.
In the interrupt status register, ~ia. 18, receive link out-of-sync interrupts will never occur for devices with slave designations on their Master~Slave~pins 80. Also, outbound data parity error interrupts will never occur for devices which have mode designations other than zero.
In the position register, Fig. 19, bits ~ive through seven will always be read as zero, and it s~ould be expected to read back from this register exactly what was written to it in all cases.
In the transmit link MS~counter load register, Fig. 20, for NLI circuits 50A designated as a master, the value which should be placed-into this register is B~H. For NLI circuits 50~ designated~
a slave, the value which should be placed into this register is 08H.
In the transmit link LS-co~nter loaa register, ~ig. 21, for devices designated as a master circuit ~OA, the value which should be placed into the register iB F6H. For NLI circuits ~OB
designated slave, the value wnich should be placed into the 21)412~
register is ~AH.
In the receive link ~IS co~nter load register, Fig. 22, for ~LI circuits 50 designated as a mas-er the value which should be placed into this register is OOH. While ~LI circuits 50 devices designated slave, the value which should be placed into this register is 3DH.
In the receive link LS counter load register, Fig. 23, for NLI circuits 50 designated as a master, the value which should be placed into this register is 02H. For devices designated slave, the value which should be placed into this register is C8H.
In the extraction address register, Fig. 24, bits five through seven will always be read as a zero, and it should not be expected to read back from this register exactly what was written to it i~ all cases.
In the insertion address register, Fig. 25, bits five through seven will always be read as a zero, and it should not be expected to read back from this register exactly what was written to it in all cases.
In the insertion MS data register, Fig. 26, bits four through seven will always be read as a zero, and it should not be expected to read back from this register exactly what was written to it in all cases.
In the 56/64kbps data link address register, Fig. 27, bits five through seven will always be read as a zero, and it should not be expected to read back from this register exactly what was written to it in all cases.
The order of operations to be performed during device initialization should be as follows:
1. ~ask all interrupts by writing FFh to the control SS
register;
2. Write the appropriate data (given above) into the transmit and receive link counter load registers, Fios. 20 and 23;
3. Read the interrupt status register and assure that the ~LI 50 is giving "in-sync" indications. Continue to loop until the device does yield these indications;
There is, however, a thirty foot limitation on the length of network link cabling for this latter point to prevail due to ` 204122:2 phase delays and noise problems associated with longer cables.
Practically speaking, this maximum cable length is not a limiting factor since network and network termination functions can be easily located within the distance of one another.
Each of the ne~work termination circuits has its own form of interface to the NLI 50B for passing twenty-four channel data.
The NLI 50B preferably provided with "moden selection pins in order for the card on which it reside-s to specify the desired twenty-four channel interface required.
Referring now to Fig. 5, an NLI circuit 50 operating as a control unit, or master unit, 50A within an NSC 36 is shown simply connected with another NLI circuit 50 of a DPC 42 which has been preselected to operate as a network termination unit, or slave unit, 50B.
At the NSC 50A, a 12.352 ~Hz frequency reference and a 333 Hz phase reference are provided to the ~LI 50A on lines 80 and 82. Two sets of fixed-modulus counters 63 and 64 are driven by these reference inputs. The 12.352 MHz frequency reference is provided to each of these counters as the clock input; the 333 Hz phase reference is provided to each as the sync (reload) input.
The modulus of the XMT counter 63 is exactly the same as that of the RCV counter 64. Each consists of two stages with the first stage being an eleven bit counter that ranges on successive clock inputs from counts zero to 1543 and a second stage being a five bit counter ranging from zero to twenty-three. The first stage of each c~unter must range from zero through 1543 before the second stage is allowed to increment one time. When the first stage counter reaches count 1543, the next received 12.352 MHz clock input will cause that counter to go to zero. Similarly, when the second stage counter reaches count twenty-three, the next time that the first stage counter is at its maximum value and a 12.352 MHz clock is received, the second stage count will revert to zero. Registers are maintained within the NLI 50A as input to these counters. Figs. 20 and 23 indicate the registers addressable by the microprocessor 58, Fig. ~B, which effect counter operation. Upon the initialization of these registers by 20412~2 -the ~icroprocessor 58, each time that the 333 ~z phase reference input on line 80 is received by the XMT counter 63 and RCV
counter 64, the values from these registers are inserted as the next count or those counters. In this fashion, the microprocessor 58 can specify a phase difference between the XMT
counter 63 and RCV counter 64 simply by specifying a different value in the associated counter load registers for each. This is useful as at the NLI 50B, where there is similarly an XMT counter 65 and a receive counter 66. The modulus of these counters is exactly the same as those on the NSC 50A. The XMT counter 66 and RCV counter 65 of the NLI 50B differ from those on the NLI 50A
only in the way that 12.352 ~Hz clock and 333 Hz sync is applied to them and, potentially, in the counter load register values that their microprocessors of therir associated circuits have set for them once 333 Hz sync is received.
At the NLI 50A, voice and control message data is applied as input to a multiplexer 67 for ultimate transmission to the network termination circuit. Outputs of the X~T counter 63 are used to selet which of these inputs are to be applied to the line encoder 68. A third input to the multiplexer will be anot~er output of the XMT counter 63 indicating that it is time to present a 333 Hz sync signal on the transmitted network link.
The line encoder will act on either the logic zero or logic one data ~rom the voice or control message inputs to produce the encoded logic zero or logic one symbols in Fig. 2. When it receives an input indicating that a sync symbol should be transmitted to the network link, it produces the sync symbol of Fig. 2.
At the network termination end, 50B, the output of the NLI
line encoder 68 is received after propogation through the interconnecting wire 84. ThiS received network link data is passed through a delay network 69 and then input to a divide-by-two circuit 70 such as a toggle flip-flop. Since each symbol received from the network link begins with a low-to-high transition, the received network link, once delayed, is used as the clock input of this toggle flip-Elop 70. The result is a 2~412~2 1.544 MHz clock as input from the divide-by-two circuit 70 which is, in turn applied as input to a phase-locked loop 71 to create a 12.352 MHz clock. A property of this 12.352 ~Hz output from the phase-locked loop 71 is that it is four times higher in frequency than the 3.088 MHz data rate of the r~ceived network link and that every fourth low-to-high edge of this 12.352 MHz clock will lag in phase behind the low-to-high edge beginning each received bit interval of the received network link. The duration of this phase lag is essentially fixed as the duration of the delay block 69.
In this fashion, the 12.352 MHz clock can be used to sample each received network link bit interval four times to discern which of the three symbols was output by the NSC line encoder 68 in a given bit interval. This sampling and decoding of the received bit is the function of the line decoder and demultiplex circuits 72. The 12.352 MHz clock developed by the phase-locked loop 71 is used as the clock input to the RCV counter 65 and XMT
counter 66 at the network termination circuit. When the line decoder and demultiplex circuits 72 identify that a sync input has been received from the incoming network link, this sync indication is applied to the sync (reload) input of the RCV
counter 65 and the XMT counter 66 through means of the phase sync acquisition circuit 73.
Since both the RCV counter 65 and XMT counter 66 operate in a fixed modulus and since the value that they take on when a sync is received is fixed by the microprocessor of the associated network termination circuit by loading the associated counter load registers (Figs. 20 through 23), the phase sync acquisition circuit 73 can compare the current value of each counter against its load register values to predict that a sync symbol should be received as the next input bit from the incoming network link.
Sould either the next bit received from the incoming network link not be a sync symbol, an out-of-sync condition is indicated at the network termination circuit. Should a sync symbol be received ont he incoming network link and it not be predicted by a comparison of either counters current values to its load value, ` 21~41~22 again an out-of-sync condition is indicated t the network termination circuit.
Once the RCV counter 65 and X~IT counter 66 on the network termination initially achieve synchronization with the ~SC 36, they should remain the sync thereafter. In a synchronized condition, the RCV counter 65 will output a signal used to demultiplex the decoded voice and control message data received to appropriate card circuitry from the line decoder and demultiplex circuit 72. Similarly, voice and control message data to be transmitted to the NSC 36 will be presented from other network termination card circuitry to a multiplexer 74 for network link transmission. The XMT counter 66 will provide another input to this multiplexer 74 for insertion during sync bit intervals on the transmitted network link. A XMT counter 66 output will control which bit, whether voice, control message, or sync type, is to be transmitted at a given time.
On the other hand, it is important to note that the transmitted network link data from the network termination NLI
50B is not~pulse-width modulation encoded. This output is strictly logic zero or logic one throughout the 3.088 MHz bit interval. The XMT counter 66 will cause the sync bits to output to the network link to formulate a unique patterns of logic zeroes and logic ones.
The RCV counter 6S on the network termination NLI 50B is clearly fre~uency synchronized to its XMT counter 66. The phase difference between these two counters is controlled by the termination circuits microprocessor by speciEying the value on receiving a sync input. Similarly, the XMT counter 63 at the NSC
36 is clearly frequency synchronized to its RCV counter 64, and the phase difference is controlled by the microprocessor 58 setting of the values when sync is applied. Since the RCV
counter 65 is synchronized to the XMT counter 63 of the NLI 50A
by our pulse-width modulation scheme, the network termination XMT
counter 66 is synchronized to the RCV counter 64. The entire system is thus frequency synchronized and, with appropriate values in all counter's 63-66 load registers, phase synchronized i~ achieved, as well.
For purposes of a illustration, consider the time delay along the path of a bit output by the line encoder 68 of NLI 50A
at the NSC 36, propogating through the network link cable to the network termination circuit DSP 44, propogatinq through the line decoder and demultipl~xer 72, being looped back as input to the transmit multiplexer 74, propogating through the multiplexer and inerconnecting network link cable back to the NSC, and being received at the input latch 75. If the length o the interconnecting cable is limited, with the circuitry of Fig. 5, the round trip interval can be less than one 3.088 MHz bit interval. It is this circuitry and method of Fig. 5 with its inherent synchronization and controlled time delay that allows simple receipt of the non-encoded network link data transmitted from the network termination multiplexer 74 wi~h a latch 75 at the NSC 36. This latch 75 is clocked with a 3.088 MHz signal derived by the NSC RCV counter 64 by simple division of the 12.352 MHz clock that RCV counter 64 receives. The instant which begins a 3.083 MHz output bit interval by the NSC line encoder 68 is the same instant that a bit is sampled and received by its received network link latch 75 The data received by the NSC latch 75 is demultiplexed to go to the appropriate NSC circuitry by a demultiplexer 76 controlled by an output of the RCV counter 64. Further, since the entire system is in synchronization, it is known when to expect sync bits at the NSC end from the network termination end. The farend sync check circuit 77 receives input from the RCV counter 64 to identify those instants when logic one level sync bits should be received from the network termination end and then samples the received network link bits output from the demultiplexer 76. Should the far-end sync check circuit 77 discern that a logic one sync bit was either not received from the network link when it was expected or was received when it was not expected, an indication that the network termination end 50B
is out of sync with respect to the NSC end 50A will result and the NSC microprocessor 58 will be interrupted.
Referring to Figs. 6A and 63, the transmit link section and receive link s~oction of the network termination, or slave, unit 50B are seen. These operate in association with the waveforms shown in Fig. 6C, 6D, 6E and 6F of the drawing.
The circuitry of Fig. 6A is incorporated together with that of Fig. 7A in one integrated circuit. Also, different portions of the circitry in figure 6A (7A) are applicable when the device is employed on the NSC end is a network link interface 50A than would be the case if the device were employed in the network termination end as in an NLI 50B. Similarly, different portions of the circuitry in Fig. 6~(7B) are applicable when the device is employed at the NSC end as a network link interface 50A than would be the case if the device were employed at the network ter~Tination end as an NLI 50B.
It is presumed that the master/slave pin of the NLI 50, Fig. 8, is fixed to logic zero (indicating slave mode) in this application, enabling the appropriate NLI 50B portion of the circuitry of the NLI 50. The NLI receives input from the fixed-modulus XMT counter 66. The XMT counter 66, Fig. 5, consists of two stages with its first stage being an 11 bit counter that ranges on successive clock inputs from counts 0 to 1543 and its second stage a five bit counter ranging from 0 to 23. The first stage of each counter must range from 0 through 1543, and the second stage is a five bit counter ranging from 0 to 23. The first stage of each counter must range from 0 through 1543 before the second stage is allowed to increment one time. When the first stage counter reaches count 1543, the next received clock input will cause that counter to go to zero. Similarlyr when the second stage counter reaches count 23, the next time that the first stage counter is at its maximum value and clock is received, the second stage count will revert to 0. The first stage counter outputs 66~ are labelled I"VAL00 through ICVAL10 on Fig. 6A, but outputs ICVAL02 and ICVAL03 are unused. The second stage counter outputs 66E~ are labelled IFRMCT0 through IFRMCT4 on ` Z041~22 Fig. 6A. The XMT counter 65 is~clocked by the low to high edge of ~n inverted copy of the same 12.352 MHZ clock plus which forced X~T counter 56 outputs to go to a state with ICVALOO, ICVALOl=OO.
Essentially, si~nals at 197 and 198 are NORed togetner to provide a network link bit output lasting one 3.088 MHz period.
If output 195 is low then output 196 is high. r~hen output 195 is high, the data input to the circuit labelled DATA IN will be whatever is transmitted on the network link. If output 196 is high, however, the output will be whatever is also on output 194.
The output 194 signal is the means whereby sync bits are output to the network link from the network termination NLI 50B to the NSC
NLI 50A, with a unique pattern being maintained. Output 194 is equal to the value of output 193 sampled after the output 193 signal has settled from the change in counter state. Similarlly, output 195 is equal to the value of output 192 sampled after the output 192 signal has settled from the change in counter state.
Also, output 196 is the complement of output 195.
The following combinational logic expressions serve to fully describe the operation of the relevant protion of the circuit:
Qut~ut Candition 191=1 only when [ICVALlO-ICVALOO]=OOOOOxxxxxX where X=irrelevant 192=0 only when [ICVAL10-ICVALOO]=OOOOOlllXXX where X=irrelevant 193=0 only when [IFRMCT4-IFRMCTO]=OOOOO
194=0 only when [IFRMCT4-IFRMCTO]=OOOOO when sampled by 12.352 MHz 195=0 only when [ICVAL10-ICVALOO]=OOOOOlllXXX when sampled by 12.352 MHz where X=irrelevant 196=inverse of 19 197=1 only when [IFRMCT4-IFRMCTO]not=OOOOO when sampled by 12.352 MHz AND
[ICVAL10-ICVALOO]=OOOOOlllXXX when sampled by 12.352 MHz where X=don't care 198=1 only when [ICVAL10-ICVALOO]not=OOOOOlllXXX when sampled by 12.352 MHz where X=irrelevant AND
"DATA IN"=0 such that "DATA OUT TO NETI~ORK LINK" takes on the following values:
if [IcvALlo-IcvALoo]=ooooolllxxx when sampled by 12.352 MHz where X=irrelevant, "DATA OUT TO NETWORK LINKn=0 when tIFRMCT4-IFRMCTO]not=OOOOO
when sampled by 12.352 Mhz if [ICVAL10-ICVALOO]not=OOOOOlllXXX when sampled by 12.352 MHz X=don't care, "DATA OUT TO NETWORK LINK"=O when "DATA IN~=O
Referring to Fig. 6B, the network link receiver of the network termination end NLI 50B has the master/slave input at logic zero (indicating slave mode) to enable the appropriate portion of the circuitry. The data is received from two network }inks at the associated network termination circuitry. This is in keeping with a strategy for the switching system has redundant NSC circuits. The circuitry will interact with only one of network link 101 and 102 this is selected by the microprocessor 58 setting a link select bit to chose between data on input 101 or 102 link A or RCVD data from network link B. Whichever network link input is accepted, the data output 104 will be controlled by the decoding circuitry shown and will come from the inverting output of the flip-flop 105 of Fig. 6B. This toggle flip-flop 105 is the divide-by-two circuit 70 of Fig. 5. The multiplexing circuitry shown to select between network link copies and the inherent delay of the toggle flip-flop 105 is represented by the delay circuit 69 of Fig. 5. Since the received network link data arrives at 3.088 MHz, the output of flip-flop 105 is a 1.544 MHz clock signal. This 1.544 MHz clock is applied as input to a phase-locked loop 71 to create the 12.352 MHz phase locked loop signal (FROM PLL) signal shown on Fig. 6B and which is used to clock the XMT counter 66 and RCV
counter 65. The load input signal (CTR SYNC-) to the XMT counter 66 and the RCV counter 65 is developed by the circuitry shown on Fig. 6B and represents the means whereby system synchronizatiion is achieved. The CTR SYNC~ signal is activated by the circuitry depicted in Figure 6B upon recipt of sync 24 symbols in t~ii?
received pulse-wiæth modulation encoded network link data.
The operation of the circuitry in Fig. 6B is illustrated in Figs. 6C through 6F. Fia. 6C depicts the arrival of sync 24 symbols on the received network link and the development of the CTR SYNC- signal to synchronize the switching system. Fias. 6D
throuah 6F indicate the continuation of operation during intervals between received sync 24 symbols for clarity. Noting the labelled points in the circuitry of Fig. 6B, it is seen from Figs. 6C through 6F that:
Line 7 indicates the received network link data. The figure begins with the last portion of a non-sync bit's arrival followed by the arrival of the two consecutive sync 24 symbols. In each bit interval on line 7, the shaded portion represents logic zero and the non-shaded portion represents logic one.
Line 6 represents the T-FF 1.544 MHz output to the phase-locked loop.
Line 1 through 6 represent internal signals of the phase-locked loop, with line 2 indicating the 12.352 MHz clock used by the circuitry in Fig. 6B and line 5 illustrating the phase-locked loop frequency and phase synchronization with the T-FF
output of line 6. The 12.352 MHz clock is used either directly or in inverted form to clock the flip-flop, counter, and shift register stages in the circuitry depicted in Fig. 6B.
Line 8 indicates the Q output of FFl. Each pulse-width modulated bit is sampled four times by FFl in accordance with the high to low transitions of the 12.352 MHz clock. Each pulse-width encoded bit is thus reproduced at the output of FFl with a slight delay from its actual arrival at the network termination circuit. The Q output of FFl is applied as the load input to a synchronous four-bit counter which, in turn, is clocked by the low to high transitions of 12.352 MHz. Whenever a logic zero level is termination card. The Q output of FFl is applied as the load input to a synchronous four-bit counter which, in turn, is clocked by the low-to-high transitions of 12.352MHz. Whenever a logic zero level is apparent on this counter's load input during a low-to-nigh transition of 12.352 MHz, the counter's output becomes [QD-~A]=000. Should the counter's load input be logic one during a low-to-high transition of 12.352 ,~Hz, the counter will increment its count by one.
Line 9 indicates the output of the 4-bit counter during successive 12.352 MHz clock cycles when the network link data received conforms to the pattern of line 7. Note that it is only during those intervals where sync 24 sym~ols are received from the network link that the counter's output reaches the value where sync 24 symbols are received from the network link that the counter's output reaches the value [QD-QA~=0011. Flip-flop FF2A
and FF2B receive their D-inputs directly from this counter's output. FF2A and FF2B are clocked by low-to-high transitions on the inverting output (XQ) of FFl. The low-to-high transition on the inverting ouput of FFl occurs when the delayed and sampled received network link data has reverted from logic one to logic zero, concluding its positive pulse. Flip-flops FF2A and FF2B
and succeeding stages will assess at which of the four sample points taken in the 3.088 MHz bit interval this positive pulse concluded in order to decode the received symbol from amongst the set possible 20,22,24.
Lines 10 to 11 indicate the output of FF2A and FF2B, respectively, when the network link data received conforms to the patterns of line 7. Note from Figure 6B that FF3A and FF3B
receive their D-input from FF2A and FF2B, respectively. -FF3A and FF3B are clocked by the low-to-high transition of the actual received network link data (delayed by the multiplex circuitry) such that their outputs are updated once every 3.088 MHz interval. In a given 3.088 MHz bit interval, the 4-bit counter counts up once for each of the (up to 3) times that the receive network link data sampled by FFl is at logic one, FF2A and FF2B
and then when the actual network link data transitions from logic one to logic zero, the "highest count" that tAe 4-bit counter achieved is latched in FF3A and FF3B.
Lines 12 and 13 indicate tne output of FF3A and FF3B, respectively, when the network link data received conforms to the 204122~
patterns of line 7. Flip-flops 4A and 4B are clocked by the nigh -to-low transitions of the combinational logic which acts on the outputs of FF3A and FF33. The output of FF4A will be the decoded output of each network link bit to the network termination card's circuitry. FF4A will cause a logic one, indicating that a zero symbol 20 was received. F~4A will cause a logic one to be output to the circuit when both the first and second quarters of a received network link bit interval is logic one, indicating that a zero symbol ZO is received. The output of flip-flop FF4B is fed to an eight bit shift register for the purpose of determining the appropriate time to cause a CTR LOAD~signal to the XMT
counter 66 and the RCV counter 65.
Lines 14 and 16 indicate the output of FF4A and FF4B, respectively, when the network link data received conforms to the pattern of line 7.
Line 17 indicates the output of the 8-bit shift register [SR] which receives input from FF4B and is clocked by low-to-high transitions of the 12.352 MHz clock provided by the phase-locked loop.
Line 18 indicates the CTR SY~C~ signal applied to the XMT
counter 66 and the RCV counter 65 to achieve system synchronization. This CTR SYNC- signal is formulated by sampling the output of the depicted combinational logic driven by the SR outputs after a settling period by low-to-high transitions on the 12.352 MHz clock provided by the phase-locked loop.
The remaining lines on Figs. 6C through 6F indicate the outputs of the synchronized XMT counter 66 and RCV counter 65.
Specifically, by comparing lines 20 and 25 it is shown that the 3.088 MHz bit inerval is maintained in phase on both the received and transmitted network link. The timing diagrams represented in Figs. 6C through 6F and in Fig. 7D complement each other.
Together they mesh and fully describe the timing of the switching system and its particular time-division multiplex strategy. The circuitry described in figures 6A and 6B provide the core of this functionality on the network termination end 50B of the network links.
204 ~ 222 Referring to Figs. 7A and 7~, the transmit link encoder section and r-ceive link decoder section of che master control unit 50A are shown. These circuits operate in accordance with the waveform shown in Figs. 7C and 7D.
Referring to Fig. 7A, it is identical to that depicted in Fig. 6A. ~imilarly, the circuitry depicted in Fig. 7B is identical to that depicted in Fig. 6B. This is the case as they ~ave been fabricated in one integrated circuit. Different portions of the circuitry in Fig. 7A(6A) are applicable when the NLI 50 is employed on the NSC end of a network link than would be the case if the NLI 50 were employed on the network termination end 50B. Similarly, different portions of the circuitry in Fig.
7B(6B) are applicable when the NLI 50 is employed on the NSC end of a network link than wou]d be the case if the device were employed at the network termination end. In Fig. 7A, the master/slave pin of the device is fixed to logic one (indicating master mode), enabling the appropriate portion of the circuitry.
The transmitter circuit of Fig. 7A receives input from the fixed-modulus X~T counter 63, Fig. 5. The XMT counter 63 consists of two stages with its first stage being an 11 bit counter that ranges on successive clock input from counts 0 to 1543. The second stage is a five bit ounter ranging from 0 to 23. The first stage of each counter must range from 0 through 1543 bedfore the second stage is allowed to increment one time. When the first stage counter reaches count 23, the next time that the first stage counter outputs are maximum value and clock is received, the second stage count will revert to zero. The first stage counter outputs 169 are referred to as ICVAL00 through ICVAL10. Outputs ICVAL02 and ICVAL03 are unused. The second stage counter outputs 170 are referred to as IFRMCT0 through ~FRMCT4 on Fig. 7A. THe X~T counter 63 is clocked by the low-to-high edge of an inverted copy of the same 12.352 MHz clock in Fig. 5. Further, the data input to the circuit for eventual output to the network link is presented for a full 3.088 MHz interval in phase with the high-to-low edge of the same 12.352 MHz clock pulse which forc~s XMT counter 63 outputs to go to ~ ICVALOO, ICVALOl=OO. 2041222 ~ ssentially, the sisnal at 179 i3 inverted to provide a network link bit output lasting one 3.088MHz period. Note that 173 is e~ual to the value of 178 sampled after the 178 signal nas settled from the change in counter state. The 178 signal is formed by NO~ing tne signal 174, 175, 176, and 177. The 174, 175, 176, and 177 signals each play a role in creating the eventual pulse-width modulated output to the network link. The 174 signal is formulated to insure that the pulse-width modulated output during the first quarter of eacn 3.088 MHz bit interval is a logic one during sync bit times. The 177 signal is formulated to insure that the second quarter of a 3.088MHz bit interval is at logic one during sync bit times. The 176 signal is formulated to insure that the third quarter of a 3.088 MHz bit interval is at logic one during sync bit times. The 175 signal is formulated to cause the second quarter of a 3.088 MHz bit interval to be at logic one during non-sync bit times when the data input (DATA IN) to tne circuit is itself at logic one;
similarly the second quarter of the network link output 3.088 MHz bit interval will be caused to be logic zero when the data input (DATA IN) is itself logic zero during such intervals.
The following combinational logic expressions serve to describe the operation of the relevant portion of the circuit of Fig. 7A:
Qut~ut Condition 171=0 only when [IFRMCT4-IFRMCTO]=OOOOO
172=1 only when [ICVAL10-ICVALOO]=OOOOOXXXXXX where X=irrelevant 173=0 only wnen [ICVAL10-ICVALOO]=OOOOOlllXXX where X=irrelevant 174=1 only when [IcvALlo-IcvALool=xxxxxxxxxoo where X=irrelevant 175=1 only when [ICVAL10-ICVALOO]not=OOOOOlllXXX where X=irrelevant AND
ICVALl=O
AND
"DATA IM"=l 176=1 only wAen 2-412~2 FR.lCTeOOOOO
[ICVAL10-ICVALOO]not=OOOOOlllXXO where X=irrelevant 177=1 only when FR~ICT=OOOOO
AND
[ICVAL10-ICVALOO]not=OOOOOlllXXX where X=irrelevant AND
ICVALl=O
178=NOR(174, 175, 176, 177) 179=178 sampled by 12.352 MHz "DATA ~UTPUT TO NETr~ORK LIN~n=complement of 179 Referring to Fig. 7B, the master/slave pin of the NLI 50A is fixed to logic one (indicating master mode) in this application, enabling the appropriate portion of the circuitry. Data comes in from the network link and passes through the NLI 50A and from its data output to the NSC 36 circuitry. The 12.352 MHz clock and 333 Hz (ISYNC) sync inputs to the ~LI 50 continues through to where the 12 MHz-clock and 333 Hz (SYNC) sync signals which clock and load, respectively, both the NLI X~T counter 63 and RCV
counter 64 to synchronize the switching system.
In Fig. 7B, the data (RCVD DATA FROM NETWORK LINK) at input 150 is, in fact received in a synchronous fashion in accordance with the overall timing control of the switching system. The the input 152 (INPUT DATA MUX CONTROL) will always be set to logic one by the microprocessor of the NSC 36 to enable the path from input 150 to output 153 (DATA OUTPUT TO CARD CIRCUITRY). Since the data received from the network link on the NSC NLI 50B is not encoded, a property of the method employed is realized in that there is no need for any circuitry to perform decoding.
The overall timing control of the switching system has been described in the discussion of Fig. 5. Some critical elements in achieving the described synchronous operation are depicted in Fig. 7B and are illustrated in the timing diagram of Fig. 7C.
Various points on Fig. 7B have been labelled A, B, C, D, E and F
and the timing for each is shown in Fig. 7C. In Fig. 7C, the ~1~412~2 12.352 ~1iz clock and 333 Hz (ISYNC) sync signals provided to the ci~cuit ~re depicted. The nature of those provided signals is that the 12.352 MH7 clock toggles indefinitely. Every 37056 12.352 MHz cycles (with is a thrPe msec interval), tne ISYNC
signal which is normally at logic one transitions to logic zero for an interval lasting two 12.352 MHz cycles with the indicated phase. This pattern of the ISYNC signal similarly continues indefinit~ly. The X~T count~r 63 and RCV counter 64 on the NSC
end of the switching system are clocked by an inverted form of this 12.352 MHz signal (12 MHZ-). The circuitry of Fig. 7B forms the load signal (SYNC) to phase synchronize these two counters from which system timing control is administered through the indicated stages labelled A through F. The timing of Signals A
through F and SYNC are depicted in Fig. 7C relative to the circuit's controlling 12.352 MHz and ISYNC input timing.
Fig. 7D has been provided to indicate the relationship between the circuitry depicted in Figs. 7A and 7B, the XMT
counter 63 and RCV counter 64 of Fig. 5, and the synchronous operation of both the transmitted and received network link data.
Referring to Fig. 7D:
Line 3 indicates the timing of the 12.352 MHz clock input in the circuit of Fig. 7B.
Line 4 indicates the timing of the 333 Hz phase synchronization input to the circuit of ~ig. 7B (ISYNC).
Line 6 indicates the 12MHz- clock input depicted in Fig. 7B
to the XMT counter 63 and RCV counter 64 of Fig. 5 which control the overall timing of the NSC end 50A operation.
Line 7 indicat~s the 333 Hz [SYNC] phase sync input depicted in Fig. 7~ to the XMT counter 63 and RCV counter 64 of Fig. 5 which control the overall timing of the NLI 50A operation Line 10 represents a 3.088 MHz output of the RCV counter 64 which, on its low-to-high transition, is used by the latch 75 indicated in Fig. 5 to sample the received network link data at the NLI 50A.
Line 12 represents a 3.088 MHz output of the XMT counter 63 which, on its low-to-high transition, is used by the line encoder 2041~22 68 indicated in Fig. 5 to begin the network transmission interval of each bit output by the NLI 50A.
Line 13 indicates the timing of network link data received at the NLI 50A by the latch 75 de~icted in Fig. 5. The solid area of that line is where data is insured valid, with all propogation delays settled, by the method employed for the switching system.
Lines 14 through 17 indicates the role of each network link bit received in th~ time-division multiplexed strategy employed in this switching system.
Line 19 indicates the timing of PCM data delivered to the circuitry of Fig. 7A for eventual output to the network link.
Line 21 indicates the role of each network link bit transmitted and its role in the time-division multiplexed strategy employed in this switching system. Each network link bit transmitted is shown to begin with a low-to-high transition of the 3.088 MHz clock indicated on line 12. Pulse-width modulation encoding is enforced on each bit transmitted during these 3.088 MHz intervals.
The timing diagrams represented in Fig. 7D and in Figs. 6C
through 6F complement each other. Together they mesh and fully describe the timing of the switching system and its particular time-division m~ltiplex strategy. The circuitry described in Figs. 7A and 7~ provide the core of this functionality on the NLI 50A.
The NLI 50 of Fig. 8 will generate and control the network links connecting the control subsystem associated with line 30 and network termination shelves, or NSC circuits 36. An NLI 50 will be found on each end of a 3.088MHz network link, with each NLI 50 handling a ~air of links -- one for each direction of transmission. On a given card, the NLI 50 will convert the PCM, signaling, and message information passed to it into a serial stream, add some framing and synchronization bits, and transmit this data in encoded form on a network link. In the other direction, the NLI 50 will perform the line decoding and extract PCM, signaling, and message information to hand off to the appropriate card circuitry. The coding employed for data transmitted on a network link from the control subsystem to the network termination unit will be of a ~ulse width modulation form, with varying length pulses used to represent zeros, ones, and synchronization digits. On the other hand, the coding of network link data sent from the network termination units to the control subsystem will be strictly NR~, Fig. lA. There are several forms in wnich PCM and signaling data may be passed to and from the NLI and separate modes of the device have been defined for each.
Referring again to Fig. 9, each NLI 50 will control twenty-four channels of PCM and signaling data. Since the NSC circuit 36 deals with a 768 channel group, it must have thirty-two NLI
circuits 50 on board to handle all channels it must service. The DAS 37, Fig. 3, supports ninety-six channels and, thus, four NLI
circuits 50 are required per board. The DPC, PRI, BRL, and DSP
circuits each support twenty-four channels, requiring only one NLI circuit 50 per board. In addition to differences in the number of NLI circuits 50 for each of these circuits, there are differences in the way each handles the passing of data to and from its NLI circuit 50 and also in the way the internal timing of each ~LI circuit 50 is controlled. Fig. 9 shows how the NLI
50 will be employed in the system of Fig. 3, and Fig. 10 indicates the mode of device data I/O and internal timing control used on each card. The modes of the NLI 50 I/O are specified by hard-wiring WLI mode select pins A and B 81, Fig. 8. Internal timing control of an NLI 50 is fixed by hard-wiring the NLI
Master/Slave~pin 80, Fig. 8.
The NLI 50 and NSC circuits 36 will operate in Mode 0, specified by wiring both mode select pins A and B 81 to logic 0. In Mode 0, data for network link transmission is presented as eleven parallel bits consisting of eight PCM and three "system" bits.
The three system bits consist of a parity bit, a framing bit, and a superframe-synchronous signaling (SFSS) bit. The same eleven bit parallel format is used for output of data received from a network link. NLI circuits 50 on NSC cards 36 will be provided with a 12.352MHz clock and a 333 Hz synchronizaiton pulse by a system clock. To use these signals for master timinq control, each NLI ;0 should have its Master/Slave pin 80 set to logic one.
NLI circuits 50 on DSl port 42, P~I 40, and BRL 38 will operate in Mode 1, specified by wiring mode pin A as logic 0 and pin B as logic one. In Mode 1, PCM data for network link transmission is presented as a 1.544MHz serial bit stream. The serial PCM stream is organized in frames consisting of twenty-four eight bit samples, with each such set of 192 bits preceeded by a frame bit. Signaling data in Mode 1 is presented as four parallel inputs (A, B, C, and D) to the NLI 50, concurrent in timing with receipt of the eighth bit of each channel's sample on the serial PC~ input stream. In ~ode 1, PCM data received from a network link is output by the NLI 50 in the same 1.544MHz serial format as used for transmission. Signaling data received from the network link will not, however, appear at the NLI pins --this data will replace the least significant bit, or LSB, of the PCM on the serial output stream during the system-defined "signaling framesn. It should be noted that the BRL 38 will not use the signaling bit handling features of the NLI SO. NLI
circuits S0 on data port circuits 42, PRI circuits 40, and BRL
circuits 38 should have their Master/Slave~Pins 80 set to logic zero such that internal timing is controlled by the 12.352MHz clock provided by the NLI circuits phase-locked loop, Fig. 5, (PLL) in conjunction with synchronization information obtained from the received network link.
NLI circuits 50 on DAS circuits 37 will operate in Mode 2, specified by wiring Mode Pin A as logic one and Pin B as logic zero. In Mode 2, PCM data for network link transmission is presented to the NLI 50 as eight parallel PCM bi~s. Likewise, da~a received from a network link will be output from the NLI S0 as eight parallel PCM bits. A-port signaling data will be extracted from the LSB of PCM of each channel on the received link during the system-defined A-port signaling frames and will be stored for eventual reading by the circuits microprocessor. NLI
circuits 50 in DAS circuits 37 should have their Master/Slave~pins -80 set to logic zero such that internal timing is controlled by tne 12.352MHz clock provided by the card's phase-lock~d loop (PL~), Fig. 5, in c~njunction with synchronization information obtained from the received network link.
The NLI circuits 50 on DSP circuits 37 will operate in Mode 3, specified by wiring both mode select pins A and B 81 as logic 1. In Mode 3, PCM data for transmission is presented to the NLI
50 as a 1.536~Hz serial data stream consisting of twenty-four eight bit PCM samples. PCM data received from a network link is also output from the NLI as a 1.536~Hz serial data stream consisting of twenty-four 8 bit PCM samples. A-port signaling data will be extracted from the LSB of PCM of each channel on the received link during the system defined A-signaling frames and wil~ be stored for eventual reading by the circuit's microprocessor. NLI 50 on DSP circuits 37 should have their Master/Slave~pins 80 set to logic zero such that internal timing is controlled by the 12.352MHz clock provided by the circuit's phase-locked loop (PLL), Fig. 5, in conjunction with synchronization information obtained from the received network link.
The NLI 50 performs numerous functions. It converts twenty-four channels of PCM and signaling data into a 3.088MHz serial bit stream and converts a received 3.088MHz serial bit stream into PCM and signaling data. It embeds message information into each transmitted network link using a packet protocol and extracts message information from each received link. It also embeds clock into each transmitted network link through use of pulse-width modulated line coding described above, providing link synchronization by embedding "sync" bits 24 in the serial data stream and extracts clock and sync from each received link. PCM
and signaling data insertion/extraction registers are provided for background testing, and a signaling store with microprocessor access is provided for received A-signaling bits. There is also a ~icroprocessor interface for message information handling and chip control.
Referring to Fig. 11, the NLI 50 has five interfaces: an 204122~
-outbound data interface, the tr~nsmit link interface 82, the receive link interEace 86, an in~ound data interface 88, and a microprocessor interface 90. The outbound data interface 82 ~rovides means for a card to hand off PCM and signaling data to be transmitted on a network link. This data is merged with information specified for transmission by the microprocessor interface 90 and is sent in pulse-width modulation encoded form to the outbound network link by the transmit link interface 84.
In the other direction, data rec~ived form a n~twork link 47 arrives at the receive link interface 86 where PCM and signaling data is extracted and sent to tne inbound data interface 88 for output from the NLI 50. Message information is also extracted from the received network link 47 and is routed to the microprocessor interface 90. The connections between the microprocessor interface 90 and both the receive and transmit interfaces 86 and 84 are made via FIFOs 91.
While there are several formats for data flowing across the NLI inbound and outoound data interfaces 88 and 82, the format of data on each network link 47, whether created by the transmit link interface 84 or received at the receive link interface 86, will always be as indicated in Fig. 12.
The outbound data inter~ace 82 will accept either parallel or serial in~ut for network link transmission. The operation of the outbound data interface 82 is dependent on the strapping of the NLI mode select pins.
As stated previously, each of the thirty-two NLI circuits 50 on the NSC circuit 36 receives parallel data for each of twenty-four channels for network link transmission. This data is obtained from a 768 channel TDM bus. Referring to Fig. 12, each NLI 50 will latcn a set of twenty-four, eleven bit samples at an approximate 192kHz rate. The timing for this latching is derived from counters within the NLI 50 which are driven by the 12.352MHZ
control time base clock, Fig.5, and 333Hz synchronization pulse provided to each element on the ~lSC circuit 36. To identify which set of twenty-four channels of the 768 channel bus are intended for a given circuit, each NLI 50 has a position register loaded witn a value from zero to thirty-one. Eac~
50A on NSC circuit 3~ will have a different value in its position register. The eleven bits handed to each NLI 50A originate at the TSI circuit 34 and consist of eight PCM and three system bits. The theee system bits include a parity bit, a frame bit, and a superframe-synchronous signaling tSFSS) bit. All of these inputs except the S~SS bit are sourced from the switching complex. The SFSS bit is generated by the signaling circuit on the TSI circuit 34 and is passed to the NLI 50A in parallel with the other ten. The parity bit received by the NLI 50A is on the eight PCil and one frame bit generated by the TSI 34, and checking of ttlis parity is performed in the outbound data interface 82, Fig. 11. If a parity error is detected, the appropriate bit of an NLI interrupt status register, Fig. 18, will be set and the DPC circuit's microprocessor will be interrupted. Regardless of the priority check results, the ten remaining data bits are transferred to the transmit link interface 84.
On DPC circuits 42, Fig. 4A, and PRI circuits 40, Figs. 3 and 9, serial PCM and parallel signaling data is received at the outbound data interface 82 for transmission on a network link 47.
The serial stream contains twenty-four channels of PCM data and a frame bit is received at a 1.544MHz rate. A pin 92, Fig. 8, of the NLI 50 has been provided to source a transmit 1.544MHz clock to be used on DPC circui~s 42 and PRI circuits 40 in generating this data stream. An eight k~z transmit sync output pin 100, Fig. 8, has been provided on the NLI 50, so that channel order can be derived on the NLI 50. Timing of each of these clock signals is derived from the received network link synchronization information in conjunction with the 12.352~Hz input to the NLI 50 from tne NLI PLL pin.
The eight bit PCM sample of each channel is extracted from the received serial stream and is converted into parallel form.
The frame bit of the serial stream is latched and passed in parallel with the parallel PCM data of each channel to the transmit link interface 84. The four bits of signaling information received at the outbound data interface 82 represent the A,B,C, and D signaling bics for ~ach channel. 3ased on system-defined superframe timing, the appropriate signaling bit of the four received is selected ~nd sent to the transmit link interface 82 in parallel -~ith the PCM and frame bits. Under microprocessor control, .his signaling data may also be specified to replace the LS~ of outgoina PC~I samples. This type of control is maintained on a channel-by-channel basis through processor specifications for each channel in the transmit signaling control registers, Fig. 5.
Operation of the outbound data interface 82 is comparable on BRL circuits 38, Fig. 9, except that no signaling bits are passed to the NLI 50.
On DAS circuits 37, twenty-four eight bit parallel PCM
samples are presented to the outbound data interface 82 every 125 microseconds for transmission to a network link. The ~LI 50 will supply the DAS 37 with an eight kHz transmit sync output on pin g3 t~ be used with the on board 12.352MHz clock such that the timing and channel order for passing data to the outbound data interface 82 can be derived. The DAS circuit 37, will supply the NLI 50 with data for transmission at a 192kHz rate. This data will, in turn, be transferred to the transmit data interface 84.
On DSP circuits 42, serial PC~ data is received at the outbound data interface 82 for transmission on a network link 47.
The serial stream contains twenty-four channels of PCM data and is received at a 1.536MHz rate. The 1.536MHz transmit clock pin 95 of the NLI 50 has been provided to source the clock to be used on the DSP circuit 44 in generating this data stream. The eight kHz transmit sync pin 93 is also used for determining channel order. The 8 bit PC;~ sample of eacn channel is extracted from the serial stream, converted into parallel form and passed to the transmit link interface 84.
The transmit link interface 84 receives data from the outbound data interface 82 and the microprocessor interface 90.
Sixt~en bit data for link tr3nsmission is formed by combining the (up to) ten bits from tne outbound data interface 82 with four bits from the microprocessor interface 90, generating odd parity on the set, and appending a bit fixed as logic one. Twenty-four such words are formed every 125usec. Two link sync bits are added to these twenty-Eour, sixteen bi. words and the entire block of information is serialized. The setting o~ the NLI's ~laster/Slave~pin 80 determines tne coding employe2 on the outbound 3.083MHz stream. NLI circuits 50 strapped to function as a master 50A employ a pulse-width modulation coding in order for the NLI circuits 50 operatinq as a slave 50B at the far end of the network link to be able to derive a clock from the low-to-high transition which begins each bit interval. N~I circuits 50 which are strapped as a slave 50B output the 3.088M~z stream as simple NRZ, the ones represented as high voltages for the entire bit interval and zeros as low voltages.
The receive link interface 86 receives a 3.088MHz network link and passes the stream immediately through a decoder.
Transitions of data on the received stream are detected in the pulse-width modulation decoder, Fig. 5, and a 3.088MHz clock is derived. This clock is divided by two to form a 1.544M~z signal which, with respect to NLI circuits 50B specified for slave operation by their Master/Slave~pin 80 setting, will be sent out of the NLI 50B to a phase-locked loop circuit, Fig. 5, where 12.352MHz is created and passed back to the NLI 50 for use in deriving all timing. The serial data output of the decoder is clocked into a shift register at a 3.088MHz rate to convert the data into parallel form. Sixteen bit words are formed in this fashion consisting of ten bits bound for the inbound data interface 88, four bits for the microprocessor interface 90, a parity bit on the entire word, and a fixed bit of logic one. An odd parity cllecker is used to verify a properly received data word and, if a parity error is detected, the appropriate bit of the NLI interrupt status register, Fig. 5, will be set and the microprocessor of the NLI circuit 50B will be interrupted. In the 3.088MHz link there are 386 bits transmitted every 125 microseconds. Since only 384 are used for channel data (twenty-four sets of sixteen bit words), two extra bits of link sync information are also rec~ived in the data stream. These bits are . 2041222 routeæ to the counter/-imer circuit 92, Fig. 11, where they are used for acquiring synchronization to the link transmitter.
The inbound data interface 88 receives ten bits from the receive link inter'ace 86 and tr~nsmits this ~ata in either parallel or serial form. The mode select pins on the ~LI 50 are used to selec~ the output mode ror each card.
~ n tne NSC circuit 36, data from each of the thirty-two inbound data interfaces 88 are merged to form a 768 channel TDM
bus. Each NLI master circuit 50A will source a set of twenty-four eleven bit samples at an approximate 192kHz rate. The timing for this latching is derived from counters within the NLI
circuit 50A which are driven by the 12.352MHZ clock and 333Hz synchronization pulse provided to each NLI 50A on the NSC circuit 36 by the clock card 32, Fig. 3. Each NLI circuit 50A has a position register loaded with a value from zero to thirty-one to determine when it should output to this 768 channel bus. r~hen a given NLI circuit 50A is not outputting data, it will keep its outpu. pins in a high impedance state. When a given NLI circuit 50 is outputting data, tne EXG pin 97 of that NLI 50 will generate a low level pulse which is used for special purposes on the NSC circuit 36.
Eleven bits of output are provided by the inbound data interface 88 of each NLI circuit 50, consisting of eight PCM and three system bits. The three system bits include a parity bit, a frame bi~ and a SFSS bit. All of these outputs except the SFSS
bit are sent to the TSI circuit 34, with the parity bit generated on the nine non-SFSS data bits. The SFSS bit is sent to the signaling circuit of the TSI circuit 34 in parallel with the other ten.
In DPC circuits 42 and PRI circuits 40, serial PCM data is output by t~e inbound data interface 88. The serial stream contains twenty-four channels of PCM data and a frame bit and is transmitted at a 1.544MHz rate. The receive 1.544MHz clock pin 92, ~ig. 8, of the NLI nas been provided to be used by DPC 42 and PRI 40 in latc~ing this data stream. A 333Hz receive sync output pin 94 has also been provided such that channel and frame order ~-` " 20~2~
can be derived on these circuits. Timin~ of each of these clock si`~nals is derived from the received network link sync information in conjunction with the 12.352~Hz input from the NLI
phase locked loop circuit.
Signaling information obtained for each channel in the SFSS
bit position on tlle received net~ork link may be inserted into the LSB of each PC~I word output b;~ the inoound data interface 88 in accordance with the system-defined superframe timing. This is selectable on a channel-by-channel basis under micropeocessor control by setting the bit corresponding to a channel in the received link signaling control registers, Figs. 33 - 35.
Operation of the inbound data interface 88 is comparable on BRL
circuits 38, except that no signaling bit information is ever inserted into PC~I samples.
In DAS circuits 37, twenty-four eight bit parallel PCM samples are output by the inbound data interface 88 every 125usec. Each of the four MLI circuits 5~ on the card will be assigned a distinct value in their position register, Fig. 19, to define when each should present parallel output onto a common output bus. When a given device is not passing data from its inbound data interface 88 to this bus, its output pins will remain in a high impedance state. The DAS circuit 37 circuitry will make use of the OSYC pin 98, Fig. 8, of the NLI circuit S0 to determine when output data should be latched from a given NLI circuit 50B.
In DSP circuits 42, serial PCM data is output by the inbound data interface 88. The serial stream contains twenty-four channels of PCM data and is transmitted at a 1.536MHz rate. The 1.536MHz rec2ive clock pin 92 has been provided to source the clock to be used on the DSP circuit 44 in generating this data stream. An 8kHz receive sync pin 100, Fig. 8, and the 1.536MHz and 8kHz pins provided for interaction with the inbound data interface 88 and those provided for interaction with the outbound data interface 82 are distinct. Each set has a different phase than the other. The eight bit PC~ sample of each channel is e~tracted from the serial stream, converted into parallel form and passed to the transmit link interface 84.
2041~2 For channels received by the DSP circuit 42, signaling bits are present in the LSB of PC:~ samples during ~he system-defined signaling frames. A-signaling bits will be captured by the NLI
circui. 50 and s~ored in the receive signaling data registers, Figs. 36 - 38, for reading by the card microprocessor.
The microprocessor interface 90 provides a variety of registers with which the microprocessor can communicate with the NLI circuit 50 and control its function. One major function controlled by the microprocessor interface 90 is associated with passing messages between circuits. This circuit will perform the necessary functions associated with embedding message information into tne 3.088MHz network link transmitted and, conversely, with extracting such information from the received link. The message and associated control information is allocated four out of every sixteen bits on a network link. These information bits are sent using a packet protocol at a 768 kbit/sec rate.
Communications between the control and the network termination units is always initiated from the NSC circuit 36.
'~hen message information needs to be sent to a network card, microprocessor of the NSC 36 will buffer up to 64 bytes -- the first being a byte count -- in an NLI transmit FIFO, through means of writing to a transmit message data register, Fig. 28. Therea~ter, the microprocessor will write a word to th NLI control register, Fig. 17, containing a logic one in the send message bit position. The NLI S0 will "packetize~ the message bytes according to the protocol depicted in Fig. 13, adding flag, status field, and checksum bytes around this information field. Note that during times when no messages are being sent, the NLI circuit 50 will output non-flag characters in the 768kbit/sec field.
The NLI circuit 50 constantly searches for incoming message information by checking for an opening flag in the message field of its received link. Once the opening flag is recognized and the byte count is determined, the NLI circuit 50 will buffer the message bytes in a receive FIFO. A running checksum on the message bytes will be kept as they are receive~ and this will be compared ~o the checksum byte~appended to the incoming message. If the checksum received differs from that calculated, the appropriate bit of an interrupt status register, Fig. 18, will be set and the circuits microprocessor will oe interrupted.
Upon receipt of a valid message, the receive FIFO full bit of the interrupt status register, Fig. 18, will be set and the received status field bits will be interpreted and acted upon.
In the NSC circuit 36, a received message will be detected by polling each interrupt status register, Fig. 18, of the NLI
circuits 50 to see if this receive FIFO full bit is set. The message may then be read out of the NLI circuit 50 through the receive message data register, Fig. 29. The first byte read will be the byte count, and the microprocessor should loop that number of times, re~ding the (up to) sixty-three other message bytes.
The NLI circuit 50 will function in a similar fashion in all other modes with ~he following exceptions. First, on receipt of an inbound message, the circuit's microprocessor will be interrupted along with the indic~tion of receive FIFO full in the ~ILI interrupt status register, Fig. 18. Secondly, on receipt of a message, the receive FIFO will become "locked" such that the message will not be overwritten by a second message to the card.
Obviously, any subsequent messages which are passed while the FIFO remains locked will be lost. The processor must act to unlock the FIFO by altering the appropriate bit of the control register, Fig. 17, upon extracting the current message from the rec~ive FIFO. The FIFO lock mechanism is not available for devices, such as those on the NSC card 36, with master designations on the Master/Slave~pin 80. Finally, no message should be transmitted by an NLI 50 specified to operate in Modes 1 through 3 until a message has been received requesting a response. ~owever, there is nothing in the circuit to restrict sending an unsolicited message.
The NLI circuit 50 will "packetize" messages from the pro~essor using a protocol consisting of adding an opening flag, a status field, and a checksum on all preceeding bytes except the ~3 20412~2 opening flag. The opening flag represents the beginning of a message frame and will always have the value of 7E ~ex (01111110 Binary). The status field is an eight bit field used for sending control information from the ~SC circuit 3~ to network cards --its contents have no meaning on links bound to an NSC 36. The st3tus field bits are used to cause either a reset or a non-maskable interru~t (NMI) to the processor on an NSC circuit 36 or to cause it to switch which bus from which serial information is received. The (up to) sixty-four ~ytes of message information will be transmitted after the status field, with the first byte of the information field always being byte count of that field.
While transmitting this data, a checksum value is calculated.
This checksum byte will be inserted on the link af-er completion OL the information field to provide the far end with a means of checking message integrity.
It should be noted that the byte count beginning the information field may take on the range from zero to sixty-three.
A zero byte count message may be sent, for instance, to simply pass status field information between cards. However, a zero byte count message properly received at a slave device, even with the receive FIFO locked, will be interpreted and acted upon. A
sixty-three byte count message is one with a complet~ly full information field comprising one byte count digit and sixty-three actual data bytes.
The NLI circuit 50 is designed to recognize parity errors on data coming into the NLI circuit 50, as well as generate parity on data leaving the NLI circuit 50. Parity errors can be detected on outbound parallel data from the TSI Mode 0, on received 3.088MHz serial data in all modes or on bytes transferred ,rom either of the two FIFOS maintained within the NLI circuit S0. Odd parity is employed on the 3.088MHz serial links, even parity is employed on the two internal FIFOs, and the type of parity is selected via the control register for Mode 0 TSI data checking and generation. Violations of parity are indicated as to type in the NLI interrupt status register, Fig.
18, and are always accompanied by an interrupt of the circuit's microprocessor. Should the microprocessor wish to mask any of these parity error interru~ts, i~ may do so by setting the corresponding bit of the control register, Fig. 15. Further, should the microproc~ssor wish to cause any or all of ~hese errors to test its own diagnostic software, bits of the control register, ~ig. 14, have also be~n speciEied for this purpose.
Similar to the parity checking, the NLI circuit 50 will always observe the checksum byte associated with each received message. Should the checksum value calculated during message receipt not correspond exactly to that appended to the message, the circuit's microprocessor will receive an interrupt and an indication of such will be placed in the interrupt status register. Such interrupts may be masked or "caused" for diagnostic software checking by setting the appropriate bits of the control register.
Should the NLI 50 ever lose synchronization with the transmitter of its received network link, an indication of such will-be made in the interrupt status register and the circuit's microprocessor will be interrupted. For NLI circuits strapped as a master 50A, the interrupt status register indication will be in the receive link out-of-sync bit location; for NLI circuits 50 strapped as slave units 50B, the interrupt will be indicated in the master clock out-of-sync bit. Further, in NLI circuits 50 operating as a master unit 50A, checks will be made that the internal counters are in step with the synchronization signal provided on a NLI sync input pin 97. Should such synchronization ever be lost, the master clock out-of-sync bit of the interrupt status register, Fig. 18, will be set and the circuit's processor interrupted. Consistent with the handling of other error interrupts, these types may be masked, or ~causedn, for diagnostic software checking by setting the appropriate bits of the control register.
The NLI circuit 50 also provides features for background testing of several system functions. There are registers in each NLI circuit 50 which allow the insertion of a known PCM and signaling pattern in place of the data of one channel to be -output on tne transmit networ~ link. The microprocessor can specify ~n eight bit PC`~ and/or ~ four bit A,B,C, and D si~naling value in ~he transmit insertion data registers, Figs. 26 and 41, and a channel number desianation in tne transmit insertion address register, Fig. 25. ~y setting the enable PC~ insertion bit of the control regis.er, Fig. 16, the microprocessor will cause the ~,B,C and ~ signalinq value to be substituted during -the system defined superframe timing on the SFSS bit for that channel. In this fashion, an NSC 36 can, for a channel out-of-service, send known values on the link to the switching complex and to a signaling circuit of the TSI 34 where action can be taken to check their operation. PCM insertion can take place without signaling insertion and vice versa. There are, similarly, extraction data register, Figs. 39 and 40, and an address register, Fig. 24, in the NLI 50 for latching a given channel's PCM and signaling data as it is received from a network link 47. The insertion and extraction registers can be used ei~her individually or as a pair to monitor a variety of system functions.
The NLI circuit 50 will have a lOmsec output pin for providing each card with a real-time signal for interrupting its processor. This lOmsec signal will be derived from the 12.352MHz clock input to the NLI circuit 50. This interrupt should be acknowledged by reading the clear timer/NMI register of the NLI
circuit 50, Fig. 43, after which the output signal will go inactive until the next interval has elapsed.
The NLI circuit 50 has an output pin for providing DSP
circuits 42 with an interrupt signal for their microprocessor each time A-port signaling bits have been received for all channels on the network link. This 1.5msec signal will be derived from the 12.352MHz clock input to the NLI circuit 50 in accordance witn the system-defined superframe structure. This interrupt should be acknowledged by reading the clear timer/NMI
resister OL the NLI circuit 50, Fig. 43, after which the output si~nal will go inactive until tne next interval has elapsed.
Four pins have been provided on the NLI circuit 50 to 20~1222 accommodate 56 or 54kbps data links. Two pins r~present clock sianals generated oy the ~LI cir~uit 50 for use in transferring 56 or 64kbps data in~o and out of t:~e ~LI circuit. The two clock signals are not in phase. The remaining two pins are the avenues for 56 or ~4kbps data T/O. On the PRI circuit 40, these pins will be used in transferring data between the NLI circuit 50 and a serial communications controller (SCC), which in turn will be connected to the circuit's microprocessor. In this fashion, the processor will be able to receive data from one channel within the NLI circuit 50 and, likewise, source the data bound to that channel. The 56 or 64kbps channel with which the processor can interact will be one of those arriving/departing on the Tl line connected to the circuit. Data link operation must be enabled and 56 or 64kbps operation specified by setting the appropriate bits in the control register, Fig. 16.
A DTAC~ output pin 102, Fig. 8, is provided on each NLI
circuit 50 for use in handshaking during data transEers with a terminal circuit microprocessor.
The registers which compose the microprocessor interface to the NLI are described below and shown in Figs. 14 et seq.
Addresses for each of the registers are given along with their names. These addreses contain five bits and their designation is from A5-Al. On 68000-microprocessor based circuits which employ the NLI circuit 50, it should be expected that the NLI registers will not be at contiguous locations in the processor's address spectrum -- the NLI registers may be placed in either the upper byte only or lower byte only of the processor's data bus. In addition to the address given with each register, there are Read-Only (RO) designations given to the appropriate registers. Any register without an RO designation is read/writeable.
In the control MS register, Fig. 14, of the NLI circuit 50, receive link out-of-sync interrupts cannot be generated for an NLI circuit witn slave designation on its Master/Slave~pin 80;
outbound data parity errors c~n only be caused on NLI circuits 50 strapped for Mode 0 -- the only operating mode where parity flows into the outbound data interface 82.
2~ 22 In the control SS register, Fig. 15, of the ~LI circui. 50, even if a siven interrupt is masked, the status register, ~
lô~ wiil continue to give indications that a given event has occurred. Set.ing bits of .his register simply effects the operation of tne interrupt output pin.
In the concrol TS register, Fia. 16, the IDE bit will be cleared whenever the device goes out of sync and the IDE
bit must be set after the device acguires sync, regar~less of the mode of operation. Bit three will always be read as zero, and it should not be expected to read back from this register exactly what was written to it in all cases. If in Mode 0, the SUFRM bit should be set to select 333Hz sync operation.
In the control LS register, Fig. 17, the receive FIFO lock, will never be activated and can never be set for devices with a master designation on their Master/Slave~pins 80. Bit five will always be read as a zero, ~nd it should not be expected to read back from this register exactly what was wr;tten to it in all cases.
In the interrupt status register, ~ia. 18, receive link out-of-sync interrupts will never occur for devices with slave designations on their Master~Slave~pins 80. Also, outbound data parity error interrupts will never occur for devices which have mode designations other than zero.
In the position register, Fig. 19, bits ~ive through seven will always be read as zero, and it s~ould be expected to read back from this register exactly what was written to it in all cases.
In the transmit link MS~counter load register, Fig. 20, for NLI circuits 50A designated as a master, the value which should be placed-into this register is B~H. For NLI circuits 50~ designated~
a slave, the value which should be placed into this register is 08H.
In the transmit link LS-co~nter loaa register, ~ig. 21, for devices designated as a master circuit ~OA, the value which should be placed into the register iB F6H. For NLI circuits ~OB
designated slave, the value wnich should be placed into the 21)412~
register is ~AH.
In the receive link ~IS co~nter load register, Fig. 22, for ~LI circuits 50 designated as a mas-er the value which should be placed into this register is OOH. While ~LI circuits 50 devices designated slave, the value which should be placed into this register is 3DH.
In the receive link LS counter load register, Fig. 23, for NLI circuits 50 designated as a master, the value which should be placed into this register is 02H. For devices designated slave, the value which should be placed into this register is C8H.
In the extraction address register, Fig. 24, bits five through seven will always be read as a zero, and it should not be expected to read back from this register exactly what was written to it i~ all cases.
In the insertion address register, Fig. 25, bits five through seven will always be read as a zero, and it should not be expected to read back from this register exactly what was written to it in all cases.
In the insertion MS data register, Fig. 26, bits four through seven will always be read as a zero, and it should not be expected to read back from this register exactly what was written to it in all cases.
In the 56/64kbps data link address register, Fig. 27, bits five through seven will always be read as a zero, and it should not be expected to read back from this register exactly what was written to it in all cases.
The order of operations to be performed during device initialization should be as follows:
1. ~ask all interrupts by writing FFh to the control SS
register;
2. Write the appropriate data (given above) into the transmit and receive link counter load registers, Fios. 20 and 23;
3. Read the interrupt status register and assure that the ~LI 50 is giving "in-sync" indications. Continue to loop until the device does yield these indications;
4 Write tlle appropriate values (card specific) into the ~9 20412~
SUFRM bit of tne con-rol TS re~ister, Fig. 16, and into the position register, Fig. 19;
SUFRM bit of tne con-rol TS re~ister, Fig. 16, and into the position register, Fig. 19;
5. Enable the IDE bit of the control TS register regardless of tne type of PC~/system bit I/O employed;
6. Write card-specific data into the appropriate registers (which may be the control TS, control LS, transmit link signaling control, receive link signaling control, and/or 56/6kbps data link address registers); and
7. Enable desired interrupts in the control SS register, Fig. 15.
While a particular embodiment of the invention has been disclosed in detail, it should be appreciated that many variations may be made without departing from the spirit and scope of the invention as defined in the appended claims.
While a particular embodiment of the invention has been disclosed in detail, it should be appreciated that many variations may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (45)
1. In a telecommunications network of transceiving informational sources, the improvement being a switching interface system for communication between said sources, comprising:
a control unit connected with some of said sources including means for encoding information from said sources in a serial, pulse width binary format, and means for serially transmitting pulse width binary encoded pulses of said encoding information at a preselected transmission bit rate; and a network termination unit connected with other ones of said sources including means responsive to the serially transmitted, pulse width binary encoded pulses for extracting therefrom a clock signal, and means responsive to said clock signal for synchronous decoding of the serially transmitted, pulse width binary encoded pulses for provision to said other ones of said sources connected with the network termination unit.
a control unit connected with some of said sources including means for encoding information from said sources in a serial, pulse width binary format, and means for serially transmitting pulse width binary encoded pulses of said encoding information at a preselected transmission bit rate; and a network termination unit connected with other ones of said sources including means responsive to the serially transmitted, pulse width binary encoded pulses for extracting therefrom a clock signal, and means responsive to said clock signal for synchronous decoding of the serially transmitted, pulse width binary encoded pulses for provision to said other ones of said sources connected with the network termination unit.
2. The switching interface system of claim 1 in which the network termination unit has an encoder for encoding data from the sources connected therewith into a pulse format and means responsive to the clock signal for transmitting the encoded data to the control unit in frequency synchronism with said transmission bit rate.
3. The switching interface system of claim 1 in which the extracted clock signal has a frequency which is substantially equal to the transmission bit rate frequency.
4. The switching interface system of claim 3 in which said control unit has a primary clock with a frequency which is a binary power multiple of the transmission bit rate, and said network termination unit has means for developing a clock signal which has a bit rate equal to the frequency of said primary clock.
5. The switching interface system of claim 1 in which said control unit has a decoder for decoding data from said network termination unit, and means for maintaining said decoder in frequency synchronism with the transmission bit rate of the transmitted pulse width binary encoded pulses.
6. The switching interface system of claim 5 in which said control unit includes means for maintaining said decoder in phase synchronism with the transmitted pulse width binary encoded pulses.
7. The switching interface system of claim 6 in which said phase synchronization means includes means to cause the time that a bit of data enters the encoding means to coincide with the instant that a bit emerges from the decoding means.
8. The switching interface system of claim 1 in which the control unit includes means for encoding said information in a binary pulse width modulated format with logic one states and logic zero states being represented by pulses of two different selected widths, respectively.
9. The switching interface system of claim 8 in which the leading edge transitions of said pulses of two different selected widths occur at the same time during a bit interval.
10. The switching interface system of claim 9 in which said leading edge transitions are positive transitions.
11. The switching interface system of claim 8 in which said pulses of two different widths create pulse transitions in every data bit interval.
12. The switching interface system of claim 11 in which said pulse transitions are positive transitions.
13. In a telecommunications network of transceiving informational sources, the improvement being a switching interface system for communication between said sources, comprising:
a control unit connected with some of said sources including means for encoding information from said sources in a serial, pulse width binary format, and means for serially transmitting pulse width binary encoded pulses of said encoding information at a preselected transmission bit rate; and a network termination unit connected with other ones of said sources including means responsive to the serially transmitted, pulse width binary encoded pulses for extracting therefrom a clock signal including means for generating said clock signal at a frequency which is a preselected multiple of the transmission bit rate, and means responsive to said clock signal for synchronous decoding of the serially transmitted, pulse width binary encoded pulses for provision to said other ones of said sources connected with the network termination unit.
a control unit connected with some of said sources including means for encoding information from said sources in a serial, pulse width binary format, and means for serially transmitting pulse width binary encoded pulses of said encoding information at a preselected transmission bit rate; and a network termination unit connected with other ones of said sources including means responsive to the serially transmitted, pulse width binary encoded pulses for extracting therefrom a clock signal including means for generating said clock signal at a frequency which is a preselected multiple of the transmission bit rate, and means responsive to said clock signal for synchronous decoding of the serially transmitted, pulse width binary encoded pulses for provision to said other ones of said sources connected with the network termination unit.
14. The switching interface system of claim 13 in which said multiple is four.
15. The switching interface system of claim 13 in which said clock signal extracting means includes a phase locked loop circuit with an input and an output, means for delaying the leading edge of the width modulated pulses to produce delayed pulse width modulated pulses, and means responsive to said delayed width modulated pulses for applying a corresponding delayed intermediate signal to the input of said phase locked loop, the output of said phase locked loop providing said clock signal at the preselected multiple of the transmission bit rate.
16. The switching interface system of claim 15 in which said delayed intermediate signal applying means includes a binary counter for producing an intermediate signal which has a frequency that is a preselected fraction of the transmission bit rate for interfacing with the input of the phase locked loop.
17. The switching interface system of claim 1 in which said control unit includes means for periodically inserting phase synchronization pulses into said serially transmitted pulse width binary encoded pulses to provide phase synchronizational information to the network termination unit.
18. The switching interface system of claim 17 in which said control unit includes means responsive to an external clock for generating a phase reference signal, and means responsive to the phase reference signal generating means to insert said phase synchronization pulses into a stream of said serially transmitted pulse width binary encoded pulses.
19. The switching interface system of claim 17 in which said pulse width binary encoded pulses have a leading edge transition of a selected transitional sense, and said synchronizational pulses have a leading edge transition having the same transitional sense as said selected transitional sense of the binary encoded pulses.
20. The switching interface system of claim 19 in which said transitional sense is positive from a relatively low voltage to a relatively high voltage.
21. The switching interface system of claim 17 in which said network termination unit includes means responsive to said phase synchronization pulses to transmit data to said control unit in phase synchronism with said pulse width binary encoded data pulses at said preselected transmission bit rate.
22. In a telecommunications network of transceiving informational sources, the improvement being a switching interface system for communication between said sources, comprising:
a control unit connected with some of said sources including means for encoding information from said sources in a serial, pulse width binary format, means for serially transmitting pulse width binary encoded pulses of said encoding information at a preselected transmission bit rate, and means for periodically inserting phase synchronization pulses into said serially transmitted pulse width binary encoded pulses to provide phase synchronizational information to a network termination unit; and said network termination unit connected with other ones of said sources including means responsive to the serially transmitted, pulse width binary encoded pulses to extract therefrom a clock signal, and means responsive to said clock signal for synchronous decoding of the serially transmitted, pulse width binary encoded pulses for provision to said other ones of said sources connected with the network termination unit, means responsive to said phase synchronization pulses to transmit data to said control unit, in phase synchronism with said pulse width binary encoded data pulses at said preselected transmission bit rate including a phase synchronization acquisition circuit for generating a synchronization control signal, and means responsive to the synchronization control signal for controlling the synchronous transmission of data to said control unit to maintain the transmission of data to the control unit in synchronization with the synchronization pulses generated thereby.
a control unit connected with some of said sources including means for encoding information from said sources in a serial, pulse width binary format, means for serially transmitting pulse width binary encoded pulses of said encoding information at a preselected transmission bit rate, and means for periodically inserting phase synchronization pulses into said serially transmitted pulse width binary encoded pulses to provide phase synchronizational information to a network termination unit; and said network termination unit connected with other ones of said sources including means responsive to the serially transmitted, pulse width binary encoded pulses to extract therefrom a clock signal, and means responsive to said clock signal for synchronous decoding of the serially transmitted, pulse width binary encoded pulses for provision to said other ones of said sources connected with the network termination unit, means responsive to said phase synchronization pulses to transmit data to said control unit, in phase synchronism with said pulse width binary encoded data pulses at said preselected transmission bit rate including a phase synchronization acquisition circuit for generating a synchronization control signal, and means responsive to the synchronization control signal for controlling the synchronous transmission of data to said control unit to maintain the transmission of data to the control unit in synchronization with the synchronization pulses generated thereby.
23. In a telecommunications network of transceiving informational sources, the improvement being a switching interface system for communication between said sources, comprising:
a control unit connected with some of said sources including means for encoding information from said sources in a serial, pulse width binary format, means for serially transmitting pulse width binary encoded pulses of said encoding information at a preselected transmission bit rate, and means for periodically inserting phase synchronization pulses into said serially transmitted pulse width binary encoded pulses to add phase synchronizational information thereto; and a network termination unit connected with other ones of said sources including means responsive to the serially transmitted, pulse width binary encoded pulses to extract therefrom a clock signal, means responsive to said clock signal for synchronous decoding of the serially transmitted, pulse width binary encoded pulses for provision to said other ones of said sources connected with the network termination unit, and means responsive to said phase synchronization pulses to transmit data to said control unit in phase synchronism with said pulse width binary encoded data pulses at said preselected transmission bit rate including a counter triggered by said clock signal, means responsive to said counter for identifying time division multiplexing channels of the telecommunication network, and means responsive to said binary encoded pulses for maintaining said counter in phase synchronization with said phase synchronization pulses of said control unit.
a control unit connected with some of said sources including means for encoding information from said sources in a serial, pulse width binary format, means for serially transmitting pulse width binary encoded pulses of said encoding information at a preselected transmission bit rate, and means for periodically inserting phase synchronization pulses into said serially transmitted pulse width binary encoded pulses to add phase synchronizational information thereto; and a network termination unit connected with other ones of said sources including means responsive to the serially transmitted, pulse width binary encoded pulses to extract therefrom a clock signal, means responsive to said clock signal for synchronous decoding of the serially transmitted, pulse width binary encoded pulses for provision to said other ones of said sources connected with the network termination unit, and means responsive to said phase synchronization pulses to transmit data to said control unit in phase synchronism with said pulse width binary encoded data pulses at said preselected transmission bit rate including a counter triggered by said clock signal, means responsive to said counter for identifying time division multiplexing channels of the telecommunication network, and means responsive to said binary encoded pulses for maintaining said counter in phase synchronization with said phase synchronization pulses of said control unit.
24. The switching interface system of claim 23 in which said control unit has one microprocessor, said network termination unit has another microprocessor, and one of said time division multiplexing channels is dedicated to passing messages from said one microprocessor of the control unit to said other microprocessor of the network termination unit.
25. In a telecommunications network of transceiving informational sources, the improvement being a switching interface system for communication between said sources, comprising:
a control unit connected with some of said sources including means for encoding information from said sources as a series of data pulses in said serial pulse width binary format, means for generating pulse width encoded synchronization pulses, and means for transmitting said series of data pulses and pulse width encoded synchronization pulses together on a time division multiplexing basis at a preselected bit rate; and a network termination unit connected with other ones of said sources including means responsive to at least said pulse width encoded synchronization pulses to derive a clock signal, means responsive to said clock signal for synchronous decoding of the series of pulse width encoded data pulses for connection to said other ones of the sources connected with the network termination unit, and means responsive to said pulse width encoded synchronization pulses to control synchronization of the synchronous decoding means of the network termination unit with the encoding means of the control unit.
a control unit connected with some of said sources including means for encoding information from said sources as a series of data pulses in said serial pulse width binary format, means for generating pulse width encoded synchronization pulses, and means for transmitting said series of data pulses and pulse width encoded synchronization pulses together on a time division multiplexing basis at a preselected bit rate; and a network termination unit connected with other ones of said sources including means responsive to at least said pulse width encoded synchronization pulses to derive a clock signal, means responsive to said clock signal for synchronous decoding of the series of pulse width encoded data pulses for connection to said other ones of the sources connected with the network termination unit, and means responsive to said pulse width encoded synchronization pulses to control synchronization of the synchronous decoding means of the network termination unit with the encoding means of the control unit.
26. The switching interface system of claim 25 in which said data pulses have preselected pulse widths, and the synchronization pulses have a pulse width differing from the preselected pulse widths of the data pulses.
27. The switching interface system of claim 25 in which said network termination unit includes means for coding information from the other ones of said sources as a series of uniform binary data pulses, means for qenerating uniform synchronization pulses having a pulse width which is substantially the same as that of the uniform binary data pulses in synchronism with said pulse width encoded pulses, and means for transmitting said uniform synchronization pulses together with said uniform binary data pulses as a series of uniform pulses.
28. The switching interface system of claim 27 in which said control unit includes means responsive to said uniform synchronization pulses to decode said binary data pulses from the termination unit.
29. The switching interface system of claim 28 in which said control unit includes means responsive to said uniform synchronization pulses to determine whether they are in phase synchronization with transmission of the pulse width encoded synchronization pulses of the control unit.
30. The switching interface system of claim 27 in which at least some preselected ones of said uniform synchronization pulses received by the control unit have a binary logic state opposite to that of the pulse width encoding synchronization pulses transmitted by the control unit.
31. The switching interface system of claim 25 in which said series of data pulses are pulse width binarily encoded by said encoding means, with logic-one data pulses having a different pulse width than logic-zero data pulses, and in which said means for generating synchronization pulses generates said synchronization pulses with a pulse width that differs from both the logic-zero data pulses and the logic-one data pulses.
32. The switching interface system of claim 25 in which said preselected bit rate at which the data pulses in the synchronization pulses are transmitted is a substantially uniform rate, and said clock signals in the network termination unit are produced at a preselected uniform frequency which is a preselected multiple of the uniform bit rate.
33. The switching interface system of claim 25 in which said network termination unit has means for transmitting data from the other ones of the sources connected thereto to the control unit which includes means responsive to said synchronization pulses for maintaining said data transmitted to the control unit in phase synchronization with the pulse width encoded synchronization pulses from the control unit.
34. In a telecommunications network of transceiving informational sources, the improvement being a switching interface system for communication between said sources, comprising:
a control unit connected with some of said sources including means for encoding information from said sources as a series of data pulses, means for generating pulse width encoded synchronization pulses, and means for transmitting said series of data pulses and pulse width encoded synchronization pulses together on a time division multiplexing basis at a preselected bit rate; and a network termination unit connected with other ones of said sources including means responsive to at least said pulse width encoded synchronization pulses to derive a clock signal, means responsive to said clock signal for synchronous decoding of the series of data pulses for connection to said other ones of the sources connected with the network termination unit, means for transmitting data from the other ones of the sources connected thereto to the control unit which includes means responsive to said synchronization pulses for maintaining said data transmitted to the control unit in phase synchronization with the pulse width encoded synchronization pulses from the control unit including a phase synchronization acquisition circuit responsive to the synchronization pulses received at the network termination unit to develop a synchronization control signal for controlling the phase synchronization of the encoding means, and means responsive to said pulse width encoded synchronization pulses to control synchronization of the synchronous decoding means of the network termination unit with the encoding means of the control unit.
a control unit connected with some of said sources including means for encoding information from said sources as a series of data pulses, means for generating pulse width encoded synchronization pulses, and means for transmitting said series of data pulses and pulse width encoded synchronization pulses together on a time division multiplexing basis at a preselected bit rate; and a network termination unit connected with other ones of said sources including means responsive to at least said pulse width encoded synchronization pulses to derive a clock signal, means responsive to said clock signal for synchronous decoding of the series of data pulses for connection to said other ones of the sources connected with the network termination unit, means for transmitting data from the other ones of the sources connected thereto to the control unit which includes means responsive to said synchronization pulses for maintaining said data transmitted to the control unit in phase synchronization with the pulse width encoded synchronization pulses from the control unit including a phase synchronization acquisition circuit responsive to the synchronization pulses received at the network termination unit to develop a synchronization control signal for controlling the phase synchronization of the encoding means, and means responsive to said pulse width encoded synchronization pulses to control synchronization of the synchronous decoding means of the network termination unit with the encoding means of the control unit.
35. The switching interface system of claim 34 in which the phase synchronization acquisition circuit includes means associated with said decoding means for generating synchronization pulse receipt signals in response to receipt of said synchronization pulses from the control unit, a counter of said encoding means responsive to said synchronization control signal to count clock pulses in phase synchronism with the synchronization pulses, means responsive to said counter for generating said synchronization control signal to indicate when the next synchronization pulse should be received when the counter is in phase synchronism with the synchronization pulses, and means responsive to said synchronization pulse receipt signal and said synchronization control signal not being generated within a preselected time period of one another for generating an out-of-sync signal.
36. The switching interface system of claim 35 including means responsive to said out-of-sync signal for resynchronization of said counter.
37. The switching interface system of claim 35 in which said network termination unit includes means responsive to said out-of-sync signal for producing an out-of-sync indication.
38. In a telecommunications network of informational sources, the improvement being a switching interface system for communication between said sources, comprising:
a control unit connected with some of said sources including means for binarily encoding information from a series of data pulses, means for decoding information received in a series of data pulses, means for generating a series of synchronization pulses of a preselected width differing from width of the data pulses, and means for transmitting said encoded information and said synchronization pulses together at a preselected bit rate; and a network termination unit connected with other ones of said sources including means responsive to at least said synchronization pulses to derive a clock signal means responsive to said clock signal for synchronous encoding and transmission of information from said other one of the sources to the control unit, and means responsive to said synchronization pulses to control phase synchronization of the encoding and transmitting means of said network termination unit with said decoding means of the control unit.
a control unit connected with some of said sources including means for binarily encoding information from a series of data pulses, means for decoding information received in a series of data pulses, means for generating a series of synchronization pulses of a preselected width differing from width of the data pulses, and means for transmitting said encoded information and said synchronization pulses together at a preselected bit rate; and a network termination unit connected with other ones of said sources including means responsive to at least said synchronization pulses to derive a clock signal means responsive to said clock signal for synchronous encoding and transmission of information from said other one of the sources to the control unit, and means responsive to said synchronization pulses to control phase synchronization of the encoding and transmitting means of said network termination unit with said decoding means of the control unit.
39. The switching interface system of claim 38 in which said clock signal deriving means includes means responsive in part to the preselected bit rate of the series of data pulses to derive said clock signal.
40. In a telecommunications network of informational sources, the improvement being a switching interface system for communication between said sources, comprising:
a control unit connected with some of said sources including means for encoding information from a series of data pulses, means for decoding information received in a series of data pulses, means for generating synchronization pulses of a preselected width differing from width of the data pulses, and means for transmitting said encoded information and said synchronization pulses together at a preselected bit rate; and a network termination unit connected with other ones of said sources including means responsive to at least said synchronization pulses to derive a clock signal, means responsive to said clock signal for synchronous encoding and transmission of information from said other ones of the sources to the control unit, means responsive to said synchronization pulses to control phase synchronization of the encoding and transmitting means of said network termination unit with said decoding means of the control unit, means responsive to the synchronization pulses from the control unit for detecting phase nonsynchronization with said control unit, and means responsive to said nonsynchronization detecting means to alter the timing of the encoding and transmitting means to eliminate the condition of nonsynchronization.
a control unit connected with some of said sources including means for encoding information from a series of data pulses, means for decoding information received in a series of data pulses, means for generating synchronization pulses of a preselected width differing from width of the data pulses, and means for transmitting said encoded information and said synchronization pulses together at a preselected bit rate; and a network termination unit connected with other ones of said sources including means responsive to at least said synchronization pulses to derive a clock signal, means responsive to said clock signal for synchronous encoding and transmission of information from said other ones of the sources to the control unit, means responsive to said synchronization pulses to control phase synchronization of the encoding and transmitting means of said network termination unit with said decoding means of the control unit, means responsive to the synchronization pulses from the control unit for detecting phase nonsynchronization with said control unit, and means responsive to said nonsynchronization detecting means to alter the timing of the encoding and transmitting means to eliminate the condition of nonsynchronization.
41. In a telecommunications network of informational sources, the improvement being a switching interface system for communication between said sources, comprising:
a control unit connected with some of said sources including means for encoding information from a series of data pulses, means for decoding information received in a series of data pulses, means for generating synchronization pulses of a preselected width differing from width of the data pulses, and means for transmitting said encoded information and said synchronization pulses together at a preselected bit rate; and a network termination unit connected with other ones of said sources including means responsive to at least said synchronization pulses to derive a clock signal, means responsive to said clock signal for synchronous encoding and transmission of information from said other one of the sources to the control unit, means responsive to said synchronization pulses to control phase synchronization of the encoding and transmitting means of said network termination unit with said decoding means of the control unit, and means responsive to the synchronization pulse from the control unit for transmitting to the control unit an indication of phase nonsynchronization.
a control unit connected with some of said sources including means for encoding information from a series of data pulses, means for decoding information received in a series of data pulses, means for generating synchronization pulses of a preselected width differing from width of the data pulses, and means for transmitting said encoded information and said synchronization pulses together at a preselected bit rate; and a network termination unit connected with other ones of said sources including means responsive to at least said synchronization pulses to derive a clock signal, means responsive to said clock signal for synchronous encoding and transmission of information from said other one of the sources to the control unit, means responsive to said synchronization pulses to control phase synchronization of the encoding and transmitting means of said network termination unit with said decoding means of the control unit, and means responsive to the synchronization pulse from the control unit for transmitting to the control unit an indication of phase nonsynchronization.
42. A method of communication in a synchronous digital data communication network, comprising the steps of:
receiving at a controller circuit a stream of binary data pulses in a nonself-clocking format in which clock signals are not carried with the stream of binary data pulses;
converting the nonself-clocking data stream to a corresponding self-clocking pulse width modulated binary data stream;
transmitting the pulse width modulated binary data stream to a termination unit of the network;
extracting a clock signal from the transmitted, binary pulse width modulated data stream received at the termination unit; and employing the extracted clock signal to decode the transmitted, pulse width modulated data stream to a stream of binary data pulses in nonself-clocking format.
receiving at a controller circuit a stream of binary data pulses in a nonself-clocking format in which clock signals are not carried with the stream of binary data pulses;
converting the nonself-clocking data stream to a corresponding self-clocking pulse width modulated binary data stream;
transmitting the pulse width modulated binary data stream to a termination unit of the network;
extracting a clock signal from the transmitted, binary pulse width modulated data stream received at the termination unit; and employing the extracted clock signal to decode the transmitted, pulse width modulated data stream to a stream of binary data pulses in nonself-clocking format.
43. The method of claim 42 including the step of employing the extracted clock signal to transmit a stream of data from the termination unit to the controller circuit in synchronism with the transmissions of the pulse width modulated data stream transmitted to the termination unit.
44. The method of claim 42 including the step of inserting a pulse width modulated synchronization pulse into the self-clocking pulse width modulated binary data stream, and employing the pulse width modulated synchronization pulse to maintain phase synchronization of communications between the controller circuit and the termination circuit.
45. The method of claim 42 in which the step of transmitting includes the step of transmitting each pulse width modulated pulse at the beginning of each clock cycle.
- 46. A method of communication in a synchronous digital data communication network, comprising the steps of:
receiving at a controller circuit a stream of binary data pulses in a nonself-clocking formation which clock signals are not carried with the stream of binary data pulses;
converting the nonself-clocking data stream to a corresponding self-clocking pulse width modulated binary data stream;
transmitting the pulse width modulated data stream to a termination unit of the network with preselected transitions at a preselected time during each clock cycle;
extracting a clock signal from the transmitted, pulse width modulated data stream received at the termination unit; and employing the extracted clock signal to decode the transmitted, pulse width modulated data stream to a stream of binary data pulses in nonself-clocking format.
- 46. A method of communication in a synchronous digital data communication network, comprising the steps of:
receiving at a controller circuit a stream of binary data pulses in a nonself-clocking formation which clock signals are not carried with the stream of binary data pulses;
converting the nonself-clocking data stream to a corresponding self-clocking pulse width modulated binary data stream;
transmitting the pulse width modulated data stream to a termination unit of the network with preselected transitions at a preselected time during each clock cycle;
extracting a clock signal from the transmitted, pulse width modulated data stream received at the termination unit; and employing the extracted clock signal to decode the transmitted, pulse width modulated data stream to a stream of binary data pulses in nonself-clocking format.
Priority Applications (3)
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|---|---|---|---|
| US07/416,077 US5140611A (en) | 1989-09-29 | 1989-09-29 | Pulse width modulated self-clocking and self-synchronizing data transmission and method for a telephonic communication network switching system |
| CA002041222A CA2041222C (en) | 1989-09-29 | 1991-04-25 | Pulse width modulated self-clocking and self-synchronizing data transmission telephonic switching system |
| GB9109326A GB2255479B (en) | 1989-09-29 | 1991-04-30 | Network switching system |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/416,077 US5140611A (en) | 1989-09-29 | 1989-09-29 | Pulse width modulated self-clocking and self-synchronizing data transmission and method for a telephonic communication network switching system |
| CA002041222A CA2041222C (en) | 1989-09-29 | 1991-04-25 | Pulse width modulated self-clocking and self-synchronizing data transmission telephonic switching system |
Publications (2)
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| CA2041222A1 CA2041222A1 (en) | 1992-10-26 |
| CA2041222C true CA2041222C (en) | 1996-10-22 |
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|---|---|---|---|
| CA002041222A Expired - Fee Related CA2041222C (en) | 1989-09-29 | 1991-04-25 | Pulse width modulated self-clocking and self-synchronizing data transmission telephonic switching system |
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| Country | Link |
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| US (1) | US5140611A (en) |
| CA (1) | CA2041222C (en) |
| GB (1) | GB2255479B (en) |
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| EP2434648A1 (en) * | 2010-09-25 | 2012-03-28 | ATLAS Elektronik GmbH | Encoder and decoder, encoding method and decoding method and system comprising encoder and decoder |
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|---|---|---|---|---|
| US2429613A (en) * | 1943-10-19 | 1947-10-28 | Standard Telephones Cables Ltd | Pulse multiplex communication system |
| BE479412A (en) * | 1944-08-07 | |||
| US2454792A (en) * | 1944-08-19 | 1948-11-30 | Standard Telephones Cables Ltd | Pulse multiplex communication system |
| US2495739A (en) * | 1945-04-02 | 1950-01-31 | Standard Telephones Cables Ltd | Selectable band width electrical pulse multichannel communication system |
| US4129751A (en) * | 1977-08-30 | 1978-12-12 | Bell Telephone Laboratories, Incorporated | PCM data throttle |
| US4207524A (en) * | 1977-12-23 | 1980-06-10 | Purchase Francis J | Radio coupled device for detecting and analyzing weak transmissions |
| US4175214A (en) * | 1978-08-07 | 1979-11-20 | Gte Automatic Electric Laboratories Incorporated | Apparatus and method for a pulse regeneration system |
| US4327441A (en) * | 1980-03-31 | 1982-04-27 | Texas Instruments Incorporated | Method and apparatus for synchronizing and calibrating a receiver to a pulse width modulation transmitter |
| US4497068A (en) * | 1982-01-25 | 1985-01-29 | Eaton Corporation | Encoding system for optic data link |
| US4547764A (en) * | 1983-10-31 | 1985-10-15 | Burroughs Corporation | Pulse width decoder for double frequency encoded serial data |
| US4885738A (en) * | 1985-12-31 | 1989-12-05 | American Telephone And Telegraph Company, At&T Bell Laboratories | Method of and apparatus for establishing a wideband communication facility through a switched communications network having narrow bandwidth time division multiplexed channels |
| US4651114A (en) * | 1986-02-03 | 1987-03-17 | The United States Of America As Represented By The Secretary Of The Air Force | Pulse repetition modulator apparatus |
-
1989
- 1989-09-29 US US07/416,077 patent/US5140611A/en not_active Expired - Lifetime
-
1991
- 1991-04-25 CA CA002041222A patent/CA2041222C/en not_active Expired - Fee Related
- 1991-04-30 GB GB9109326A patent/GB2255479B/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CA2041222A1 (en) | 1992-10-26 |
| GB2255479B (en) | 1995-05-10 |
| GB9109326D0 (en) | 1991-06-19 |
| GB2255479A (en) | 1992-11-04 |
| US5140611A (en) | 1992-08-18 |
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