CA2046253A1 - Integrated circuit package and compact assemblies thereof - Google Patents
Integrated circuit package and compact assemblies thereofInfo
- Publication number
- CA2046253A1 CA2046253A1 CA2046253A CA2046253A CA2046253A1 CA 2046253 A1 CA2046253 A1 CA 2046253A1 CA 2046253 A CA2046253 A CA 2046253A CA 2046253 A CA2046253 A CA 2046253A CA 2046253 A1 CA2046253 A1 CA 2046253A1
- Authority
- CA
- Canada
- Prior art keywords
- assemblies
- clusters
- rectangular structure
- integrated circuit
- rectangular
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
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- H01L2924/0001—Technical content checked by a classifier
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
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- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
- H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
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- H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities
Abstract
An integrated circuit package comprises a thermally conductive plate for receiving an integrated circuit and an open rectangular structure of conductor and insulator for surrounding the sides of the circuit and presenting one or more linear arrays of conductive connectors extending laterally through the rectangular structure.
Preferably the rectangular structure also includes transverse contacts. Advantageously the plate includes extensions beyond the rectangular structure for acting as cooling fins on opposing sides of the rectangular structure. The linear arrays and cooling fins are preferably on different pairs of parallel sides. The integrated circuit package permits the aggregation of packages into assemblies and into clusters of assemblies rich in interconnections. Vertically stacked packages form a rectangular parallelepiped having a plurality of parallel planar cooling fins projecting from two opposing surfaces and another pair of planar surfaces providing rectangular arrays of contacts to the enclosed integrated circuits. In addition, transverse contacts permit electrical interconnection of the stacked packages. Linear clusters can be aggregated as a linear array of such assemblies with their contact surfaces interconnected either directly by an anisotropically conducting plane or indirectly by an intervening transformation plane.
In a preferred linear cluster, successive assemblies are rotated by 90° with respect to the axis of the array. In such clusters each package in the rotated assembly contacts each package in the neighboring assemblies. In low power equipment, elimination of the cooling fins permits even higher levels of interconnection such as rectangular clusters of assemblies.
Preferably the rectangular structure also includes transverse contacts. Advantageously the plate includes extensions beyond the rectangular structure for acting as cooling fins on opposing sides of the rectangular structure. The linear arrays and cooling fins are preferably on different pairs of parallel sides. The integrated circuit package permits the aggregation of packages into assemblies and into clusters of assemblies rich in interconnections. Vertically stacked packages form a rectangular parallelepiped having a plurality of parallel planar cooling fins projecting from two opposing surfaces and another pair of planar surfaces providing rectangular arrays of contacts to the enclosed integrated circuits. In addition, transverse contacts permit electrical interconnection of the stacked packages. Linear clusters can be aggregated as a linear array of such assemblies with their contact surfaces interconnected either directly by an anisotropically conducting plane or indirectly by an intervening transformation plane.
In a preferred linear cluster, successive assemblies are rotated by 90° with respect to the axis of the array. In such clusters each package in the rotated assembly contacts each package in the neighboring assemblies. In low power equipment, elimination of the cooling fins permits even higher levels of interconnection such as rectangular clusters of assemblies.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/587,308 US5043794A (en) | 1990-09-24 | 1990-09-24 | Integrated circuit package and compact assemblies thereof |
US587,308 | 1990-09-24 |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2046253A1 true CA2046253A1 (en) | 1992-03-25 |
CA2046253C CA2046253C (en) | 1995-09-05 |
Family
ID=24349283
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002046253A Expired - Fee Related CA2046253C (en) | 1990-09-24 | 1991-07-04 | Integrated circuit package and compact assemblies thereof |
Country Status (4)
Country | Link |
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US (1) | US5043794A (en) |
EP (1) | EP0478188A3 (en) |
JP (1) | JPH0821644B2 (en) |
CA (1) | CA2046253C (en) |
Families Citing this family (53)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2233821A (en) * | 1989-07-11 | 1991-01-16 | Oxley Dev Co Ltd | Ceramic package including a semiconductor chip |
JP2978533B2 (en) * | 1990-06-15 | 1999-11-15 | 株式会社日立製作所 | Semiconductor integrated circuit device |
US5847448A (en) * | 1990-12-11 | 1998-12-08 | Thomson-Csf | Method and device for interconnecting integrated circuits in three dimensions |
US5157480A (en) * | 1991-02-06 | 1992-10-20 | Motorola, Inc. | Semiconductor device having dual electrical contact sites |
JPH0513666A (en) * | 1991-06-29 | 1993-01-22 | Sony Corp | Complex semiconductor device |
FR2688630B1 (en) * | 1992-03-13 | 2001-08-10 | Thomson Csf | METHOD AND DEVICE FOR THREE-DIMENSIONAL INTERCONNECTION OF ELECTRONIC COMPONENT PACKAGES. |
FR2696871B1 (en) * | 1992-10-13 | 1994-11-18 | Thomson Csf | Method of 3D interconnection of housings of electronic components, and 3D components resulting therefrom. |
US5455385A (en) * | 1993-06-28 | 1995-10-03 | Harris Corporation | Multilayer LTCC tub architecture for hermetically sealing semiconductor die, external electrical access for which is provided by way of sidewall recesses |
JP2931741B2 (en) * | 1993-09-24 | 1999-08-09 | 株式会社東芝 | Semiconductor device |
EP0658937A1 (en) * | 1993-12-08 | 1995-06-21 | Hughes Aircraft Company | Vertical IC chip stack with discrete chip carriers formed from dielectric tape |
EP0669653A1 (en) * | 1994-02-21 | 1995-08-30 | ABB Management AG | Power semiconductor module and circuit arrangement with at least two semiconductor modules |
US5500555A (en) * | 1994-04-11 | 1996-03-19 | Lsi Logic Corporation | Multi-layer semiconductor package substrate with thermally-conductive prepeg layer |
US5434745A (en) * | 1994-07-26 | 1995-07-18 | White Microelectronics Div. Of Bowmar Instrument Corp. | Stacked silicon die carrier assembly |
US6320257B1 (en) * | 1994-09-27 | 2001-11-20 | Foster-Miller, Inc. | Chip packaging technique |
JP2573809B2 (en) * | 1994-09-29 | 1997-01-22 | 九州日本電気株式会社 | Multi-chip module with built-in electronic components |
US5701233A (en) * | 1995-01-23 | 1997-12-23 | Irvine Sensors Corporation | Stackable modules and multimodular assemblies |
JP2944449B2 (en) * | 1995-02-24 | 1999-09-06 | 日本電気株式会社 | Semiconductor package and manufacturing method thereof |
US5514907A (en) * | 1995-03-21 | 1996-05-07 | Simple Technology Incorporated | Apparatus for stacking semiconductor chips |
US5572405A (en) * | 1995-06-07 | 1996-11-05 | International Business Machines Corporation (Ibm) | Thermally enhanced ball grid array package |
JPH0917919A (en) * | 1995-06-29 | 1997-01-17 | Fujitsu Ltd | Semiconductor device |
US5633530A (en) * | 1995-10-24 | 1997-05-27 | United Microelectronics Corporation | Multichip module having a multi-level configuration |
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-
1990
- 1990-09-24 US US07/587,308 patent/US5043794A/en not_active Expired - Lifetime
-
1991
- 1991-07-04 CA CA002046253A patent/CA2046253C/en not_active Expired - Fee Related
- 1991-09-13 EP EP19910308391 patent/EP0478188A3/en not_active Ceased
- 1991-09-18 JP JP3265518A patent/JPH0821644B2/en not_active Expired - Lifetime
Also Published As
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EP0478188A2 (en) | 1992-04-01 |
JPH04234199A (en) | 1992-08-21 |
EP0478188A3 (en) | 1992-07-08 |
CA2046253C (en) | 1995-09-05 |
JPH0821644B2 (en) | 1996-03-04 |
US5043794A (en) | 1991-08-27 |
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