CA2050123A1 - Apparatus and method for parallel generation of cyclic redundancy check (crc) codes - Google Patents

Apparatus and method for parallel generation of cyclic redundancy check (crc) codes

Info

Publication number
CA2050123A1
CA2050123A1 CA2050123A CA2050123A CA2050123A1 CA 2050123 A1 CA2050123 A1 CA 2050123A1 CA 2050123 A CA2050123 A CA 2050123A CA 2050123 A CA2050123 A CA 2050123A CA 2050123 A1 CA2050123 A1 CA 2050123A1
Authority
CA
Canada
Prior art keywords
code word
crc code
crc
term corresponding
preliminary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2050123A
Other languages
French (fr)
Other versions
CA2050123C (en
Inventor
Subrahmanyam Dravida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Publication of CA2050123A1 publication Critical patent/CA2050123A1/en
Application granted granted Critical
Publication of CA2050123C publication Critical patent/CA2050123C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H03M13/091—Parallel or block-wise CRC computation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6575—Implementations based on combinatorial logic, e.g. Boolean circuits

Abstract

A method and apparatus are disclosed for the efficient generation of cyclic redundancy check (CRC) codes employing CRC generator polynomials of the form (1 + x)~f(x). The efficiency is achieved by independently and concurrently generating in parallel a preliminary CRC code word corresponding to f(x) and a term corresponding to (1 + x) over a message M(x). The term corresponding to (1 + x) is generated in a manner to have either a zero (0) state or a one (1) state.
Then, the term corresponding to (1 + x) is used to modify the preliminary CRC
code word to obtain an overall CRC code word being generated over message M(x). If the term corresponding to (1 + x) is a 0 state, then the overall CRC code word is obtained by shifting the bits of the preliminary CRC code word once to the left. If the term corresponding to (1 + x) is a 1 state, then the overall CRC code word is obtained by shifting the bits of the preliminary CRC code word once to the left and adding f(x) to the shifted preliminary CRC code word.
CA002050123A 1990-10-11 1991-08-29 Apparatus and method for parallel generation of cyclic redundancy check (crc) codes Expired - Fee Related CA2050123C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US59589990A 1990-10-11 1990-10-11
US595,899 1990-10-11

Publications (2)

Publication Number Publication Date
CA2050123A1 true CA2050123A1 (en) 1992-04-12
CA2050123C CA2050123C (en) 1997-12-09

Family

ID=24385167

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002050123A Expired - Fee Related CA2050123C (en) 1990-10-11 1991-08-29 Apparatus and method for parallel generation of cyclic redundancy check (crc) codes

Country Status (5)

Country Link
US (1) US5282214A (en)
EP (1) EP0480621B1 (en)
JP (1) JPH087700B2 (en)
CA (1) CA2050123C (en)
DE (1) DE69117857T2 (en)

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JP2821324B2 (en) * 1992-11-04 1998-11-05 三菱電機株式会社 Error correction circuit
US5390196A (en) * 1992-11-12 1995-02-14 Bull Hn Information Systems Inc. Byte-wise determination of a checksum from a CRC-32 polynomial
JP3000811B2 (en) * 1993-01-25 2000-01-17 日本電気株式会社 Cyclic coding and CRC device and processing method thereof
GB9312135D0 (en) * 1993-06-11 1993-07-28 Inmos Ltd Generation of checking data
GB9312136D0 (en) * 1993-06-11 1993-07-28 Inmos Ltd Transmission of messages
KR950009690B1 (en) * 1993-09-14 1995-08-26 재단법인한국전자통신연구소 Crc synchronizing apparatus
US5878057A (en) * 1995-10-06 1999-03-02 Tektronix, Inc. Highly parallel cyclic redundancy code generator
US5805614A (en) * 1996-07-03 1998-09-08 General Signal Corporation Fault tolerant switch fabric with control and data correction by hamming codes
US5812556A (en) * 1996-07-03 1998-09-22 General Signal Corporation Fault tolerant switch fabric with control and data correction by hamming codes and error inducing check register
US5796733A (en) * 1996-07-03 1998-08-18 General Signal Corporation Time division switching system
GB2321374A (en) * 1997-01-21 1998-07-22 Ico Services Ltd Spread spectrum satellite communication
US6006354A (en) * 1997-02-12 1999-12-21 Stmicroelectronics, Inc. Security device for a video digital to analog converter
DE69731074T2 (en) * 1997-04-30 2005-10-06 Hewlett-Packard Development Co., L.P., Houston Arrangement and method for transmitting data over a plurality of channels
DE19838865C2 (en) * 1998-08-26 2001-03-01 Ericsson Telefon Ab L M Parallel CRC generation circuit for generating a CRC code and method for generating such a circuit
US6519738B1 (en) * 2000-03-07 2003-02-11 International Business Machines Corporation Method and apparatus for high-speed CRC computation based on state-variable transformation
US6609225B1 (en) * 2000-12-21 2003-08-19 Cisco Technology, Inc. Method and apparatus for generating and checking cyclic redundancy code (CRC) values using a multi-byte CRC generator on a variable number of bytes
US6766493B1 (en) 2000-12-21 2004-07-20 Cisco Technology, Inc. Method and apparatus for generating and checking cyclic redundancy code (CRC) values using a CRC generator and binary galois field multiplier
GB2383725A (en) * 2001-12-27 2003-07-02 Ubinetics Ltd Data decoding with Cyclic Redundancy Check
US7458006B2 (en) * 2002-02-22 2008-11-25 Avago Technologies General Ip (Singapore) Pte. Ltd. Methods for computing the CRC of a message from the incremental CRCs of composite sub-messages
US7225387B2 (en) * 2004-02-03 2007-05-29 International Business Machines Corporation Multilevel parallel CRC generation and checking circuit
US8438265B2 (en) * 2004-11-04 2013-05-07 International Business Machines Corporation Method of offloading iSCSI PDU corruption-detection digest generation from a host processing unit, and related iSCSI offload engine
JP4935787B2 (en) * 2008-09-12 2012-05-23 日本電気株式会社 Cyclic code processing circuit

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3805232A (en) * 1972-01-24 1974-04-16 Honeywell Inf Systems Encoder/decoder for code words of variable length
US3775746A (en) * 1972-05-19 1973-11-27 Ibm Method and apparatus for detecting odd numbers of errors and burst errors of less than a predetermined length in scrambled digital sequences
US4312068A (en) * 1976-08-12 1982-01-19 Honeywell Information Systems Inc. Parallel generation of serial cyclic redundancy check
JPS58147807A (en) * 1982-02-26 1983-09-02 Toshiba Corp Error correcting circuit
US4498174A (en) * 1982-08-25 1985-02-05 Ael Microtel Limited Parallel cyclic redundancy checking circuit
US4454600A (en) * 1982-08-25 1984-06-12 Ael Microtel Limited Parallel cyclic redundancy checking circuit
US4677623A (en) * 1983-11-11 1987-06-30 Hitachi, Ltd. Decoding method and apparatus for cyclic codes
US4593393A (en) * 1984-02-06 1986-06-03 Motorola, Inc. Quasi parallel cyclic redundancy checker
US4809273A (en) * 1987-01-29 1989-02-28 International Business Machines Corporation Device for verifying operation of a checking code generator
US4890286A (en) * 1987-12-11 1989-12-26 Sanyo Electric Co., Ltd. Method and apparatus for decoding error correcting code
US5121396A (en) * 1988-10-27 1992-06-09 International Business Machines Corp. Preservation of crc integrity upon intentional data alteration during message transmission
US5111463A (en) * 1989-11-09 1992-05-05 Exabyte Corporation Error correction method and apparatus
US5103451A (en) * 1990-01-29 1992-04-07 Motorola, Inc. Parallel cyclic redundancy check circuit

Also Published As

Publication number Publication date
JPH05127934A (en) 1993-05-25
CA2050123C (en) 1997-12-09
US5282214A (en) 1994-01-25
EP0480621B1 (en) 1996-03-13
DE69117857D1 (en) 1996-04-18
EP0480621A3 (en) 1992-05-13
DE69117857T2 (en) 1996-08-14
JPH087700B2 (en) 1996-01-29
EP0480621A2 (en) 1992-04-15

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