CA2050658A1 - Dual hardware channels and hardware context switching in a graphics rendering processor - Google Patents

Dual hardware channels and hardware context switching in a graphics rendering processor

Info

Publication number
CA2050658A1
CA2050658A1 CA2050658A CA2050658A CA2050658A1 CA 2050658 A1 CA2050658 A1 CA 2050658A1 CA 2050658 A CA2050658 A CA 2050658A CA 2050658 A CA2050658 A CA 2050658A CA 2050658 A1 CA2050658 A1 CA 2050658A1
Authority
CA
Canada
Prior art keywords
task
channel
hardware
context switching
graphics processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2050658A
Other languages
French (fr)
Other versions
CA2050658C (en
Inventor
John M. Peaslee
Jeffrey C. Malacarne
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
John M. Peaslee
Jeffrey C. Malacarne
Hughes Aircraft Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by John M. Peaslee, Jeffrey C. Malacarne, Hughes Aircraft Company filed Critical John M. Peaslee
Publication of CA2050658A1 publication Critical patent/CA2050658A1/en
Application granted granted Critical
Publication of CA2050658C publication Critical patent/CA2050658C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/04—Display device controller operating with a plurality of display units

Abstract

An improved graphics processor (10) has rapid response to higher priority tasks. It is implemented with multiple channels of FIFO input circuits (60, 62 and 61, 63) and with task interrupt and context switching capability. The graphics processor (10) servicing a first channel task is interrupted when a higher priority task is available in a second channel. Context switching facilitates interrupting of the lower priority first channel task, then saving of the context of the first channel task, then performing high-er priority second channel task, then restoring the interrupted first channel task, and then continuing with the processing of the restored first channel task. It is also imple-mented with concurrent downloading from a host computer (14) and processing by the graphics processor (10) and implemented with general purpose graphics processingcapability, including multi-level nested interrupts and nested subroutines.
CA002050658A 1990-09-14 1991-09-04 Dual hardware channels and hardware context switching in a graphics rendering processor Expired - Fee Related CA2050658C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US58270990A 1990-09-14 1990-09-14
US582,709 1990-09-14

Publications (2)

Publication Number Publication Date
CA2050658A1 true CA2050658A1 (en) 1992-03-15
CA2050658C CA2050658C (en) 1997-01-28

Family

ID=24330218

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002050658A Expired - Fee Related CA2050658C (en) 1990-09-14 1991-09-04 Dual hardware channels and hardware context switching in a graphics rendering processor

Country Status (4)

Country Link
US (1) US5371849A (en)
EP (1) EP0475421A3 (en)
JP (1) JPH04299389A (en)
CA (1) CA2050658C (en)

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Also Published As

Publication number Publication date
EP0475421A3 (en) 1993-02-03
EP0475421A2 (en) 1992-03-18
CA2050658C (en) 1997-01-28
JPH04299389A (en) 1992-10-22
US5371849A (en) 1994-12-06

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