CA2056254C - Bi-directional buffer line amplifier - Google Patents
Bi-directional buffer line amplifierInfo
- Publication number
- CA2056254C CA2056254C CA002056254A CA2056254A CA2056254C CA 2056254 C CA2056254 C CA 2056254C CA 002056254 A CA002056254 A CA 002056254A CA 2056254 A CA2056254 A CA 2056254A CA 2056254 C CA2056254 C CA 2056254C
- Authority
- CA
- Canada
- Prior art keywords
- transmit
- network
- amplifier
- receive
- gain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/40—Applications of speech amplifiers
Abstract
An improved bi-directional buffer line amplifier is disclosed that provides a high performance analog interface between a Digital Network Interface Circuit (DNIC) and a transmission line. The buffer line amplifier includes a transmit amplifier network including an input connected to a DNIC transmit signal output. The input is arranged to receive transmit signals from the DNIC. A
transmit output is connected to a matching network via a selectable gain amplifying circuit. The selectable gain amplifying circuit applies the transmit signals to the matching network in a first or a second gain level. In the first gain level the gain amplifying circuit is removed from the transmit amplifier network and the transmit amplifier network operates as a unity gain amplifier.
This allows the buffer line amplifier to work efficiently with transmission line loop lengths from zero to a nominal distance. In the second gain level the gain amplifying circuit is connected in series between the transmit amplifier network and the matching network, thereby, significantly amplifying the transmit signals. This allows the buffer line amplifier to work efficiently with transmission line loop lengths of a substantially greater distance than the nominal distance. A receive amplifier network is also included that cancels the transmit signals from receive signals. This provides the necessary phase error cancellation required by the DNIC for the error free reception of the receive signals.
transmit output is connected to a matching network via a selectable gain amplifying circuit. The selectable gain amplifying circuit applies the transmit signals to the matching network in a first or a second gain level. In the first gain level the gain amplifying circuit is removed from the transmit amplifier network and the transmit amplifier network operates as a unity gain amplifier.
This allows the buffer line amplifier to work efficiently with transmission line loop lengths from zero to a nominal distance. In the second gain level the gain amplifying circuit is connected in series between the transmit amplifier network and the matching network, thereby, significantly amplifying the transmit signals. This allows the buffer line amplifier to work efficiently with transmission line loop lengths of a substantially greater distance than the nominal distance. A receive amplifier network is also included that cancels the transmit signals from receive signals. This provides the necessary phase error cancellation required by the DNIC for the error free reception of the receive signals.
Description
2~55~25~L
AN IMPROVED BI-DIRECTlONAL ~U~K LINE AMPLIFIER
BACKGROUND OF THE lNv~NllON
1. Field of the Invention The present invention relates in general to the field of telec.r ications, and more palrticularly, to an improved bi-directional buffer line amplifier for use with a U-inter~ace Basic Rate ISDN (Integrated Services Digital Network).
2. Description of the Prior Art.
Modern digital telec~- ication systems have operating requirements that interface their digital operation to an analog tr~n! ;ssion environment. Many such systems use a Digital Network Interface Circuit (DNIC) device to interface a digitally operating system to an analog tr~n~ sion line. The DNIC is capable of providing high speed, full duplex digital transmission up to 160kbit/s over a standard analog twisted wire pair.
Further, the DNIC uses adaptive echo-cancelling tech-niques that transfers data in a (2B+D) format compatible to the ISDN basic rate. Such dsvices are ideal for pro-viding the nun interface point in an IS~N application.
Such devices are used in ~smartn telephone instru-ments that have both a voice and data capability. Within such a telephone instrument the DNIC would terminate the line and encode/decode the data and voice for transmis-sion. Additional electronics could provide interfaces for a standard telephone instrument and any nu~ber of data ports supporting standard data rates for such things as computer c~ ications. One such device is the MT8972 DNIC, manufactured by the MITEL~ Corporation.
The design of the analog interface between the DNIC
and the transmission line is a difficult problem due to a concession between two issues. The first issue, is the design of a network of components, connected via a trans-former, that provide the necessary near-end cancellation of the transmitted signal. The cancellation must be de-signed for transmission line loop lengths from zero to a ~ ~ 5 ~? 5 ~
large distance, and for 22, 24 and 26 gauge cable. The second i~sue, is the design of an intentional phase error in the near-end cancellation to meet a required one~half sampling clock within the DNIC. Thereby, allowing the DNIC to internally cancel correctly.
The solution to the above issues achieves a circuit that functions correctly for only moderata transmission line loop lengths, nonetheless, many cu~tomers require extended ranges for their particular applications.
In these cases, loop extender circuits are used to extend the operating range or the transmission line length over which the DNIC may operate efficiently.
These loop extender circuits are found between the DNIC
and the tr~n! ;s~ion line and basically combine signal equalization and amplification for the receive and trans-mit paths of the DNIC. One such device is the MH89726/728, manufactured by the MIT~L~ Corporation.
However, a major problem with the loop extender circuits is that they can not be used for zero or near tr~nq~
sion line loop lengths. In the MICROELECTRONICS DIGITAL
COMMUNICATIONS HANDBOOK, issue seven, by the MITEL~
Corporation, application sheet MSAS-~6, Figure 2, page 15-11, suggests the use of three switches or jumpers to connect or bypass the loop extender circuit depending on the loop length to be achieved. The problem with this method is that, to correctly design a circuit to include the compromise issues discussed above would require also changing the electronic network components, that is, a clock correction to meet the one-half sampling clock re-quirement for long loops and no-clock correction for near loops.
Accordingly, it is an object of the present inven-tion to provide an improved bi-directional buffer line amplifier that will perform efficiently with transmission lines that have loop lengths ranging from zero to a long range, with no data transmission errors.
.~!
;,, ;~55~5~
SUMMARY OF THE INVENTION
The above and other objects, advantages, and capa-bilities are realized in an improved bi-directional buffer line amplifier used in inter~acing an analog tr~n~ricsion line to a Digital Interface Network Circuit (DNIC). The bi-directional buffer line amplifier in-aludes a transformer connecting a transmission line to the buffer line amplifier, and a matching network that matches the buffer line amplifier to the impedance of the tr~n! ;ssion line.
The buf~er line amplifiar further includes a trans-mit amplifier network including an input connected to a DNIC transmit signal output. The input is arranged to receive transmit signals from the D~IC. A transmit out-put is connected to the matching network via selectable gain amplifying circuit. The selectable gain amplifying circuit is arranged to apply thQ transmit signals to the matching network in a first gain level or alternatively, a second gain level.
In the first gain level, the gain amplifying circuit is removed from the transmit amplifier network and the transmit amplifiar network operate~ as a unity gain am-plifier. In this configuration, the matching network via the transformer, couples the transmit ~ignals to the tr~n~r;~sion line. The first gain level allows the buffer line amplifier to work efficiently with transmis-sion line loop lengths from zero to a n~ in~l distance.
In the second gain level, the gain amplifying cir-cuit is ccnnected in series between the transmit ampli-fier networX and the matching network, thereby, signifi-cantly amplifying the transmit signals. In this configu-ration, the matching network via the transformer couples the amplified transmit signals to the transmission line.
The second gain level allows the buffer line amplifier to work efficiently with transmission line loop lengths of a substantially greater distance than th2 nominal distanceO
The bi-directional buffer line amplifier further in-cludes a receive amplifier network. The receive ampli-fier network includes a first input connected to the : - , ~ .. , :
-,... , ~
i5;~5~
transmit amplifier network output and a second input con-nected to the matching network. The receive amp~ifier network first input receivPs the transmit signals from the transmit amplifier network output and the second in-put receives, receive signals transmitted on the trans-mission line. The receive amplifier network cancels the transmit signals from the receive signals and connects the receive signals to the receive signal input o~ the DNIC. This provides the necessary phase error cancella-tion required by the DNIC for the error free reception of the receive signals.
BRIEF DESCRIPTION OF THE DRAWINGS
A better underst~n~ing of the invention may be had from the consideration of the following detailed descrip-tion taken in conjunction with the single sheet of draw-ings included herewith, illustrating the improved bi-directional buffer line amplifier in accordance with the present invention.
DESCRIPTION OF A PREFERRED EMBODIMENT
The present invention is an improved bi-directional buffer line amplifier that provides a high performance analog interface between a Digital Network Interface Cir-cuit (DNIC) and an outside transmission line. The buffer line amplifier operates with transmis~ion lines having 24 and 26 gauge cable and of various lengths.
Turning now to the single sheet of drawings the fol-lowing major components of the present invention are illustrated. A DNIC 10 is connected to a bi-directional buf~er line amplifier or Buffer Line Amplifier 19. The Buffer Line Amplifier 19 is further connected to a Match-ing Network 55 and to a gain resistor 40 and shorting switch Sl. The Matching Network 55 is further c~nnected to the tip and ring leads of a communication tr~n! ;ssion line via transformer Tl.
Within the Buffer Line Amplifier 19, the RC network consisting of capacitors 12, 13, 16 and 18 and resistors 14, 15 and 17 provide the necessary gain and phase delay . ~
; ' : ~ i ' . .
~5~S~
to interact with the received signal. This interaction causes the DNIC 10 to cancel the transmitted signal cor-rectly. Further, any changes at the U-interface point will not alter this cancellation behavior, since the impedances between the Tx and Rx connect:ion~ are constant.
The Transmit amplifier comprising capacitor 21, re-sistor 22, operational amplifier 20, ancl resistor 23 is configured as a unity gain amplifier when gain resistor 40 is shorted. Resistor 40 is shorted by closing switch Sl. This connects Tx gain directly to Tx out and buffers the transmitted signal from the DNIC 10.
The Matching Network 55 consists of resistors 50 and 52 and capacitor 51. The components of the Matching Net-work 55 are select~d to provide an optimal balance such that the re~eive side of the Buffer Line Amplifier 19 cancels the transmitted side effectivaly. The gain of the receive amplifier is structured so that when the sig-nal at Rx in+ input is one-half and in phase with the signal at the Rx in- input, the transmitted signal (signal from Tx out) is completely cancelled lea~ing only the received signal at the Rx in+ input to pass through the receive amplifier to the DNIC 10.
The values and topology of the Matching Network 55 components is designed uniqu~ly for the specific trans-former Tl used. The Matching Network 55 must be re-evaluated for each transformer designed in this applica-tion. Transformer T1 must exhibit a low leakage induc-tance, and is gensrally a low DCR broadband transformer.
Due to the isolation between the near-end cancella-tion at the DNIC and the cancellation at the transformer Tl, th~ design at the DNIC is constant. This reguires only a design effort at the transformer for the specific transformer, cable or frequancy requirements of the tr~n~ ;~sion line.
With switch S1 closed and gain resistor 40 shorted the buffer line amplifier 19 interfaces the transmission line to the DNIC 10 ~or loop lengths from zero distance to a nominal short loop range. In the event that an ,:
. .
~5~;~S4 extended transmission line loop length is reguired, switch Sl is opened applying gain resistor 40 between the Tx gain and ~x out outputs of Buffer Line Amplifier 19.
The value of resistor 40 is that value which is deter-mined to be effective for the loop range required. TheMatching Network 55 is optimized to function efficiently with gain resistor 40 and will allow a possible 10 dB
gain in the transmitted signal for achieving long loop ranges. Therefore, S1 in combination w:ith resistor 40 allow buffer line amplifier 19 to provide an analog in-terface for zero to short loop lengths and for long loop lengths.
The present invention as described above is a unique circuit device which can be electrically altered to oper-ate within short and long trAn! ission line loop lengths.By using a Buffer Line Amplifier with unity gain, an in-terface can ~e designed between the DNIC and the buffer to satisfy the one-clock sampling problem with no effect on the various cable conditions. Further, a matching network can be designed that is solely dependent on the conditions of the transmission line, such as length and cable type. ~his allows more freedom in designing a transformer and matching network that is more consistent in manufacturing and which maintains a high degree of Z5 circuit per~ormance. Finally, the gain of the Buffer Line Amplifier can be easily altered by the switching in or out of a single resistor. The addition of a gain re~
sistor of a specific value allows for a higher transmit level, and therefore, operation of the buffer line ampli-fier in long transmission line loop ranges. The removalof the gain resistor allows the same Buffer Line Ampli-fier to operate effectively in loop lengths of zero dis-tance to a nl in~l short loop range with no errors.
It will be obvious to those skilled in the art that numerous modifications to the present invention can be made without departing from the scope of the invention as dafined by the appended claims. In this context, it should be recognized that the essence of the invention resides in a new and improved bi-directional buffer line , ~
, , :.
Z~ S4 amplifier that performs ef~iciently in various transmis-sion line loop lengths.
,; . . . . . - .
,. .. ..
AN IMPROVED BI-DIRECTlONAL ~U~K LINE AMPLIFIER
BACKGROUND OF THE lNv~NllON
1. Field of the Invention The present invention relates in general to the field of telec.r ications, and more palrticularly, to an improved bi-directional buffer line amplifier for use with a U-inter~ace Basic Rate ISDN (Integrated Services Digital Network).
2. Description of the Prior Art.
Modern digital telec~- ication systems have operating requirements that interface their digital operation to an analog tr~n! ;ssion environment. Many such systems use a Digital Network Interface Circuit (DNIC) device to interface a digitally operating system to an analog tr~n~ sion line. The DNIC is capable of providing high speed, full duplex digital transmission up to 160kbit/s over a standard analog twisted wire pair.
Further, the DNIC uses adaptive echo-cancelling tech-niques that transfers data in a (2B+D) format compatible to the ISDN basic rate. Such dsvices are ideal for pro-viding the nun interface point in an IS~N application.
Such devices are used in ~smartn telephone instru-ments that have both a voice and data capability. Within such a telephone instrument the DNIC would terminate the line and encode/decode the data and voice for transmis-sion. Additional electronics could provide interfaces for a standard telephone instrument and any nu~ber of data ports supporting standard data rates for such things as computer c~ ications. One such device is the MT8972 DNIC, manufactured by the MITEL~ Corporation.
The design of the analog interface between the DNIC
and the transmission line is a difficult problem due to a concession between two issues. The first issue, is the design of a network of components, connected via a trans-former, that provide the necessary near-end cancellation of the transmitted signal. The cancellation must be de-signed for transmission line loop lengths from zero to a ~ ~ 5 ~? 5 ~
large distance, and for 22, 24 and 26 gauge cable. The second i~sue, is the design of an intentional phase error in the near-end cancellation to meet a required one~half sampling clock within the DNIC. Thereby, allowing the DNIC to internally cancel correctly.
The solution to the above issues achieves a circuit that functions correctly for only moderata transmission line loop lengths, nonetheless, many cu~tomers require extended ranges for their particular applications.
In these cases, loop extender circuits are used to extend the operating range or the transmission line length over which the DNIC may operate efficiently.
These loop extender circuits are found between the DNIC
and the tr~n! ;s~ion line and basically combine signal equalization and amplification for the receive and trans-mit paths of the DNIC. One such device is the MH89726/728, manufactured by the MIT~L~ Corporation.
However, a major problem with the loop extender circuits is that they can not be used for zero or near tr~nq~
sion line loop lengths. In the MICROELECTRONICS DIGITAL
COMMUNICATIONS HANDBOOK, issue seven, by the MITEL~
Corporation, application sheet MSAS-~6, Figure 2, page 15-11, suggests the use of three switches or jumpers to connect or bypass the loop extender circuit depending on the loop length to be achieved. The problem with this method is that, to correctly design a circuit to include the compromise issues discussed above would require also changing the electronic network components, that is, a clock correction to meet the one-half sampling clock re-quirement for long loops and no-clock correction for near loops.
Accordingly, it is an object of the present inven-tion to provide an improved bi-directional buffer line amplifier that will perform efficiently with transmission lines that have loop lengths ranging from zero to a long range, with no data transmission errors.
.~!
;,, ;~55~5~
SUMMARY OF THE INVENTION
The above and other objects, advantages, and capa-bilities are realized in an improved bi-directional buffer line amplifier used in inter~acing an analog tr~n~ricsion line to a Digital Interface Network Circuit (DNIC). The bi-directional buffer line amplifier in-aludes a transformer connecting a transmission line to the buffer line amplifier, and a matching network that matches the buffer line amplifier to the impedance of the tr~n! ;ssion line.
The buf~er line amplifiar further includes a trans-mit amplifier network including an input connected to a DNIC transmit signal output. The input is arranged to receive transmit signals from the D~IC. A transmit out-put is connected to the matching network via selectable gain amplifying circuit. The selectable gain amplifying circuit is arranged to apply thQ transmit signals to the matching network in a first gain level or alternatively, a second gain level.
In the first gain level, the gain amplifying circuit is removed from the transmit amplifier network and the transmit amplifiar network operate~ as a unity gain am-plifier. In this configuration, the matching network via the transformer, couples the transmit ~ignals to the tr~n~r;~sion line. The first gain level allows the buffer line amplifier to work efficiently with transmis-sion line loop lengths from zero to a n~ in~l distance.
In the second gain level, the gain amplifying cir-cuit is ccnnected in series between the transmit ampli-fier networX and the matching network, thereby, signifi-cantly amplifying the transmit signals. In this configu-ration, the matching network via the transformer couples the amplified transmit signals to the transmission line.
The second gain level allows the buffer line amplifier to work efficiently with transmission line loop lengths of a substantially greater distance than th2 nominal distanceO
The bi-directional buffer line amplifier further in-cludes a receive amplifier network. The receive ampli-fier network includes a first input connected to the : - , ~ .. , :
-,... , ~
i5;~5~
transmit amplifier network output and a second input con-nected to the matching network. The receive amp~ifier network first input receivPs the transmit signals from the transmit amplifier network output and the second in-put receives, receive signals transmitted on the trans-mission line. The receive amplifier network cancels the transmit signals from the receive signals and connects the receive signals to the receive signal input o~ the DNIC. This provides the necessary phase error cancella-tion required by the DNIC for the error free reception of the receive signals.
BRIEF DESCRIPTION OF THE DRAWINGS
A better underst~n~ing of the invention may be had from the consideration of the following detailed descrip-tion taken in conjunction with the single sheet of draw-ings included herewith, illustrating the improved bi-directional buffer line amplifier in accordance with the present invention.
DESCRIPTION OF A PREFERRED EMBODIMENT
The present invention is an improved bi-directional buffer line amplifier that provides a high performance analog interface between a Digital Network Interface Cir-cuit (DNIC) and an outside transmission line. The buffer line amplifier operates with transmis~ion lines having 24 and 26 gauge cable and of various lengths.
Turning now to the single sheet of drawings the fol-lowing major components of the present invention are illustrated. A DNIC 10 is connected to a bi-directional buf~er line amplifier or Buffer Line Amplifier 19. The Buffer Line Amplifier 19 is further connected to a Match-ing Network 55 and to a gain resistor 40 and shorting switch Sl. The Matching Network 55 is further c~nnected to the tip and ring leads of a communication tr~n! ;ssion line via transformer Tl.
Within the Buffer Line Amplifier 19, the RC network consisting of capacitors 12, 13, 16 and 18 and resistors 14, 15 and 17 provide the necessary gain and phase delay . ~
; ' : ~ i ' . .
~5~S~
to interact with the received signal. This interaction causes the DNIC 10 to cancel the transmitted signal cor-rectly. Further, any changes at the U-interface point will not alter this cancellation behavior, since the impedances between the Tx and Rx connect:ion~ are constant.
The Transmit amplifier comprising capacitor 21, re-sistor 22, operational amplifier 20, ancl resistor 23 is configured as a unity gain amplifier when gain resistor 40 is shorted. Resistor 40 is shorted by closing switch Sl. This connects Tx gain directly to Tx out and buffers the transmitted signal from the DNIC 10.
The Matching Network 55 consists of resistors 50 and 52 and capacitor 51. The components of the Matching Net-work 55 are select~d to provide an optimal balance such that the re~eive side of the Buffer Line Amplifier 19 cancels the transmitted side effectivaly. The gain of the receive amplifier is structured so that when the sig-nal at Rx in+ input is one-half and in phase with the signal at the Rx in- input, the transmitted signal (signal from Tx out) is completely cancelled lea~ing only the received signal at the Rx in+ input to pass through the receive amplifier to the DNIC 10.
The values and topology of the Matching Network 55 components is designed uniqu~ly for the specific trans-former Tl used. The Matching Network 55 must be re-evaluated for each transformer designed in this applica-tion. Transformer T1 must exhibit a low leakage induc-tance, and is gensrally a low DCR broadband transformer.
Due to the isolation between the near-end cancella-tion at the DNIC and the cancellation at the transformer Tl, th~ design at the DNIC is constant. This reguires only a design effort at the transformer for the specific transformer, cable or frequancy requirements of the tr~n~ ;~sion line.
With switch S1 closed and gain resistor 40 shorted the buffer line amplifier 19 interfaces the transmission line to the DNIC 10 ~or loop lengths from zero distance to a nominal short loop range. In the event that an ,:
. .
~5~;~S4 extended transmission line loop length is reguired, switch Sl is opened applying gain resistor 40 between the Tx gain and ~x out outputs of Buffer Line Amplifier 19.
The value of resistor 40 is that value which is deter-mined to be effective for the loop range required. TheMatching Network 55 is optimized to function efficiently with gain resistor 40 and will allow a possible 10 dB
gain in the transmitted signal for achieving long loop ranges. Therefore, S1 in combination w:ith resistor 40 allow buffer line amplifier 19 to provide an analog in-terface for zero to short loop lengths and for long loop lengths.
The present invention as described above is a unique circuit device which can be electrically altered to oper-ate within short and long trAn! ission line loop lengths.By using a Buffer Line Amplifier with unity gain, an in-terface can ~e designed between the DNIC and the buffer to satisfy the one-clock sampling problem with no effect on the various cable conditions. Further, a matching network can be designed that is solely dependent on the conditions of the transmission line, such as length and cable type. ~his allows more freedom in designing a transformer and matching network that is more consistent in manufacturing and which maintains a high degree of Z5 circuit per~ormance. Finally, the gain of the Buffer Line Amplifier can be easily altered by the switching in or out of a single resistor. The addition of a gain re~
sistor of a specific value allows for a higher transmit level, and therefore, operation of the buffer line ampli-fier in long transmission line loop ranges. The removalof the gain resistor allows the same Buffer Line Ampli-fier to operate effectively in loop lengths of zero dis-tance to a nl in~l short loop range with no errors.
It will be obvious to those skilled in the art that numerous modifications to the present invention can be made without departing from the scope of the invention as dafined by the appended claims. In this context, it should be recognized that the essence of the invention resides in a new and improved bi-directional buffer line , ~
, , :.
Z~ S4 amplifier that performs ef~iciently in various transmis-sion line loop lengths.
,; . . . . . - .
,. .. ..
Claims (5)
1. A circuit arrangement for interfacing an analog transmission line to a Digital Interface Network Circuit (DNIC), said DNIC including a transmit signal output and a receive signal input, said circuit arrangement comprising:
magnetic coupling means connecting said transmission line to said circuit arrangement;
matching network means connected to said magnetic coupling means for matching the circuit arrangement to the impedance of said transmission line;
a transmit amplifier network including an input connected to said DNIC transmit signal output and arranged to receive transmit signals from said DNIC, and an output connected to said matching network via selectable gain amplifying means, said selectable gain amplifying means arranged to apply said transmit signals to said matching network in a first gain level or alternatively a second gain level;
in said first gain level said gain amplifying means is removed from said transmit amplifier network and said transmit amplifier network operates as a unity gain amplifier, and said matching network via said magnetic coupling means applies said transmit signals to said transmission line having a transmission line loop length from zero to a nominal distance; and in said second gain level said gain amplifying means is connected in series between said transmit amplifier network and said matching network amplifying said transmit signals, and said matching network via said magnetic coupling means applies said amplified transmit signals to said transmission line having a transmission line loop length of a substantially greater distance than said nominal distance.
_8_
magnetic coupling means connecting said transmission line to said circuit arrangement;
matching network means connected to said magnetic coupling means for matching the circuit arrangement to the impedance of said transmission line;
a transmit amplifier network including an input connected to said DNIC transmit signal output and arranged to receive transmit signals from said DNIC, and an output connected to said matching network via selectable gain amplifying means, said selectable gain amplifying means arranged to apply said transmit signals to said matching network in a first gain level or alternatively a second gain level;
in said first gain level said gain amplifying means is removed from said transmit amplifier network and said transmit amplifier network operates as a unity gain amplifier, and said matching network via said magnetic coupling means applies said transmit signals to said transmission line having a transmission line loop length from zero to a nominal distance; and in said second gain level said gain amplifying means is connected in series between said transmit amplifier network and said matching network amplifying said transmit signals, and said matching network via said magnetic coupling means applies said amplified transmit signals to said transmission line having a transmission line loop length of a substantially greater distance than said nominal distance.
_8_
2. The circuit arrangement as claimed in claim 1, wherein said circuit arrangement further includes a receive amplifier network, said receive amplifier network having a first input connected to said transmit amplifier network output and a second input connected to said matching network, said receive amplifier network first input arranged to receive said transmit signals and said receive amplifier network second input arranged to receive signals transmitted on said transmission line, whereby, said receive amplifier network cancels said transmit signals from said receive signals and connects said receive signals to said receive signal input of said DNIC.
3. The circuit arrangement as claimed in claim 2, wherein said selectable gain amplifying means includes a resistor connected between said transmit amplifying network output and said matching network means and a shorting device connected across said resistor and selectable into a first or alternatively a second position, whereby, in said first position said shorting device is enabled, electrically removing said resistor from said circuit arrangement, allowing said transmit amplifier means to operate in said first gain level.
4. The circuit arrangement as claimed in claim 3, wherein, in said second position said shorting device is disabled, electrically inserting said resistor between said transmit amplifier network and said matching network, allowing said transmit amplifier means to operate in said second gain level.
5. Each and every novel feature or novel combination of features herein disclosed.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/627,274 US5119365A (en) | 1990-12-14 | 1990-12-14 | Bi-directional buffer line amplifier |
| US627,274 | 1990-12-14 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2056254A1 CA2056254A1 (en) | 1992-06-15 |
| CA2056254C true CA2056254C (en) | 1998-09-15 |
Family
ID=24513985
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002056254A Expired - Fee Related CA2056254C (en) | 1990-12-14 | 1991-11-26 | Bi-directional buffer line amplifier |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US5119365A (en) |
| CA (1) | CA2056254C (en) |
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| US5272722A (en) * | 1991-04-26 | 1993-12-21 | The United States Of America As Represented By The Secretary Of The Navy | Low level serial transceiver |
| US5473666A (en) * | 1992-09-11 | 1995-12-05 | Reliance Comm/Tec Corporation | Method and apparatus for digitally controlling gain in a talking path |
| US5835535A (en) * | 1992-11-23 | 1998-11-10 | Motorola, Inc. | Data bus interface apparatus which measures voltage potential on the uplink line of the data bus and removes an AC component |
| US5912924A (en) * | 1996-08-15 | 1999-06-15 | Seeq Technology, Inc. | Bidirectional channels using common pins for transmit and receive paths |
| US7312739B1 (en) | 2000-05-23 | 2007-12-25 | Marvell International Ltd. | Communication driver |
| US7433665B1 (en) | 2000-07-31 | 2008-10-07 | Marvell International Ltd. | Apparatus and method for converting single-ended signals to a differential signal, and transceiver employing same |
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| US7606547B1 (en) | 2000-07-31 | 2009-10-20 | Marvell International Ltd. | Active resistance summer for a transformer hybrid |
| US6590433B2 (en) * | 2000-12-08 | 2003-07-08 | Agere Systems, Inc. | Reduced power consumption bi-directional buffer |
| JP4335014B2 (en) | 2002-03-15 | 2009-09-30 | ジェノム コーポレイション | System and method for compensating for line loss via a digital visual interface (DVI) link |
| US8154995B2 (en) * | 2005-01-26 | 2012-04-10 | At&T Intellectual Property I, L.P. | System and method of managing digital data transmission |
| US7312662B1 (en) | 2005-08-09 | 2007-12-25 | Marvell International Ltd. | Cascode gain boosting system and method for a transmitter |
| US7577892B1 (en) | 2005-08-25 | 2009-08-18 | Marvell International Ltd | High speed iterative decoder |
| US8054876B2 (en) * | 2005-12-13 | 2011-11-08 | Infinera Corporation | Active delay line |
| US8565105B2 (en) * | 2008-09-29 | 2013-10-22 | Broadcom Corporation | Method and system for ethernet switching, conversion, and PHY optimization based on link length in audio/video systems |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3883864A (en) * | 1974-02-22 | 1975-05-13 | Gte Automatic Electric Lab Inc | Analog-to-digital and digital-to-analog converter apparatus |
| CA1168707A (en) * | 1980-04-22 | 1984-06-05 | Norscan Instruments Ltd. | Apparatus to monitor electrical cables, including splice joints and the like for the ingress of moisture |
| ATE70681T1 (en) * | 1985-05-17 | 1992-01-15 | Alcatel Nv | TELECOMMUNICATION LINE CIRCUIT. |
| US4980908A (en) * | 1989-05-30 | 1990-12-25 | Voicetek Corporation | Voice-switched gain control for voice communication equipment connected to telephone lines |
-
1990
- 1990-12-14 US US07/627,274 patent/US5119365A/en not_active Expired - Fee Related
-
1991
- 1991-11-26 CA CA002056254A patent/CA2056254C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CA2056254A1 (en) | 1992-06-15 |
| US5119365A (en) | 1992-06-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |