CA2057666A1 - Modular implementation for a parallelized key equation solver for linear algebraic codes - Google Patents

Abstract

Abstract of the Disclosure Apparatus and method for implementing a parallelized algorithm for solving the key equation for the decoding of a linear algebraic code. A computational loop has one branching condition that branches into two straight-line loops. One of these executes three multiplication operations and the other executes five multiplication operations, 2t iterations of these two loops being required to decode t symbols in error. These loops are coupled such that during each successive 2t iterations, four multiplication operations are executed simultaneously in pairs, the fifth multiplication operation in said other loop being paired with a multiplication operation in the next iteration of said one loop. During one of the paired multiplication operations an inverse table look up operation is executed, and during another of the multiplication operations an addition operation is executed.

Description

SA9-91-003 20~76~6 MODULAR IMPLEMENTATION FOR A PARALLELIZED KEY EQUATION
SOLVER FOR LINEAR ALGEBRAIC CODES

This invention relates to an apparatus and method for decoding linear algebraic codes, and more particularly to an apparatus and parallel computation method that solves the key equation for decoding of Reed-Solomon (RS) codes by use of an algorithm that improves latency without requiring additional hardware over that employed in prior art apparatus for solving said equation.

Backqround of the Invention The following prior art references are considered by applicants to be the most pertinent to the present invention:

[A] E.R. Berlekamp, "Algebraic Coding Theory,"
McGraw Hill, pp. 178-199, 1968;
[B] J.L. Massey, "Shift-Register Synthesis and BCH
Decoding," IEEE Trans. on IT, IT-15, January 1969;
[C] K.Y. Liu, "Architecture for VLSI Design of Reed-Solomon Decoders," IEEE Trans. on Computers, Feb.
1984, pp. 178-189.
[D] D.L. Whiti.g, "Bit-Serial Reed-Solomon Decoders in VLSI," PhD thesi , California Institute of Technology, 1984; and [E] R.T. Chien, "Cyclic Decoding Procedures for BCH
Codes," IEEE Trans. on IT-10, pp.357-363, October 1964.
At p. 184 in reference [A], Berlekamp discloses an algorithm for solving the "key equation" which is the main step in decoding RS codes. As hereafter used in the ~pecification and claims, the term "key equation" is defined as the equation which must be solved to determine the coefficients for the error locator and error evaluation polynomials for a given set of error syndromes. Berlekamp s algorithm, for the simultaneous computation of both error locator and evaluator polynomial coefficients, consists of a computational loop with one conditional branching condition that divides the SA9-91-003 2 2a~76~6 loop into two straight-line loops, hereafter referred to as the A and B loops, respectively. The decoding of t symbols in error requires 2t iterations or traversals of this loop. The A-loop executes three multiplications and the B-loop executes five multiplications.
In reference [b], Massey proposed splitting Berlekamp's algorithm by first computing the error location coefficients. These are then used in the computation of the error evaluation polynomials.
Reference [C] describes an implementation of the "Berlekamp-Massey" algorithm disclosed in reference [B].
However, this implementation requires 4t+1 multipliers, 6t registers +t registers for the remaining syndromes and a total of 6t multiplication delays for the computation of error locator and error evaluator polynomials.
Furthermore, this reference does not disclose or suggest implementation using bit slice circuits.
In reference [D] at pp. 65 and 104, Whiting noted some arbitrariness in the statement of the conditional branching of Berlekamp's algorithm. Whiting also indicated that a parallel implementation of Berlekamp's algorithm would involve storing twice as many polynomial coefficients and either an additional multiplier or time-multiplexing a single multiplier as compared with the hardware resources required by the parallelization of the algorithm as modified in reference [B].

Summary of the Invention According to the invention, the key equation for the decoding operation is parallelized without requiring additional hardware over that required in reference [B]
by effectively removing the arbitrariness in the branching condition.
Applicants' algorithm removes the arbitrariness of the branching condition in a way that the loop executing five multiplications cannot directly repeat This loop is coupled with the following loop executing only three multiplications such that now two iterations require eight multiplications resulting in an average of four multiplications per loop iteration. This coupled loop ~A9-91-003 3 20~7~

structure is illustrated in hardware, modular in form, to facilitate implementation in VLSI (very large scale integration).

Brief Description of the Drawings Fig. 1 is a block diagram of an apparatus embodying the invention for decoding a linear algebraic code;
Fig. 2 is a flow chart showing the sequence of steps followed to implement applicants algorithm for solving the key equation for decoding linear algebraic codes;
Figs. 3A and 3B constitute a side-by-side condensed comparison of Berlekamp's prior art key equation solving algorithm and of applicants modified algorithm;
Fig. 4 is a diagram of a two "level" circular shift register used in the implementation of applicants parallelized algorithm;
Figs. 5A and 5B describe the multiplication dependence diagrams for both A and B loops that are executed by the key equation solver algorithm;
Fig, 6 is a schedule of a parallelized algorithm according to the invention, depicting the coupling of the A and B loops, during two successive iterations, each comprising an odd and even cycle;
Figs. 7A and 7B depict a block diagram of a latch and a tabulation of its states, respectively;
Figs. 8A, 8B and 8C depict a block diagram of a multiplexor, a circuit diagram thereof and a tabulation of its states, respectively;
Fig. 9 is a schematic diagram of a bit slice circuit of applicants' correction unit;
Fig. 10 is a schematic diagram of a modular byte slice circuit of the correction unit;
Fig. 11 is a schematic diagram of a clock generation circuit;
Fig. 12 is a schematic diagram of a control signal circuit;
Fig. 13 is a schematic diagram of an inversion circuit;

SA9-91-003 4 2~576~6 Fig. 14 is a schematic diagram of a circuit depicting the result of the inversion by the circuit of Fig. 13;
Fig. 15 is a schematic diagram of a termination circuit, for terminating the computation after 2t iterations;
Figs. 16A and 16B are, respectively, a tabulation showing the conditions under which each of the clocks is active, and a matrix showing the relationship between the shift registers containing the different variables and the different operations performed thereon;
Figs. 17A and 17B are schematic diagrams of initialization bit slice circuits for the first input data bit to a syndrome latch and for the seven remaining bits, respectively;
Fig. 18 is a schematic diagram of a terminal column bit slice circuit;
Fig. 19 is a schematic diagram of an initial byte slice of the error correction unit;
Fig. 20 is a schematic diagram of a terminal byte slice of the error correction unit; and Fig. 21 is a schematic diagram of a eomplete eorrection unit for t=8.

Introduction Assume a Galois field of 256 elements, GF (28), whose elements correspond to 8-bit bytes. Thus the algorithm according to the invention and its hardware implementation operate on bytes using modulo-2 Galois field arithmetic; and the input data are 2t bytes, assumed, for illustration, to be the syndromes for a RS code, where t is the number of errors to be corrected.
As hereinafter used in the specification and claims, the term "bytes" is used for ease of understanding and is to be considered merely as illustrative, as the invention may be implemented with symbols pertaining to other fields.
According to the invention, the key equation solving circuitry is modified to provide a parallelized algorithm and a modular hardware implementation for solving the key SA9-91-003 5 2 ~ ~ 7 ~ ~ ~

equation for the decoding of a linear algebraic code, such as the RS code.
Assume that, as above, t = the number of errors to be corrected, and that v, u, p, q and S are single variable polynomials. The key equation is the congruence:
v(z) S(z) - q(z) mod(z2t) whose solution, provided it exists, is the rational function:
r(z) = q(Z) .

A given set of syndromes ~Si~2i=0l for a linear algebraic code may be viewed as the coefficients of a polynomial S(z). The roots of the denominator polynomial v(z) in the key equation solution are the error locations and the residues of r(z) at these roots are the error values.

DescriPtion of Preferred Embodiment As illustrated in Fig. 1, the apparatus embodying the invention comprises a decoder 10 for decoding a linear algebraic code, such as a Reed-Solomon (RS) code.
A noisy codeword c(x), including any error pattern e(x), is supplied via a line 11 to a syndrome generator 12 and a buffer 13. The syndrome output S(x) from generator 12 passes to a key equation solving circuit 14.
According to the invention, circuit 14 outputs an srror locator polynomial v(x) and an error evaluation polynomial q(x) for the particular set S(x) of error syndromes to a "Chien" searching circuit 15 and an error value computation circuit 16, respectively. Circuit 15 preferably is of the type disclosed in Reference [E].
The output of circuits 15 and 16 are gated at 17 to provide an output ê(x) representing the estimated error pattern. This output ê(x) is summed at 18 with the output from buffer 13 (which corresponds to the codeword plus error pattern input to the buffer from line 11) to provide in line 19 a corrected codeword c(x).
Thus, given S (the syndrome polynomial) and t (the number of errors to be corrected), the e~uation solving SA9-91-003 6 2 ~ ~ 7 ~

circuitry 14 derives v and q (the error locator and error evaluation polynomials, respectively).
In Reference [D] Whiting considered the hardware and latency that would be involved if the serial key equation solver algorithms of References [Al and [B] were parallelized. Table 1 is a performance comparison of Whiting's versions 1 and 2 for parallelizing Berlekamp's algorithm described in Reference lA] and the so-called Berlekamp-Massey (BM) algorithm described in Reference [B] with applicants' algorithm.
Table 1 Multipliers Storaqe LatencY
B Version 13t 6t 4t B Version 22t 6t 6t BM 2t 6t 6t Applicants'2t 6t 4t ApPlicants' Alaorithm In Detail Applicant~' algorithm receives as input a data vector of 2t field elements [S0, ..., S2t_l]
a~ output IvO. ..., vt 1]~ and [ql~ ~ gt-l]~
are the coefficients of the denominator and numerator of a rational approximant to S(z) which generally may be viewed as a power series whose coefficients are the field elements {Si}. For an input vector of 2t field elements, the denominator degree of the rational approximant produced cannot exceed t. The degree of the numerator polynomial is strictly smaller than that of the denominator polynomial. The algorithm terminates after 2t iterations.
Fig. 2 is a flow chart of applicants' algorithm.
The computation is divided into five steps as follows:

Step 1 (Initialization).

V <---- [ 1]
u <-- [O]
q <---- [O]

-'` 2~76~

p < - [ 1]
r ~-- 0 t <-- t R ~-- 0 <---- --1 In Step 1 the vector variables v, u, p and q are initialized. Each of these vectors has t components.
The convention used above assigns the 'lall zeros" vector to u-and q, whereas the least significant coefficient of both v and p are assigned the value 1 and the other coefficients are 0. The scalar variable i used to count the number of iterations is initially assigned the value -1. The scalar variable r counts the number of times Step 2 of the algorithm is performed, whereas the scalar variable R counts the difference in the number of times Step 2 and Step 4 are performed. The scalar variable t used to decide on termination of the algorithm is initiated as t, the number of errors which are correctable.

Step 2 (Linear Dependence Test) <-- i+l R <-- R+l u <---- [ Ou]
p <-- [ Op]

e <-- Si + ~ Si_j Vj In Step 2, i and R are incremented by 1, and u and p are shifted to the right by one position (indicated in the above convention as substituting the contents of the vector by a vector to which a 0 has been appended at the right).
The main computation performed in Step 2 is the convolution of the content of the S vector with the content of the v vector resulting in the value e, which is generally known as the "discrepancy" (see Reference [A]). In effect this computation checks whether the SA9-91-003 8 2~7~

syndromes as weighted by the current value of v are linearly independent.
If e=O, then the syndromes as so weighted is linearly dependent. In such case, Step 2 is repeated as shown in Fig. 2. The algorithm continues to Step 3, provided e~O.
:
Step 3 (Update) r <-- r + R
t' <-- t' - R
T <-- lv v <-- v ~ eu u <-- T
T' <-- eq q <-- q - ep p <-- T' In Step 3, the scalar variables r and t' are stepped up and down respectively by R, which is the number of times Step 2 was performed. The content of v is updated by subtracting from it~ current value the previous value of u multiplied by the non-zero discrepancy e which was computed in Step 2.
The current (not updated) value of v is ~imultaneously used to update the value of u through the intermediary variable T that temporarily stores the current value of v divided by the non-zero discrepancy e.
Thus, in Step 3, both v and u are updated using their previous values and the discrepancy e.
In a completely analogous manner q and p are updated using an intermediary variable T'. The updating Step 3 i~ not repeated and unconditionally leads into Step 4.

Step 4 (Polynomial Iteration) i <-- i+l u <---- [ Ou]
p <-- [ Op]

f ~~~ Si + ~ Si_j V
j=l SA9-91-003 9 2~5 ~ 6~

v <-- v - fu ~ <-- q - fp R <-- R - 1 In Step 4, the iteration count variable i is incremented and at the same time the value of R is decreased. As long as R is greater than 0, step 4 will be repeated until R is O; whereupon the program control statement will take the computation back to Step 2, as shown in Fig. 2.
Upon initiation of Step 2, the algorithm checks how many times Step 2 has been performed by compar ng the value of R with the threshold value t'. If R=t , the algorithm will proceed to Step 5 which is the "Exit Test."

Step 5 (Exit Test) i <-- i+l e <-- Si + ~ Si j V
j=l Once entered, Step 5 will produce either a "Not Correctable" exit or will produce the error locator and error evaluator polynomial coefficients; i.e., the vectors v and q, respectively.

Comparison of Berlekamp's and APPlicants' Alqorithms The differences between Berlekamp s algorithm and applicants' improved algorithm can be noted from the side-by-side condensed comparison in Figs. 3A and 3B. In Figs. 3A and 3B the computational layout of the applicants' algorithm has been collapsed into a form equivalent to Berlekamp's which is given in the simplified form disclosed in reference lD]. Applicants' algorithm differs from Berlekamp's in the following respects which are apparent from comparison of Figs. 3A
and 3B: ~1) in the initialization step; (2) in the "discrepancy" e-computation; and (3) in the loop branching condition.

- 2~7~

The e-computations in Berlekamps algorithm and in applicants' algorithm differ in that Berlekamp's variable summation is replaced in applicants algorithm by a fixed summation which is translated into a circular shift register 20 (Fig. 4) for processing the input vector [SO, Sl..., S2t 1] Shift register 20 has two "levels," an upper level Sl and a lower level S2. Shift register 20 is initially loaded in parallel, in the locations denoted in Fig. 4. This feature is essential in order to implement a parallelized algorithm for solving the key equation.
According to an important feature of the invention, and unlike Berlekamp's algorithm, Step 3 of applicants algorithm cannot repeat.
To demonstrate this difference, the loops of Berlekamp's and applicants' algorithms have been divided into two kinds, depending upon the types of conditional branching within the loop body. In Table 2, an "If"
branch, is referred to as an A-loop and an "Else" branch ls referred to as a B-loop.

Table 2 "IF" (TYPE A LOOP) r~
e <-- Si + ~ Si j V
j=l v ~-- v - e[Ou]
q <__ q - e[ opl "ELSE" (TYPE B LOOP) e <-- Si + ~ Si j V
j=l v ~-- v - e[Ou]
q <-- q - e[Op]
u <---- --v P <-- --q' As will be noted in Fig. 3B, in applicants loop structure the conditional branching control condition has been changed to "If e=O or 2r2i+1 then." This change SA9-91-003 11 2 ~ 5 7 ~ 6 6 prevents the "Else" condition from recurring consecutively and thus prevents a B-B loop (Table 2) from occurring. In other words, as will be noted from Fig. 2, Step 3 cannot repeat.
The optimum speed-up achievable by paralleli~ation for Berlekamp s and applicants algorithm is derived by considering an operational dependence graph. In a hardware implementation, the only time consuming arithmetical operations considered are multiplications, which are represented in the form of an edge in the dependence graph. Figs. 5A and 5B show the multiplication dependence graphs for a type A-loop and for a type B-loop, respectively. The nodes connected by an edge are labelled by the variables that are being multiplied.
At the beginning of the algorithm the variables have their initial values. As illustrated in Figs. 5A and 5B, the variable at the "tail" node is a factor of the variable at the "head" node. On this (multiplication) dependence graph, all nodes have two entries representing two factors except for the node e, where one factor will alway~ be a syndromes vector. All full-line edges denote dependencies within the same iteration, while dashed edges represent dependencies between the current and the immediately preceding iteration. The dotted edges denote dependencies between the current and any preceding iteration.
As all edges have a unit weight representing a multiplication time, the critical cycle is established by determining Maximum(cycle length/number of dashed edges in the cycle) = ~. For both algorithms, the critical cycle is e --> v --> e(next iteration) with ~ = 2.
Consequently, a lower bound of the latency time is two multiplication times/iteration.
The number of multipliers necessary for achieving this minimal time must now be determined. As the latency time is required to be optimal, the worst case of the iterations must be considered. The syndrome inputs are therefore assumed to have values that do not permit any multiplier savings in early iterations. The node 2~7 ~

variables from the dependency graph are considered to be scalars. Each vector contains t nontrivial symbols and the number of multipliers in the vector case is the t-fold of the number of multipliers in the scalar case.
A type B-loop requires five multiplications while three multiplications are sufficient for a type A-loop.
In Berlekamp's algorithm, a sequence of only B-loops will occur if e~0 during the whole algorithm. Therefore, the minimal number of multipliers necessary for achieving a latency time of two multiplication cycles/iteration is 3 for Berlekamp's algorithm.
According to the invention, applicants' have combined a type B-loop with the following type A-loop thus resulting in a requirement of eight multiplications for two iterations. It is sufficient to consider the following two sequences A and B-A and all their combinations A-A, A-B-A, B-A-A and B-A-B-A. With applicants' algorithm, and as previously stated, a sequence B-B is not possible (see Fig. 2).
From Figs. 5A and 5B, it is obvious that all the combinations mentioned result in a valid schedule. It ~hould be noted that if the last iteration is of type B, the updating of u and p becomes redundant. Consequently, the applicants' algorithm can be executed in 4t+1 multiplication cycles requiring 2t multipliers. In fact, it is pos~ible to reduce the number of multiplication cycles by two if the initial conditions of the data vectors are exploited.

Hardware ImPlementation To achieve a simple and homogenous hardware implementation, a common schedule is generated for type B-A and type A or A-A loops. This schedule is given in Fig. 6. Using this schedule, a modular design has been derived for the entire correction unit of applicants' key equation solving circuitry 14. The correction unit is depicted in Fig. 21 and is built up, using elementary logic units and modules now to be described.
Fig. 7A schematically denotes a latch 25 and Fig. 7B
the latch outputs corresponding to various input -- 2~7~6~

conditions. Fig. 8A schematically denotes a multiplexor circuit 2fi, shown more completely in Fig. 8B to pravide the outputs tabulated in Fig. 8C.
According to a feature of the invention, and as illustrated in Fig. 9, a bit-slice circuit 30 of the correction unit denoted as an A-circuit is provided.
Circuit 30 comprises six one-bit latches 25a-f designated S1, S2, q, p, u and v, each storing one bit of the named variables. Circuit 30 also comprises nine multiplexor circuits 26a-i and one exclusive OR (XOR) gate 27.
Multiplexor circuits 26a and 26b are used for loading and shifting syndrome inputs. Multiplexors 26d, 26e, 26g are used for multiplexing the factors that enter into multipliers M1 and M2 (Fig. 10). Multiplexor 26i multiplexes the inputs to XOR gate 27. Multiplexor 26c sWitches the p latch 25d to serve as an intermediate storage for the previous q value in latch 25c.
Multiplexors 26f and 26h modify or shift the data from the u and p latches 25d and 25e, respectively. XOR
gate 27 is used to implement the summation v+e-u or q+e~p.
Circuit 30 constitutes a completely operational one-bit unit implementation for the key eguation solver algorithm.
As shown in Fig. 10, eight bit-slice A-circuits 30 labelled AO-A7 plus the two multipliers M1 and M2 constitute a byte-slice B-circuit 40. Circuit 40 can be divided into these eight bit slice A-circuits 30 because the only interaction between the various bit positions occurs during multiplication operations. An eight-input OR gate 41 and a succeeding latch 25g are involved in determining the error location degree and the proper positioning of error locator vector v for the iterative Chien searcher circuit 15 (Fig. 1).

Clock and Control Circuitry The complete control and clock circuitry is depicted in Figs. 11-16.
The clock generator circuit 49 shown in Fig. 11 generates four clock signals CLK1 to CLK4 from the main SA9-91-003 14 2 ~ 5 ~ 6 ~ ~

CLOCK. The input signals which control the clock generator circult are INPUT, END and CU. The INPUT
signal is activated only before the start of the computation. While INPUT=l, only the contents of the syndrome latches 25a, 25b can be modified. The END
signal disables all clocks and therefore freezes the content of all latches, except for latch 51 (whose output is the ODD signal) after the completion of the computation. INPUT and END are both O during the actual computation.
The main enabling signal that controls all four clocking signals is ODD. It is an alternating signal that allows distinguishing between the two different operational cycles, odd and even, that as shown in Fig. 6, constitute one iteration.
The ODD signal is generated as the output of latch 51 which is enabled by the main system CLOCK. The input to latch 51 is obtained from the inverted value of INPUT and the ODD output through AND gate 50. During an odd operational cycle (ODD=l), the contents of the e, q, Sl and S2 latches are modified while CLK2=1. The CLK2 ~ignal i~ obtained as the output of AND gate 54. The enabling clock signal CLKl, obtained as the output of OR
gate 53, is identical to CLK2 during the computation but is also enabled by INPUT for loading the contents of the Sl and S2 syndrome latches 25a, 25b, respectively. INPUT
al o guarantees that each computation starts with an odd operational cycle, implemented by AND gate 50.
During an even operational cycle (ODD=O), the contents of the u and v latches 25e, 25f are modified while CLK4=1. CLK4 is obtained as the output of AND
gate 57. Since the p latches 25d are used for both the storage of the coefficients of the p polynomial, during an odd cycle, as well as for the temporary storage of the last values of the coefficients of the q polynomial during a switch from Step 2 to Step 4 (which occurs during an even cycle), a separate enabling clock CLK3 is generated. CLK3 is generated as the output of OR gate 55 from either a CLK4 or a CLK2 enabled by the control signal CU.

SA9-91-003 15 2 a ~ ~ ~ 6 6 The control signal circuitry 59 is shown in Fig. 12.
The output VALID of latch 61 controls whether a counter 65 for the scalar variable R is upcounting; i.e., whether the algorithm executes Step 2 (VALID=l) or is downcounting (Step 4, VALID=O). This latch 61 is enabled by CLK2 and its input is generated as the output of OR
gate 64. This gate is activated either when e=O and VALID=1 (i.e., while the algorithm executes Step 2) or when R=O and VALID=O. VALID switches from 1 to O if e~O;
and it switches back from O to 1 if R=O. It can only be changed during an odd operation cycle which occurs when CLK2=1.
The control signal CU=l indicates that the latest e value does not equal O but that the status of the VALID
latch is still l; i.e., that the algorithm is executing Step 3 (B-loop). While CU=l and until VALID switches back to 0, no B~loop can be started. This effectively implements the branching condition which prohibits the occurrence of consecutive B-B loops and hence the repetition of Step 3.
The CU signal, generated as the output of AND
gate 60, is active for one odd and the succeeding even operational cycle and is used for controlling the modification of the content of the u latches 25e~ If CU(=1) is active at the end of a computation (Step 3) or VALID=O (Step 4), the errors are NOT CORRECTABLE which is indicated by WRONG=1, a signal generated as the output of OR gate 67.
The output of latch 66 is equal to the signal CU, delayed by two operational cycles. The signal CPl is active during an even operational cycle while the output of latch 66 is active. It controls whether the p latches 25d are used for storing the coefficients of the p polynomial (CP1=0) or for temporary storage of the last coefficients of the q polynomial (CP1=1). CP1 is generated as the output of AND gate 62. Signal CP2 is active only during the odd operational cycle while CU is active. CP2 is generated as the output of AND gate 63.
CP2 controls the modification of the p latches 25d and of one of the factors of the first multiplier MlFl 20~7~

(Fig. 10); namely, v, if CP2=0 or p while it stores the coefficients of the last q polynomial if CP2=1.
Fig. 13 depicts a circuit 70 that computes the inverse of the discrepancy value e. This circuit comprises multiplexors 71 and a ~OM lookup inversion table 72. Multiplexors 71 allow sharing of table 72.
The output dRES of ROM inversion table 72 is stored in an 8-bit register 75 comprising eight latches, li~e 25, shown in Fig. 14. Register 75 is controlled through eight multiplexors 76 by CP2. CP2 determines whether the value dRES is used directly for the modification of the u latch 25e, or is used later for the modification of p latch 25d.
As illustrated in Fig. 15, a termination circuit 80 comprises a counter 81 that counts the CLK2 signals and stops the computation after 2t+1 iterations.
Fig. 16A tabulates the Boolean equations for the four clock signals CLKl-CLK4 generated by circuit 49, previously described and shown in Fig. 11. Fig. 16B is a matrix whose columns are the distinct latch labels, S, u, v, u, q, and p and whose rows correspond to the distinct arithmetic operations performed on them during the algorithm execution. The matrix entries indicate the control or clock signals which are activated during specific operations performed on a specific register.
Figs. 16A and 16B summarize the control and clocking operations previously described in detail.
It should be noted that for implementing applicants invention, the bit-slice A-circuit 30 described in Fig. 9 and the byte-slice B-circuit 40 described in Fig. 10 are deemed sufficient. However, for the sake of completeness and to reduce hardware complexity, Figs. 17A/17B and Fig. 18 illustrate how the bit-slice A-circuit can be simplified for the initial and final column, respectively. Note that there is one circuit like in Fig. 17A and seven like in Fig. 17B for an 8-bit byte.
Figs. 19 and 20 describe the initial BO and terminal Bt byte slice B-circuits respectively. These hardware simplifications can be achieved because in the initial step, the computation is trivial and does not require any SA9-91-003 17 2~7~6~

multiplications and in the last step the algorithm does not require all the operations.
Finally, Fig. 21 schematically shows a correction unit 84 for t=8 error corrections. As earlier noted, the correction unit 84 in combination with the clock generation circuitry 49 and control signal circuitry consists of an initial byte slice B0-circuit, seven regular B-circuits and a terminal B8-circuit. An e-register 85 and a (t+l)-input adder 86, are part of this unit.
While the invention has been shown and described with respect to a preferred embodiment thereof, it will be understood by those skilled in the art that changes in form and detail may be made in this embodiment without departing from the scope and teaching of the invention.
Accordingly, the apparatus and method herein disclosed are to be considered merely as illustrative, and the invention is to be limited only as specified in the claims.

Claims (11)

1. Apparatus for implementing a parallelized algorithm for solving the key equation for the decoding of a linear algebraic code, said apparatus comprising:
circuit means implementing two iteration loops, one executing three multiplication operations and the other loop executing five multiplication operations every two iterations;
means for coupling said loops, such that the coupled loops execute four multiplication operations per iteration; and means for scheduling selectively each loop to execute its multiplication operations in parallel with predesignated multiplication operations of the other loop or of the same loop.

2. The apparatus of claim 1, including a bit slice circuit comprising:
a plurality of latches, each for storing one bit of each of a plurality of vector variables whose values are symbols in a preselected field and are used in said algorithm, each latch storing a bit at the same relative position within the symbol; and a plurality of switches for multiplexing a plurality of operations on said variables as necessary to implement the algorithm.

3. The apparatus of claim 1, including a bit slice circuit comprising:
a plurality of latches, each for storing one bit of each of a plurality of vector variables whose values are bytes and are used in said algorithm, each latch storing a bit at the same relative position within the byte;
syndrome generator means for generating input bytes to the algorithm;
means for generating clock signals;

means responsive to the input bytes and clock signals for generating control signals; and a plurality of switches, each receiving one bit from the input bytes and clock and control signals for executing the algorithm.

4. The apparatus of claim 1, including:
a symbol slice circuit comprising n bit-slice circuits, where n is the number of digits in a symbol from a preselected field, each bit slice circuit comprising a plurality of latches, each for storing one bit of each of a plurality of vector variables whose values are symbols in a preselected field and are used in said algorithm, each latch storing a bit at the same relative position within the symbol; and a plurality of switches for multiplexing a plurality of operations on said variables as necessary to implement the algorithm.

5. The apparatus of claim 4, wherein said symbol slice circuit includes a pair of multipliers for multiplying the symbols in the preselected field.

6. Apparatus for implementing a parallelized algorithm for solving the key equation for the decoding of a linear algebraic code, said apparatus comprising:
means including a computational loop with one branching condition that branches into two straight-line loops, one of which executes three multiplication operations and the other of which executes five multiplication operations, 2t iterations of these two loops being required to decode t symbols in error; and means for coupling said loops, such that during each successive 2t iterations, four multiplication operations are executed simultaneously in pairs, the fifth multiplication operation in said other loop being paired with a multiplication operation in the next iteration of said one loop.

7. The apparatus of claim 6, wherein said coupling means includes means operative during one of said paired multiplication operations to execute an inverse table look up operation, and operative during another of said multiplication operations to execute an addition operation.

8. The apparatus of claim 6, wherein said coupling means is modular, and there are t+l modules.

9. A method of implementing a parallelized algorithm for solving the key equation for the decoding of a linear algebraic code, said method comprising the steps of:
providing two iteration loops, one executing three multiplication operations and the other loop executing five multiplication operations every two iterations;
coupling said loops, such that the coupled loops execute four multiplication operations per iteration; and scheduling selectively each loop to execute its multiplication operations in parallel with predesignated multiplication operations of the other loop or of the same loop.

10. A method of implementing a parallelized algorithm for solving the key equation for the decoding of a linear algebraic code, said method comprising the steps of:
providing a computational loop with one branching condition that branches into two straight-line loops, one executing three multiplication operations and the other executing five multiplication operations, 2t iterations of these two loops being required to decode t symbols in error; and coupling said loops, for, during each successive 2t iterations, executing four multiplication operations simultaneously in pairs, the fifth multiplication operation in said other loop being paired with a multiplication operation in the next iteration of said one loop.

11. The method of claim 10, including the step of:

executing an inverse table look up operation during one of said paired multiplication operations and executing an addition operation during another of said multiplication operations.