CA2059232A1 - Field effect transistor - Google Patents
Field effect transistorInfo
- Publication number
- CA2059232A1 CA2059232A1 CA002059232A CA2059232A CA2059232A1 CA 2059232 A1 CA2059232 A1 CA 2059232A1 CA 002059232 A CA002059232 A CA 002059232A CA 2059232 A CA2059232 A CA 2059232A CA 2059232 A1 CA2059232 A1 CA 2059232A1
- Authority
- CA
- Canada
- Prior art keywords
- semiconductor layer
- layer
- undoped
- field effect
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 230000005669 field effect Effects 0.000 title claims description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 213
- 239000012535 impurity Substances 0.000 claims abstract description 26
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 56
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 42
- 239000000758 substrate Substances 0.000 claims description 39
- 239000000463 material Substances 0.000 claims description 20
- 239000000203 mixture Substances 0.000 claims description 17
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 24
- 230000005533 two-dimensional electron gas Effects 0.000 description 20
- 238000000034 method Methods 0.000 description 18
- 230000007704 transition Effects 0.000 description 17
- 230000005684 electric field Effects 0.000 description 15
- 230000008569 process Effects 0.000 description 6
- 241001663154 Electron Species 0.000 description 5
- 230000008859 change Effects 0.000 description 5
- 230000005428 wave function Effects 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 239000002131 composite material Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000002674 ointment Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- NLZUEZXRPGMBCV-UHFFFAOYSA-N Butylhydroxytoluene Chemical compound CC1=CC(C(C)(C)C)=C(O)C(C(C)(C)C)=C1 NLZUEZXRPGMBCV-UHFFFAOYSA-N 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 230000005283 ground state Effects 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000009738 saturating Methods 0.000 description 1
- 241000894007 species Species 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
- H01L29/8128—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate with recessed gate
Abstract
Abstract of the Disclosure The invention provides a FET by forming a channel layer in layer including "n" type impurity at high concentration, which is sandwitched by a first semiconductor layer and a second semiconductor layer lightly doped with impurity. Therefore even when electrons in the channel layer obtain high energy, the electrons in this arrangement rush out essentially to the second semiconductor layer excelling in electron carrying characteristic, thus a travelling speed of the electrons in the channel layer is not lowered.
Furthermore the channel layer being formed in layer and allowed to include impurity at high concentration, the current drive capability can be improved.
Furthermore the channel layer being formed in layer and allowed to include impurity at high concentration, the current drive capability can be improved.
Description
2~ 9 ~r~
1 Title of the Invention FIELD EFFECT TRANSISTOR
BackRround_of the Invention (Field of the Invention) The present invention relates -to a structure of a field effect transistor (FET) necessitating a very high speed operation.
(Related Background Art) Conventionally, as a very high speed device o~
this kind, for example, a first HEMT (high electron-mobility transistor) is introduced as shown in Fig. 1.
An InP semiconductor substrate 1 is formed thereon with :
an undoped InP layer 2. The undoped InP layer 2 is formed thereon with an n-AlxInlxAs layer 3 on which donors are selectively added to AlxInlxAs. The n-AlxIn ~s layer 3 is ~ormed thereon with an n -InGaAs layer ~, a gate electrode 5 is formed in Schottky contact with the n-AlxInlxAs layer 3 e~posed at a recess formed at a center portion, and ohmic electrodes 6 and 7 are formed on the n+-InGaAs layer 4.
There is also a second HEMT having the same structure as the first HEMT but made of different composite materials. In the second HEMT, a GaAs semiconductor substrate is used instead of the InP
semiconductor substrate 1, and an undoped GaAs layer, an n-AlGaAs layer, and an n+-GaAs layer are laminated . , .~
~ 3..
1 respectively instea~ o~ the uncloped InP layer 2, the n-AlxInlxAs layer 3, and the n-InGaAs layer 4.
There is also a third HEMT with a struc-ture as indicated in Fig. 2. Namely, an InP semiconductor substrate 11 is formed thereon with an undoped AlInAs layer 12. On the undoped AlInAs layer 12 is further formed an undoped InyGa1yAs layer 13, and on this undoped InyGa1yAs layer 13 is formed an n-AlxInlxAs layer 14 in which donors are selectively added to AlxInlxAs.
Further on the n-AlxInlxAs layer 14 is formed an n+-InGaAs layer 15, and a gate electrode 16 is formed in Schott~y contact with the n-AlxInlxAs layer 14 exposed at a recess formed at a center portion, and ohmic electrodes 17 and 18 are formed on the n-InGaAs layer 1~ .
In addition, there is a four-th HEMT having the same structure as the third HEMT but with differen-t composite materials. In the fourth HEMT, a GaAs semiconductor substrate is used instead of an InP
semiconductor substrate 11, and an undoped GaAs layer, an undoped InyGa1yAs layer, and an n-AlxGalxAs layer are laminated respectively instead of -the undoped AlInAs layer 12, the undoped InyGa1yAs layer 13, and the ;~
n-AlxInlxAs layer 14. The donors are selectively added to this n-AlxGalxAs layer. Further an n-InGaAs layer is used instead of the n+-InGaAs layer 15.
However, as in the conventional first HEMT of the ~ ,3 1 prior art hereinbe~ore described, ~or a system using heterojunction of AlInAs/InP, electrons travel in an InP layer being a channel and such electrons often produce a real space transfer ~or making transition to the AlInAs layer disposed in the upper layer o-~ the InP
layer. This real space transfer may be explained as follows. An energy band indicated in Fig. 3 is ~ormed s at a heterojunction portion of the n-AlInAs layer 3 and the undoped InP layer 2, and the two-dimensional electron gas is accumulated at the oblique-lined portion of the drawing. However, if a high electric field is applied across a drain and a source and energy of the two-dimensional electron gas becomes higher, the electrons in the two-dimensional electron gas make transition to the n-AlInAs layer 3 as shown by the arrow mark in the drawing.
Generally, a high electric field is applied across a drain and a source during its operation, and as carrying characteristic of electrons is in~erior in the AlInAs layer than in the InP layer, when this real space transfer occurs the high-frequency characteris*ic of FET becomes degraded.
As in the second HEMT o~ the prior art ; hereinbefore described, for a system using the heterojunction o~ AlGaAs/GaAs, electrons travel in an GaAs layer which is to become a channel and such electrons sometimes produce a real space transfer for J ~ r~
I making transition to the AlGa~s layer disposed in the upper layer of the GaAs layer. For exampl.e, this real space transfer may be explained as follows. An energy band in Fig. 4 is formed at the heterojunction portion of the n-AlGaAs layer and the undoped Ga~s, and the two-dimensional electron gas is accumulated at the oblique lined portion of the drawing. However, i-~ a high electric ~ield is applied across a drain and a source and energy of the two-dimensional electron gas becomes higher, the elec-trons in -the two-dimensional electron gas are transferred to the n-AlGaAs layer as shown by arrow mark in the drawing.
Generally, a high electric field is applied across a drain and a source during its operation, and as carrying characteristic of electrons is inferior in the AlGaAs layer than in the GaAs layer, thus when this real space trans~er occurs it deteriorates the high-frequency characteristic of FET.
In addition, as in the third HEMT o~ -the prior art hereinbefore described, even in a system using the heterojunction of AlInAs/InGaAs, electrons tra~el in an InGaAs layer 13 which is to become a channel and such electrons sometimes produce real space transfer for making transition to the AlInAs layer 14 disposed in the upper layer of the InGaAs layer 13. This real space transition may be explained as below. An energy band in Fig. 5 is formed at the heterojunction portion , ,;
~: :: .. . . ..
~2~ S ~3.', ~ V ~
1 of the n-AlInAs layer 14 and the undoped InGaAs layer 13, and the two-dimensional electron gas is accumulated at oblique lined portion of the drawing. However, if a high electric field is applied across a drain and a source and energy o~ the two-dimensional electron gas becomes higher, the electrons in the two-dimensional electron gas are trans~erred to the n-AlInAs layer 14 as shown by arrow mark in the drawing.
Generally, a high electric ~ield is imposed across a drain and a source during its operation, and because carrying characteristic o~ electrons in the AlInAs layer is inferior to that o-~ the InGaAs layer, when this real space transfer occurs, it deteriorates the high-~requency characteristic o~ FET.
Also as in the ~ourth HEMT of the prior art hereinbefore described, even for a system using the heterojunction o~ AlGaAs/InGaAs, electrons travel in an InGaAs layer which will be a channel and such electrons sometimes produce real space transition ~or trans~erring to the AlGaAs layer disposed in -the upper layer o~ the InGaAs layer. This real space -transfer can be explained as ~ollows. An energy band in Fig. 6 is formed at the heterojunction portion o~ the n-AlGaAs layer and the undoped InGaAs layer, and the two-dimensional electron gas is accumulated at the oblique lined portion o~ the drawing. However, i~ a high electric ~ield is applied across a drain and a source ~ '7'' `
~2~
1 and energy o~ the two-dimensional electron gas becomes higher, the electrons in the two-dimensional electron gas make transition to the ~I-AlGaAs layer as shown by arrow mark in the drawing.
Generally, a high electric field is applied across a drain and a source during its operation, and because carrying characteristic of electrons in the AlInAs layer is inferior than in the InGaAs layer, when a real space trans~er occurs, it deteriorates the high-frequency characteristic of FET.
The first HEMT of the prior art abovementioned uses as a channel a two-dimensional electron gas layer 8 in Fig. 1 produced on a heterojunction inter-Eace between the undoped InP layer 2 and the n-AlInAs layer 3. This channel is formed within InP having a higher electron saturating speed than GaAs or InGaAs, thus producing a high-frequency device with upgraded performance. However, a limit has been placed against raising the electron gas density because maximum current density of such HEMT is determined by the upper limit of two-dimensional electron gas density and the channel layer being in -two-dimensional status. This results in an inability to produce a high-frequency device exhibiting a satisfactorily large output.
The fact as hereinbefore described applies also to the conventional cases of the second, third, and fourth HEMTs o~ the prior art. Electron gas density cannot be ~S~3~
1 satisfactorily increased by the conven-ti.onal second HEMT because the second HEMT uses as a channel a two-dimensional electron gas layer produced on a heterojunction interface between the undoped GaAs layer and the n-AlGaAs layer. Also, the electron gas density is not fully raised by the conventional third HEMT
because the third HEMT uses as its channel a two-dimensional electron gas layer 19 in Fig. 2 produced on a heterojunction inter~ace between the undoped InGaAs layer 13 and the n-AlInAs layer 14, as well as by the conventional fourth HEMT because the fourth HEMT uses as its channel a two-dimen~ional electron gas layer produced on a heterojunction inter+~ace between the undoped InGaAs layer and the n-AlGaAs layer. Therefore high-frequency devices with a sufficiently high outpu-t have not been produced by the respective conventional HEMTs described above.
For other very high speed devices there has been developed, for example, a DMT (Doped-channel hetero MIS-FET) with the structures as in Fig. 7. A GaAs semiconductor subs-trate 21 is formed -thereon an undoped GaAs layer 22, on which is formed an n+-GaAs layer 23 that will be a channel. Further, on the n+-GaAs layer 23 is +ormed an undoped AlGaAs layer 24 and an n-GaAs layer 2~. A gate electrode 26 is formed in Schottky contact with an undoped AlGaAs layer 24 exposed at a recess, and ohmic electrodes 27 and 28 are formed on -: ~ ; ' ! ' ' ~'.:
,.. . , . .. ~ . .
Z~ ~r,~
1 the n -GaAs layer 2~.
Because such DMT uses a high densi-ty and -thinly formed n-GaAs layer 23 as a channel layer, a suf+~iciently large output can be obtained. The AlGaAs layer 24 thereabove is undoped to improve its Schottky withstanding voltage. However in this DMT, because channel layer contains a large amount of impurities the travelling speed of electrons in t.he channel layer is lowered comparing with that of HEMT. As a result a high-frequency operational charac-teristic o~ DMT was inferior to that of HEMT.
Furthermore, as the DMT, as in the case of the second HEMT hereinbefore described, uses heterojunction of the AlGaAs/GaAs, the electrons -travelling in the n+-GaAs layer 23 that will be a channel, are sometimes in real spatial transition to the AlGaAs layer 24 disposed in the upper layer of the n-GaAs layer 23.
Thus due to this real spatial transition there is a case where the high-frequency characteristic of FET is further degraded.
summarY of the Invention The present invention is made to solve such problems, and to form a field effect transistor (FET) comprising: a first semiconductor layer; a channel layer having a crystalline structure substantially lattice-matching the first semiconductor layer, the ..
- ' : ' '` ~ :
. ' , ' ', " " ". '' -' ''''': .",,"' ' ', " ' , ,~
Z~
1 channel ].ayer being thinly ~ormed containing an "n"
type impurity at a high concentration; a second semiconductor layer having a crystalline structure substantially lattice-matching the channel layer, the second semiconductor layer being lightly doped with impurity made of materials with a higher electron carrying characteristic than that o~ -the channel layer;
and a third semiconductor layer in heterojunction with the second semiconductor layer, the third semiconductor layer ~eing lightly doped with impurity and in Schottky contact with a gate electrode.
In a FET of the structure in accordance with the present invention, if a higher electric ~ield is applied across the drain and the source, electrons which travel in the channel layer including impurity at a high concentration obtain energy. Thus the electrons rush out to the ~irst semiconductor layer and the second semiconductor layer both sandwiching the channel layer, to essentially travel in the second semiconductor layer excelling in electron carrying characteristic.
Because the channel layer is allowed to contain a high concentration ~f impurity the channel is formed by a large amount o~ electrons.
For this reason, according to the present invention a FET excelling in current driving ~unction can be obtained without lowering the speed of electron 9 , .
!. ' . ,. , ~ , . ;
3~
1 travelling in a channel.
The present invention will become more fully unders-tood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not to be considered as limiting the present invention.
Further scope of applicability of the presen-t invention will become apparent from the detailed description given hereinafter. However, it should be i~
understood -that the detailed description and speci~ic examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art form this detailed description.
Brief DescriPtion of -the Drawin~s Fig. 1 is a sectional view of conventional first and second HEMTs respectively. :;
Fig. 2 is a sectional view of conventional third and fourth HEMTs respectively.
Fig. 3 is an energy band profile illustrating a real space transition in a heterojunction of AlInAs/InP
system of the first HEMT in the prior art.
~ ig. 4 is an energy band profile illustrating a real space transition in a heterojunction o~
.. , , .,. . .. ,: : :
. :.:~: : :, .: , ~. :: : : : :
- . . :: : -:
:. :: . .. .
- ~ . . .- : : . :
~r~ 3,~.03,,~
1 AlGaAs/GaA~ system of the second HEMT in the prior art.
Fig. 5 is an energy band profile illustrating a real space transition in a heterojunction of AlInAs/InGaAs system of the third HEMT in the prior art.
Fig. 6 is an energy band profile illustrating a real space transition in a heterojunction of AlGaAs/InGaAs system of the fourth HEMT in the prior art.
Fig. 7 is a sectional view showing a conventional DMT.
Fig. 8 is a sectional view o$ a FET with refer~nce to first and the second embodiments according to the present invention.
Figs. 9A, 9B and 9C are sectional views of processing steps showing a method of producing a FET
with reference to the first and the second embodiments as shown in Fig. 8.
Fig. 10 shows an energy band adjacent to a channel of the FET with reference to the first embodiment.
Fig. 11 shows an energy band adjacent to a channel o~ the FET with reference to the second embodiment.
Fig. 12 is a sectional view of a FET with reference to the third and the fourth embodiments according to the present invention.
Figs. 13A, 13B and 13C are sectional views o~
processing steps showing a method of producing a FET
; - ,; :
: ~ .. . . : -~r ~.~ r;,2 1 with re~erence to the third and the ~ourth embodiments as shown in Fig. 12.
Fig. 14 shows an energy band adjacent to a channel of the FET with re~erence to the third and the fourth embodiments.
Description o~ the Preferred Embodiment Fig. 8 shows a structure of a FET according to a first embodiment o~ the present inven-tion. A method o~
producing the same is shown by a sectional view o~
processing steps in Fig. 9, which is described below.
On a semi-insulative InP semiconductor substrate 31 there are sequentially epitaxially grown a first semiconductor layer 32, a channel layer 33, a second semiconductor layer 34, a third semiconductor layer 35, and a contact layer 36 (see Fig. 9A). The epitaxial growth is carried out by an MBE (molecular beam epitaxy) method or an OMVPE (organic metal vapor phase epitaxy) method.
The first semiconductor layer 32 is made of undoped InP with thickness o~ 1 ~m. The channel layer 33 is made of n+ type InP doped by Si at a concentration of 2 x 1013/cm3, the thickness being 100 A. The second semiconductor layer 34 is made of undoped InP with a thickness of 200 ~ and having a higher electron carrying characteristic than the channel layer 33. The third semiconductor layer 35 is . ., . , : -, ~,,, . .~
;~ ~ <J 9 . ~ ~ r ~IJ
1 made o~ undoped AlxIn~lAs having a -thickness of 200 A with an Al composition ratio X o~ 0.4 or more and 0.6 or less (0.4 ~ x < 0.6). The contact layer 36 is made of nt type InGaAs having a thickne.ss of 500 R with donors doped at a concentration of 4 x 1018/cm3.
Here the channel layer 33 has carrier density and thickness enough to form a quantum well that will be described later. Electrons within the channel layer 33 have energy, therefore they exist in a slightly more expanded region than the thickness of the channel layer 33. In view of this, the second semiconductor layer 34 disposed on the channel layer 33 has a thickness allowing the expanded region of the electrons may no-t reach the third semiconductor layer 35.
That is, the energy band adjacent with the channel of -the first semiconductor layer 32, the channel layer 33, and the second semiconductor layer 34 will take a structure as shown in Fig. 10. The drawing on its lef-t shows the surface of the substrate, and the center portion corresponds to a channel doping surface. The channel layer 33 having higher density with thinner structure is sandwitched on its both sides by the semiconductor layers 32 and 34, the thickness being as thin as 100 A, a conducting band produces a bent portion to form a V like potential to form a quantum well as shown in the drawing. Incidentally, the channel layer 33 is made to have a thickness of 100 ~, z~
.q~r.J
1 but -~or ~orming the quantum well on the conducting band, the channel layer may preferably have a certain specific thinness, ~or example, 200 ~ or less.
The electrons in the channel layer when being at a ground state exist in the lowest subband EA. By obtaining energy when an electric -~ield is applied, -the electrons are sequentially transferred to a second subband EB and a third subband EC positioned above the subband EA, and move successively to higher energy 10 leveled subbands.
An existential probability o-~ electrons represents expansion of a wave function at the respective subbands as in Fig. 10, and approximates zero at the slightly more expanded portion than the thickness o~ the channel layer 33. The undoped InP layer at the substrate sur~ace or the second semiconductor layer 34 has a thickness such that the electrons existing in the expanded region may not reach the third semiconductor layer 3~.
2n The third semiconductor layer 3~ is formed by Schottky contact with the gate electrode to be described later (see Fig. 9A). The semiconductor layer 35 has a thickness enough to prevent the current ~lowing from the gate electrode to the second semiconductor 34 by a tunnel effect. The third semiconductor layer 3~, the second semiconductor layer 3~, and the channel layer 33, while their respective ,, , . ... :.. : ::, . ;: . :.. . :: :: : . ~ -~ a3~"" ~ r~
l thickness sa-tisfies the conditions relating to layer thickness hereinbe-~ore described, provide a total thickness of such layers thin enough to satis-~y o~erational characteristic of the FET. Such total ~hickness may pre~erably be 500 A or less. The topmost contact layer 36 is to protect the substrate sur~ace :
and to take ohmic-contact with the drain and source electrodes as hereinafter described and has no relation with the essence o~ the invention.
After such layers are sequentially ~ormed on the semiconductor substrate 31, the topmost contact layer 36 is ~ormed thereon with AuGe/Ni metal. Next, an ohmic electrode pattern is ~ormed using an ordinary photolithography techni~ue, and a drain electrode 37 and a source electrode 38 ohmic-contacting with the contact layer 36 are ~ormed (see Fig. 9B~. The contact layer 36 centered between the drain electrode 37 and the source electrode 38 is selectively removed by etching, to ~orm a recess 39 (see Fig. 9C).
Next there is formed a gate electrode 40 made of Ti/Pt/Au metal in Schottky contact with the third semiconductor layer 35 being exposed at the recess 39.
As a result a FET is completed having a s-tructure as shown in Fig. 8.
In the structure aforementioned, with voltage applied across the drain electrode 37 and source elec-trode 38, an electric ~ield is applied on electrons , . ,. .; , , ;; " ,v,, : :
, q~ ~ c~r, ~
1 in the channel layer 33. The electrons distributed in the subband EA move to -the higher energy level subb~nd EB by the energy given by the applied electric ~ield. In the subband EA at -the lowest position, the existential probability of elec-trons is high at the center portion of the channel layer 33 as shown by -the expansion o~
the wave ~unction in Fig. 10, electron speed is thereby lowered largely a~ected by the scattering o~ impurity.
However, in the subbands EB and EC above the subband EA, the existential probability o~ electrons has a peak value shi~ted from the center portion as shown in the drawing, thus being hardly a~ected by the scattering o~ impurity. As a result, the travelling speed o~
electrons in the channel layer 33 distributed in the subbands EB and EC with higher energy levels becomes increased.
When voltage applied across the drain and source is increased, a ~urther higher electric ~ield is applied to the electrons in the channel layer 33. Thus the electrons sequentially move to a even higher energy level subband to ~inally rush out from V shape potential into the first semiconductor 32 and second semiconductor 34 both sandwiching the channel layer 33.
In this process, the amount o~ electrons rushing out is far greater in the second semiconductor layer 34 disposed on the channel layer 33, which allows the electrons to mostly travel in that second semiconductor : . : .: ' : . :
~ .. ,;. , . ~ ,: :: : . , . ::
~ ~0~
1 layer 34. I~he layers 32 and 3~ sandwiching the channel layer 33 are undoped and in addition a higher electron carrying characteristic is given to the second semiconductor layer 34 therefore it becomes the essential passage of the electrons. Thus even when a highly doped channel layer 34 easily affected by impurity scattering is used, although the mobility of electrons is lower under low electric field compared with conventional HEMT, a high frequency characteristic is exhibited equivalent to or higher than that of HEMT
in actual operation of the device under a high electric field.
Also in the FET according to the present embodiment, the third semiconductor layer 35 and the channel layer 33 made of AlInAs are positioned at intervals more than a distance of the expansion of the wave function of the electrons in the channel layer 33 as described above. For this reason, deterioration of -the high-frequency carrying characteris-tic due to the actual space transition does not arise like the conventional first HEMT as hereinbefore described in which -the AlInAs layer having ~n inferior electron carrying characteristic and the channel layer made of InP both are in close vicinity with each other. In the conventional first HEMT a mutual conductance characteristic gln against change of a gate voltage Vg had a peak of value gm for a certain specific gate . - ' ~ ': ' .' :7 ~ ~ .J ~ g r ~1 1 voltage value. However, in the mutual conductance characteristic in this embodiment, a peak of value gm is maintained ~or the change of the gate voltage within a certain variation range. Therefore according to the embodiment, the designing of FET becomes easier and with a stable FET characteristic made possible to be obtained, a higher gain can be always secured, thus resulting in an output wi-thout distortion.
The channel layer 33 has thickness of a certain lG extent and has a structure being possible to dope impurity at a higher concentration, therefore the channel is formed of a large amount of electrons. This permits a far more excellent current drive capability compared with the conventional first HEMT wherein the current drive capability is limited by the upper limit of concentration of the two-dimensional electron gas.
The gate electrode 40 is in Schottl~y contact with the third semiconductor layer 35 made of undoped AlInAs. This makes a Schottky barrier higher and enables to operate the device at higher-bias condition, resulting in improved output characteristic.
Furthermore, the noise reduction performance is improved because of higher speed of the electrons travelling in the channel.
Therefore, the FET of the embodiment is effective when applied to a basic structure of super high frequency, high output elemen-ts with low noise.
' ,, ',, . `: : ', r~
1 In the first embodiment, it has been explained that the third semiconductor layer 35 made o~ AlInAs is ~ormed on the second semiconductor layer 34 made of InP. However, it is generally considered as dif~icult to maintain a good intereace crystallinity between AlInAs and InP. For this reason, an undoped InGaAs thin layer may be formed between the second semiconductor layer 34 and the third semiconductor layer 35 which will exhibit the same result as the embodiment described above.
It also has been explained that the first and second semiconductor layers 32 and 34 sandwiching the channel layer 33 are to be undoped InP. However it is not necessarily limited to such ma-terial. Other materials may be employed ~or example, the undoped InGaAs having a higher electron carrying characteristic with a crystalline structure substantially lattice matching the channel layer 33 which will exhibit the same e~fect as the embodiment abovementioned. Further, because the electrons forming the channel essentially travel in the second semiconductor layer 34, the first semiconductor layer 32 does not always have to be the same material as the second semiconductor layer 34 and may be a material having a crystalline structure substantially lattice-matching the semiconductor substrate 31 and the channel layer 33.
~ Wr~
1 The present invention is now described ~or a ~ET
according to a second embodiment. A structure of the FET o~ the second embodiment is similar to the FET of the first embodiment as shown in Fig. ~. A method o+' producing the same is also similar to the first embodiment and is produced through the same producing process in Fig. 9. A di~erence between the FETs of the ~irst and second embodiments is the difference in materials forming the respective layers.
In this embodiment, a semi-insulative GaAs semiconductor substrate is used instead of the semi-insulative InP semiconductor substrate 31, the respective layers hereinafter described being sequentially and epitaxially grown on the semi-insulative GaAs semiconductor substrate.
The ~irst semiconductor layer 32 made of the undoped InP is replaced by a new first semiconductor layer which is made of substantially undoped p type GaAs with thickness of 1 ~m the same as that o~ the previous first semiconductor layer 32. The substantially undoped state may preferably mean an impurity concentration of 5 x 1017/cm3 or less. The channel layer 33 made of the n type InP is replaced by a new channel layer, which is formed o~ nt type GaAs doped with Si at a concentration of 2 x 101~/cm3 having the same thickness o~ 100 A as the ~ormer channel layer 33. The second semiconductor layer 34 made of undoped 1 InP is rep].aced by a new second semiconductor layer, which is made oE substantially undoped n type GaAs having a higher electron carrying characteristic than that of the channel layer and having a thickness of 200 A the same as the ~ormer second semiconductor layer 34.
The third semiconductor layer 35 made of undoped AlInAs is replaced by a new third semiconductor layer, which is made of substantially undoped n type AlxGalxAs having composite ratio X of Al of above zero and 0.3 or less (0 < X ~ 0.3) with thickness of 200 A the same as that of the third semiconductor layer 35. The contact layer 36 made of the n+ type InGaAs is replaced by a new contact layer, which is made of n+ type GaAs doped with donors at a concentration of 4 x 1018/cm3 with -thickness of 500 ~ the same as that of the former contact layer 36. A gate electrode and an ohmic electrode are ~ormed o~ the same materials as those of the first embodiment. .
An energy band adjacent to a channel of the FET
according to the second embodiment has a structure the same as the ~irst embodiment as shown in Fig. 11. Also in this second embodiment, the channel layer being made of the n+-GaAs having a high concentration and formed in thin layer, the both sides of the channel layer are sandwiched by the first and second semiconductor layers made of substantially undoped GaAs with a thickness as thin as 100 A. Thus a bent portion is produced in a .J r 5~
1 conduction band to ~orm a V shape potential to make up a quantum well shown in the drawing. The electrons in the n+-GaAs channel in -the embodiment ~lso move sequentially to a higher energy level subbands by obtaining energy by an electric field being applied.
In the second embodiment, as in the first embodiment, in the higher energy level subbands EB and EC the peak o~ existential probability Oe electrons is shifted from the center portion, therefore the electrons in the channel layer are hardly a~ected by scattering o~ impurity, resulting in a higher travelling speed o~ the electrons.
I~ voltage applied across the drain / source is increased, the electrons in the channel layer ~inally rush out ~rom the V shape potential into the ~irst and second semiconductor layers made of substantially undoped GaAs and sandwiching the channel layer. In this process, the amount of electrons rushing out is ~ar greater in the second semiconductor layer excelling in carrying characteristic which is disposed on the channel layer, and hence as in the first embodiment the electrons in the channel layer become travelling at high speed. There~ore also in the second embodiment, even when a highly doped channel layer made o~ n+ type GaAs which is easily a~ected by scattering o~ impurity is used, although the electron mobility is low under a low electric field compared with a conventional HEMT, a . ,~ .~r~
1 high frequency characteristic equivalent to or more satisfactory than that of the HEMT is exhibited under the higher electric field in which the device is actually operated.
Also in the FET of the second embodiment, the third semiconductor layer made of AlGaAs and the channel layer made of GaAs are positioned at interval of a distance more than the expansion of the wave function of the electrons in the channel layer. Thus a deterioration o~ high-frequency characteristic due to the actual space transition is not produced like the conventional second HEMT or DMT having a structure where the AlGaAs layer with an inferior carrying characteristic o~ electrons is in close vicinity with the channel layer. The mutual conductance characteristic of FET in this second embodiment, also has a characteristic to maintain a peak value gm for a change of the gate voltage limited within a certain variation range. Therefore also in the second embodiment, the designing of FET is made easier and the obtained FET characteristic being stable to always secure a higher gain, an output without distortion can be obtained.
Because the channel layer formed of the n+ type GaAs has a thickness of a certain extent the channel layer can be doped with impurity at high concentration, therefore in the second embodiment also the channel is ::
,- ... , ~
;
2 ~ ~ $1 ~ 3 r ~
1 formed o~ a large amount o~ electrons. Thus, a ~ar superior current drive capability can be obtained comparing with the conven-tional second HEMT where the current drive capability is limited by the upper limit of concentration of the two-dimensional electron gas.
In addition the gate electrode being in Scho-ttky contact with the third semiconductor layer made o~
substantially undoped AlGaAs, also in the second embodiment the Schottky barrier becomes higher. In view of this, the device can be operated under the condition of a large bias, resulting in upgraded output characteristic. The noise reduction characteristic also is improved because of a higher electron speed travelling in the channel.
The FET according to the second embodiment also is effective when applied to the basic structure of super high ~requency, high output elements with lower noise.
Incidentally, it has explained in the second embodiment that the first and second semiconductors sandwiching the channel layer are to be undoped GaAs, however it is not necessarily limited to such material.
Other materials may be employed, ~or example, an undoped InGaAs having a higher electron carrying characteristic with a crystalline structure ;
substantially lattice-matching the channel layer which will exhibit the same e~fect as the second embodiment mentioned above. Furthermore, because the elec-trons ~ .J ~
1 forming the channel essentially -travel in the second semiconductor layer made oY substantially undoped GaAs, the first semiconductor layer does not necessarily have to be of the same material as the second semiconductor layer and may have a crystalline s-tructure substantially lattice-matching the GaAs substrate and the n type GaAs channel layer.
The present invention is now described for a F~T
according to a third embodiment. Fig. 12 shows a structure o~ the FET according to the third embodiment of the present invention. A method o~ producing the same is shown in sectional views o~ a production process in Fig. 13. The method o~ producing in -this case is as ~ollows.
On a semi-insulator InP semiconductor substrate 41 there are sequentially and epitaxially grown a buffer layer 42 ~or lattice-matching the substrate 41, a first semiconductor layer 43, a channel layer 44, a second semiconductor layer 45, a third semiconductor layer 46, and a contact layer 47 (see Fig. 13A). This epitaxial growth is carried out by the MBE method or OMVPE method as in the respective embodiments abovementioned. - ;.
The buffer layer 42 for lattice-matching the substrate 41 is made of undoped AlInAs wi~h a thickness o~ 1 ~m. The ~irst semiconductor layer 43 made o~
undoped InyGa1yAs having a composition ratio Y o~ In o~
0.45 or more and 0.65 or less (0.45 ~t Y ~ 0.653 and a t . 'j:
. ,' ' ~ , - , :
.. . ..
2~
1 thickness of 100 A. The channel layer 44 is made of n+
type InyGa1yAs (0.4~ ~ Y < 0.65) doped with Si at a concentration o+~ 2 x 1018/cm3 with a thickness o~ 100 A.
The second semiconductor layer 45 is made o~ undoped InyGalyAs (0.45 ~ Y ~ 0.65) having a thickness of 100 A
and a h.igher electron carrying characteristic than that of the channel layer 44. The third semiconductor layer 46 is made of undoped AlxInlxAs having a composition ratio X of Al of 0.4 or more and 0.6 or less (0.4 ~ X ~
0.6) and a thickness of 200 ~. The contact layer 47 is made of n+ type InGaAs doped with donors at a concentration of 4 x 1018/cm3 with a thickness of 500 A.
Here, the channel layer- 44 has carrier density and thickness enough to form a quantum well as in the first and second embodiments as hereinbefore described.
Because the electrons in the channel layer 44 have energy they exist in a region slightly more expanded than the thickness of the channel layer 44. For this reason, the second semiconductor layer 4~ disposed on the channel layer 44 has a thickness allowing the . .
expanded region of the electrons will not reach the third semiconductor layer 46.
An energy band adjacent to a channel of the FET
according to the third embodiment has a structure the same as the respective embodiments as shown in the Fig.
14. Also in this third embodiment, the channel layer 44 made of n-Iny~a1yAs having a high concentration and ,, ;, ... .:: . , .::
q,~
~ . -f ~
1 thinly formed, both sides o~ the channel layer 44 are sandwiched by the ~irst and second semiconductor layers 43 and 45 made of undoped InyGa1yAs with a thickness of as thin as 100 ~. Thus a bent portion is formed in a conduction band to produce a V shape potential and to provide a quantum well as shown in the drawing. Also in the third embodiment, the thickness of the channel layer 44 is preferred to have a certain thinness enough to form a quantum well at the conduction band, for example, 200 A or less. Also, the second semiconductor layer 45 has a thickness allowing the electrons expanded into the channel layer 44 not to reach the third semiconductor layer 46.
The gate electrode to be described la-ter is formed by being in Schottky contact with the third semiconductor layer 46, which has a thickness enough to prevent the current flowing from the gate electrode to the second semiconductor layer 4~ by a tunnel effect.
The third semiconductor layer 46, the second semiconductor layer 45, and the channel layer 44 while satisfying the respective conditions relating to the layer thlckness as abovementioned, the total thickness thereof is thin enough to satisfy the operational performance of the FET. Such total thic~ness may preferably be ~00 R or less. The contact layer 47 being the topmost layer is provided for protecting the substrate surface and for making ohmic contact with the . ~ ., ., . -. i , . :
,:
:
: , , . : . . ~ ,- ,: .
2~ '.h ~
1 drain / source electrodes. Hence that contact layer has no relation to the essence of the invention.
Next, after the respective layers have been sequentially formed on the semiconductor substrate 41 as hereinbefore described, AuGe/Ni metal is ~ormed on the contact layer 47 being the topmos-t layer. An electrode pattern is formed using an ordinary photolithography technique, and a drain electrode 48 and a source electrode 49 are formed in ohmic contact with the contact layer 47 (see Fig. 13B). Next, the contact layer 47 centered between the drain electrode 48 and source electrode 49 is selectively removed by etching to form a recess 50 (see Fig. 13C).
In the next process, there is ~ormed a gate electrode 51 made of Ti/Pt/Au in Schottky contact with the third semiconductor layer 46 exposed at the recess 50. As a result the FET having a structure as shown in Fig. 12 is completed.
Also in the present embodiment, the electrons in the channel layer 44 made of n~-InyGa1 ~s move successively to higher energy level subbands by obtaining energy from an electric field being applied.
Therefore, also in this third embodiment, same as in the respective previous embodiments, because the peak o~ an existential probability o~ the electrons is being shifted from the center portion at the higher energ~
level subbands EB and EC, the elec-trons in the channel :- . ,. : ,;: .
1 layer 4~ are hardly affected by scattering of impuri-ty, resulting in a higher travelling speed of the electrons.
If voltage applied across the drain / source is raised, the electrons in the channel layer 44 finally rush out from the V shape potential into -the first and second semiconductor layers 43 and 4~ made of undoped InyGa1yAs sandwiching the channel layer 44. In this process, the amount of electrons rushing out is far greater in the second semiconductor layer 4~ excelling in electron carrying characteristic and disposed on the channel layer 44, hence as in the respective embodiments hereinbe~ore described the electrons in the channel become -travelling at a high speed. Therefore also in the third embodiment, even when a highly doped channel layer 44 made of the n~ type InyGalyAs easily affected by scattering of impurity is used, a high-frequency characteristic equivalent to or superior than that of the HEMT is exhibi-ted under a higher electric field in which the device is actually operated, although the electron mobility at a low electric field is lower comparing with that of the conventional HEMT.
Also in the FET of the third embodiment, the third semiconductor layer 46 made of AlInAs and the channel layer 44 made of n+ type InyGalyAs are positioned at interval of a distance more than the expansion of the - : ~
: , ~
1 wave function of the electrons in the channel layer 44.
Therefore a deterioration of high-frequency charac-teristic due to the actual space transition i5 not produced like the conventional third HEMT having a structure where the AlInAs layer with an inferior carrying characteristic of electrons is in close ~icinity of the channel layer. Also in the mutual conductance characteristic o~ FET according to the third embodiment, it has a characteristic of a peak o~
gm value is maintained against the change of the gate voltage having a certain variation range. Therefore according to the third embodiment also, the designing of FET is easier and with a stable FET characteristic ~ ~' obtained, a higher gain is always secured, as a result an output without distortion is obtained.
The channel layer 44 formed of the n+ type InyGa1yAs has a thickness of a certain extent so that the channel layer 44 can be doped with impurity at a high concentration, therefore in the third embodiment also the channel is formed of a large amount of ~-electrons. Thus, ~ar superior current drive capability can be obtained compared with the conventional third HEMT wherein the current dri~e capability is limited by the upper limit o~ concentration of the two-dimensional electron gas.
In addition, the gate electrode 51 being in Schottky contact with the third semiconductor layer 46 ~0 . j . - : . .
Z~ 7~
1 made of undoped AlInAs, in the third embodiment also the Schottky barrier becornes high. Therefore the device can -thus be operated under the condition of high bias which upgrades the output characteristic.
Furthermore the noise reduction characteristic also is improved because of a higher electron speed when travelling in the channel.
In view of above, the FET according to the third embodiment is effective i~ applied to the basic structure of elements requiring super-high frequency and large output with lowered noise.
It has been explained in the third embodiment that the first and second semiconductor layers 43 and 45 sandwiching the channel layer 44 to be an undoped InGaAs. However it is not necessarily limited to such material in this embodiment. Other materials may be employed, for example, the undoped InP having a higher electron carrying characteristic with a crystalline structure substantially lattice-matching the channel layer 44 which will exhibit the same effect as the third embodiment abovementioned. Furthermore, because the electrons forming the channel essentially travel in the second semiconductor layer 45 made o~ undoped InGaAs, the first semiconductor layer 43 does not necessarily have to be the same material as the second semiconductor layer 45 and it may be a material having a crystalline structure substantially lattice- matching - ., ~ , 2~
1 the InP semiconductor substrate 41 and -the n+ type InGaAs channel layer 44.
The present invention is now described for a FET
according to a fourth embodiment. Fig. 12 also shows a structure of the ~ET according to the fourth embodiment of the present invention. A method of producing the same is similar to that of the third embodiment as shown in Fig. 13, and produced through similar processing steps as shown in Fig. 13. Difference between the FETs according to the fourth and third embodiments is the difference in materials forming respective layers.
A semi-insulative GaAs semiconductor substrate is used instead of the semi-insulative InP semiconductor 5 substrate 41, and following layers are sequentially epitaxially grown on the semi-insulative GaAs , semiconductor substrate.
The buffer layer 42 made of undoped AlInAs for lattice-matching the substrate 41 is replaced by another buffer layer which is made of undoped GaAs with a thickness of l ~m the same as the former buffer layer 42. The first semiconductor layer 43 made of the undoped InyGa1yAs (0.45 ~ y ~ 0.65) is replaced by a new first semiconductor layer, which is made of undoped InyGa1yAs having a composition ratio "y" of In of zero or more and 0.35 or less (0 ~ y ~ 0.35) with a thickness of 50 A. The channel layer 44 made of the n+
1 type InyGa1yAs (0.45 ~ y < 0.65) is replaced by a new channel layer, which is made of n+ type InyGa1 ~s (0 ~ y ~ 0.35) doped with Si at a concentration of 2 x 1018/cm3 having a thickness o~ 100 A the same as that of the former channel layer 44. The second semiconductor layer 45 made o~ the undoped InyGalyAs ~0.45 < y ~ 0.65) is replaced by a new second semiconductor layer, which is made of undoped InyGa1yAs (0 ~ y < 0.35) having a higher electron carrying characteristic than that of the channel layer and a thickness of 100 A the same as the former second semiconductor layer 45. The third semiconductor layer 46 made o-E the undoped AlxInlxAs (0.4 ~ X < 0.6) is replaced by a new third semiconductor layer, which is made of undoped AlxGalxAs having a composition ratio X of Al o~ zero or more and 0.3 or less (0 ~ X S 0.3) and a thickness of 200 A the same as that of the former third semiconductor 46.
Also, a new contact layer is formed with the same materials and thickness as those of the former contact layer 47 made of the n+ type InGaAs. A gate electrode and an ohmic electrode are formed in likewise manner and with the same materials as those of the third embodiment.
An energy band adjacent to a channel of the FET
according to the fourth embodiment has a structure the same as the third embodiment as hereinbefore described ~;
in Fig. 14. Also in this fourth embodiment, the "- ~ ' . ' ' :' ' ~ '~. '` .: ' ' . '', ' '' 1 channel layer made o~ high concentration and thinly formed n~-InyGa1 ~s layer, both sides of the channel layer are sandwiched by the first and second semiconductor layers made of the undoped InyGa1yAs and formed thinly to a thickness of 100 ~. Thus a bent portion is produced in a conduction band to form a V
shape potential and to provide a quantum well shown in the drawing. In the present embodiment, the electrons in the channel layer made of n+-InyGa1yAs also move successively to a plurality of higher energy level subbands by obtaining energy from an electric field being applied. Therefore in the fourth embodiment also, as in the respective previous embodiments, since the peak of an existential probability of the electrons is shifted from the center portion at the higher energy level subbands EB and EC, the electrons in the channel layer is hardly affected by scattering of impurity, thus resulting in a higher travelling speed of electrons.
If voltage impressed across the drain / source is raised, the electrons in the channel layer finally rush out from the V shape potential into the first and second semiconductor Iayers made of undoped InyGa1yAs sandwiching the channel layer. In this process, the amount of electrons rushing out is far greater in the second semiconductor layer excelling in electron carrying characteristic and disposed on the channel . ' ' ~ ' .'' ' ' ~.'' ' ' j ; ' 1 layer, as in the respective embodiments hereinbe~ore described, and the electrons in the channel become travelling at a high speed. I'herefore also in the fourth embodiment even when a highly doped channel layer made of n~ type InyGa1yAs easily affected by scattering of impurity is used, a high-frequency characteristic equivalent to or superior than that of the HEMT is exhibited under high electric field in which the device is actually operated although the , electron mobility at a low electric ~ield is lower comparing with that of the conventional HEMT.
Also in the FET o~ the fourth embodiment, the third semiconductor layer made of AlGaAs and the channel layer made of the nt type InyGa1yAs are positioned at interval of a distance more than -the expansion o~ the wave function of the electrons in the channel layer. Thus a deterioration of high-frequency characteristic due to the actual space transition is not produced like the conventional fourth HEMT having a structure where the AlGaAs layer with inferior carrying characteristic of electrons is in close vicinity with the channel layer. The mutual conductance characteristic of FET according to the fourth embodiment, also has a characteristic of a peak of value ~ gm is maintained against the change of the gate voltage having a certain variation range. Therefore also by the fourth embodiment, the designing o~ FET is ~: . ,, :,:~ ~ ., J : ~ :
~,C^~3r:,"r,'l;"
1 made easier and with a stable FET characteristic obtained, a higher gain is always secured, thus resulting in an output without distortion.
The channel layer formed of the n type InyGa1 ~s has a thickness of certain extent so that the channel layer can be doped with impurity a-t a high concentration, hence also in the fourth embodiment the channel is ~ormed o~ a large amount of electrons.
Thus, far superior current drive capability can be , obtained comparing with the conventional fourth HEMT
wherein the current drive capability is limited by the upper limit of concentration of the two-dimensional electron gas.
The gate electrode being in Schottky contact with the third semiconductor layer made of undoped AlGaAs, the Schottky barrier in the fourth embodiment also becomes high. The device can thus be operated under a high bias condition which upgrades the output characteristic. The noise reduction characteristic also is improved because the travelling speed of electron in the channel becomes higher.
The FET according to the fourth embodiment is effective when applied to the basic structure using elements requiring a super high-frequency and large output with lowered noise.
In the fourth embodiment it has explained that the first and second semiconductor layers sandwiching the : , . ~ ~ , .
.. . . ~ : : .
r~
1 channel layer are to be undoped InGaAs. However it is not necessarily limited to such material. Other materials may be employed, ~or example, the undoped GaAs having a higher elec-tron carrying characteristic with a crystalline structure substantially lattice-matching the channel layer which will exhibit the same ef~ect as the ~ourth embodiment described above. E'urthermore, because the electrons ~orming the channel essentially travel in the second semiconductor layer made o~ undoped InGaAs, the first semiconductor layer does not have to be necessarily the same material as the second semiconductor layer and it may have a crystalline structure substantially lattice-rnatching the GaAs semiconductor substrate and the n~ type InGaAs channel layer.
From the invention thus described, it will be obvious that the invention may be varied in many ways.
Such variations are not to be regarded as a departure ~rom the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.
1 Title of the Invention FIELD EFFECT TRANSISTOR
BackRround_of the Invention (Field of the Invention) The present invention relates -to a structure of a field effect transistor (FET) necessitating a very high speed operation.
(Related Background Art) Conventionally, as a very high speed device o~
this kind, for example, a first HEMT (high electron-mobility transistor) is introduced as shown in Fig. 1.
An InP semiconductor substrate 1 is formed thereon with :
an undoped InP layer 2. The undoped InP layer 2 is formed thereon with an n-AlxInlxAs layer 3 on which donors are selectively added to AlxInlxAs. The n-AlxIn ~s layer 3 is ~ormed thereon with an n -InGaAs layer ~, a gate electrode 5 is formed in Schottky contact with the n-AlxInlxAs layer 3 e~posed at a recess formed at a center portion, and ohmic electrodes 6 and 7 are formed on the n+-InGaAs layer 4.
There is also a second HEMT having the same structure as the first HEMT but made of different composite materials. In the second HEMT, a GaAs semiconductor substrate is used instead of the InP
semiconductor substrate 1, and an undoped GaAs layer, an n-AlGaAs layer, and an n+-GaAs layer are laminated . , .~
~ 3..
1 respectively instea~ o~ the uncloped InP layer 2, the n-AlxInlxAs layer 3, and the n-InGaAs layer 4.
There is also a third HEMT with a struc-ture as indicated in Fig. 2. Namely, an InP semiconductor substrate 11 is formed thereon with an undoped AlInAs layer 12. On the undoped AlInAs layer 12 is further formed an undoped InyGa1yAs layer 13, and on this undoped InyGa1yAs layer 13 is formed an n-AlxInlxAs layer 14 in which donors are selectively added to AlxInlxAs.
Further on the n-AlxInlxAs layer 14 is formed an n+-InGaAs layer 15, and a gate electrode 16 is formed in Schott~y contact with the n-AlxInlxAs layer 14 exposed at a recess formed at a center portion, and ohmic electrodes 17 and 18 are formed on the n-InGaAs layer 1~ .
In addition, there is a four-th HEMT having the same structure as the third HEMT but with differen-t composite materials. In the fourth HEMT, a GaAs semiconductor substrate is used instead of an InP
semiconductor substrate 11, and an undoped GaAs layer, an undoped InyGa1yAs layer, and an n-AlxGalxAs layer are laminated respectively instead of -the undoped AlInAs layer 12, the undoped InyGa1yAs layer 13, and the ;~
n-AlxInlxAs layer 14. The donors are selectively added to this n-AlxGalxAs layer. Further an n-InGaAs layer is used instead of the n+-InGaAs layer 15.
However, as in the conventional first HEMT of the ~ ,3 1 prior art hereinbe~ore described, ~or a system using heterojunction of AlInAs/InP, electrons travel in an InP layer being a channel and such electrons often produce a real space transfer ~or making transition to the AlInAs layer disposed in the upper layer o-~ the InP
layer. This real space transfer may be explained as follows. An energy band indicated in Fig. 3 is ~ormed s at a heterojunction portion of the n-AlInAs layer 3 and the undoped InP layer 2, and the two-dimensional electron gas is accumulated at the oblique-lined portion of the drawing. However, if a high electric field is applied across a drain and a source and energy of the two-dimensional electron gas becomes higher, the electrons in the two-dimensional electron gas make transition to the n-AlInAs layer 3 as shown by the arrow mark in the drawing.
Generally, a high electric field is applied across a drain and a source during its operation, and as carrying characteristic of electrons is in~erior in the AlInAs layer than in the InP layer, when this real space transfer occurs the high-frequency characteris*ic of FET becomes degraded.
As in the second HEMT o~ the prior art ; hereinbefore described, for a system using the heterojunction o~ AlGaAs/GaAs, electrons travel in an GaAs layer which is to become a channel and such electrons sometimes produce a real space transfer for J ~ r~
I making transition to the AlGa~s layer disposed in the upper layer of the GaAs layer. For exampl.e, this real space transfer may be explained as follows. An energy band in Fig. 4 is formed at the heterojunction portion of the n-AlGaAs layer and the undoped Ga~s, and the two-dimensional electron gas is accumulated at the oblique lined portion of the drawing. However, i-~ a high electric ~ield is applied across a drain and a source and energy of the two-dimensional electron gas becomes higher, the elec-trons in -the two-dimensional electron gas are transferred to the n-AlGaAs layer as shown by arrow mark in the drawing.
Generally, a high electric field is applied across a drain and a source during its operation, and as carrying characteristic of electrons is inferior in the AlGaAs layer than in the GaAs layer, thus when this real space trans~er occurs it deteriorates the high-frequency characteristic of FET.
In addition, as in the third HEMT o~ -the prior art hereinbefore described, even in a system using the heterojunction of AlInAs/InGaAs, electrons tra~el in an InGaAs layer 13 which is to become a channel and such electrons sometimes produce real space transfer for making transition to the AlInAs layer 14 disposed in the upper layer of the InGaAs layer 13. This real space transition may be explained as below. An energy band in Fig. 5 is formed at the heterojunction portion , ,;
~: :: .. . . ..
~2~ S ~3.', ~ V ~
1 of the n-AlInAs layer 14 and the undoped InGaAs layer 13, and the two-dimensional electron gas is accumulated at oblique lined portion of the drawing. However, if a high electric field is applied across a drain and a source and energy o~ the two-dimensional electron gas becomes higher, the electrons in the two-dimensional electron gas are trans~erred to the n-AlInAs layer 14 as shown by arrow mark in the drawing.
Generally, a high electric ~ield is imposed across a drain and a source during its operation, and because carrying characteristic o~ electrons in the AlInAs layer is inferior to that o-~ the InGaAs layer, when this real space transfer occurs, it deteriorates the high-~requency characteristic o~ FET.
Also as in the ~ourth HEMT of the prior art hereinbefore described, even for a system using the heterojunction o~ AlGaAs/InGaAs, electrons travel in an InGaAs layer which will be a channel and such electrons sometimes produce real space transition ~or trans~erring to the AlGaAs layer disposed in -the upper layer o~ the InGaAs layer. This real space -transfer can be explained as ~ollows. An energy band in Fig. 6 is formed at the heterojunction portion o~ the n-AlGaAs layer and the undoped InGaAs layer, and the two-dimensional electron gas is accumulated at the oblique lined portion o~ the drawing. However, i~ a high electric ~ield is applied across a drain and a source ~ '7'' `
~2~
1 and energy o~ the two-dimensional electron gas becomes higher, the electrons in the two-dimensional electron gas make transition to the ~I-AlGaAs layer as shown by arrow mark in the drawing.
Generally, a high electric field is applied across a drain and a source during its operation, and because carrying characteristic of electrons in the AlInAs layer is inferior than in the InGaAs layer, when a real space trans~er occurs, it deteriorates the high-frequency characteristic of FET.
The first HEMT of the prior art abovementioned uses as a channel a two-dimensional electron gas layer 8 in Fig. 1 produced on a heterojunction inter-Eace between the undoped InP layer 2 and the n-AlInAs layer 3. This channel is formed within InP having a higher electron saturating speed than GaAs or InGaAs, thus producing a high-frequency device with upgraded performance. However, a limit has been placed against raising the electron gas density because maximum current density of such HEMT is determined by the upper limit of two-dimensional electron gas density and the channel layer being in -two-dimensional status. This results in an inability to produce a high-frequency device exhibiting a satisfactorily large output.
The fact as hereinbefore described applies also to the conventional cases of the second, third, and fourth HEMTs o~ the prior art. Electron gas density cannot be ~S~3~
1 satisfactorily increased by the conven-ti.onal second HEMT because the second HEMT uses as a channel a two-dimensional electron gas layer produced on a heterojunction interface between the undoped GaAs layer and the n-AlGaAs layer. Also, the electron gas density is not fully raised by the conventional third HEMT
because the third HEMT uses as its channel a two-dimensional electron gas layer 19 in Fig. 2 produced on a heterojunction inter~ace between the undoped InGaAs layer 13 and the n-AlInAs layer 14, as well as by the conventional fourth HEMT because the fourth HEMT uses as its channel a two-dimen~ional electron gas layer produced on a heterojunction inter+~ace between the undoped InGaAs layer and the n-AlGaAs layer. Therefore high-frequency devices with a sufficiently high outpu-t have not been produced by the respective conventional HEMTs described above.
For other very high speed devices there has been developed, for example, a DMT (Doped-channel hetero MIS-FET) with the structures as in Fig. 7. A GaAs semiconductor subs-trate 21 is formed -thereon an undoped GaAs layer 22, on which is formed an n+-GaAs layer 23 that will be a channel. Further, on the n+-GaAs layer 23 is +ormed an undoped AlGaAs layer 24 and an n-GaAs layer 2~. A gate electrode 26 is formed in Schottky contact with an undoped AlGaAs layer 24 exposed at a recess, and ohmic electrodes 27 and 28 are formed on -: ~ ; ' ! ' ' ~'.:
,.. . , . .. ~ . .
Z~ ~r,~
1 the n -GaAs layer 2~.
Because such DMT uses a high densi-ty and -thinly formed n-GaAs layer 23 as a channel layer, a suf+~iciently large output can be obtained. The AlGaAs layer 24 thereabove is undoped to improve its Schottky withstanding voltage. However in this DMT, because channel layer contains a large amount of impurities the travelling speed of electrons in t.he channel layer is lowered comparing with that of HEMT. As a result a high-frequency operational charac-teristic o~ DMT was inferior to that of HEMT.
Furthermore, as the DMT, as in the case of the second HEMT hereinbefore described, uses heterojunction of the AlGaAs/GaAs, the electrons -travelling in the n+-GaAs layer 23 that will be a channel, are sometimes in real spatial transition to the AlGaAs layer 24 disposed in the upper layer of the n-GaAs layer 23.
Thus due to this real spatial transition there is a case where the high-frequency characteristic of FET is further degraded.
summarY of the Invention The present invention is made to solve such problems, and to form a field effect transistor (FET) comprising: a first semiconductor layer; a channel layer having a crystalline structure substantially lattice-matching the first semiconductor layer, the ..
- ' : ' '` ~ :
. ' , ' ', " " ". '' -' ''''': .",,"' ' ', " ' , ,~
Z~
1 channel ].ayer being thinly ~ormed containing an "n"
type impurity at a high concentration; a second semiconductor layer having a crystalline structure substantially lattice-matching the channel layer, the second semiconductor layer being lightly doped with impurity made of materials with a higher electron carrying characteristic than that o~ -the channel layer;
and a third semiconductor layer in heterojunction with the second semiconductor layer, the third semiconductor layer ~eing lightly doped with impurity and in Schottky contact with a gate electrode.
In a FET of the structure in accordance with the present invention, if a higher electric ~ield is applied across the drain and the source, electrons which travel in the channel layer including impurity at a high concentration obtain energy. Thus the electrons rush out to the ~irst semiconductor layer and the second semiconductor layer both sandwiching the channel layer, to essentially travel in the second semiconductor layer excelling in electron carrying characteristic.
Because the channel layer is allowed to contain a high concentration ~f impurity the channel is formed by a large amount o~ electrons.
For this reason, according to the present invention a FET excelling in current driving ~unction can be obtained without lowering the speed of electron 9 , .
!. ' . ,. , ~ , . ;
3~
1 travelling in a channel.
The present invention will become more fully unders-tood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not to be considered as limiting the present invention.
Further scope of applicability of the presen-t invention will become apparent from the detailed description given hereinafter. However, it should be i~
understood -that the detailed description and speci~ic examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art form this detailed description.
Brief DescriPtion of -the Drawin~s Fig. 1 is a sectional view of conventional first and second HEMTs respectively. :;
Fig. 2 is a sectional view of conventional third and fourth HEMTs respectively.
Fig. 3 is an energy band profile illustrating a real space transition in a heterojunction of AlInAs/InP
system of the first HEMT in the prior art.
~ ig. 4 is an energy band profile illustrating a real space transition in a heterojunction o~
.. , , .,. . .. ,: : :
. :.:~: : :, .: , ~. :: : : : :
- . . :: : -:
:. :: . .. .
- ~ . . .- : : . :
~r~ 3,~.03,,~
1 AlGaAs/GaA~ system of the second HEMT in the prior art.
Fig. 5 is an energy band profile illustrating a real space transition in a heterojunction of AlInAs/InGaAs system of the third HEMT in the prior art.
Fig. 6 is an energy band profile illustrating a real space transition in a heterojunction of AlGaAs/InGaAs system of the fourth HEMT in the prior art.
Fig. 7 is a sectional view showing a conventional DMT.
Fig. 8 is a sectional view o$ a FET with refer~nce to first and the second embodiments according to the present invention.
Figs. 9A, 9B and 9C are sectional views of processing steps showing a method of producing a FET
with reference to the first and the second embodiments as shown in Fig. 8.
Fig. 10 shows an energy band adjacent to a channel of the FET with reference to the first embodiment.
Fig. 11 shows an energy band adjacent to a channel o~ the FET with reference to the second embodiment.
Fig. 12 is a sectional view of a FET with reference to the third and the fourth embodiments according to the present invention.
Figs. 13A, 13B and 13C are sectional views o~
processing steps showing a method of producing a FET
; - ,; :
: ~ .. . . : -~r ~.~ r;,2 1 with re~erence to the third and the ~ourth embodiments as shown in Fig. 12.
Fig. 14 shows an energy band adjacent to a channel of the FET with re~erence to the third and the fourth embodiments.
Description o~ the Preferred Embodiment Fig. 8 shows a structure of a FET according to a first embodiment o~ the present inven-tion. A method o~
producing the same is shown by a sectional view o~
processing steps in Fig. 9, which is described below.
On a semi-insulative InP semiconductor substrate 31 there are sequentially epitaxially grown a first semiconductor layer 32, a channel layer 33, a second semiconductor layer 34, a third semiconductor layer 35, and a contact layer 36 (see Fig. 9A). The epitaxial growth is carried out by an MBE (molecular beam epitaxy) method or an OMVPE (organic metal vapor phase epitaxy) method.
The first semiconductor layer 32 is made of undoped InP with thickness o~ 1 ~m. The channel layer 33 is made of n+ type InP doped by Si at a concentration of 2 x 1013/cm3, the thickness being 100 A. The second semiconductor layer 34 is made of undoped InP with a thickness of 200 ~ and having a higher electron carrying characteristic than the channel layer 33. The third semiconductor layer 35 is . ., . , : -, ~,,, . .~
;~ ~ <J 9 . ~ ~ r ~IJ
1 made o~ undoped AlxIn~lAs having a -thickness of 200 A with an Al composition ratio X o~ 0.4 or more and 0.6 or less (0.4 ~ x < 0.6). The contact layer 36 is made of nt type InGaAs having a thickne.ss of 500 R with donors doped at a concentration of 4 x 1018/cm3.
Here the channel layer 33 has carrier density and thickness enough to form a quantum well that will be described later. Electrons within the channel layer 33 have energy, therefore they exist in a slightly more expanded region than the thickness of the channel layer 33. In view of this, the second semiconductor layer 34 disposed on the channel layer 33 has a thickness allowing the expanded region of the electrons may no-t reach the third semiconductor layer 35.
That is, the energy band adjacent with the channel of -the first semiconductor layer 32, the channel layer 33, and the second semiconductor layer 34 will take a structure as shown in Fig. 10. The drawing on its lef-t shows the surface of the substrate, and the center portion corresponds to a channel doping surface. The channel layer 33 having higher density with thinner structure is sandwitched on its both sides by the semiconductor layers 32 and 34, the thickness being as thin as 100 A, a conducting band produces a bent portion to form a V like potential to form a quantum well as shown in the drawing. Incidentally, the channel layer 33 is made to have a thickness of 100 ~, z~
.q~r.J
1 but -~or ~orming the quantum well on the conducting band, the channel layer may preferably have a certain specific thinness, ~or example, 200 ~ or less.
The electrons in the channel layer when being at a ground state exist in the lowest subband EA. By obtaining energy when an electric -~ield is applied, -the electrons are sequentially transferred to a second subband EB and a third subband EC positioned above the subband EA, and move successively to higher energy 10 leveled subbands.
An existential probability o-~ electrons represents expansion of a wave function at the respective subbands as in Fig. 10, and approximates zero at the slightly more expanded portion than the thickness o~ the channel layer 33. The undoped InP layer at the substrate sur~ace or the second semiconductor layer 34 has a thickness such that the electrons existing in the expanded region may not reach the third semiconductor layer 3~.
2n The third semiconductor layer 3~ is formed by Schottky contact with the gate electrode to be described later (see Fig. 9A). The semiconductor layer 35 has a thickness enough to prevent the current ~lowing from the gate electrode to the second semiconductor 34 by a tunnel effect. The third semiconductor layer 3~, the second semiconductor layer 3~, and the channel layer 33, while their respective ,, , . ... :.. : ::, . ;: . :.. . :: :: : . ~ -~ a3~"" ~ r~
l thickness sa-tisfies the conditions relating to layer thickness hereinbe-~ore described, provide a total thickness of such layers thin enough to satis-~y o~erational characteristic of the FET. Such total ~hickness may pre~erably be 500 A or less. The topmost contact layer 36 is to protect the substrate sur~ace :
and to take ohmic-contact with the drain and source electrodes as hereinafter described and has no relation with the essence o~ the invention.
After such layers are sequentially ~ormed on the semiconductor substrate 31, the topmost contact layer 36 is ~ormed thereon with AuGe/Ni metal. Next, an ohmic electrode pattern is ~ormed using an ordinary photolithography techni~ue, and a drain electrode 37 and a source electrode 38 ohmic-contacting with the contact layer 36 are ~ormed (see Fig. 9B~. The contact layer 36 centered between the drain electrode 37 and the source electrode 38 is selectively removed by etching, to ~orm a recess 39 (see Fig. 9C).
Next there is formed a gate electrode 40 made of Ti/Pt/Au metal in Schottky contact with the third semiconductor layer 35 being exposed at the recess 39.
As a result a FET is completed having a s-tructure as shown in Fig. 8.
In the structure aforementioned, with voltage applied across the drain electrode 37 and source elec-trode 38, an electric ~ield is applied on electrons , . ,. .; , , ;; " ,v,, : :
, q~ ~ c~r, ~
1 in the channel layer 33. The electrons distributed in the subband EA move to -the higher energy level subb~nd EB by the energy given by the applied electric ~ield. In the subband EA at -the lowest position, the existential probability of elec-trons is high at the center portion of the channel layer 33 as shown by -the expansion o~
the wave ~unction in Fig. 10, electron speed is thereby lowered largely a~ected by the scattering o~ impurity.
However, in the subbands EB and EC above the subband EA, the existential probability o~ electrons has a peak value shi~ted from the center portion as shown in the drawing, thus being hardly a~ected by the scattering o~ impurity. As a result, the travelling speed o~
electrons in the channel layer 33 distributed in the subbands EB and EC with higher energy levels becomes increased.
When voltage applied across the drain and source is increased, a ~urther higher electric ~ield is applied to the electrons in the channel layer 33. Thus the electrons sequentially move to a even higher energy level subband to ~inally rush out from V shape potential into the first semiconductor 32 and second semiconductor 34 both sandwiching the channel layer 33.
In this process, the amount o~ electrons rushing out is far greater in the second semiconductor layer 34 disposed on the channel layer 33, which allows the electrons to mostly travel in that second semiconductor : . : .: ' : . :
~ .. ,;. , . ~ ,: :: : . , . ::
~ ~0~
1 layer 34. I~he layers 32 and 3~ sandwiching the channel layer 33 are undoped and in addition a higher electron carrying characteristic is given to the second semiconductor layer 34 therefore it becomes the essential passage of the electrons. Thus even when a highly doped channel layer 34 easily affected by impurity scattering is used, although the mobility of electrons is lower under low electric field compared with conventional HEMT, a high frequency characteristic is exhibited equivalent to or higher than that of HEMT
in actual operation of the device under a high electric field.
Also in the FET according to the present embodiment, the third semiconductor layer 35 and the channel layer 33 made of AlInAs are positioned at intervals more than a distance of the expansion of the wave function of the electrons in the channel layer 33 as described above. For this reason, deterioration of -the high-frequency carrying characteris-tic due to the actual space transition does not arise like the conventional first HEMT as hereinbefore described in which -the AlInAs layer having ~n inferior electron carrying characteristic and the channel layer made of InP both are in close vicinity with each other. In the conventional first HEMT a mutual conductance characteristic gln against change of a gate voltage Vg had a peak of value gm for a certain specific gate . - ' ~ ': ' .' :7 ~ ~ .J ~ g r ~1 1 voltage value. However, in the mutual conductance characteristic in this embodiment, a peak of value gm is maintained ~or the change of the gate voltage within a certain variation range. Therefore according to the embodiment, the designing of FET becomes easier and with a stable FET characteristic made possible to be obtained, a higher gain can be always secured, thus resulting in an output wi-thout distortion.
The channel layer 33 has thickness of a certain lG extent and has a structure being possible to dope impurity at a higher concentration, therefore the channel is formed of a large amount of electrons. This permits a far more excellent current drive capability compared with the conventional first HEMT wherein the current drive capability is limited by the upper limit of concentration of the two-dimensional electron gas.
The gate electrode 40 is in Schottl~y contact with the third semiconductor layer 35 made of undoped AlInAs. This makes a Schottky barrier higher and enables to operate the device at higher-bias condition, resulting in improved output characteristic.
Furthermore, the noise reduction performance is improved because of higher speed of the electrons travelling in the channel.
Therefore, the FET of the embodiment is effective when applied to a basic structure of super high frequency, high output elemen-ts with low noise.
' ,, ',, . `: : ', r~
1 In the first embodiment, it has been explained that the third semiconductor layer 35 made o~ AlInAs is ~ormed on the second semiconductor layer 34 made of InP. However, it is generally considered as dif~icult to maintain a good intereace crystallinity between AlInAs and InP. For this reason, an undoped InGaAs thin layer may be formed between the second semiconductor layer 34 and the third semiconductor layer 35 which will exhibit the same result as the embodiment described above.
It also has been explained that the first and second semiconductor layers 32 and 34 sandwiching the channel layer 33 are to be undoped InP. However it is not necessarily limited to such ma-terial. Other materials may be employed ~or example, the undoped InGaAs having a higher electron carrying characteristic with a crystalline structure substantially lattice matching the channel layer 33 which will exhibit the same e~fect as the embodiment abovementioned. Further, because the electrons forming the channel essentially travel in the second semiconductor layer 34, the first semiconductor layer 32 does not always have to be the same material as the second semiconductor layer 34 and may be a material having a crystalline structure substantially lattice-matching the semiconductor substrate 31 and the channel layer 33.
~ Wr~
1 The present invention is now described ~or a ~ET
according to a second embodiment. A structure of the FET o~ the second embodiment is similar to the FET of the first embodiment as shown in Fig. ~. A method o+' producing the same is also similar to the first embodiment and is produced through the same producing process in Fig. 9. A di~erence between the FETs of the ~irst and second embodiments is the difference in materials forming the respective layers.
In this embodiment, a semi-insulative GaAs semiconductor substrate is used instead of the semi-insulative InP semiconductor substrate 31, the respective layers hereinafter described being sequentially and epitaxially grown on the semi-insulative GaAs semiconductor substrate.
The ~irst semiconductor layer 32 made of the undoped InP is replaced by a new first semiconductor layer which is made of substantially undoped p type GaAs with thickness of 1 ~m the same as that o~ the previous first semiconductor layer 32. The substantially undoped state may preferably mean an impurity concentration of 5 x 1017/cm3 or less. The channel layer 33 made of the n type InP is replaced by a new channel layer, which is formed o~ nt type GaAs doped with Si at a concentration of 2 x 101~/cm3 having the same thickness o~ 100 A as the ~ormer channel layer 33. The second semiconductor layer 34 made of undoped 1 InP is rep].aced by a new second semiconductor layer, which is made oE substantially undoped n type GaAs having a higher electron carrying characteristic than that of the channel layer and having a thickness of 200 A the same as the ~ormer second semiconductor layer 34.
The third semiconductor layer 35 made of undoped AlInAs is replaced by a new third semiconductor layer, which is made of substantially undoped n type AlxGalxAs having composite ratio X of Al of above zero and 0.3 or less (0 < X ~ 0.3) with thickness of 200 A the same as that of the third semiconductor layer 35. The contact layer 36 made of the n+ type InGaAs is replaced by a new contact layer, which is made of n+ type GaAs doped with donors at a concentration of 4 x 1018/cm3 with -thickness of 500 ~ the same as that of the former contact layer 36. A gate electrode and an ohmic electrode are ~ormed o~ the same materials as those of the first embodiment. .
An energy band adjacent to a channel of the FET
according to the second embodiment has a structure the same as the ~irst embodiment as shown in Fig. 11. Also in this second embodiment, the channel layer being made of the n+-GaAs having a high concentration and formed in thin layer, the both sides of the channel layer are sandwiched by the first and second semiconductor layers made of substantially undoped GaAs with a thickness as thin as 100 A. Thus a bent portion is produced in a .J r 5~
1 conduction band to ~orm a V shape potential to make up a quantum well shown in the drawing. The electrons in the n+-GaAs channel in -the embodiment ~lso move sequentially to a higher energy level subbands by obtaining energy by an electric field being applied.
In the second embodiment, as in the first embodiment, in the higher energy level subbands EB and EC the peak o~ existential probability Oe electrons is shifted from the center portion, therefore the electrons in the channel layer are hardly a~ected by scattering o~ impurity, resulting in a higher travelling speed o~ the electrons.
I~ voltage applied across the drain / source is increased, the electrons in the channel layer ~inally rush out ~rom the V shape potential into the ~irst and second semiconductor layers made of substantially undoped GaAs and sandwiching the channel layer. In this process, the amount of electrons rushing out is ~ar greater in the second semiconductor layer excelling in carrying characteristic which is disposed on the channel layer, and hence as in the first embodiment the electrons in the channel layer become travelling at high speed. There~ore also in the second embodiment, even when a highly doped channel layer made o~ n+ type GaAs which is easily a~ected by scattering o~ impurity is used, although the electron mobility is low under a low electric field compared with a conventional HEMT, a . ,~ .~r~
1 high frequency characteristic equivalent to or more satisfactory than that of the HEMT is exhibited under the higher electric field in which the device is actually operated.
Also in the FET of the second embodiment, the third semiconductor layer made of AlGaAs and the channel layer made of GaAs are positioned at interval of a distance more than the expansion of the wave function of the electrons in the channel layer. Thus a deterioration o~ high-frequency characteristic due to the actual space transition is not produced like the conventional second HEMT or DMT having a structure where the AlGaAs layer with an inferior carrying characteristic o~ electrons is in close vicinity with the channel layer. The mutual conductance characteristic of FET in this second embodiment, also has a characteristic to maintain a peak value gm for a change of the gate voltage limited within a certain variation range. Therefore also in the second embodiment, the designing of FET is made easier and the obtained FET characteristic being stable to always secure a higher gain, an output without distortion can be obtained.
Because the channel layer formed of the n+ type GaAs has a thickness of a certain extent the channel layer can be doped with impurity at high concentration, therefore in the second embodiment also the channel is ::
,- ... , ~
;
2 ~ ~ $1 ~ 3 r ~
1 formed o~ a large amount o~ electrons. Thus, a ~ar superior current drive capability can be obtained comparing with the conven-tional second HEMT where the current drive capability is limited by the upper limit of concentration of the two-dimensional electron gas.
In addition the gate electrode being in Scho-ttky contact with the third semiconductor layer made o~
substantially undoped AlGaAs, also in the second embodiment the Schottky barrier becomes higher. In view of this, the device can be operated under the condition of a large bias, resulting in upgraded output characteristic. The noise reduction characteristic also is improved because of a higher electron speed travelling in the channel.
The FET according to the second embodiment also is effective when applied to the basic structure of super high ~requency, high output elements with lower noise.
Incidentally, it has explained in the second embodiment that the first and second semiconductors sandwiching the channel layer are to be undoped GaAs, however it is not necessarily limited to such material.
Other materials may be employed, ~or example, an undoped InGaAs having a higher electron carrying characteristic with a crystalline structure ;
substantially lattice-matching the channel layer which will exhibit the same e~fect as the second embodiment mentioned above. Furthermore, because the elec-trons ~ .J ~
1 forming the channel essentially -travel in the second semiconductor layer made oY substantially undoped GaAs, the first semiconductor layer does not necessarily have to be of the same material as the second semiconductor layer and may have a crystalline s-tructure substantially lattice-matching the GaAs substrate and the n type GaAs channel layer.
The present invention is now described for a F~T
according to a third embodiment. Fig. 12 shows a structure o~ the FET according to the third embodiment of the present invention. A method o~ producing the same is shown in sectional views o~ a production process in Fig. 13. The method o~ producing in -this case is as ~ollows.
On a semi-insulator InP semiconductor substrate 41 there are sequentially and epitaxially grown a buffer layer 42 ~or lattice-matching the substrate 41, a first semiconductor layer 43, a channel layer 44, a second semiconductor layer 45, a third semiconductor layer 46, and a contact layer 47 (see Fig. 13A). This epitaxial growth is carried out by the MBE method or OMVPE method as in the respective embodiments abovementioned. - ;.
The buffer layer 42 for lattice-matching the substrate 41 is made of undoped AlInAs wi~h a thickness o~ 1 ~m. The ~irst semiconductor layer 43 made o~
undoped InyGa1yAs having a composition ratio Y o~ In o~
0.45 or more and 0.65 or less (0.45 ~t Y ~ 0.653 and a t . 'j:
. ,' ' ~ , - , :
.. . ..
2~
1 thickness of 100 A. The channel layer 44 is made of n+
type InyGa1yAs (0.4~ ~ Y < 0.65) doped with Si at a concentration o+~ 2 x 1018/cm3 with a thickness o~ 100 A.
The second semiconductor layer 45 is made o~ undoped InyGalyAs (0.45 ~ Y ~ 0.65) having a thickness of 100 A
and a h.igher electron carrying characteristic than that of the channel layer 44. The third semiconductor layer 46 is made of undoped AlxInlxAs having a composition ratio X of Al of 0.4 or more and 0.6 or less (0.4 ~ X ~
0.6) and a thickness of 200 ~. The contact layer 47 is made of n+ type InGaAs doped with donors at a concentration of 4 x 1018/cm3 with a thickness of 500 A.
Here, the channel layer- 44 has carrier density and thickness enough to form a quantum well as in the first and second embodiments as hereinbefore described.
Because the electrons in the channel layer 44 have energy they exist in a region slightly more expanded than the thickness of the channel layer 44. For this reason, the second semiconductor layer 4~ disposed on the channel layer 44 has a thickness allowing the . .
expanded region of the electrons will not reach the third semiconductor layer 46.
An energy band adjacent to a channel of the FET
according to the third embodiment has a structure the same as the respective embodiments as shown in the Fig.
14. Also in this third embodiment, the channel layer 44 made of n-Iny~a1yAs having a high concentration and ,, ;, ... .:: . , .::
q,~
~ . -f ~
1 thinly formed, both sides o~ the channel layer 44 are sandwiched by the ~irst and second semiconductor layers 43 and 45 made of undoped InyGa1yAs with a thickness of as thin as 100 ~. Thus a bent portion is formed in a conduction band to produce a V shape potential and to provide a quantum well as shown in the drawing. Also in the third embodiment, the thickness of the channel layer 44 is preferred to have a certain thinness enough to form a quantum well at the conduction band, for example, 200 A or less. Also, the second semiconductor layer 45 has a thickness allowing the electrons expanded into the channel layer 44 not to reach the third semiconductor layer 46.
The gate electrode to be described la-ter is formed by being in Schottky contact with the third semiconductor layer 46, which has a thickness enough to prevent the current flowing from the gate electrode to the second semiconductor layer 4~ by a tunnel effect.
The third semiconductor layer 46, the second semiconductor layer 45, and the channel layer 44 while satisfying the respective conditions relating to the layer thlckness as abovementioned, the total thickness thereof is thin enough to satisfy the operational performance of the FET. Such total thic~ness may preferably be ~00 R or less. The contact layer 47 being the topmost layer is provided for protecting the substrate surface and for making ohmic contact with the . ~ ., ., . -. i , . :
,:
:
: , , . : . . ~ ,- ,: .
2~ '.h ~
1 drain / source electrodes. Hence that contact layer has no relation to the essence of the invention.
Next, after the respective layers have been sequentially formed on the semiconductor substrate 41 as hereinbefore described, AuGe/Ni metal is ~ormed on the contact layer 47 being the topmos-t layer. An electrode pattern is formed using an ordinary photolithography technique, and a drain electrode 48 and a source electrode 49 are formed in ohmic contact with the contact layer 47 (see Fig. 13B). Next, the contact layer 47 centered between the drain electrode 48 and source electrode 49 is selectively removed by etching to form a recess 50 (see Fig. 13C).
In the next process, there is ~ormed a gate electrode 51 made of Ti/Pt/Au in Schottky contact with the third semiconductor layer 46 exposed at the recess 50. As a result the FET having a structure as shown in Fig. 12 is completed.
Also in the present embodiment, the electrons in the channel layer 44 made of n~-InyGa1 ~s move successively to higher energy level subbands by obtaining energy from an electric field being applied.
Therefore, also in this third embodiment, same as in the respective previous embodiments, because the peak o~ an existential probability o~ the electrons is being shifted from the center portion at the higher energ~
level subbands EB and EC, the elec-trons in the channel :- . ,. : ,;: .
1 layer 4~ are hardly affected by scattering of impuri-ty, resulting in a higher travelling speed of the electrons.
If voltage applied across the drain / source is raised, the electrons in the channel layer 44 finally rush out from the V shape potential into -the first and second semiconductor layers 43 and 4~ made of undoped InyGa1yAs sandwiching the channel layer 44. In this process, the amount of electrons rushing out is far greater in the second semiconductor layer 4~ excelling in electron carrying characteristic and disposed on the channel layer 44, hence as in the respective embodiments hereinbe~ore described the electrons in the channel become -travelling at a high speed. Therefore also in the third embodiment, even when a highly doped channel layer 44 made of the n~ type InyGalyAs easily affected by scattering of impurity is used, a high-frequency characteristic equivalent to or superior than that of the HEMT is exhibi-ted under a higher electric field in which the device is actually operated, although the electron mobility at a low electric field is lower comparing with that of the conventional HEMT.
Also in the FET of the third embodiment, the third semiconductor layer 46 made of AlInAs and the channel layer 44 made of n+ type InyGalyAs are positioned at interval of a distance more than the expansion of the - : ~
: , ~
1 wave function of the electrons in the channel layer 44.
Therefore a deterioration of high-frequency charac-teristic due to the actual space transition i5 not produced like the conventional third HEMT having a structure where the AlInAs layer with an inferior carrying characteristic of electrons is in close ~icinity of the channel layer. Also in the mutual conductance characteristic o~ FET according to the third embodiment, it has a characteristic of a peak o~
gm value is maintained against the change of the gate voltage having a certain variation range. Therefore according to the third embodiment also, the designing of FET is easier and with a stable FET characteristic ~ ~' obtained, a higher gain is always secured, as a result an output without distortion is obtained.
The channel layer 44 formed of the n+ type InyGa1yAs has a thickness of a certain extent so that the channel layer 44 can be doped with impurity at a high concentration, therefore in the third embodiment also the channel is formed of a large amount of ~-electrons. Thus, ~ar superior current drive capability can be obtained compared with the conventional third HEMT wherein the current dri~e capability is limited by the upper limit o~ concentration of the two-dimensional electron gas.
In addition, the gate electrode 51 being in Schottky contact with the third semiconductor layer 46 ~0 . j . - : . .
Z~ 7~
1 made of undoped AlInAs, in the third embodiment also the Schottky barrier becornes high. Therefore the device can -thus be operated under the condition of high bias which upgrades the output characteristic.
Furthermore the noise reduction characteristic also is improved because of a higher electron speed when travelling in the channel.
In view of above, the FET according to the third embodiment is effective i~ applied to the basic structure of elements requiring super-high frequency and large output with lowered noise.
It has been explained in the third embodiment that the first and second semiconductor layers 43 and 45 sandwiching the channel layer 44 to be an undoped InGaAs. However it is not necessarily limited to such material in this embodiment. Other materials may be employed, for example, the undoped InP having a higher electron carrying characteristic with a crystalline structure substantially lattice-matching the channel layer 44 which will exhibit the same effect as the third embodiment abovementioned. Furthermore, because the electrons forming the channel essentially travel in the second semiconductor layer 45 made o~ undoped InGaAs, the first semiconductor layer 43 does not necessarily have to be the same material as the second semiconductor layer 45 and it may be a material having a crystalline structure substantially lattice- matching - ., ~ , 2~
1 the InP semiconductor substrate 41 and -the n+ type InGaAs channel layer 44.
The present invention is now described for a FET
according to a fourth embodiment. Fig. 12 also shows a structure of the ~ET according to the fourth embodiment of the present invention. A method of producing the same is similar to that of the third embodiment as shown in Fig. 13, and produced through similar processing steps as shown in Fig. 13. Difference between the FETs according to the fourth and third embodiments is the difference in materials forming respective layers.
A semi-insulative GaAs semiconductor substrate is used instead of the semi-insulative InP semiconductor 5 substrate 41, and following layers are sequentially epitaxially grown on the semi-insulative GaAs , semiconductor substrate.
The buffer layer 42 made of undoped AlInAs for lattice-matching the substrate 41 is replaced by another buffer layer which is made of undoped GaAs with a thickness of l ~m the same as the former buffer layer 42. The first semiconductor layer 43 made of the undoped InyGa1yAs (0.45 ~ y ~ 0.65) is replaced by a new first semiconductor layer, which is made of undoped InyGa1yAs having a composition ratio "y" of In of zero or more and 0.35 or less (0 ~ y ~ 0.35) with a thickness of 50 A. The channel layer 44 made of the n+
1 type InyGa1yAs (0.45 ~ y < 0.65) is replaced by a new channel layer, which is made of n+ type InyGa1 ~s (0 ~ y ~ 0.35) doped with Si at a concentration of 2 x 1018/cm3 having a thickness o~ 100 A the same as that of the former channel layer 44. The second semiconductor layer 45 made o~ the undoped InyGalyAs ~0.45 < y ~ 0.65) is replaced by a new second semiconductor layer, which is made of undoped InyGa1yAs (0 ~ y < 0.35) having a higher electron carrying characteristic than that of the channel layer and a thickness of 100 A the same as the former second semiconductor layer 45. The third semiconductor layer 46 made o-E the undoped AlxInlxAs (0.4 ~ X < 0.6) is replaced by a new third semiconductor layer, which is made of undoped AlxGalxAs having a composition ratio X of Al o~ zero or more and 0.3 or less (0 ~ X S 0.3) and a thickness of 200 A the same as that of the former third semiconductor 46.
Also, a new contact layer is formed with the same materials and thickness as those of the former contact layer 47 made of the n+ type InGaAs. A gate electrode and an ohmic electrode are formed in likewise manner and with the same materials as those of the third embodiment.
An energy band adjacent to a channel of the FET
according to the fourth embodiment has a structure the same as the third embodiment as hereinbefore described ~;
in Fig. 14. Also in this fourth embodiment, the "- ~ ' . ' ' :' ' ~ '~. '` .: ' ' . '', ' '' 1 channel layer made o~ high concentration and thinly formed n~-InyGa1 ~s layer, both sides of the channel layer are sandwiched by the first and second semiconductor layers made of the undoped InyGa1yAs and formed thinly to a thickness of 100 ~. Thus a bent portion is produced in a conduction band to form a V
shape potential and to provide a quantum well shown in the drawing. In the present embodiment, the electrons in the channel layer made of n+-InyGa1yAs also move successively to a plurality of higher energy level subbands by obtaining energy from an electric field being applied. Therefore in the fourth embodiment also, as in the respective previous embodiments, since the peak of an existential probability of the electrons is shifted from the center portion at the higher energy level subbands EB and EC, the electrons in the channel layer is hardly affected by scattering of impurity, thus resulting in a higher travelling speed of electrons.
If voltage impressed across the drain / source is raised, the electrons in the channel layer finally rush out from the V shape potential into the first and second semiconductor Iayers made of undoped InyGa1yAs sandwiching the channel layer. In this process, the amount of electrons rushing out is far greater in the second semiconductor layer excelling in electron carrying characteristic and disposed on the channel . ' ' ~ ' .'' ' ' ~.'' ' ' j ; ' 1 layer, as in the respective embodiments hereinbe~ore described, and the electrons in the channel become travelling at a high speed. I'herefore also in the fourth embodiment even when a highly doped channel layer made of n~ type InyGa1yAs easily affected by scattering of impurity is used, a high-frequency characteristic equivalent to or superior than that of the HEMT is exhibited under high electric field in which the device is actually operated although the , electron mobility at a low electric ~ield is lower comparing with that of the conventional HEMT.
Also in the FET o~ the fourth embodiment, the third semiconductor layer made of AlGaAs and the channel layer made of the nt type InyGa1yAs are positioned at interval of a distance more than -the expansion o~ the wave function of the electrons in the channel layer. Thus a deterioration of high-frequency characteristic due to the actual space transition is not produced like the conventional fourth HEMT having a structure where the AlGaAs layer with inferior carrying characteristic of electrons is in close vicinity with the channel layer. The mutual conductance characteristic of FET according to the fourth embodiment, also has a characteristic of a peak of value ~ gm is maintained against the change of the gate voltage having a certain variation range. Therefore also by the fourth embodiment, the designing o~ FET is ~: . ,, :,:~ ~ ., J : ~ :
~,C^~3r:,"r,'l;"
1 made easier and with a stable FET characteristic obtained, a higher gain is always secured, thus resulting in an output without distortion.
The channel layer formed of the n type InyGa1 ~s has a thickness of certain extent so that the channel layer can be doped with impurity a-t a high concentration, hence also in the fourth embodiment the channel is ~ormed o~ a large amount of electrons.
Thus, far superior current drive capability can be , obtained comparing with the conventional fourth HEMT
wherein the current drive capability is limited by the upper limit of concentration of the two-dimensional electron gas.
The gate electrode being in Schottky contact with the third semiconductor layer made of undoped AlGaAs, the Schottky barrier in the fourth embodiment also becomes high. The device can thus be operated under a high bias condition which upgrades the output characteristic. The noise reduction characteristic also is improved because the travelling speed of electron in the channel becomes higher.
The FET according to the fourth embodiment is effective when applied to the basic structure using elements requiring a super high-frequency and large output with lowered noise.
In the fourth embodiment it has explained that the first and second semiconductor layers sandwiching the : , . ~ ~ , .
.. . . ~ : : .
r~
1 channel layer are to be undoped InGaAs. However it is not necessarily limited to such material. Other materials may be employed, ~or example, the undoped GaAs having a higher elec-tron carrying characteristic with a crystalline structure substantially lattice-matching the channel layer which will exhibit the same ef~ect as the ~ourth embodiment described above. E'urthermore, because the electrons ~orming the channel essentially travel in the second semiconductor layer made o~ undoped InGaAs, the first semiconductor layer does not have to be necessarily the same material as the second semiconductor layer and it may have a crystalline structure substantially lattice-rnatching the GaAs semiconductor substrate and the n~ type InGaAs channel layer.
From the invention thus described, it will be obvious that the invention may be varied in many ways.
Such variations are not to be regarded as a departure ~rom the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.
Claims (19)
1. A field effect transistor comprising:
a first semiconductor layer;
a channel layer having a crystalline structure substantially lattice-matching the first semiconductor layer, the channel layer being thinly formed containing an "n" type impurity at a high concentration;
a second semiconductor layer having a crystalline structure substantially lattice-matching the channel layer, the second semiconductor layer being lightly doped with impurity made of materials with a higher electron carrying characteristic than that of the channel layer; and a third semiconductor layer in heterojunction with the second semiconductor layer, the third semiconductor layer being lightly doped with impurity and being in Schottky contact with a gate electrode.
a first semiconductor layer;
a channel layer having a crystalline structure substantially lattice-matching the first semiconductor layer, the channel layer being thinly formed containing an "n" type impurity at a high concentration;
a second semiconductor layer having a crystalline structure substantially lattice-matching the channel layer, the second semiconductor layer being lightly doped with impurity made of materials with a higher electron carrying characteristic than that of the channel layer; and a third semiconductor layer in heterojunction with the second semiconductor layer, the third semiconductor layer being lightly doped with impurity and being in Schottky contact with a gate electrode.
2. A field effect transistor as claimed in claim 1, wherein the first semiconductor layer is formed on a semiconductor substrate.
3. A field effect transistor as claimed in claim 1, wherein the field effect transistor further comprises a semiconductor substrate, and a buffer layer formed on the semiconductor substrate, the first semiconductor layer is formed on the buffer layer.
4. A field effect transistor as claimed in claim 1, wherein the first semiconductor layer is lightly doped with impurity.
5. A field effect transistor as claimed in claim 1, wherein the field effect transistor further comprises a contact layer formed on the third semiconductor layer and an ohmic electrode formed on the contact layer.
6. A field effect transistor as claimed in claim 1, wherein the gate electrode is formed on a recess formed on the third semiconductor layer.
7. A field effect transistor as claimed in claim 1, wherein the channel layer is made of InP, and the third semiconductor layer is made of AlXIn1XAs with a composition ratio X of Al of 0.4 or more and 0.6 or less.
8. A field effect transistor as claimed in claim 1, wherein the field effect transistor further comprises, a semi-insulative InP semiconductor substrate, the first semiconductor layer is formed on said semi-insulative InP semiconductor substrate, the first semiconductor layer being made of undoped InP, the channel layer is formed on the first semiconductor layer, the channel layer being made of n+
type InP doped with Si at a high concentration, the second semiconductor layer is formed on the channel layer, the second semiconductor layer being made of undoped InP, and the third semiconductor layer is formed on the second semiconductor layer, the third semiconductor layer being made of undoped AlxInlxAs with a composition ratio X of Al of 0.4 or more and 0.6 or less, the field effect transistor further comprises:
a contact layer made of n type InGaAs formed on the third semiconductor layer, a gate electrode in Schottky contact with said third semiconductor layer exposed on a recess formed on the contact layer and said third semiconductor layer, and an ohmic electrode formed on said contact layer.
type InP doped with Si at a high concentration, the second semiconductor layer is formed on the channel layer, the second semiconductor layer being made of undoped InP, and the third semiconductor layer is formed on the second semiconductor layer, the third semiconductor layer being made of undoped AlxInlxAs with a composition ratio X of Al of 0.4 or more and 0.6 or less, the field effect transistor further comprises:
a contact layer made of n type InGaAs formed on the third semiconductor layer, a gate electrode in Schottky contact with said third semiconductor layer exposed on a recess formed on the contact layer and said third semiconductor layer, and an ohmic electrode formed on said contact layer.
9. A field effect transistor as claimed in claim 8, wherein a first semiconductor layer and a second semiconductor layer made of undoped InGaAs are provided instead of the first semiconductor layer and second semiconductor layer made of undoped InP.
10. A field effect transistor as claimed in claim 8, wherein an undoped InGaAs layer is provided between the second semiconductor layer and the third semiconductor layer.
11. A field effect transistor as claimed in claim l, wherein the channel layer is made of GaAs, and the third semiconductor layer is made of AlxGalxAs with a composition ratio X of Al of above zero and 0.3 or less.
12. A field effect transistor as claimed in claim l, wherein the field effect transistor further comprises, a semi-insulative GaAs semiconductor substrate, the first semiconductor layer is formed on the semi-insulative GaAs semiconductor substrate, the first semiconductor layer being made of substantially undoped p- type GaAs, the channel layer is formed on the first semiconductor layer, the channel layer being made of n+
type GaAs doped with Si at a higher concentration, the second semiconductor layer is formed on the channel layer, the second semiconductor layer being made of substantially undoped n- type GaAs, and the third semiconductor layer is formed on the second semiconductor layer, the third semiconductor layer being made of substantially undoped n-type AlXGa1-XAs with a composition ratio X of Al of above zero and 0.3 or less, the field effect transistor further comprises:
a contact layer made of n+ type GaAs formed on the third semiconductor layer, a gate electrode in Schottky contact with said third semiconductor layer exposed on a recess formed on the contact layer and said third semiconductor layer, and an ohmic electrode formed on said contact layer.
type GaAs doped with Si at a higher concentration, the second semiconductor layer is formed on the channel layer, the second semiconductor layer being made of substantially undoped n- type GaAs, and the third semiconductor layer is formed on the second semiconductor layer, the third semiconductor layer being made of substantially undoped n-type AlXGa1-XAs with a composition ratio X of Al of above zero and 0.3 or less, the field effect transistor further comprises:
a contact layer made of n+ type GaAs formed on the third semiconductor layer, a gate electrode in Schottky contact with said third semiconductor layer exposed on a recess formed on the contact layer and said third semiconductor layer, and an ohmic electrode formed on said contact layer.
13. A field effect transistor as claimed in claim 12, wherein a first semiconductor layer made of substantially undoped p- type InGaAs is provided instead of the first semiconductor layer made of a substantially undoped p-type GaAs, and a second semiconductor layer made of substantially undoped n- type InGaAs is provided instead of the second semiconductor layer made of substantially undoped n-type GaAs.
14. A field effect transistor as claimed in claim 1, wherein the channel layer is made of InyGa1-yAs with a composition ratio Y of In of 0.45 or more and 0.65 or less, and the third semiconductor layer is made of AlxInlxAs with a composition ratio X of Al of 0.4 or more and 0.6 or less.
15. A field effect transistor as claimed in claim 1, wherein the field effect transistor further comprises:
a semi-insulative InP semiconductor substrate, and a buffer layer made of undoped AlInAs for lattice-matching the semi-insulative InP semiconductor substrate, the first semiconductor layer is formed on the buffer layer, the first semiconductor layer being made of undoped InyGa1-yAs with a composition ratio Y of In of 0.45 or more and 0.65 or less, the channel layer is formed on the first semiconductor layer, the channel layer being made of n+
type of said InyGa1-yAs doped with Si at a higher concentration, the second semiconductor layer is formed on the channel layer, the second semiconductor layer being made of undoped said InyGa1-yAs, and the third semiconductor layer is formed on the second semiconductor layer, the third semiconductor layer being made of undoped AlxInlxAs with a composition ratio X of A1 of 0.4 or more and 0.6 or less, the field effect transistor further comprises:
a contact layer made of n+ type InGaAs formed on the third semiconductor layer, a gate electrode in Schottky contact with said third semiconductor layer exposed on a recess formed on the contact layer and said third semiconductor layer, and an ohmic electrode formed on said contact layer.
a semi-insulative InP semiconductor substrate, and a buffer layer made of undoped AlInAs for lattice-matching the semi-insulative InP semiconductor substrate, the first semiconductor layer is formed on the buffer layer, the first semiconductor layer being made of undoped InyGa1-yAs with a composition ratio Y of In of 0.45 or more and 0.65 or less, the channel layer is formed on the first semiconductor layer, the channel layer being made of n+
type of said InyGa1-yAs doped with Si at a higher concentration, the second semiconductor layer is formed on the channel layer, the second semiconductor layer being made of undoped said InyGa1-yAs, and the third semiconductor layer is formed on the second semiconductor layer, the third semiconductor layer being made of undoped AlxInlxAs with a composition ratio X of A1 of 0.4 or more and 0.6 or less, the field effect transistor further comprises:
a contact layer made of n+ type InGaAs formed on the third semiconductor layer, a gate electrode in Schottky contact with said third semiconductor layer exposed on a recess formed on the contact layer and said third semiconductor layer, and an ohmic electrode formed on said contact layer.
16. A field effect transistor as claimed in claim 15, wherein a first semiconductor layer and a second semiconductor layer made of undoped InP is provided instead of the first and second semiconductor layers made of the undoped InyGa1-yAs.
17. A field effect transistor as claimed in claim 1, wherein the channel layer is made of InyGa1-yAs with a composition ratio Y of In of zero or more and 0.35 or less, and the third semiconductor layer is made of AlxGa1-xAs with a composition ratio X of Al of zero or more and 0.3 or less.
18. A field effect transistor as claimed in claim 1, wherein the field effect transistor further comprises:
a semi-insulative GaAs semiconductor substrate, and a buffer layer made of undoped GaAs for lattice-matching the semi-insulative GaAs semiconductor substrate, the first semiconductor layer is formed on the buffer layer, the first semiconductor layer being made of undoped InyGa1-yAs with a composition ratio Y of In of zero or more and 0.35 or less, the channel layer is formed on the first semiconductor layer, the channel layer being made of said n+ type InyGa1-yAs doped with Si at a high concentration, the second semiconductor layer is formed on the channel layer, the second semiconductor layer being made of undoped said InyGa1-yAs, and the third semiconductor layer is formed on the second semiconductor layer, the third semiconductor layer being made of undoped AlxGa1-xAs with a composition ratio X of Al of zero or more and 0.3 or less, the field effect transistor further comprises:
a contact layer made of n+ type InGaAs formed on the third semiconductor layer, a gate electrode in Schottky contact with said third semiconductor layer exposed on a recess formed on the contact layer and said third semiconductor layer, and an ohmic electrode formed on said contact layer.
a semi-insulative GaAs semiconductor substrate, and a buffer layer made of undoped GaAs for lattice-matching the semi-insulative GaAs semiconductor substrate, the first semiconductor layer is formed on the buffer layer, the first semiconductor layer being made of undoped InyGa1-yAs with a composition ratio Y of In of zero or more and 0.35 or less, the channel layer is formed on the first semiconductor layer, the channel layer being made of said n+ type InyGa1-yAs doped with Si at a high concentration, the second semiconductor layer is formed on the channel layer, the second semiconductor layer being made of undoped said InyGa1-yAs, and the third semiconductor layer is formed on the second semiconductor layer, the third semiconductor layer being made of undoped AlxGa1-xAs with a composition ratio X of Al of zero or more and 0.3 or less, the field effect transistor further comprises:
a contact layer made of n+ type InGaAs formed on the third semiconductor layer, a gate electrode in Schottky contact with said third semiconductor layer exposed on a recess formed on the contact layer and said third semiconductor layer, and an ohmic electrode formed on said contact layer.
19. A field effect transistor as claimed in claim 18, wherein a first semiconductor layer and a second semiconductor layer made of undoped GaAs is provided instead of the first and second semiconductor layers made of undoped InyGa1-yAs.
Applications Claiming Priority (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP002790/1991 | 1991-01-14 | ||
| JP03002790A JP3122472B2 (en) | 1991-01-14 | 1991-01-14 | Field effect transistor |
| JP002791/1991 | 1991-01-14 | ||
| JP002789/1991 | 1991-01-14 | ||
| JP03002789A JP3122471B2 (en) | 1991-01-14 | 1991-01-14 | Field effect transistor |
| JP03002791A JP3122473B2 (en) | 1991-01-14 | 1991-01-14 | Field effect transistor |
| JP002792/1991 | 1991-01-14 | ||
| JP03002792A JP3122474B2 (en) | 1991-01-14 | 1991-01-14 | Field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2059232A1 true CA2059232A1 (en) | 1992-07-15 |
Family
ID=27453713
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002059232A Abandoned CA2059232A1 (en) | 1991-01-14 | 1992-01-13 | Field effect transistor |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US5436470A (en) |
| EP (1) | EP0495452A3 (en) |
| KR (1) | KR960000385B1 (en) |
| CA (1) | CA2059232A1 (en) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2914049B2 (en) * | 1992-10-27 | 1999-06-28 | 株式会社デンソー | Compound semiconductor substrate having heterojunction and field effect transistor using the same |
| JP2674539B2 (en) * | 1994-12-21 | 1997-11-12 | 日本電気株式会社 | Field effect transistor |
| US5693964A (en) * | 1995-07-31 | 1997-12-02 | Matsushita Electronics Corporation | Field-effect transistor and fabrication method |
| US5767539A (en) * | 1996-04-05 | 1998-06-16 | Nec Corporation | Heterojunction field effect transistor having a InAlAs Schottky barrier layer formed upon an n-InP donor layer |
| JP3058262B2 (en) * | 1996-11-28 | 2000-07-04 | 日本電気株式会社 | Heterojunction field effect transistor |
| JP3159198B2 (en) | 1999-02-19 | 2001-04-23 | 住友電気工業株式会社 | Field effect transistor |
| US6271547B1 (en) * | 1999-08-06 | 2001-08-07 | Raytheon Company | Double recessed transistor with resistive layer |
| US6797994B1 (en) | 2000-02-14 | 2004-09-28 | Raytheon Company | Double recessed transistor |
| US6515316B1 (en) | 2000-07-14 | 2003-02-04 | Trw Inc. | Partially relaxed channel HEMT device |
| KR100542685B1 (en) * | 2001-06-18 | 2006-01-16 | 매그나칩 반도체 유한회사 | Operational transconductance amplifier for output buffer |
| JP4765211B2 (en) * | 2001-07-06 | 2011-09-07 | 住友電気工業株式会社 | Pin type light receiving element |
| JP2004006461A (en) * | 2002-05-31 | 2004-01-08 | Nec Corp | Semiconductor device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6123364A (en) * | 1984-07-11 | 1986-01-31 | Agency Of Ind Science & Technol | Field effect transistor |
| JPS61198784A (en) * | 1985-02-28 | 1986-09-03 | Fujitsu Ltd | Field effect type semiconductor device |
| DE3689433T2 (en) * | 1985-08-20 | 1994-04-14 | Fujitsu Ltd | Field effect transistor. |
| JPS63218165A (en) * | 1987-03-06 | 1988-09-12 | Tosoh Corp | Alkaline electrolyte type formaldehyde fuel cell |
| JP2695832B2 (en) * | 1988-04-20 | 1998-01-14 | 株式会社東芝 | Heterojunction field effect transistor |
| US5091759A (en) * | 1989-10-30 | 1992-02-25 | Texas Instruments Incorporated | Heterostructure field effect transistor |
-
1992
- 1992-01-09 US US07/818,537 patent/US5436470A/en not_active Expired - Fee Related
- 1992-01-13 KR KR1019920000324A patent/KR960000385B1/en not_active IP Right Cessation
- 1992-01-13 CA CA002059232A patent/CA2059232A1/en not_active Abandoned
- 1992-01-14 EP EP19920100502 patent/EP0495452A3/en not_active Withdrawn
-
1995
- 1995-01-09 US US08/370,427 patent/US5508530A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| KR960000385B1 (en) | 1996-01-05 |
| US5508530A (en) | 1996-04-16 |
| KR920015643A (en) | 1992-08-27 |
| EP0495452A3 (en) | 1993-04-28 |
| EP0495452A2 (en) | 1992-07-22 |
| US5436470A (en) | 1995-07-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6177685B1 (en) | Nitride-type III-V HEMT having an InN 2DEG channel layer | |
| US5548129A (en) | Quantum well structure with self-aligned gate and method of making the same | |
| EP0514079B1 (en) | High electron mobility transistor and method of manufacture | |
| EP0477515B1 (en) | Heterojunction field effect transistor with monolayer in channel region | |
| JPH07335867A (en) | Field-effect transistor | |
| CA2059232A1 (en) | Field effect transistor | |
| US5596211A (en) | Field effect transistor having a graded bandgap InGaAsP channel formed of a two-dimensional electron gas | |
| JP3173080B2 (en) | Field effect transistor | |
| JPH0812916B2 (en) | Field effect transistor | |
| US5298441A (en) | Method of making high transconductance heterostructure field effect transistor | |
| JP2500453B2 (en) | Field effect transistor | |
| US5473175A (en) | Multi-2DEG HEMT | |
| US5453631A (en) | Field effect transistor having a multi-layer channel | |
| JP2758803B2 (en) | Field effect transistor | |
| US5408111A (en) | Field-effect transistor having a double pulse-doped structure | |
| JP2994863B2 (en) | Heterojunction semiconductor device | |
| JP2811753B2 (en) | Speed modulation type field effect transistor | |
| CA2055665C (en) | Field effect transistor | |
| JP3021894B2 (en) | Heterojunction field effect transistor | |
| JP2616634B2 (en) | Field effect transistor | |
| JPH0684959A (en) | High electron mobility field effect semiconductor device | |
| JP2764507B2 (en) | Power field effect transistor | |
| JP3122471B2 (en) | Field effect transistor | |
| GB2239557A (en) | High electron mobility transistors | |
| JP3122472B2 (en) | Field effect transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| FZDE | Discontinued |