CA2059476C - Electrically erasable phase change memory - Google Patents

Electrically erasable phase change memory

Info

Publication number
CA2059476C
CA2059476C CA002059476A CA2059476A CA2059476C CA 2059476 C CA2059476 C CA 2059476C CA 002059476 A CA002059476 A CA 002059476A CA 2059476 A CA2059476 A CA 2059476A CA 2059476 C CA2059476 C CA 2059476C
Authority
CA
Canada
Prior art keywords
phase change
electrically erasable
set forth
change memory
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA002059476A
Other languages
French (fr)
Inventor
Stanford R. Ovshinsky
Stephen J. Hudgens
Wolodymyr Czubatyj
David A. Strand
Guy C. Wicker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Energy Conversion Devices Inc
Original Assignee
Energy Conversion Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=24578871&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=CA2059476(C) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Energy Conversion Devices Inc filed Critical Energy Conversion Devices Inc
Application granted granted Critical
Publication of CA2059476C publication Critical patent/CA2059476C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Patterning of the switching material
    • H10N70/063—Patterning of the switching material by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/04—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using optical elements ; using other beam accessed elements, e.g. electron or ion beam

Abstract

An electrically erasable phase change memory utilizing a stoichiometrically balanced phase change material in which both the switching times and the switching energies required for the transitions between the amorphous and the crystalline states are substantially reduced below those attainable with prior art electrically erasable phase change memories. One embodiment of the invention comprises an integrated circuitimplementation of the memory in a high bit density configuration in which manufacturing costs are correspondingly reduced and performance parameters are further improved.

Description

The present invention relates to electrically erasable phase change memories .

BACKGROUND AND PRIOR ART

The general concept of utilizing electrically erasable phase change materials (i.e., materials which can be electrically switched between generally amorphous and generally crystalline states) for electronic memory applications is well known in the art and is disclosed, for example, in U.S. patent 3,271,591 - Ovshinsky, issued September 6, 1966 and in U.S. patent 3,530,441 - Ovshinsky, issued September 22, 1970, both assigned to the same ~signPe as the present invention.
As disclosed in the aforementioned Ovshinsky patents, such phase change m~trri~l~ can be electrically switched between two dirr~ t structural states of generally amorphous and generally crystalline local order or between different ~etect~ble states of local order across the complete spectrum between the completely amorphous and completely crystalline states. That is, the switching of such materials is not required to take place between completely amorphous and completely crystalline states but rather can be in incremental steps of local order changes to provide a "gray scale" represented by a multiplicity of conditions of local order across the spectrum between completely amorphous and completely crystalline states. The m~teri~l~ dessribed can also beswitched between only two structural states of generally amorphous and generallycrystalline local order to accommodate storage and retrieval of digital information.
The Ovshinsky electrically erasable phase change memories were fully adequate for many applir~tion~ at the time they were originally introduced and were utilized in a number of applications. However, because further development of that early technology was not possible because of lack of the necessary resources to carry the same forward, subsequent developments in other fields of solid state, electronic memories and in other types of memories in general, such as those lltili7ing m~ n~tic and op~cal media, gradually displaced that early electrically erasable phase change technology.
As a result of the aforementioned lack of ongoing development support, there areat the present time several limit~tions in the electrically erasable memory applications of the Ovshinsky phase change materials which have prevented their widespread use in electrically erasable phase change memories. One of these has been the relatively slow (by present standards) electrical switching speed which such prior art m~teri~l~ have exhibited, particularly in the direction of greater local order or in the direction of increasing cryst~lli7~tion. Another has been the relatively high energy required for initi~ting the phase change between one state and the other.
For example, the switching times of such prior art phase change materials are typically in the range of a few milli~econds for the set time from the amorphous state to the crystalline state and perhaps a microsecond or so reset time from the crystalline state back to arnorphous state. The electrical energy required to switch such prior art 10 m~t~ri~l~ was typically measured in the range of about a microjoule.
The concept of utili~ing the Ovshinsky phase change materials in non-erasable ornon-reversible, write-once electric~lly programmable memories is also well known in the prior art. This type of electrically programmable phase change memory is disclosed, for example, in U.S. patents 4,499,557 - Holmberg et al., issued February 12, 1985 and 4,599,705 - Holmberg et al., issued July 8, 1986, and assigned to the same assignee as the present invention. The aforementioned Holmberg et al. patents include tetrahedrally chemically bonded m~teri~l~ such as carbon, silicon and germanium and alloys thereof as phase change materials which are utilized in a non-reversible or non-resettable mode.
Such materials are 11icclose~ as having, for example, characteristics which require 20 threshold setting voltages of up to 10 volts, currents up to 25 milli~mps and setting times of up to 100 micr~secontl~. Thus, the set energy required is up to 250 milliwatts with set times up to 100 micr~secon~
Accordingly, because of the lack of ongoing development support, these materialshave not found widespread use in reversible or electrically erasable memory applications, where other types of memories offer substantially lower switching times and energies.
Instead, other forms of solid state, electronic memories have evolved and have enjoyed some limited use in these applications. These memories typically use several solid state microelectronic circuit elements for each memory bit, as many as three or four transistors per bit, for example, in some memory applications. The primary memory elements in 30 such solid state memories are typically floating gate field effect transistor devices which hold a charge on the field effect transistor gate to store a memory bit. Since this charge 2~9476 _ 3 can leak off with the passage of time, the storage of information is thus not truly non-volatile as it is in the phase change media where information is stored through changes in the actual structure of the material.
Such solid state, electronic memories which are presently in use are also relatively expensive to m~mlfacture and their cost is typically about twice the cost per bit of storage capacity in relation to magnetic disk storage. On the other hand, solid state, electronic memories have certain advantages over magnetic disk memories in that solid state memories have no moving parts, are easy to transport and store and are more versatile in their adaptability for use with portable colnpulels and other portable 10 electronic devices. In addition, such solid state memories are usually true random access systems as opposed to disk types which require physical movement of the disk head to the proper data track for ~ccessing the desired memory location.
However, in spite of such advantages of solid state electtically erasable memories, their substantially higher costs have prevented them from enjoying a substantial share of the market now dominated by disk type memory systems. Although solid state memories based on phase change m~tçnAl~ have shown potential for m~mlf~Gture at reduced costs, the perform~nce parameters available from such systems as known in the prior art have not been adequate to permit their widespread use as replacements for disk type systems or other solid state memory systems of the type described above.

SUMMARY OF THE INVENTION

The present invention provides a new solid state, erasable, electronic memory utilizing unique phase change materi~l~ in novel and specially adapted configurations which exhibit orders of m~nitllde higher switching speeds at energy levels which are remarkably reduced from those ~tt~in~hle in prior art systems. The new memory has stable and truly non-volatile structural states, which can be selected between two switchable structural states of detectably different local order for application to typical digital systems, or which can be selected from a number of inte~...c~li~tç structural states of detectably different local order to provide a gray scale of available memory setting conditions. The m~gnit~lde of the improvement in switching times and in switching - 4 2~59476 energies is truly enormous, being in the range of a number of orders of m~gnit~l-le and not just incremental in nature, and is totally unexpected and beyond what was thought possible with prior art m~teri~l~
One emb~iment of the invention utiliæs an electrically switchable material of a composition and stoichiometry such that the elements of the m~teri~l are distributed within the m~sçn~l in the amorphous state and are substantially fully absorbed per unit volume of the m~teri~l in one or more stable crystalline phases in the crystalline state.
The elçment~ are also preferably absorbed in the one or more crystalline phases with substantially the same local atomic density of the con~t~ ent elements as present in the 10 amorphous state. Migration of the elemç~ts within the material in the course of the switching tr~n~ition~ is thus minimi7e~ and both the switching times and energy levels are thereby very substantially reduced from those ~tt~in~hle in prior art electrically erasable phase change systems.
In another embodiment, the characteristics of the electrical switching parameters are generated relative to the m~teri~l transition parameters such that optimum switching transitions are provided, thereby further enh~n~ing pelrollllance relative to that ~tt~in~ble in the prior art.
In still another embodiment, a memory configuration lltili7ing the novel materials of the invention is set forth in which the bit density of the memory is greatly increased 20 and enh~nce l over prior art configurations and in which p~,lro. ~ nce parameters are further il~luved.
Other embodiments and features of the present invention as well as other advantages and objects thereof will be set forth and become ~pa~ent the detaileddescription which follows, taken in connection with the accompanying drawings.

DESCRIPTION OF THE DRAWINGS

Fig. 1 is a fr~gment~ry cross sectional view of a portion of an integrated circuit electrically erasable phase change memory configuration embodying the present invention;

Fig. 2 is a fragmentary cross sectional view of a portion of an integrated circuit electrically erasable phase change memory configuration illustrating another embodiment of the present invention;
Fig. 3 is a top plan view of a portion of the integrated circuit configurations of Figs. 1 and 2;
Fig. 4 is a partial circuit diagram of a portion of the circuitry of the integrated circuit configurations of Figs. 1 and 2;
Fig. 4A is a diagr~mm~tic~l illustration of a portion of a single crystal semiconductor substrate with integrated memory and addressing matrixes embodying the 10 present invention;
Fig. 5 is a graphical presentation of data taken on samples of electrically erasable phase change m~teri~l~ embodying the present invention and showing resistance in the crystalline state after switching from the amorphous state in relation to switching energy;
Fig. 6 is a graphical presentation of data on device resistance in relation to switching energy for different pulse widths;
Fig. 7 is a graphical present~tion of data relating to device "on" resi~t~nre as a function of the number of set pulses sequentially applied to the device and illustrating gray scale capability; and Fig. 8 is a graphical presentation of data relating to device "on" resi~tance as a 20 function of load resist~nce which controls current flow after firing of the device.

DETAILED DESCRIPIION OF THE INVENTION

We have discovered that while prior art erasable electrical phase change memories have been based on changes in local structural order, they have also typically ~ccommodated such structural changes by atomic movement of certain species within the material to permit phase separation as the material is ~wilchcd from the amorphous state to a multi-phase crystalline state. For example, in the case of electrically switchable chalcogenide alloys formed of tellurium and germanillm, such as those comprising about 80% to 85% tellurium and about 15% germanium along with certain other elements in small quantities of about one to two percent each, such as sulfur and arsenic, the more 6 2QS9~76 ordered or crystalline state was typically characteriæd by the formation of a highly electric~lly conductive crystalline Te filament within the switchable pore of the memory material. A typical composition of such a prior art material would be, for example, Te8lGel5S2As2. Another example of such a prior art material is Te8lGel5S2Sb2. Because Te is so highly conductive in its crystalline state, a very low re~i~t~nce condition was therefore established through the crystalline Te filament which was a number of orders of m~gnitu~le lower than the resiit~nce of the pore in the less ordered or amorphous state.
However, the form~tinn of the conductive Te fil~ment in the crystalline state 10 required migration of the Te atoms from their atomic configuration in the amorphous state to the new locally concentrated atomic configuration in the crystalline Te filament state. Similarly, when the material was switched back to the amorphous state, the Te which had precipitated out into the crystalline fil~ment was required to migrate within the material from its locally concentrated form in the fil~ment back to its atomic configuration in the amorphous state.
We have found that this atomic migration, diffusion or re-arr~ngemçnt between the amorphous and crystalline states required in each case a holding or dwell time necess~ry to accommodate the migration, thereby making the switching time and energy relatively high compared to other types of erasable sçmi.~on~luctor memories. We have 20 now discovered certain new principles which permit a rem~rk~ble improvement in both switching time and energy for this type of electrically erasable phase change memory.
One simple form of a material which meets the selection criteria of the present invention is Te52Ge24Sb24 average composition by atomic percent, which is distributed throughout the material in the amorphous state and which crystallizes into two crystalline phases of app~ ..ate compositions of Te52Gel8Sb~O for one phase and Tes2Ge30Sbl8 for the other phase which are present in about equal atomic fractions but in proportion to each other such that all of the atoms of the elements present in the amorphous state are absorbed in the two crystalline phases of the crystalline state. Thus, there are available readily formed multi-element crystalline phases which absorb or consume substantially 30 all of the elements which are present in the amorphous state, thereby avoiding the 7 20~9476 precipitation out of the lattice of any separate elements which are not subst~nti~lly fully absorbed in the readily formed major crystalline phases.
Because of the lack of any substantial atomic migration associated with the phase changes between the amorphous and crystalline structures, the phase transitions occur rapidly and with a high degree of stability of both the amorphous and crystalline states.
A further criterion of another embo~liment of the present invention is that the semiconductor band gap of the m~t~ri~l be subst~nti~lly reduced in the transition from the amorphous to the crystalline state, or even that it substantially or completely collapse such that the conduction and valence bands are close to each other or overlap. If the 10 band gap is very small in the crystalline state relative to the amorphous state, thermally generated carriers under normal operating conditions will provide good conductivity and low resistance in the crystalline state co,,,p~u~,d to the amorphous state.
Another composition which meets the criteria of the invention is Te5lGe40Sbg, which forms a single crystalline phase of substantially the same composition as the elements in the amorphous state. Thus, the material is col"po~;t;on~lly substantially the same in the amorphous state and in the single crystalline phase which is formed when the materi~l is electrically switched to the crystalline state. This material exhibits a further advantage in accordance with another above-mentioned criterion of the invention in that its electronic band gap is caused to collapse in the transition from the amorphous 20 state and the crystalline state such that it is no longer a semiconductor but rather is a metal or a semi-metal. That is, its band gap collapses and the conduction and valence bands overlap in the crystalline state, thereby providing a very high electricalconductivity and exhibiting essentially a metallic form of electrical conduction. This yields a very high ratio of resi~t~nces between the "on" and "off" or "set" and "reset"
con-lition~.
The transition of the aforementioned material to a semi-metal state was determined by measu~ing the temperature dependence of the electrical conductivity of the material. In a semiconductor, electrical conductivity increases with increasing tt;lnl)eldture. It was found that, instead, the electrical conductivity of the aforementioned 30 material in the crystalline state actually decreased slightly with increasing temperature, 2059~76 _ 8 thereby exhibiting the pl~,p.,lLies of a m~teri~l in which the valence and conduction bands actually overlap.
Other available crystalline structural phases for these elements have been detPrminçd to be Te52Ge43Sb5 and Te20Ge20Sb60. Similar plcfcll~d crystalline structural phases can be de~ ell for other combin~tion~ of elements in accordance with the teachings of the present invention such that the formation of the available multi-element crystalline phases subst~ntizllly absorbs all of the elements present in the amorphous state.
The elements of the erasably switchable alloy are selected such that substantially 10 all of the elements in the composition are distributed in the amorphous state and are all subst~nti~lly absorbed per unit volume of the m~teri~l into stable crystalline phases in the tr~n~ition from the amorphous state to the crystalline state. The result is a material which can be very rapidly switched ~l~ccn the two states at a very low energy, that is, at switching times and energy levels far below those ~tt~in~ble or heretofore even thought possible with prior art erasable electrical memory m~t~ri~
The compositional stoichiometry of the con~tituent elements within the material is such that all of the constituent elements are substantially fully absorbed per unit volume of m~teri~l in one or more crystalline phases which are formed in the crystalline state.
In addition, the constitllP-nt elements are preferably absorbed in the one or more 20 crystalline phases with substantially the same average local atomic density distribution, i.e., the same average local concentration, of the constituent elements as present in the amorphous state. Thus, the material is fully crystallized per unit volume and the local atomic density of the con~tituent elements is only minim~lly disturbed by the transitions between the amorphous and crystalline states. Atomic migration within the material during phase tr~n~ition~ is thus minimi7~rl and electrical switching speeds and energies are rem~rk~bly reduced by orders of magnitude below prior art electrically erasable phase change memories.
The elements of the m~teri~l will usually be substantially homogeneously distributed within the material as originally deposited but may become locally somewhat 30 concentrated in certain regions of the material to conform to the crystalline phase locations and concentrations of the atoms in the matrix. However, in the phase transition 20~9476 g from the crystalline to the amorphous state, the material becomes molten and diffusion takes place which would tend to distribute the atoms somewhat homogeneously within the bulk of the m~teri~l Such homogeneous distribution in the amorphous state is not necess~ry, however, for the m~teri~l to function in accordance with the invention. The elements of the phase change material are thus described herein as being distributed throughout the material in the amorphous state, but it is to be understood that such distribution may include some loc~li7~ concentrations of some or all of the elements that may occur with switching back and forth between amorphous and crystalline states.
It is to be understood, of course, that the local atomic den~iti~s of the constituent elements can not be exactly the same in both the amorphous and the crystalline states.
Some accommodation in the local atomic arrangement is necess~ry to permit the changes in structural order bet-.~n the amorphous and the crystalline states. What is to be avoided, however, in applying the principles of the present invention, is what is now understood to be the gross distortion in local atomic density which was characteristic of prior art electrically erasable phase change memories. The phrase "subst~n~i~lly the same average local atomic density distribution" is thus to be interpreted to permit a reasonable range of atomic re-arrangement and resulting variation in local atomic density between the amorphous and crystalline states which still yields the perform~nce advantages in accordance with the teachings of the present invention.
The terms "substantially amorphous" and "amorphous" as used herein mean a condition which is relatively ~tomi~lly less ordered or more disordered and has as a result thereof detectably different electrical characteristics such as a lower electrical conductivity. The terms "substantially crystalline" and "crystalline" mean a condition which is relatively atomically more ordered and has as a result thereof a detectably different electrical characteristic such as a higher electrical conductivity.
It has been determined that, in one embodiment of the invention, the material forms a multi-element and multi-phase crystalline structure in the crystalline state and that the crystalline phases in this state have cryst~lli7~tion te,l~peldtures which are relatively close to each other. For example, in the phase change m~teri~l having the composition Te52Ge24Sb24 in the amorphous state, which crystallizes into two crystalline phases as described herein, it has been determined that one of these two phases 2059~76 _, 10 crystallizes at 155 C and the other crystallizes at 172 C. It is believed that this multi-phase crystalline structure with crystalline phases which form at tempefalulcS close to each other is a p,~fel.~d form of the crystalline structure of the material of the present invention because the m~ten~l is believed to be more readily switchable from thecrystalline state to the amorphous state and more stable also in the amorphous state.
If the material has only one crystalline phase (sometimes referred to herein as a "single crystalline phase"), but otherwise conforms to the criteria of the invention, it may be fully satisfactory for some applications but less OplilllUIII for other applications because it is so stable in the crystalline state that it may be more difficult to switch it 10 back to the amorphous state and less stable in the amorphous state once switched back to that con~1ition However, such p~u~llies may be more adaptable to certain appliration~
of the invention and may provide prope~lies which are actually p-~ire--~d for some applir~tion~. In any event, such single crystalline phase material will typically exhibit the greatly ellh~nce~l speed and low switching energy characteristics of the present mventlon.
In ~ ition, since the one or more crystalline phases are stable and readily formed phases, the tr~n~ition is reliably pelro---led and two stable and truly non-volatile conditions are provided.
One of the important principle of the present invention is, however, that 20 substantially all of the elements present in the amorphous state be subst~nti~lly fully absorbed in the crystalline phase or phases when the m~teri~l is switched to thecrystalline state. This greatly minimi7es atomic migration and allows switching between phases to take place rapidly and with low switching energy. It is also believed that, as noted above, in the case of multi-phase crystalline formations, the crystallization temperatures of the dir~elent crystalline phases should advantageously be close to each other to accommodate formation of the multiple phases in the same general temperature zone.
It is further believed that relatively small crystallite sizes in the crystalline phase or phases may further contribute to the rapid formation of the crystalline phase or phases 30 and to the lower energy requirements for the transitions between amorphous and crystalline states.

20~9476 , 11 In accordance with still another aspect of the present invention, we have found that the ~ ching characteristics of such m~te~i~le may be controlled such that optimum switching transitions can be effected. It has been found that, in order for the materials of the present invention to perform at the substantially enh~nced levels which are att~in~ble over the pelÇollllance parameters of the prior art, exact compositional stoichiometry is not required since the m~te~i~l lattice will typically tolerate a certain level of extraneous atomic material without substantial degradation in the performance level of the material.
The word "substantially" is therefore used herein to mean that level of conformance to the stoichiometric principles taught herein which enable the attainment of the implo~elllents in pe.rollllance parameters over prior art electrically erasable memones as provided by the present invention.
As noted above, it is also believed that the relatively small crystallite siæ range of the crystalline phases may contribute to the rapid tr~n~ition between the crystalline and amorphous states. We have post~ ted that a crystalline structure which approaches a microcrystalline lattice in structure switches more rapidly between amorphous and crystalline states because the microstructures require less atomic adjustment toaccommodate the tr~n~iti-~n~ between the amorphous and crystalline structural states. At the same time, the multi-phase nature of the crystalline state further enh~nces and stabilizes the tr~n~ition to the amorphous state.
One characteristic of the phase change materials of the present invention is that they appear to tend toward the formation of more and smaller cryst~llites per unit volume of the material. Crystallite sizes of representative materials embodying the present invention have been found to have small crystallite siæs in the range of from about 100 to 500 Angstroms and generally less than the range of about 1,000 to 5,000 Angst~oms ch~r~rt~ricti~ of prior art materials. Crystallite size as referred to herein is in general the fli~meter of the cryst~llites, or the "characteristic limen~ion" thereof equivalent to the diameter where the crystallites are not spherically shaped. Thus, the term "characteristic dimension" means the average ~ t~nce across the crystallite, that is, either the diameter or the equivalent thereof.
It has been deterrnined that the composition in the amorphous state of the class of TeGeSb m~teri~l~ which meet the criteria of the present invention appear to be generally - 2059~76 ._ 12 characterized by subst~nti~lly reduced concentrations in Te below those present in prior art materials used as electrically erasable phase change m~teri~ In the compositions in this class which were found to provide the subst~nti~lly improved electrical switching performance charactçri~tics, the average concentrations of Te in the amorphous state were well below 70%, typically below about 60% and ranged in general from as low as about 23% up to about 56% Te. Concentrations of Ge were above about 15% and ranged from a low of about 17% to about 44% average in the amorphous state, rçm~ining generally below 50% Ge, with the rem~inder of the principal constituent elements in this class being Sb. The percentages given are atomic ~ .ges which 10 total 100% of the atoms of the constituent elements. Thus, this class of materials may be characterized as Te.GebSb~ ,b)~ where a is equal to or less than about 70% and preferably equal to or less than about 60%, b is above about 15% and less than 50%, preferably between about 17% to about 44% and the rem~in~er is Sb.
In the case of the TeGeSb class of m~teri~l~, the following crystalline phases were found to be present either singly or in combination in various forms of thecrystalline state for various approximate compositions falling within the above ranges of the amorphous state:

Table I
Observed Crystalline Phases of TeGeSb Name of Phase At % Te At % Ge At % Sb a 51 44 s 23 l9 58 The average for these elements in the amorphous state was in one sample about 53% Te, 21% Ge and 26% Sb.

Referring now to Fig. 1, there is shown a cross sectional view of a portion of the structure of an electrically erasable phase change memory embodying the present invention. The memory structure is formed on a single crystal silicon semiconductor wafer 10 which is p-doped and which forms a p-substrate for the deposition of the rem~ining elements of the configuration illustrated.
Formed in the p-substrate 10 are n+ ch~nnel~ 12, which may be formed by diffusion in a manner well known in the art. These n+ ch~nnel~ extend across the chip in a direction perpendicular to the plane of the illustration and form one set of electrodes, in this case the y set, of an x-y electrode grid for addressing the individual 10 memory elements.
On top of this n+ grid structure is formed an n-doped crystalline epitaxial layer 14, again by techniques well known in the art. The n doped epitaxial layer 14 may be about 5,000 Angstroms thick, for example. Using known masking and doping techniques, p-doped isolation channels 16 are then formed in the n-epitaxial layer 14.
These p-doped isolation channels 16 extend all the way down to the p substrate 10 as shown in Fig. 1 and also extend completely around and isolate and define islands 18 of the n-epitaxial layer 14. The islands 18 are shown more clearly in the top view of Fig. 2 wherein the p isolation ch~nnpl~ are shown as forming an isolation grid defining and isolating the islands 18 of n epitaxial m~ten~l Instead of the p-doped isolation channels.
20 SiO2 isolation trenches may be used for isolation of the islands 18. The technique of formation of such SiO2 isolation trenches is well known to those skilled in the art.
A layer 20 of therm~lly grown SiO2 is then formed on the structure just describe~l and etched out to form ap~ s 22 over the islands 18. Diffusion regions 24 of p+
material are then formed within the areas defined by the a~~ s 22 as shown in Fig. 1.
The semicon-~uctor junctions of the p+ regions and the n epitaxial layer form p-n junction diodes 26 in series with each of the regions of the n epitaxial layer exposed through the a~l~u~s 22 of the SiO2 layer 20.
The memory elements 30 are then deposited over the p+ regions 24 in individual ohmic electrical series contact with the diodes 26. The memory elements 30 are 30 comprised of bottom thin electrical contact layers of molybdenum 32 and carbon 34, the memory layer 36 formed of a m~teri~l as described above, and upper thin electrical _ 14 contact layers 38 of carbon and 40 of molybdenum. The contact layers 32, 34, 38 and 40 of carbon and molybdenum form excellent electrical contacts with the memory layers 36 and also form diffusion barriers which effectively block diffusion of element~ into and out of the memory layers 36.
The carbon layers 34 and 38 have a relatively high electrical resistivity and are more (lifficult to etch and are therefore preferably relatively thin, typically in the range of 100 to l,000 Angstroms or so. The molybdenum layers 32 and 40 should be thicker, say in the range of l,000 to 2,000 Ang~L~o~s or so in order to act as effective diffusion barriers for the memory layers 36.
The memory layer 36 is formed of a multi-element phase change m~t~ri~l as disclosed herein. The layer 36 is preferably sputter deposited in the substantially amorphous state, but may be formed in other ways such as by evaporation or by chemical vapor deposition, which may be enh~nced by plasma techniques such as RFglow discharge. The memory layer 36 may typically range in thickness from about 200 Angstroms to about 5,000 Angstroms and is preferably about 200 to 1,000 Angstroms in thi~kness The lateral dimension or diameter of the pore of phase change material 36 may be in the range of about one micrometer or so, although there is no practical limit on the lateral dimension. It has been determined that the diameter of the actualconductive path of crystalline material formed in the "set" condition is as small as one-20 quarter to one-third of a micrometer. The pore diameter can thus be as small as lithography resolution limits will permit.
In a ~ ,fel.~d embodiment of the present invention, the pore diameter is selected such that it confol...s subst~nti~lly with the diameter of the crystalliæd low resistance path which is formed when the material is switched to the crystalline state. As noted above, the actual diameter of the crystalliæd low resist~nce path has been determined to be in the range of about one quarter to about one third or more of a micrometer. The diameter of the pore of memory m~tçn~l 36 is therefore preferably less than about one micrometer so that the volume of the memory material 36 is limited as much as isfeasible to the volume of the phase change material 36 which is actually switched back 30 and forth between the crystalline and amorphous states. This further reduces the switching time and the electrical energy required to initiate the phase change. The pore diameter as used herein means the cross sectional lateral dimension of the memory layer 36 which çxtenfls under the contact regions formed with the memory layer 36 and with the lower p+ layer and the upper conductors 42 as shown in the embodiment of Fig. l and, in the case of the embo-liment of Fig. 2, with the lower metal layer 29 of the Schottky diode.
It is further p~ ;d that the pore regions of the memory elements 30 be thermally isolated and/or controlled except only for the required electrical contacts with the upper and lower contacts as necess~ry for proper operation of the memory elements.
This further confines, limits and controls the heat transfer from the switched volume of 10 the pore and the electrical energy required for the phase transitions. This is accomplished in the embodiments of Figs. l and 2 by the oxide layers 20 and 39 which surround the lateral peripheral portions of the memory element~ 30.
As used herein, the "set" condition refers to the low re~i~t~nce substantially crystalline state and the "reset" condition refers to the high resistance or subst~nti~lly amorphous state.
The layers 32, 34, 36, 38 and 40 are etched and an oxide layer 39 is formed thereover and etched to leave openings above the memory elements 30 as shown.
Alternatively, the memory elements may be formed in a two step etch process withlayers 32 and 34 being first deposited and etched and then rem~ining layers 36, 38 and 20 40 being deposited thereover and separately etched to the selected flimension Deposited on top of the entire structure just described is the second electrode grid structure formed of aluminum conductors 42, which extend perpendicular in direction to the conductors 12 and complete the x-y grid connection to the individual memory elements. Overlaying the complete integrated structure is a top encapsulating layer 44 of a suitable encapsulant such as Si3N4 or a plastic m~teri~l such as polyamide, which seals the structure against moisture and other external elements which could cause deterioration and degradation of perform~nce, particularly of the phase change materials in the memory layer 36. The Si3N4 encapsulant can be deposited, for example, using a low temperature plasma deposition process. The polyamide material can be spin deposited and baked after30 deposition in accordance with known techniques to form the encapsulant layer 44.

The embodiment of Fig. 2 is the same as Fig. 1 except that a diode 27 is formed of a Schottky barrier between the n layer 14 and a metal layer 29 which may be, for example, pl~tinllm silicide. In other ~specls, the embodiment of Fig. 2 is formed in the same manner as that of Fig. 1 and like elements are labeled with like numerals.
The integrated structure thus formed is an x-y memory matrix connected as shown in Fig. 3 in which each memory element 30 is connected in series with a diode 26 between a horizontal x-line 42 and a vertical y-line 12. The diodes 26 serve to isolate electric~lly each of the memory elements 30. Other circuit configurations for the electrically erasable memory of the present invention are, of course, possible and feasible 10 to implement.
With the integrated structure as shown in the embodiment of Figs. 1 and 2, however, a completely vertically integrated structure of the memory element and its isolating diode is formed, thus minimi7ing the area occupied on the substrate by each of the combin~tion~ of memory elements and diodes. This means that the density of the memory elements in the chip is limited essentially only by the resolution of thelithography.
In Fig. 4A, there is diagr~mm~ti~lly illustrated a por~ion of a single crystal semiconductor substrate 50 with a memory matrix 51 embodying the present invention formed thereon. Also formed on the same substrate 50 is an addressing matrix 52 which 20 is suitably connecte~l through integrated connections 53 to the memory matrix 51. The addressing matrix 52 in~h~des signal generating means which define and control the set, reset and read pulses applied to the memory matrix 51. The addressing matrix 52 may be integrated with and formed simultaneously with the memory matrix 51.
In prior art semiconductor memories having the high switching speeds and low switching energies deemed necess~ry for most applications of such memories, at least one transistor is required along with a capacitor for each memory element. The formation of such memories in integrated circuit form requires at least three connections along with other additional complexities which occupy a certain minimum substrate area regardless of how the integrated circuit is laid out. The integrated circuit configuration 30 of the electrically erasable memory of the present invention requires only two connections to each memory element and these are made in vertical relationship to each 20~9476 other. Further, each memory element, complete with isolating diode and the pair of contacts for the element, is itself fully vertically integrated such that a much higher bit density is att~inçd over that possible with prior art integrated circuits ~lrolllling the same or similar functions.
In fact, the memory of the present invention allows a bit density which is greater than that ~tt~in~ble even in solid state dynamic random access memories (DRAM's), which are volatile and therefore lack the further advantages that non-volatility ~tt~in~ble with the present invention provides. The increase in bit density ~tt~in~ble with the present invention is tr~n~l~ted into a coll~sponding reduction in manufacturing costs 10 because of the smaller areas of the wafer occupied per bit of the integrated circuit configuration. This allows the memory of the present invention to compete with and surpass other available memories for a wider range of applications, not only in terms of p~,lrol~"ance but also in terms of cost.
By comparison with prior art semiconductor memories formed of at least one transistor and a capacitor for each bit, the integrated circuit configuration of the present invention as shown in Figs. 1 and 2 can be formed on a chip with ap~ lately three times the bit density as such prior art configurations for the same lithography resolution.
In ~d-lition to the cost advantages which the higher bit density affords, the perform~nce parameters of the memory in the integrated circuit configuration of the present invention 20 are thus even further illlpluved in that the elements are position~l closer together and lead lengths, cap~cit~nres and other related parameters are thus further minimi thereby further enhancing ~.,lrol.l~ance.
Fig. 4 is a circuit diagram of a portion of the embodiments of Figs. 1-3. The circuit comprises an x-y grid with each of the memory elements 30 being connected in series with a diode 26 at the cross points of the x address lines 42 and the y address lines 12 as shown. The address lines 12 and 42 are connected to external addressing circuitry in a manner well known to those skilled in the art.
Fig. S is a graphical presentation of performance data taken from samples of memory element~ embodying the present invention. The data are presented to show 30 electrical resistance in the "set" or crystalline state and the switching energy in Joules required to switch the m~ten~l in each case from the amorphous state, as initially deposited, to the crystalline state. The high resistance of the amorphous reset state is shown in the upper right hand corner of the graph of Fig. 5 and is just under 20,000 ohms as contrasted to a set resistance of about lS0 ohms for a set energy of about 10-9 Joules. Switching times were typically in the range of lO to 80 nanoseconds and the switching set energy typically in the range of about 10-9 Joules. Reset energy was about 10-6 Joules. These data are to be colllpa~ed with the p~lro~ nre data of the prior art electrically erasable phase change memories which were in the range of microseconds to milli~econds typical switching times at switching energies in the range of 10-3 to 10-6 Joules. Thus, the perform~nce parameters of the electrically erasable memory materials lO of the present invention are a number of orders of ma~nihlde better than those ~tt~in~ble with prior art electrically erasable phase change memory materials.
In addition, it is to be noted with reference to Fig. 5 that the "set" resistance varies in a substantially linear fashion with the level of the energy of the set pulse, being about 150 ohms for a set pulse of about lO-9 Joules and about 2,000 ohms for a set pulse of about lO ll Joules, with a fairly linear characteristic in between these points. This provides a gray scale characteristic which allows the memory elements of the present invention to behave in an adaptive memory response rel~tionship, thereby allowing application to adaptive memory systems.
Fig. 6 is a graphical presentation of data on electrical switching characteristics 20 taken on samples of memory elements manufactured in accordance with and embodying the present invention. Device resistance in ohms is shown in relation to switching energy in Joules for reset pulse widths ranging from 30 to 80 n~noseconds. The reset to set re~i~t~nt~e ratios are all separated by almost a full order of m~gnihlde or more and are thus fully adequate to assure error free electrical detection between the set and reset conditions for digital memory applications. The reset energy at 30 nanoseconds is less than 10-7 Joules.
Fig. 7 is a graphical presentation of data depicting the set resi~t~nce of the device in kilohms in relation to the number of set pulses sequentially applied to the device. It is to be noted that the set resi~t~nce decreases as a function of the number of set pulses, 30 thereby providing a gray scale or adaptive memory capability. For the data shown in Fig. 7, set pulses of about 50 nanoseconds at about 5 volts and about 40 milli~mps were applied and the resistance was measured after each pulse before the next pulse in the sequence was applied. The data show that the set resistance can be driven down in increments by the sequential application of set pulses, thereby allowing the m~teri~l to be set at different levels over the spectrum between completely amorphous and completely crystalline states.
Fig. 8 shows data taken on the device "on" resistance in ohms in relation to load resistance in ohms. The load resi~t~nre is connected in series with the device and hence serves to determine the m~gnitl1de of the current flow upon firing. The data were taken using a threshold voltage of 12 volts. The "on" resistance of the device decreases 10 rapidly as a function of increasing set current down to a level of 100 ohms or so It will be seen from the foregoing that the electrically erasable phase change memory of the present invention provides r~m~rk~hle improvements in p~ilrollllance over that ~tt~in~ble with prior art electrically erasable phase change memories which permit the widespread application of such memories beyond that possible with such prior art memories. It is to be understood that the disclosure set forth herein is presented in the form of the detailed embodiments described for the pul~ose of making a full and complete disclosure of the present invention, and that such details are not to be interpreted as limiting in any way the true scope of this invention as set forth and n~l in the appended claims.

Claims (27)

1. An electrically erasable phase change memory comprising:
(a) at least one pore of phase change material which is capable of being reversibly electrically switched between at least two electrically detectable states, the first of said at least two detectable states having a local atomic order which is detectably less ordered than the local atomic order of the second of said at least two detectable states;
(b) electrical contact means making electrical contact with at least two portions of said pore to establish an electrical path through said pore between the points of contact with said at least two portions; and (c) means for applying electrical signals to said electrical contact means to cause reversible switching of at least a volume portion of said phase change material in said electrical path in said pore between said at least two detectable states, said first detectable state being characterized by an electrical conductivity which is lower than that of said second detectable state;
(d) said phase change material being comprised of a plurality of elements which are compositionally and stoichiometrically arranged such that they are distributed within said phase change material in said first detectable state and are converted into said second detectable state in said volume portion with substantially the same average local density of distribution of the constituent elements as present in said first detectable state.
2. An electrically erasable phase change memory as set forth in claim 1 in which said plurality of element distributed within said phase change material in said first detectable state are substantially fully absorbed in one or more crystalline phases in said volume portion of second detectable state.
3. An electrically erasable phase change memory as set forth in claim 1 wherein said phase change material comprises Te, Ge and Sb as the principal elements thereof, which are distributed in the amorphous state substantially in the ratio Te,GebSb100-(a+b), where the subscripts are in atomic percentages which total 100% of the constituent elements and a is equal to or less than about 70% and b is between about 15% to about 50%.
4. An electrically erasable phase change memory as set forth in claim 3 where a is equal to or less than about 60% and b is between about 17% to about 44%.
5. An electrically erasable phase change memory as set forth in claim 1 in which the band gap of said phase change material is substantially reduced in the transition from said first detectable state to said second detectable state.
6. An electrically erasable phase change memory as set forth in claim 2 in which said one or more crystalline phases includes at least one multi-element crystalline phase.
7. An electrically erasable phase change memory as set forth in claim 2 in which said one or more crystalline phases includes a plurality of multi-element crystalline phases.
8. An electrically erasable phase change memory as set forth in claim 2 in which said one or more crystalline phases comprises a plurality of crystalline phases.
9. An electrically erasable phase change memory as set forth in claim 8 in which the crystallization temperatures of said plurality of crystalline phases are all within about 100 C of each other.
10. An electrically erasable phase change memory as set forth in claim 2 in which the crystallites in said multi-element crystalline phases have a characteristic dimension of less than about 1,000 Angstroms.
11. An integrated circuit electrically erasable phase change memory comprising:
(a) a single crystal semiconductor substrate;
(b) a plurality of electrically erasable phase change memory elements formed on said substrate;

(c) each of said memory elements comprising a pore of phase change material and an integrated circuit diode positioned vertically with respect to each other on said substrate, said diode and said pore of phase change material being electrically connected in series with each other, (d) said phase change material being comprised of a plurality of elements which are compositionally and stoichiometrically arranged such that they are distributed within said phase change material in a first substantially amorphous state and are converted into a second substantially crystalline state in at least a volume portion of said pore with substantially the same average local density of distribution of the constituent elements as present in said substantially amorphous state; and (e) integrated electrical contact means extending across said substrate over the upper and lower portions respectively of said memory elements and making electrical contact on one side of each of said memory elements with said pore of phase change material and on the other side of each of said memory elements with said diode and thereby providing means for selectively and individually electrically setting, erasing and reading said memory elements.
12. An integrated circuit electrically erasable phase change memory as set forth in claim 11 further comprising signal generating means electrically connected to said contact means for generating and applying selectively to said memory elements set, erase and read pulses.
13. An integrated circuit electrically erasable phase change memory as set forth in claim 12 in which said signal generating means includes means for generating and applying set pulses of less than 100 nanoseconds in width.
14. An integrated circuit electrically erasable phase change memory as set forth in claim 11 in which said diode comprises a semiconductor junction.
15. An integrated circuit electrically erasable phase change memory as set forth in claim 14 wherein said semiconductor junction is formed at a surface extending substantially parallel to the surface of said substrate.
16. An integrated circuit electrically erasable phase change memory as set forth in claim 14 in which said semiconductor junction comprises a Schottky barrier.
17. An integrated circuit electrically erasable phase change memory as set forth in claim 14 in which said semiconductor junction comprises a p-n junction.
18. An integrated circuit electrically erasable phase change memory as set forth in claim 17 in which said p-n junction is formed at a surface extending substantially parallel to the surface of said substrate.
19. An integrated circuit electrically erasable phase change memory as set forth in claim 16 in which said Schottky barrier is formed at a surface extending substantially parallel to the surface of said substrate.
20. An integrated circuit electrically erasable phase change memory as set forth in claim 15 in which said one side and said other side of each of said memory elements which make electrical contact with said integrated electrical contact means are positioned in vertical relationship to each other.
21. An integrated circuit electrically erasable phase change memory as set forth in claim 20 in which said one side and said other side of each of said memory elements which make electrical contact with said integrated electrical contact means include contact surfaces which extend substantially parallel to each other and to the surface of said substrate.
22. An integrated circuit electrically erasable phase change memory as set forth in claim 11 in which said phase change material comprises Te, Ge and Sb as the principal elements thereof, which are distributed in the amorphous state substantially in the ratio TeaGebSb100-(a+b), where the subscripts are in atomic percentages which total 100% of the constituent elements and a is equal to or less than about 70% and b is between about 15% to about 50%.
23. An integrated circuit electrically erasable phase change memory as set forth in claim 22 where a is equal to or less than about 60% and b is between about 17% to about 44%.
24. An integrated circuit electrically erasable phase change memory as set forth in claim 11 further comprising a layer of encapsulating material extending over and encapsulating and sealing said memory elements against external environmental influences.
25. An integrated circuit electrically erasable phase change memory as set forth in claim 11 in which said pore of phase change material is less than one micrometer in diameter.
26. An electrically erasable phase change memory as set forth in claim 1 in which the diameter of said pore is less than one micrometer.
27. An electrically erasable phase change memory as set forth in claim 2 in which the diameter of said pore is less than one micrometer.
CA002059476A 1991-01-18 1992-01-16 Electrically erasable phase change memory Expired - Fee Related CA2059476C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/642,984 1991-01-18
US07/642,984 US5166758A (en) 1991-01-18 1991-01-18 Electrically erasable phase change memory

Publications (1)

Publication Number Publication Date
CA2059476C true CA2059476C (en) 1995-06-27

Family

ID=24578871

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002059476A Expired - Fee Related CA2059476C (en) 1991-01-18 1992-01-16 Electrically erasable phase change memory

Country Status (11)

Country Link
US (1) US5166758A (en)
EP (1) EP0495494B1 (en)
JP (1) JP3224253B2 (en)
KR (1) KR100196489B1 (en)
CN (1) CN1044046C (en)
AT (1) ATE139862T1 (en)
CA (1) CA2059476C (en)
DE (1) DE69211719T2 (en)
MX (1) MX9200210A (en)
RU (1) RU2130217C1 (en)
TW (1) TW231354B (en)

Families Citing this family (442)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5341328A (en) * 1991-01-18 1994-08-23 Energy Conversion Devices, Inc. Electrically erasable memory elements having reduced switching current requirements and increased write/erase cycle life
US5414271A (en) * 1991-01-18 1995-05-09 Energy Conversion Devices, Inc. Electrically erasable memory elements having improved set resistance stability
US5406509A (en) * 1991-01-18 1995-04-11 Energy Conversion Devices, Inc. Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom
US5296716A (en) * 1991-01-18 1994-03-22 Energy Conversion Devices, Inc. Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom
US5596522A (en) * 1991-01-18 1997-01-21 Energy Conversion Devices, Inc. Homogeneous compositions of microcrystalline semiconductor material, semiconductor devices and directly overwritable memory elements fabricated therefrom, and arrays fabricated from the memory elements
US5128099A (en) * 1991-02-15 1992-07-07 Energy Conversion Devices, Inc. Congruent state changeable optical memory material and device
US5359205A (en) * 1991-11-07 1994-10-25 Energy Conversion Devices, Inc. Electrically erasable memory elements characterized by reduced current and improved thermal stability
JP3454821B2 (en) * 1991-08-19 2003-10-06 エナージー・コンバーション・デバイセス・インコーポレーテッド Electrically erasable, directly overwritable, multi-bit single-cell memory elements and arrays made therefrom
USRE40790E1 (en) * 1992-06-23 2009-06-23 Micron Technology, Inc. Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device
US5229326A (en) * 1992-06-23 1993-07-20 Micron Technology, Inc. Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device
US5753947A (en) * 1995-01-20 1998-05-19 Micron Technology, Inc. Very high-density DRAM cell structure and method for fabricating it
US5869843A (en) * 1995-06-07 1999-02-09 Micron Technology, Inc. Memory array having a multi-state element and method for forming such array or cells thereof
US5789758A (en) * 1995-06-07 1998-08-04 Micron Technology, Inc. Chalcogenide memory cell with a plurality of chalcogenide electrodes
US5751012A (en) * 1995-06-07 1998-05-12 Micron Technology, Inc. Polysilicon pillar diode for use in a non-volatile memory cell
US6420725B1 (en) 1995-06-07 2002-07-16 Micron Technology, Inc. Method and apparatus for forming an integrated circuit electrode having a reduced contact area
JP3363154B2 (en) * 1995-06-07 2003-01-08 ミクロン テクノロジー、インコーポレイテッド Stack / trench diode for use with multi-state material in a non-volatile memory cell
US5831276A (en) * 1995-06-07 1998-11-03 Micron Technology, Inc. Three-dimensional container diode for use with multi-state material in a non-volatile memory cell
US5879955A (en) * 1995-06-07 1999-03-09 Micron Technology, Inc. Method for fabricating an array of ultra-small pores for chalcogenide memory cells
US5714768A (en) * 1995-10-24 1998-02-03 Energy Conversion Devices, Inc. Second-layer phase change memory array on top of a logic device
US5837564A (en) * 1995-11-01 1998-11-17 Micron Technology, Inc. Method for optimal crystallization to obtain high electrical performance from chalcogenides
US6653733B1 (en) * 1996-02-23 2003-11-25 Micron Technology, Inc. Conductors in semiconductor devices
US6025220A (en) * 1996-06-18 2000-02-15 Micron Technology, Inc. Method of forming a polysilicon diode and devices incorporating such diode
US5814527A (en) * 1996-07-22 1998-09-29 Micron Technology, Inc. Method of making small pores defined by a disposable internal spacer for use in chalcogenide memories
US5985698A (en) * 1996-07-22 1999-11-16 Micron Technology, Inc. Fabrication of three dimensional container diode for use with multi-state material in a non-volatile memory cell
US5789277A (en) 1996-07-22 1998-08-04 Micron Technology, Inc. Method of making chalogenide memory device
US6337266B1 (en) 1996-07-22 2002-01-08 Micron Technology, Inc. Small electrode for chalcogenide memories
US5998244A (en) * 1996-08-22 1999-12-07 Micron Technology, Inc. Memory cell incorporating a chalcogenide element and method of making same
US5812441A (en) * 1996-10-21 1998-09-22 Micron Technology, Inc. MOS diode for use in a non-volatile memory cell
US7935951B2 (en) * 1996-10-28 2011-05-03 Ovonyx, Inc. Composite chalcogenide materials and devices
US6015977A (en) 1997-01-28 2000-01-18 Micron Technology, Inc. Integrated circuit memory cell having a small active area and method of forming same
US5952671A (en) 1997-05-09 1999-09-14 Micron Technology, Inc. Small electrode for a chalcogenide switching device and method for fabricating same
US6087689A (en) 1997-06-16 2000-07-11 Micron Technology, Inc. Memory cell having a reduced active area and a memory array incorporating the same
US6031287A (en) * 1997-06-18 2000-02-29 Micron Technology, Inc. Contact structure and memory element incorporating the same
US7260051B1 (en) 1998-12-18 2007-08-21 Nanochip, Inc. Molecular memory medium and molecular memory integrated circuit
US6665157B2 (en) 1998-12-22 2003-12-16 Rockwell Automation Technologies, Inc. Apparatus for interrupting an electrical circuit
US6661628B2 (en) 1998-12-22 2003-12-09 Rockwell Automation Technologies, Inc. Method for interrupting a current-carrying path
US6674619B2 (en) 1998-12-22 2004-01-06 Rockwell Automation Technologies, Inc. Method for interrupting an electrical circuit
US6075719A (en) * 1999-06-22 2000-06-13 Energy Conversion Devices, Inc. Method of programming phase-change memory element
JP4491870B2 (en) * 1999-10-27 2010-06-30 ソニー株式会社 Driving method of nonvolatile memory
US6314014B1 (en) 1999-12-16 2001-11-06 Ovonyx, Inc. Programmable resistance memory arrays with reference cells
TW492103B (en) * 2000-06-02 2002-06-21 Koninkl Philips Electronics Nv Electronic device, and method of patterning a first layer
US6440837B1 (en) 2000-07-14 2002-08-27 Micron Technology, Inc. Method of forming a contact structure in a semiconductor device
US6563156B2 (en) * 2001-03-15 2003-05-13 Micron Technology, Inc. Memory elements and methods for making same
TWI233098B (en) * 2000-08-31 2005-05-21 Matsushita Electric Ind Co Ltd Data recoding medium, the manufacturing method thereof, and the record reproducing method thereof
US6339544B1 (en) * 2000-09-29 2002-01-15 Intel Corporation Method to enhance performance of thermal resistor device
US6569705B2 (en) * 2000-12-21 2003-05-27 Intel Corporation Metal structure for a phase-change memory device
US6638820B2 (en) 2001-02-08 2003-10-28 Micron Technology, Inc. Method of forming chalcogenide comprising devices, method of precluding diffusion of a metal into adjacent chalcogenide material, and chalcogenide comprising devices
US6727192B2 (en) 2001-03-01 2004-04-27 Micron Technology, Inc. Methods of metal doping a chalcogenide material
US6734455B2 (en) 2001-03-15 2004-05-11 Micron Technology, Inc. Agglomeration elimination for metal sputter deposition of chalcogenides
US7102150B2 (en) 2001-05-11 2006-09-05 Harshfield Steven T PCRAM memory cell and method of making same
US6642102B2 (en) * 2001-06-30 2003-11-04 Intel Corporation Barrier material encapsulation of programmable material
US6951805B2 (en) 2001-08-01 2005-10-04 Micron Technology, Inc. Method of forming integrated circuitry, method of forming memory circuitry, and method of forming random access memory circuitry
US6737312B2 (en) 2001-08-27 2004-05-18 Micron Technology, Inc. Method of fabricating dual PCRAM cells sharing a common electrode
US6881623B2 (en) 2001-08-29 2005-04-19 Micron Technology, Inc. Method of forming chalcogenide comprising devices, method of forming a programmable memory cell of memory circuitry, and a chalcogenide comprising device
US6784018B2 (en) 2001-08-29 2004-08-31 Micron Technology, Inc. Method of forming chalcogenide comprising devices and method of forming a programmable memory cell of memory circuitry
US6955940B2 (en) 2001-08-29 2005-10-18 Micron Technology, Inc. Method of forming chalcogenide comprising devices
US20030047765A1 (en) 2001-08-30 2003-03-13 Campbell Kristy A. Stoichiometry for chalcogenide glasses useful for memory devices and method of formation
US6507061B1 (en) * 2001-08-31 2003-01-14 Intel Corporation Multiple layer phase-change memory
US6764894B2 (en) 2001-08-31 2004-07-20 Ovonyx, Inc. Elevated pore phase-change memory
EP2112659A1 (en) 2001-09-01 2009-10-28 Energy Convertion Devices, Inc. Increased data storage in optical data storage and retrieval systems using blue lasers and/or plasmon lenses
US6567296B1 (en) * 2001-10-24 2003-05-20 Stmicroelectronics S.R.L. Memory device
US6545907B1 (en) * 2001-10-30 2003-04-08 Ovonyx, Inc. Technique and apparatus for performing write operations to a phase change material memory device
US6815818B2 (en) 2001-11-19 2004-11-09 Micron Technology, Inc. Electrode structure for use in an integrated circuit
US6791859B2 (en) 2001-11-20 2004-09-14 Micron Technology, Inc. Complementary bit PCRAM sense amplifier and method of operation
CN1311553C (en) * 2001-12-12 2007-04-18 松下电器产业株式会社 Nonvolatile memory
US6545903B1 (en) 2001-12-17 2003-04-08 Texas Instruments Incorporated Self-aligned resistive plugs for forming memory cell with phase change material
US6873538B2 (en) 2001-12-20 2005-03-29 Micron Technology, Inc. Programmable conductor random access memory and a method for writing thereto
US6625054B2 (en) * 2001-12-28 2003-09-23 Intel Corporation Method and apparatus to program a phase change memory
US6909656B2 (en) 2002-01-04 2005-06-21 Micron Technology, Inc. PCRAM rewrite prevention
US6590797B1 (en) 2002-01-09 2003-07-08 Tower Semiconductor Ltd. Multi-bit programmable memory cell having multiple anti-fuse elements
US20030128646A1 (en) * 2002-01-09 2003-07-10 Peter Nangle Asymmetrical programming mechanism for non-volatile memory
EP1331675B1 (en) * 2002-01-17 2007-05-23 STMicroelectronics S.r.l. Integrated resistive element, phase-change memory element including said resistive element, and method of manufacture thereof
US20030143782A1 (en) 2002-01-31 2003-07-31 Gilton Terry L. Methods of forming germanium selenide comprising devices and methods of forming silver selenide comprising structures
US6867064B2 (en) 2002-02-15 2005-03-15 Micron Technology, Inc. Method to alter chalcogenide glass for improved switching characteristics
US6791885B2 (en) 2002-02-19 2004-09-14 Micron Technology, Inc. Programmable conductor random access memory and method for sensing same
US6809362B2 (en) 2002-02-20 2004-10-26 Micron Technology, Inc. Multiple data state memory cell
US6891749B2 (en) 2002-02-20 2005-05-10 Micron Technology, Inc. Resistance variable ‘on ’ memory
US7087919B2 (en) 2002-02-20 2006-08-08 Micron Technology, Inc. Layered resistance variable memory device and method of fabrication
US7151273B2 (en) 2002-02-20 2006-12-19 Micron Technology, Inc. Silver-selenide/chalcogenide glass stack for resistance variable memory
US6937528B2 (en) 2002-03-05 2005-08-30 Micron Technology, Inc. Variable resistance memory and method for sensing same
US6849868B2 (en) 2002-03-14 2005-02-01 Micron Technology, Inc. Methods and apparatus for resistance variable material cells
US7623370B2 (en) 2002-04-04 2009-11-24 Kabushiki Kaisha Toshiba Resistance change memory device
US7767993B2 (en) 2002-04-04 2010-08-03 Kabushiki Kaisha Toshiba Resistance change memory device
US7663132B2 (en) 2002-04-04 2010-02-16 Kabushiki Kaisha Toshiba Resistance change memory device
US6670628B2 (en) 2002-04-04 2003-12-30 Hewlett-Packard Company, L.P. Low heat loss and small contact area composite electrode for a phase change media memory device
WO2003085675A2 (en) 2002-04-04 2003-10-16 Kabushiki Kaisha Toshiba Phase-change memory device
US6864500B2 (en) 2002-04-10 2005-03-08 Micron Technology, Inc. Programmable conductor memory cell structure
US6858482B2 (en) 2002-04-10 2005-02-22 Micron Technology, Inc. Method of manufacture of programmable switching circuits and memory cells employing a glass layer
US6855975B2 (en) 2002-04-10 2005-02-15 Micron Technology, Inc. Thin film diode integrated with chalcogenide memory cell
KR100437457B1 (en) * 2002-04-11 2004-06-23 삼성전자주식회사 Phase changeable memory cells having voids and methods of fabricating the same
US6890790B2 (en) 2002-06-06 2005-05-10 Micron Technology, Inc. Co-sputter deposition of metal-doped chalcogenides
US6825135B2 (en) 2002-06-06 2004-11-30 Micron Technology, Inc. Elimination of dendrite formation during metal/chalcogenide glass deposition
US6754124B2 (en) 2002-06-11 2004-06-22 Micron Technology, Inc. Hybrid MRAM array structure and operation
US7015494B2 (en) 2002-07-10 2006-03-21 Micron Technology, Inc. Assemblies displaying differential negative resistance
TWI233204B (en) * 2002-07-26 2005-05-21 Infineon Technologies Ag Nonvolatile memory element and associated production methods and memory element arrangements
US6768665B2 (en) * 2002-08-05 2004-07-27 Intel Corporation Refreshing memory cells of a phase change material memory device
US7129531B2 (en) * 2002-08-08 2006-10-31 Ovonyx, Inc. Programmable resistance memory element with titanium rich adhesion layer
US7209378B2 (en) 2002-08-08 2007-04-24 Micron Technology, Inc. Columnar 1T-N memory cell structure
US6864503B2 (en) 2002-08-09 2005-03-08 Macronix International Co., Ltd. Spacer chalcogenide memory method and device
US6859304B2 (en) * 2002-08-09 2005-02-22 Energy Conversion Devices, Inc. Photonic crystals and devices having tunability and switchability
US7018863B2 (en) 2002-08-22 2006-03-28 Micron Technology, Inc. Method of manufacture of a resistance variable memory cell
KR100448893B1 (en) * 2002-08-23 2004-09-16 삼성전자주식회사 Phase-changeable memory device and method for fabricating the same
US7364644B2 (en) 2002-08-29 2008-04-29 Micron Technology, Inc. Silver selenide film stoichiometry and morphology control in sputter deposition
US7010644B2 (en) 2002-08-29 2006-03-07 Micron Technology, Inc. Software refreshed memory device and method
US7163837B2 (en) 2002-08-29 2007-01-16 Micron Technology, Inc. Method of forming a resistance variable memory element
US6867996B2 (en) 2002-08-29 2005-03-15 Micron Technology, Inc. Single-polarity programmable resistance-variable memory element
US6856002B2 (en) * 2002-08-29 2005-02-15 Micron Technology, Inc. Graded GexSe100-x concentration in PCRAM
US6831019B1 (en) 2002-08-29 2004-12-14 Micron Technology, Inc. Plasma etching methods and methods of forming memory devices comprising a chalcogenide comprising layer received operably proximate conductive electrodes
US6864521B2 (en) 2002-08-29 2005-03-08 Micron Technology, Inc. Method to control silver concentration in a resistance variable memory element
US6867114B2 (en) 2002-08-29 2005-03-15 Micron Technology Inc. Methods to form a memory cell with metal-rich metal chalcogenide
US7294527B2 (en) 2002-08-29 2007-11-13 Micron Technology Inc. Method of forming a memory cell
JP3978541B2 (en) * 2002-09-25 2007-09-19 現代自動車株式会社 Engine cylinder head cover and method of assembling the same
US6985377B2 (en) 2002-10-15 2006-01-10 Nanochip, Inc. Phase change media for high density data storage
US7233517B2 (en) 2002-10-15 2007-06-19 Nanochip, Inc. Atomic probes and media for high density data storage
KR100448895B1 (en) * 2002-10-25 2004-09-16 삼성전자주식회사 Phase changeable memory cells and methods of fabricating the same
JP4205938B2 (en) 2002-12-05 2009-01-07 シャープ株式会社 Nonvolatile memory device
US6867425B2 (en) * 2002-12-13 2005-03-15 Intel Corporation Lateral phase change memory and method therefor
US6795338B2 (en) * 2002-12-13 2004-09-21 Intel Corporation Memory having access devices using phase change material such as chalcogenide
EP1576676B1 (en) 2002-12-19 2008-02-27 Nxp B.V. Electric device comprising phase change material
CN100521277C (en) * 2002-12-19 2009-07-29 Nxp股份有限公司 Electric device comprising phase change material
US6875651B2 (en) * 2003-01-23 2005-04-05 Sharp Laboratories Of America, Inc. Dual-trench isolated crosspoint memory array and method for fabricating same
US7115927B2 (en) * 2003-02-24 2006-10-03 Samsung Electronics Co., Ltd. Phase changeable memory devices
US7425735B2 (en) * 2003-02-24 2008-09-16 Samsung Electronics Co., Ltd. Multi-layer phase-changeable memory devices
US7402851B2 (en) 2003-02-24 2008-07-22 Samsung Electronics Co., Ltd. Phase changeable memory devices including nitrogen and/or silicon and methods for fabricating the same
US6849564B2 (en) * 2003-02-27 2005-02-01 Sharp Laboratories Of America, Inc. 1R1D R-RAM array with floating p-well
US7227170B2 (en) * 2003-03-10 2007-06-05 Energy Conversion Devices, Inc. Multiple bit chalcogenide storage device
US7085155B2 (en) * 2003-03-10 2006-08-01 Energy Conversion Devices, Inc. Secured phase-change devices
US6813178B2 (en) 2003-03-12 2004-11-02 Micron Technology, Inc. Chalcogenide glass constant current device, and its method of fabrication and operation
US7022579B2 (en) 2003-03-14 2006-04-04 Micron Technology, Inc. Method for filling via with metal
JP4377817B2 (en) 2003-03-18 2009-12-02 株式会社東芝 Programmable resistance memory device
US7394680B2 (en) 2003-03-18 2008-07-01 Kabushiki Kaisha Toshiba Resistance change memory device having a variable resistance element with a recording layer electrode served as a cation source in a write or erase mode
US7400522B2 (en) 2003-03-18 2008-07-15 Kabushiki Kaisha Toshiba Resistance change memory device having a variable resistance element formed of a first and second composite compound for storing a cation
US7778062B2 (en) 2003-03-18 2010-08-17 Kabushiki Kaisha Toshiba Resistance change memory device
EP1609154B1 (en) * 2003-03-18 2013-12-25 Kabushiki Kaisha Toshiba Phase change memory device
US7050327B2 (en) 2003-04-10 2006-05-23 Micron Technology, Inc. Differential negative resistance memory
JP4634014B2 (en) * 2003-05-22 2011-02-16 株式会社日立製作所 Semiconductor memory device
US6838692B1 (en) * 2003-06-23 2005-01-04 Macronix International Co., Ltd. Chalcogenide memory device with multiple bits per cell
US6930909B2 (en) * 2003-06-25 2005-08-16 Micron Technology, Inc. Memory device and methods of controlling resistance variation and resistance profile drift
US6961277B2 (en) 2003-07-08 2005-11-01 Micron Technology, Inc. Method of refreshing a PCRAM memory device
US7061004B2 (en) 2003-07-21 2006-06-13 Micron Technology, Inc. Resistance variable memory elements and methods of formation
US7106120B1 (en) 2003-07-22 2006-09-12 Sharp Laboratories Of America, Inc. PCMO resistor trimmer
US7161167B2 (en) * 2003-08-04 2007-01-09 Intel Corporation Lateral phase change memory
US7529123B2 (en) * 2003-09-08 2009-05-05 Ovonyx, Inc. Method of operating a multi-terminal electronic device
US6903361B2 (en) 2003-09-17 2005-06-07 Micron Technology, Inc. Non-volatile memory structure
US7026692B1 (en) * 2003-11-12 2006-04-11 Xilinx, Inc. Low voltage non-volatile memory transistor
JP4792714B2 (en) 2003-11-28 2011-10-12 ソニー株式会社 Storage element and storage device
CN100356606C (en) * 2003-12-12 2007-12-19 中国科学院上海微系统与信息技术研究所 Method for the manufacture of nanometer magnitude unit device in phase-change storage
US7153721B2 (en) * 2004-01-28 2006-12-26 Micron Technology, Inc. Resistance variable memory elements based on polarized silver-selenide network growth
US7105864B2 (en) 2004-01-29 2006-09-12 Micron Technology, Inc. Non-volatile zero field splitting resonance memory
DE102005004338B4 (en) * 2004-02-04 2009-04-09 Samsung Electronics Co., Ltd., Suwon Phase change memory device and associated programming method
KR100733147B1 (en) * 2004-02-25 2007-06-27 삼성전자주식회사 Phase-changeable memory device and method of manufacturing the same
US7098068B2 (en) 2004-03-10 2006-08-29 Micron Technology, Inc. Method of forming a chalcogenide material containing device
US7583551B2 (en) 2004-03-10 2009-09-01 Micron Technology, Inc. Power management control and controlling memory refresh operations
JP4907847B2 (en) * 2004-03-17 2012-04-04 オンセミコンダクター・トレーディング・リミテッド memory
DE102004015899B4 (en) * 2004-03-31 2009-01-02 Qimonda Ag Manufacturing method for a PCM memory element
US7301887B2 (en) 2004-04-16 2007-11-27 Nanochip, Inc. Methods for erasing bit cells in a high density data storage device
US7379412B2 (en) 2004-04-16 2008-05-27 Nanochip, Inc. Methods for writing and reading highly resolved domains for high density data storage
US20050232061A1 (en) 2004-04-16 2005-10-20 Rust Thomas F Systems for writing and reading highly resolved domains for high density data storage
US7354793B2 (en) 2004-08-12 2008-04-08 Micron Technology, Inc. Method of forming a PCRAM device incorporating a resistance-variable chalocogenide element
US7326950B2 (en) 2004-07-19 2008-02-05 Micron Technology, Inc. Memory device with switching glass layer
US7190048B2 (en) 2004-07-19 2007-03-13 Micron Technology, Inc. Resistance variable memory device and method of fabrication
US7084691B2 (en) * 2004-07-21 2006-08-01 Sharp Laboratories Of America, Inc. Mono-polarity switchable PCMO resistor trimmer
US7365411B2 (en) 2004-08-12 2008-04-29 Micron Technology, Inc. Resistance variable memory with temperature tolerant materials
US7151688B2 (en) 2004-09-01 2006-12-19 Micron Technology, Inc. Sensing of resistance variable memory devices
DE602004026447D1 (en) * 2004-09-22 2010-05-20 St Microelectronics Srl Memory arrangement with unipolar and bipolar selection circuits
US7646630B2 (en) * 2004-11-08 2010-01-12 Ovonyx, Inc. Programmable matrix array with chalcogenide material
US7608503B2 (en) 2004-11-22 2009-10-27 Macronix International Co., Ltd. Side wall active pin memory and manufacturing method
ATE497260T1 (en) * 2004-11-30 2011-02-15 Nxp Bv DIELECTRIC ANTIFUSE FOR AN ELECTROTHERMALLY PROGRAMMABLE DEVICE
JP4712545B2 (en) * 2004-11-30 2011-06-29 株式会社半導体エネルギー研究所 Semiconductor device
JP2006156886A (en) * 2004-12-01 2006-06-15 Renesas Technology Corp Semiconductor integrated circuit device and manufacturing method therefor
TW200633193A (en) * 2004-12-02 2006-09-16 Koninkl Philips Electronics Nv Non-volatile memory
JP2006165553A (en) * 2004-12-02 2006-06-22 Samsung Electronics Co Ltd Phase-change memory device comprising phase-change substance layer including phase-change nano particle and method for manufacturing the same
US7220983B2 (en) 2004-12-09 2007-05-22 Macronix International Co., Ltd. Self-aligned small contact phase-change memory method and device
CN101185167A (en) 2004-12-13 2008-05-21 Nxp股份有限公司 Programmable phase-change memory and method therefor
US7374174B2 (en) 2004-12-22 2008-05-20 Micron Technology, Inc. Small electrode for resistance variable devices
US7709334B2 (en) 2005-12-09 2010-05-04 Macronix International Co., Ltd. Stacked non-volatile memory device and methods for fabricating the same
JP4345676B2 (en) * 2005-01-12 2009-10-14 エルピーダメモリ株式会社 Semiconductor memory device
US7307268B2 (en) * 2005-01-19 2007-12-11 Sandisk Corporation Structure and method for biasing phase change memory array for reliable writing
CN101164176A (en) * 2005-01-25 2008-04-16 Nxp股份有限公司 Fabrication of a phase-change resistor using a backend process
US7317200B2 (en) 2005-02-23 2008-01-08 Micron Technology, Inc. SnSe-based limited reprogrammable cell
KR100663358B1 (en) * 2005-02-24 2007-01-02 삼성전자주식회사 Phase change memory devices employing cell diodes and methods of fabricating the same
DE602005018744D1 (en) * 2005-04-08 2010-02-25 St Microelectronics Srl Lateral phase change memory
US7427770B2 (en) 2005-04-22 2008-09-23 Micron Technology, Inc. Memory array for increased bit density
US7269044B2 (en) 2005-04-22 2007-09-11 Micron Technology, Inc. Method and apparatus for accessing a memory array
US7709289B2 (en) 2005-04-22 2010-05-04 Micron Technology, Inc. Memory elements having patterned electrodes and method of forming the same
EP1717817B8 (en) * 2005-04-29 2016-05-18 Micron Technology, Inc. A semiconductor memory device with information loss self-detect capability
US20060250836A1 (en) * 2005-05-09 2006-11-09 Matrix Semiconductor, Inc. Rewriteable memory cell comprising a diode and a resistance-switching material
US7812404B2 (en) * 2005-05-09 2010-10-12 Sandisk 3D Llc Nonvolatile memory cell comprising a diode and a resistance-switching material
US7269079B2 (en) 2005-05-16 2007-09-11 Micron Technology, Inc. Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory
US20060273298A1 (en) * 2005-06-02 2006-12-07 Matrix Semiconductor, Inc. Rewriteable memory cell comprising a transistor and resistance-switching material in series
US7221579B2 (en) * 2005-06-13 2007-05-22 International Business Machines Corporation Method and structure for high performance phase change memory
US7696503B2 (en) * 2005-06-17 2010-04-13 Macronix International Co., Ltd. Multi-level memory cell having phase change element and asymmetrical thermal boundary
US7598512B2 (en) * 2005-06-17 2009-10-06 Macronix International Co., Ltd. Thin film fuse phase change cell with thermal isolation layer and manufacturing method
US7514367B2 (en) * 2005-06-17 2009-04-07 Macronix International Co., Ltd. Method for manufacturing a narrow structure on an integrated circuit
US7238994B2 (en) 2005-06-17 2007-07-03 Macronix International Co., Ltd. Thin film plate phase change ram circuit and manufacturing method
US7321130B2 (en) * 2005-06-17 2008-01-22 Macronix International Co., Ltd. Thin film fuse phase change RAM and manufacturing method
US7534647B2 (en) 2005-06-17 2009-05-19 Macronix International Co., Ltd. Damascene phase change RAM and manufacturing method
US8237140B2 (en) * 2005-06-17 2012-08-07 Macronix International Co., Ltd. Self-aligned, embedded phase change RAM
US7514288B2 (en) * 2005-06-17 2009-04-07 Macronix International Co., Ltd. Manufacturing methods for thin film fuse phase change ram
US7367119B2 (en) 2005-06-24 2008-05-06 Nanochip, Inc. Method for forming a reinforced tip for a probe storage device
JP2007005580A (en) * 2005-06-24 2007-01-11 Sanyo Electric Co Ltd Memory
US7463573B2 (en) 2005-06-24 2008-12-09 Nanochip, Inc. Patterned media for a high density data storage device
US7233520B2 (en) 2005-07-08 2007-06-19 Micron Technology, Inc. Process for erasing chalcogenide variable resistance memory bits
US7309630B2 (en) 2005-07-08 2007-12-18 Nanochip, Inc. Method for forming patterned media for a high density data storage device
JP4907916B2 (en) * 2005-07-22 2012-04-04 オンセミコンダクター・トレーディング・リミテッド memory
US7274034B2 (en) 2005-08-01 2007-09-25 Micron Technology, Inc. Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication
US7332735B2 (en) 2005-08-02 2008-02-19 Micron Technology, Inc. Phase change memory cell and method of formation
US7317567B2 (en) 2005-08-02 2008-01-08 Micron Technology, Inc. Method and apparatus for providing color changing thin film material
US7767992B2 (en) * 2005-08-09 2010-08-03 Ovonyx, Inc. Multi-layer chalcogenide devices
US7525117B2 (en) * 2005-08-09 2009-04-28 Ovonyx, Inc. Chalcogenide devices and materials having reduced germanium or telluruim content
US7579615B2 (en) 2005-08-09 2009-08-25 Micron Technology, Inc. Access transistor for memory device
CN100364132C (en) * 2005-08-11 2008-01-23 上海交通大学 Silicon-contained series surfur-family compound phase transformation film material for phase transformation memory
US7304368B2 (en) 2005-08-11 2007-12-04 Micron Technology, Inc. Chalcogenide-based electrokinetic memory element and method of forming the same
US7251154B2 (en) 2005-08-15 2007-07-31 Micron Technology, Inc. Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance
US7277313B2 (en) 2005-08-31 2007-10-02 Micron Technology, Inc. Resistance variable memory element with threshold device and method of forming the same
JP4817410B2 (en) * 2005-09-12 2011-11-16 エルピーダメモリ株式会社 Phase change memory device and manufacturing method thereof
CN101292350B (en) * 2005-10-17 2012-08-22 瑞萨电子株式会社 Semiconductor device and manufacturing method thereof
US9127362B2 (en) 2005-10-31 2015-09-08 Applied Materials, Inc. Process kit and target for substrate processing chamber
US8183551B2 (en) 2005-11-03 2012-05-22 Agale Logic, Inc. Multi-terminal phase change devices
US20070111429A1 (en) * 2005-11-14 2007-05-17 Macronix International Co., Ltd. Method of manufacturing a pipe shaped phase change memory
US7397060B2 (en) * 2005-11-14 2008-07-08 Macronix International Co., Ltd. Pipe shaped phase change memory
US7394088B2 (en) 2005-11-15 2008-07-01 Macronix International Co., Ltd. Thermally contained/insulated phase change memory device and method (combined)
US7450411B2 (en) 2005-11-15 2008-11-11 Macronix International Co., Ltd. Phase change memory device and manufacturing method
US7635855B2 (en) 2005-11-15 2009-12-22 Macronix International Co., Ltd. I-shaped phase change memory cell
US7786460B2 (en) * 2005-11-15 2010-08-31 Macronix International Co., Ltd. Phase change memory device and manufacturing method
US7414258B2 (en) 2005-11-16 2008-08-19 Macronix International Co., Ltd. Spacer electrode small pin phase change memory RAM and manufacturing method
US7507986B2 (en) 2005-11-21 2009-03-24 Macronix International Co., Ltd. Thermal isolation for an active-sidewall phase change memory cell
US7449710B2 (en) 2005-11-21 2008-11-11 Macronix International Co., Ltd. Vacuum jacket for phase change memory element
CN100524878C (en) 2005-11-21 2009-08-05 旺宏电子股份有限公司 Programmable resistor material storage array with air insulating unit
US7479649B2 (en) 2005-11-21 2009-01-20 Macronix International Co., Ltd. Vacuum jacketed electrode for phase change memory element
US7829876B2 (en) 2005-11-21 2010-11-09 Macronix International Co., Ltd. Vacuum cell thermal isolation for a phase change memory device
US7599217B2 (en) 2005-11-22 2009-10-06 Macronix International Co., Ltd. Memory cell device and manufacturing method
US7834338B2 (en) * 2005-11-23 2010-11-16 Sandisk 3D Llc Memory cell comprising nickel-cobalt oxide switching element
US7816659B2 (en) * 2005-11-23 2010-10-19 Sandisk 3D Llc Devices having reversible resistivity-switching metal oxide or nitride layer with added metal
US8790499B2 (en) 2005-11-25 2014-07-29 Applied Materials, Inc. Process kit components for titanium sputtering chamber
US7459717B2 (en) * 2005-11-28 2008-12-02 Macronix International Co., Ltd. Phase change memory cell and manufacturing method
US7688619B2 (en) 2005-11-28 2010-03-30 Macronix International Co., Ltd. Phase change memory cell and manufacturing method
US7521364B2 (en) 2005-12-02 2009-04-21 Macronix Internation Co., Ltd. Surface topology improvement method for plug surface areas
US7605079B2 (en) * 2005-12-05 2009-10-20 Macronix International Co., Ltd. Manufacturing method for phase change RAM with electrode layer process
US7642539B2 (en) * 2005-12-13 2010-01-05 Macronix International Co., Ltd. Thin film fuse phase change cell with thermal isolation pad and manufacturing method
GB2433647B (en) * 2005-12-20 2008-05-28 Univ Southampton Phase change memory materials, devices and methods
US7531825B2 (en) 2005-12-27 2009-05-12 Macronix International Co., Ltd. Method for forming self-aligned thermal isolation cell for a variable resistance memory array
US8062833B2 (en) * 2005-12-30 2011-11-22 Macronix International Co., Ltd. Chalcogenide layer etching method
US7560337B2 (en) 2006-01-09 2009-07-14 Macronix International Co., Ltd. Programmable resistive RAM and manufacturing method
US7595218B2 (en) 2006-01-09 2009-09-29 Macronix International Co., Ltd. Programmable resistive RAM and manufacturing method
US7741636B2 (en) * 2006-01-09 2010-06-22 Macronix International Co., Ltd. Programmable resistive RAM and manufacturing method
US7825396B2 (en) * 2006-01-11 2010-11-02 Macronix International Co., Ltd. Self-align planerized bottom electrode phase change memory and manufacturing method
US7432206B2 (en) 2006-01-24 2008-10-07 Macronix International Co., Ltd. Self-aligned manufacturing method, and manufacturing method for thin film fuse phase change ram
US7456421B2 (en) * 2006-01-30 2008-11-25 Macronix International Co., Ltd. Vertical side wall active pin structures in a phase change memory and manufacturing methods
US7956358B2 (en) * 2006-02-07 2011-06-07 Macronix International Co., Ltd. I-shaped phase change memory cell with thermal isolation
KR101004207B1 (en) 2006-03-09 2010-12-24 파나소닉 주식회사 Resistance-varying type element, semiconductor device, and method for manufacturing the element
US7910907B2 (en) * 2006-03-15 2011-03-22 Macronix International Co., Ltd. Manufacturing method for pipe-shaped electrode phase change memory
US8395199B2 (en) * 2006-03-25 2013-03-12 4D-S Pty Ltd. Systems and methods for fabricating self-aligned memory cell
US7875871B2 (en) * 2006-03-31 2011-01-25 Sandisk 3D Llc Heterojunction device comprising a semiconductor and a resistivity-switching oxide or nitride
US7829875B2 (en) 2006-03-31 2010-11-09 Sandisk 3D Llc Nonvolatile rewritable memory cell comprising a resistivity-switching oxide or nitride and an antifuse
US7808810B2 (en) * 2006-03-31 2010-10-05 Sandisk 3D Llc Multilevel nonvolatile memory cell comprising a resistivity-switching oxide or nitride and an antifuse
US7554144B2 (en) * 2006-04-17 2009-06-30 Macronix International Co., Ltd. Memory device and manufacturing method
US7928421B2 (en) 2006-04-21 2011-04-19 Macronix International Co., Ltd. Phase change memory cell with vacuum spacer
US8129706B2 (en) * 2006-05-05 2012-03-06 Macronix International Co., Ltd. Structures and methods of a bistable resistive random access memory
US7608848B2 (en) * 2006-05-09 2009-10-27 Macronix International Co., Ltd. Bridge resistance random access memory device with a singular contact structure
KR100782482B1 (en) * 2006-05-19 2007-12-05 삼성전자주식회사 Phase change memory cell employing a GeBiTe layer as a phase change material layer, phase change memory device including the same, electronic device including the same and method of fabricating the same
US7547906B2 (en) * 2006-05-22 2009-06-16 Ovonyx, Inc. Multi-functional chalcogenide electronic devices having gain
US7423300B2 (en) 2006-05-24 2008-09-09 Macronix International Co., Ltd. Single-mask phase change memory element
US7820997B2 (en) * 2006-05-30 2010-10-26 Macronix International Co., Ltd. Resistor random access memory cell with reduced active area and reduced contact areas
US7732800B2 (en) * 2006-05-30 2010-06-08 Macronix International Co., Ltd. Resistor random access memory cell with L-shaped electrode
US20070279975A1 (en) * 2006-06-06 2007-12-06 Hudgens Stephen J Refreshing a phase change memory
JP5039035B2 (en) * 2006-06-23 2012-10-03 ルネサスエレクトロニクス株式会社 Semiconductor device
US7696506B2 (en) 2006-06-27 2010-04-13 Macronix International Co., Ltd. Memory cell with memory material insulation and manufacturing method
US7785920B2 (en) 2006-07-12 2010-08-31 Macronix International Co., Ltd. Method for making a pillar-type phase change memory element
US7932548B2 (en) 2006-07-14 2011-04-26 4D-S Pty Ltd. Systems and methods for fabricating self-aligned memory cell
US7442603B2 (en) * 2006-08-16 2008-10-28 Macronix International Co., Ltd. Self-aligned structure and method for confining a melting point in a resistor random access memory
US7560723B2 (en) 2006-08-29 2009-07-14 Micron Technology, Inc. Enhanced memory density resistance variable memory cells, arrays, devices and systems including the same, and methods of fabrication
US7772581B2 (en) 2006-09-11 2010-08-10 Macronix International Co., Ltd. Memory device having wide area phase change element and small electrode contact area
KR100810615B1 (en) * 2006-09-20 2008-03-06 삼성전자주식회사 Phase change memory device having high temp phase change pattern and method of fabricating the same
JP2008085204A (en) * 2006-09-28 2008-04-10 Toshiba Corp Semiconductor memory device, and its manufacturing method
US7504653B2 (en) * 2006-10-04 2009-03-17 Macronix International Co., Ltd. Memory cell device with circumferentially-extending memory element
US7510929B2 (en) * 2006-10-18 2009-03-31 Macronix International Co., Ltd. Method for making memory cell device
US7527985B2 (en) 2006-10-24 2009-05-05 Macronix International Co., Ltd. Method for manufacturing a resistor random access memory with reduced active area and reduced contact areas
US20080094885A1 (en) * 2006-10-24 2008-04-24 Macronix International Co., Ltd. Bistable Resistance Random Access Memory Structures with Multiple Memory Layers and Multilevel Memory States
US7863655B2 (en) 2006-10-24 2011-01-04 Macronix International Co., Ltd. Phase change memory cells with dual access devices
US7388771B2 (en) * 2006-10-24 2008-06-17 Macronix International Co., Ltd. Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states
US8500963B2 (en) * 2006-10-26 2013-08-06 Applied Materials, Inc. Sputtering of thermally resistive materials including metal chalcogenides
KR20080042548A (en) * 2006-11-10 2008-05-15 삼성전자주식회사 Hinge module and electronic equipment havint the same
US8067762B2 (en) * 2006-11-16 2011-11-29 Macronix International Co., Ltd. Resistance random access memory structure for enhanced retention
US7682868B2 (en) 2006-12-06 2010-03-23 Macronix International Co., Ltd. Method for making a keyhole opening during the manufacture of a memory cell
US7473576B2 (en) * 2006-12-06 2009-01-06 Macronix International Co., Ltd. Method for making a self-converged void and bottom electrode for memory cell
US7476587B2 (en) * 2006-12-06 2009-01-13 Macronix International Co., Ltd. Method for making a self-converged memory material element for memory cell
US7697316B2 (en) * 2006-12-07 2010-04-13 Macronix International Co., Ltd. Multi-level cell resistance random access memory with metal oxides
US7903447B2 (en) 2006-12-13 2011-03-08 Macronix International Co., Ltd. Method, apparatus and computer program product for read before programming process on programmable resistive memory cell
US8344347B2 (en) 2006-12-15 2013-01-01 Macronix International Co., Ltd. Multi-layer electrode structure
US7718989B2 (en) * 2006-12-28 2010-05-18 Macronix International Co., Ltd. Resistor random access memory cell device
US7515461B2 (en) * 2007-01-05 2009-04-07 Macronix International Co., Ltd. Current compliant sensing architecture for multilevel phase change memory
US7440315B2 (en) 2007-01-09 2008-10-21 Macronix International Co., Ltd. Method, apparatus and computer program product for stepped reset programming process on programmable resistive memory cell
US7433226B2 (en) * 2007-01-09 2008-10-07 Macronix International Co., Ltd. Method, apparatus and computer program product for read before programming process on multiple programmable resistive memory cell
KR100885184B1 (en) 2007-01-30 2009-02-23 삼성전자주식회사 Memory Devices Having Resistance Property Capable Of Being Independently Controlled By Electric And Magnetic Fields And Methods Of Operating The Same
US7663135B2 (en) 2007-01-31 2010-02-16 Macronix International Co., Ltd. Memory cell having a side electrode contact
US7535756B2 (en) 2007-01-31 2009-05-19 Macronix International Co., Ltd. Method to tighten set distribution for PCRAM
TWI347670B (en) * 2007-02-01 2011-08-21 Promos Technologies Inc Phase-change memory and fabrication method thereof
US7619311B2 (en) 2007-02-02 2009-11-17 Macronix International Co., Ltd. Memory cell device with coplanar electrode surface and method
US7701759B2 (en) * 2007-02-05 2010-04-20 Macronix International Co., Ltd. Memory cell device and programming methods
US7483292B2 (en) * 2007-02-07 2009-01-27 Macronix International Co., Ltd. Memory cell with separate read and program paths
US7463512B2 (en) 2007-02-08 2008-12-09 Macronix International Co., Ltd. Memory element with reduced-current phase change element
US8138028B2 (en) 2007-02-12 2012-03-20 Macronix International Co., Ltd Method for manufacturing a phase change memory device with pillar bottom electrode
US7884343B2 (en) * 2007-02-14 2011-02-08 Macronix International Co., Ltd. Phase change memory cell with filled sidewall memory element and method for fabricating the same
US8008643B2 (en) * 2007-02-21 2011-08-30 Macronix International Co., Ltd. Phase change memory cell with heater and method for fabricating the same
US7619237B2 (en) * 2007-02-21 2009-11-17 Macronix International Co., Ltd. Programmable resistive memory cell with self-forming gap
US7504675B2 (en) * 2007-02-22 2009-03-17 Intel Corporation Phase change memories with improved programming characteristics
US7956344B2 (en) * 2007-02-27 2011-06-07 Macronix International Co., Ltd. Memory cell with memory element contacting ring-shaped upper end of bottom electrode
JP2008217937A (en) * 2007-03-06 2008-09-18 Toshiba Corp Ferroelectric substance storage device and control method
US7728405B2 (en) * 2007-03-08 2010-06-01 Qimonda Ag Carbon memory
US7969769B2 (en) * 2007-03-15 2011-06-28 Ovonyx, Inc. Multi-terminal chalcogenide logic circuits
US7626860B2 (en) * 2007-03-23 2009-12-01 International Business Machines Corporation Optimized phase change write method
US7786461B2 (en) * 2007-04-03 2010-08-31 Macronix International Co., Ltd. Memory structure with reduced-size memory element between memory material portions
US8610098B2 (en) * 2007-04-06 2013-12-17 Macronix International Co., Ltd. Phase change memory bridge cell with diode isolation device
US7755076B2 (en) * 2007-04-17 2010-07-13 Macronix International Co., Ltd. 4F2 self align side wall active phase change memory
US7569844B2 (en) 2007-04-17 2009-08-04 Macronix International Co., Ltd. Memory cell sidewall contacting side electrode
US7483316B2 (en) * 2007-04-24 2009-01-27 Macronix International Co., Ltd. Method and apparatus for refreshing programmable resistive memory
WO2008132701A1 (en) * 2007-05-01 2008-11-06 Interuniversitair Microelektronica Centrum Vzw Non-volatile memory device
US7888771B1 (en) 2007-05-02 2011-02-15 Xilinx, Inc. E-fuse with scalable filament link
KR101350979B1 (en) * 2007-05-11 2014-01-14 삼성전자주식회사 Resistive memory device and Manufacturing Method for the same
JPWO2008142768A1 (en) * 2007-05-21 2010-08-05 株式会社ルネサステクノロジ Semiconductor device and manufacturing method thereof
US8125821B2 (en) * 2007-06-01 2012-02-28 Infineon Technologies Ag Method of operating phase-change memory
US7692951B2 (en) 2007-06-12 2010-04-06 Kabushiki Kaisha Toshiba Resistance change memory device with a variable resistance element formed of a first and a second composite compound
US8968536B2 (en) 2007-06-18 2015-03-03 Applied Materials, Inc. Sputtering target having increased life and sputtering uniformity
US7846785B2 (en) * 2007-06-29 2010-12-07 Sandisk 3D Llc Memory cell that employs a selectively deposited reversible resistance-switching element and methods of forming the same
US7902537B2 (en) 2007-06-29 2011-03-08 Sandisk 3D Llc Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same
US8233308B2 (en) 2007-06-29 2012-07-31 Sandisk 3D Llc Memory cell that employs a selectively deposited reversible resistance-switching element and methods of forming the same
US7824956B2 (en) * 2007-06-29 2010-11-02 Sandisk 3D Llc Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same
US8513637B2 (en) * 2007-07-13 2013-08-20 Macronix International Co., Ltd. 4F2 self align fin bottom electrodes FET drive phase change memory
US7777215B2 (en) * 2007-07-20 2010-08-17 Macronix International Co., Ltd. Resistive memory structure with buffer layer
US7884342B2 (en) 2007-07-31 2011-02-08 Macronix International Co., Ltd. Phase change memory bridge cell
US7729161B2 (en) 2007-08-02 2010-06-01 Macronix International Co., Ltd. Phase change memory with dual word lines and source lines and method of operating same
US9018615B2 (en) * 2007-08-03 2015-04-28 Macronix International Co., Ltd. Resistor random access memory structure having a defined small area of electrical contact
DE602007010624D1 (en) * 2007-09-07 2010-12-30 Milano Politecnico Phase change memory device for multi-bit storage
US8178386B2 (en) 2007-09-14 2012-05-15 Macronix International Co., Ltd. Phase change memory cell array with self-converged bottom electrode and method for manufacturing
US7642125B2 (en) 2007-09-14 2010-01-05 Macronix International Co., Ltd. Phase change memory cell in via array with self-aligned, self-converged bottom electrode and method for manufacturing
WO2009044769A1 (en) * 2007-10-02 2009-04-09 Ulvac, Inc. Chalcogenide film and method for producing the same
KR101281685B1 (en) 2007-10-04 2013-07-03 삼성전자주식회사 Method for writing and reading data of phase-change random access memory and apparatus thereof
US7901552B2 (en) 2007-10-05 2011-03-08 Applied Materials, Inc. Sputtering target with grooves and intersecting channels
US20090091968A1 (en) * 2007-10-08 2009-04-09 Stefan Dietrich Integrated circuit including a memory having a data inversion circuit
US7551473B2 (en) 2007-10-12 2009-06-23 Macronix International Co., Ltd. Programmable resistive memory with diode structure
US7919766B2 (en) 2007-10-22 2011-04-05 Macronix International Co., Ltd. Method for making self aligning pillar memory cell device
US20090107834A1 (en) * 2007-10-29 2009-04-30 Applied Materials, Inc. Chalcogenide target and method
US8098517B2 (en) * 2007-10-31 2012-01-17 Ovonyx, Inc. Method of restoring variable resistance memory device
US7804083B2 (en) 2007-11-14 2010-09-28 Macronix International Co., Ltd. Phase change memory cell including a thermal protect bottom electrode and manufacturing methods
JP2009135219A (en) * 2007-11-29 2009-06-18 Renesas Technology Corp Semiconductor device, and method of manufacturing same
US7646631B2 (en) 2007-12-07 2010-01-12 Macronix International Co., Ltd. Phase change memory cell having interface structures with essentially equal thermal impedances and manufacturing methods
KR101198100B1 (en) 2007-12-11 2012-11-09 삼성전자주식회사 Method of forming a phase-change material layer pattern, method of manufacturing a phase-change memory device and slurry composition used for the methods
US7791933B2 (en) * 2007-12-21 2010-09-07 International Business Machines Corporation Optimized phase change write method
US8314391B2 (en) * 2007-12-31 2012-11-20 Honeywell Asca Inc. Controlling the bends in a fiber optic cable to eliminate measurement error in a scanning terahertz sensor
US7639527B2 (en) 2008-01-07 2009-12-29 Macronix International Co., Ltd. Phase change memory dynamic resistance test and manufacturing methods
US7879643B2 (en) 2008-01-18 2011-02-01 Macronix International Co., Ltd. Memory cell with memory element contacting an inverted T-shaped bottom electrode
JP4929228B2 (en) * 2008-01-23 2012-05-09 韓國電子通信研究院 Phase change memory device and manufacturing method thereof
US7879645B2 (en) 2008-01-28 2011-02-01 Macronix International Co., Ltd. Fill-in etching free pore device
JP5268376B2 (en) * 2008-01-29 2013-08-21 株式会社日立製作所 Nonvolatile memory device and manufacturing method thereof
US8158965B2 (en) 2008-02-05 2012-04-17 Macronix International Co., Ltd. Heating center PCRAM structure and methods for making
US7834659B1 (en) 2008-03-05 2010-11-16 Xilinx, Inc. Multi-step programming of E fuse cells
US7710813B1 (en) 2008-03-05 2010-05-04 Xilinx, Inc. Electronic fuse array
US7724600B1 (en) 2008-03-05 2010-05-25 Xilinx, Inc. Electronic fuse programming current generator with on-chip reference
US7923811B1 (en) 2008-03-06 2011-04-12 Xilinx, Inc. Electronic fuse cell with enhanced thermal gradient
US8564023B2 (en) * 2008-03-06 2013-10-22 Xilinx, Inc. Integrated circuit with MOSFET fuse element
US8084842B2 (en) 2008-03-25 2011-12-27 Macronix International Co., Ltd. Thermally stabilized electrode structure
US8030634B2 (en) 2008-03-31 2011-10-04 Macronix International Co., Ltd. Memory array with diode driver and method for fabricating the same
US7825398B2 (en) 2008-04-07 2010-11-02 Macronix International Co., Ltd. Memory cell having improved mechanical stability
US7791057B2 (en) 2008-04-22 2010-09-07 Macronix International Co., Ltd. Memory cell having a buried phase change region and method for fabricating the same
US8077505B2 (en) 2008-05-07 2011-12-13 Macronix International Co., Ltd. Bipolar switching of phase change device
US7701750B2 (en) * 2008-05-08 2010-04-20 Macronix International Co., Ltd. Phase change device having two or more substantial amorphous regions in high resistance state
US8415651B2 (en) 2008-06-12 2013-04-09 Macronix International Co., Ltd. Phase change memory cell having top and bottom sidewall contacts
US8134857B2 (en) 2008-06-27 2012-03-13 Macronix International Co., Ltd. Methods for high speed reading operation of phase change memory and device employing same
US7932506B2 (en) 2008-07-22 2011-04-26 Macronix International Co., Ltd. Fully self-aligned pore-type memory cell having diode access device
US8467236B2 (en) 2008-08-01 2013-06-18 Boise State University Continuously variable resistor
US7903457B2 (en) * 2008-08-19 2011-03-08 Macronix International Co., Ltd. Multiple phase change materials in an integrated circuit for system on a chip application
US7719913B2 (en) 2008-09-12 2010-05-18 Macronix International Co., Ltd. Sensing circuit for PCRAM applications
US20100090189A1 (en) * 2008-09-15 2010-04-15 Savransky Semyon D Nanoscale electrical device
US8324605B2 (en) 2008-10-02 2012-12-04 Macronix International Co., Ltd. Dielectric mesh isolated phase change structure for phase change memory
US7897954B2 (en) 2008-10-10 2011-03-01 Macronix International Co., Ltd. Dielectric-sandwiched pillar memory device
US8289748B2 (en) * 2008-10-27 2012-10-16 Seagate Technology Llc Tuning a variable resistance of a resistive sense element
US8036014B2 (en) * 2008-11-06 2011-10-11 Macronix International Co., Ltd. Phase change memory program method without over-reset
US8664689B2 (en) 2008-11-07 2014-03-04 Macronix International Co., Ltd. Memory cell access device having a pn-junction with polycrystalline plug and single-crystal semiconductor regions
US8907316B2 (en) * 2008-11-07 2014-12-09 Macronix International Co., Ltd. Memory cell access device having a pn-junction with polycrystalline and single crystal semiconductor regions
KR20100052300A (en) * 2008-11-10 2010-05-19 주식회사 하이닉스반도체 Phase change memory device and method for manufacturing the same
IT1392556B1 (en) 2008-12-18 2012-03-09 St Microelectronics Rousset MATERIAL RESISTOR STRUCTURE AT PHASE CHANGE AND RELATIVE CALIBRATION METHOD
US7869270B2 (en) * 2008-12-29 2011-01-11 Macronix International Co., Ltd. Set algorithm for phase change memory cell
US7835200B2 (en) * 2008-12-30 2010-11-16 Stmicroelectronics S.R.L. Level shifter
US20100165716A1 (en) 2008-12-30 2010-07-01 Stmicroelectronics S.R.L. Nonvolatile memory with ovonic threshold switches
US8148707B2 (en) * 2008-12-30 2012-04-03 Stmicroelectronics S.R.L. Ovonic threshold switch film composition for TSLAGS material
US8093661B2 (en) * 2009-01-07 2012-01-10 Macronix International Co., Ltd. Integrated circuit device with single crystal silicon on silicide and manufacturing method
US8089137B2 (en) 2009-01-07 2012-01-03 Macronix International Co., Ltd. Integrated circuit memory with single crystal silicon on silicide driver and manufacturing method
US8107283B2 (en) 2009-01-12 2012-01-31 Macronix International Co., Ltd. Method for setting PCRAM devices
US8030635B2 (en) 2009-01-13 2011-10-04 Macronix International Co., Ltd. Polysilicon plug bipolar transistor for phase change memory
US8064247B2 (en) * 2009-01-14 2011-11-22 Macronix International Co., Ltd. Rewritable memory device based on segregation/re-absorption
US8933536B2 (en) 2009-01-22 2015-01-13 Macronix International Co., Ltd. Polysilicon pillar bipolar transistor with self-aligned memory element
US8084760B2 (en) 2009-04-20 2011-12-27 Macronix International Co., Ltd. Ring-shaped electrode and manufacturing method for same
US8173987B2 (en) 2009-04-27 2012-05-08 Macronix International Co., Ltd. Integrated circuit 3D phase change memory array and manufacturing method
US8097871B2 (en) 2009-04-30 2012-01-17 Macronix International Co., Ltd. Low operational current phase change memory structures
US7933139B2 (en) 2009-05-15 2011-04-26 Macronix International Co., Ltd. One-transistor, one-resistor, one-capacitor phase change memory
US7968876B2 (en) * 2009-05-22 2011-06-28 Macronix International Co., Ltd. Phase change memory cell having vertical channel access transistor
US8350316B2 (en) 2009-05-22 2013-01-08 Macronix International Co., Ltd. Phase change memory cells having vertical channel access transistor and memory plane
US8809829B2 (en) 2009-06-15 2014-08-19 Macronix International Co., Ltd. Phase change memory having stabilized microstructure and manufacturing method
US8406033B2 (en) * 2009-06-22 2013-03-26 Macronix International Co., Ltd. Memory device and method for sensing and fixing margin cells
US8238149B2 (en) * 2009-06-25 2012-08-07 Macronix International Co., Ltd. Methods and apparatus for reducing defect bits in phase change memory
US8363463B2 (en) * 2009-06-25 2013-01-29 Macronix International Co., Ltd. Phase change memory having one or more non-constant doping profiles
US8198619B2 (en) 2009-07-15 2012-06-12 Macronix International Co., Ltd. Phase change memory cell structure
US8110822B2 (en) * 2009-07-15 2012-02-07 Macronix International Co., Ltd. Thermal protect PCRAM structure and methods for making
US7894254B2 (en) * 2009-07-15 2011-02-22 Macronix International Co., Ltd. Refresh circuitry for phase change memory
US20110049456A1 (en) * 2009-09-03 2011-03-03 Macronix International Co., Ltd. Phase change structure with composite doping for phase change memory
US8064248B2 (en) * 2009-09-17 2011-11-22 Macronix International Co., Ltd. 2T2R-1T1R mix mode phase change memory array
US8178387B2 (en) * 2009-10-23 2012-05-15 Macronix International Co., Ltd. Methods for reducing recrystallization time for a phase change material
US8729521B2 (en) 2010-05-12 2014-05-20 Macronix International Co., Ltd. Self aligned fin-type programmable memory cell
US8310864B2 (en) 2010-06-15 2012-11-13 Macronix International Co., Ltd. Self-aligned bit line under word line memory array
US9082954B2 (en) 2010-09-24 2015-07-14 Macronix International Co., Ltd. PCRAM with current flowing laterally relative to axis defined by electrodes
US8395935B2 (en) 2010-10-06 2013-03-12 Macronix International Co., Ltd. Cross-point self-aligned reduced cell size phase change memory
KR101795417B1 (en) 2010-11-08 2017-11-10 삼성전자주식회사 Non-volatile memory cell array and non-volatile memory device
US8497705B2 (en) 2010-11-09 2013-07-30 Macronix International Co., Ltd. Phase change device for interconnection of programmable logic device
US8467238B2 (en) 2010-11-15 2013-06-18 Macronix International Co., Ltd. Dynamic pulse operation for phase change memory
US8486743B2 (en) 2011-03-23 2013-07-16 Micron Technology, Inc. Methods of forming memory cells
US8605495B2 (en) 2011-05-09 2013-12-10 Macronix International Co., Ltd. Isolation device free memory
US8638443B2 (en) 2011-05-24 2014-01-28 Honeywell International Inc. Error compensation in a spectrometer
US8874865B2 (en) 2011-09-09 2014-10-28 International Business Machines Corporation Memory type-specific access control of a field of a record
US8994489B2 (en) 2011-10-19 2015-03-31 Micron Technology, Inc. Fuses, and methods of forming and using fuses
US8546231B2 (en) 2011-11-17 2013-10-01 Micron Technology, Inc. Memory arrays and methods of forming memory cells
US9252188B2 (en) 2011-11-17 2016-02-02 Micron Technology, Inc. Methods of forming memory cells
US8723155B2 (en) 2011-11-17 2014-05-13 Micron Technology, Inc. Memory cells and integrated devices
US8987700B2 (en) 2011-12-02 2015-03-24 Macronix International Co., Ltd. Thermally confined electrode for programmable resistance memory
US8680499B2 (en) 2012-01-23 2014-03-25 Micron Technology, Inc. Memory cells
US8765555B2 (en) 2012-04-30 2014-07-01 Micron Technology, Inc. Phase change memory cells and methods of forming phase change memory cells
US9136467B2 (en) 2012-04-30 2015-09-15 Micron Technology, Inc. Phase change memory cells and methods of forming phase change memory cells
TWI469408B (en) * 2012-05-07 2015-01-11 Univ Feng Chia Ultra-thin multi-layered phase-change memory devices
US8927957B2 (en) 2012-08-09 2015-01-06 Macronix International Co., Ltd. Sidewall diode driving device and memory using same
US20140117302A1 (en) * 2012-11-01 2014-05-01 Micron Technology, Inc. Phase Change Memory Cells, Methods Of Forming Phase Change Memory Cells, And Methods Of Forming Heater Material For Phase Change Memory Cells
US8742390B1 (en) * 2012-11-12 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Logic compatible RRAM structure and process
US9231197B2 (en) * 2012-11-12 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Logic compatible RRAM structure and process
US9553262B2 (en) 2013-02-07 2017-01-24 Micron Technology, Inc. Arrays of memory cells and methods of forming an array of memory cells
US9508712B2 (en) 2014-01-02 2016-11-29 Globalfoundries Inc. Semiconductor device with a multiple nanowire channel structure and methods of variably connecting such nanowires for current density modulation
US9336879B2 (en) 2014-01-24 2016-05-10 Macronix International Co., Ltd. Multiple phase change materials in an integrated circuit for system on a chip application
US9881971B2 (en) 2014-04-01 2018-01-30 Micron Technology, Inc. Memory arrays
US9559113B2 (en) 2014-05-01 2017-01-31 Macronix International Co., Ltd. SSL/GSL gate oxide in 3D vertical channel NAND
US9362494B2 (en) 2014-06-02 2016-06-07 Micron Technology, Inc. Array of cross point memory cells and methods of forming an array of cross point memory cells
US9343506B2 (en) 2014-06-04 2016-05-17 Micron Technology, Inc. Memory arrays with polygonal memory cells having specific sidewall orientations
US9159412B1 (en) 2014-07-15 2015-10-13 Macronix International Co., Ltd. Staggered write and verify for phase change memory
US9450183B2 (en) * 2014-08-12 2016-09-20 Taiwan Semiconductor Manufacturing Co., Ltd. Memory structure having top electrode with protrusion
US9672906B2 (en) 2015-06-19 2017-06-06 Macronix International Co., Ltd. Phase change memory with inter-granular switching

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3271591A (en) * 1963-09-20 1966-09-06 Energy Conversion Devices Inc Symmetrical current controlling device
US3699543A (en) * 1968-11-04 1972-10-17 Energy Conversion Devices Inc Combination film deposited switch unit and integrated circuits
US3530441A (en) * 1969-01-15 1970-09-22 Energy Conversion Devices Inc Method and apparatus for storing and retrieving information
US3918032A (en) * 1974-12-05 1975-11-04 Us Army Amorphous semiconductor switch and memory with a crystallization-accelerating layer
US4177475A (en) * 1977-10-31 1979-12-04 Burroughs Corporation High temperature amorphous memory device for an electrically alterable read-only memory
US4203123A (en) * 1977-12-12 1980-05-13 Burroughs Corporation Thin film memory device employing amorphous semiconductor materials
IL61678A (en) * 1979-12-13 1984-04-30 Energy Conversion Devices Inc Programmable cell and programmable electronic arrays comprising such cells
US4499557A (en) * 1980-10-28 1985-02-12 Energy Conversion Devices, Inc. Programmable cell for use in programmable electronic arrays
US4586164A (en) * 1984-04-12 1986-04-29 Ltv Aerospace And Defense Company Random access memory device utilizing phase change materials
US4845533A (en) * 1986-08-22 1989-07-04 Energy Conversion Devices, Inc. Thin film electrical devices with amorphous carbon electrodes and method of making same
CA1337582C (en) * 1988-08-09 1995-11-21 Donald Robert Preuss Optical recording materials comprising antimony-tin alloys including a third element
SU1691890A1 (en) * 1990-02-27 1991-11-15 Ленинградское научно-производственное объединение "Красная заря" Memory chip

Also Published As

Publication number Publication date
EP0495494B1 (en) 1996-06-26
CN1064366A (en) 1992-09-09
JPH0521740A (en) 1993-01-29
KR100196489B1 (en) 1999-06-15
DE69211719D1 (en) 1996-08-01
RU2130217C1 (en) 1999-05-10
EP0495494A1 (en) 1992-07-22
CN1044046C (en) 1999-07-07
US5166758A (en) 1992-11-24
ATE139862T1 (en) 1996-07-15
TW231354B (en) 1994-10-01
DE69211719T2 (en) 1996-10-31
MX9200210A (en) 1992-08-01
KR920015557A (en) 1992-08-27
JP3224253B2 (en) 2001-10-29

Similar Documents

Publication Publication Date Title
CA2059476C (en) Electrically erasable phase change memory
US5296716A (en) Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom
US5341328A (en) Electrically erasable memory elements having reduced switching current requirements and increased write/erase cycle life
EP0846343B1 (en) Electrically erasable memory elements characterized by reduced current and improved thermal stability
US5414271A (en) Electrically erasable memory elements having improved set resistance stability
EP0938731B1 (en) Memory element with energy control mechanism
US5359205A (en) Electrically erasable memory elements characterized by reduced current and improved thermal stability
US5534711A (en) Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom
EP0601068B1 (en) Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom
USRE37259E1 (en) Multibit single cell memory element having tapered contact
EP0843901B1 (en) Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom
EP0694214B1 (en) Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom
EP0947005B1 (en) Composite memory material comprising a mixture of phase-change memory material and dielectric material
US7023009B2 (en) Electrically programmable memory element with improved contacts
US8624293B2 (en) Carbon/tunneling-barrier/carbon diode
US10991879B2 (en) Multi-level phase change memory cells and method of making the same
US11031435B2 (en) Memory device containing ovonic threshold switch material thermal isolation and method of making the same
CA2229611C (en) Electrically erasable memory elements characterized by reduced current and improved thermal stability

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed