CA2061264A1 - Etching solution for etching porous silicon, etching method using the etching solution and method of preparing semiconductor member using the etching solution - Google Patents

Etching solution for etching porous silicon, etching method using the etching solution and method of preparing semiconductor member using the etching solution

Info

Publication number
CA2061264A1
CA2061264A1 CA2061264A CA2061264A CA2061264A1 CA 2061264 A1 CA2061264 A1 CA 2061264A1 CA 2061264 A CA2061264 A CA 2061264A CA 2061264 A CA2061264 A CA 2061264A CA 2061264 A1 CA2061264 A1 CA 2061264A1
Authority
CA
Canada
Prior art keywords
etching
etching solution
porous silicon
solution
semiconductor member
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2061264A
Other languages
French (fr)
Other versions
CA2061264C (en
Inventor
Kiyofumi Sakaguchi
Takao Yonehara
Nobuhiko Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP3148164A external-priority patent/JPH04346418A/en
Priority claimed from JP3149297A external-priority patent/JPH04349621A/en
Application filed by Individual filed Critical Individual
Publication of CA2061264A1 publication Critical patent/CA2061264A1/en
Application granted granted Critical
Publication of CA2061264C publication Critical patent/CA2061264C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/0203—Making porous regions on the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques

Abstract

A method for preparing a semiconductor member comprises:
forming a substrate having a non-porous silicon monocrystalline layer and a porous silicon layer;
bonding another substrate having a surface made of an insulating material to the surface of the monocrystalline layer; and etching to remove the porous silicon layer by immersing in an etching solution.
CA002061264A 1991-02-15 1992-02-14 Etching solution for etching porous silicon, etching method using the etching solution and method of preparing semiconductor member using the etching solution Expired - Fee Related CA2061264C (en)

Applications Claiming Priority (98)

Application Number Priority Date Filing Date Title
JP4221391 1991-02-15
JP03-042212 1991-02-15
JP4221291 1991-02-15
JP03-042213 1991-02-15
JP03-055604 1991-02-28
JP5561091 1991-02-28
JP03-055614 1991-02-28
JP03-055612 1991-02-28
JP5560491 1991-02-28
JP5560891 1991-02-28
JP5560591 1991-02-28
JP03-055606 1991-02-28
JP5561291 1991-02-28
JP03-055611 1991-02-28
JP03-055609 1991-02-28
JP5560191 1991-02-28
JP5560791 1991-02-28
JP5560291 1991-02-28
JP5561491 1991-02-28
JP5561391 1991-02-28
JP5560691 1991-02-28
JP03-055610 1991-02-28
JP03-055603 1991-02-28
JP03-055613 1991-02-28
JP5560391 1991-02-28
JP03-055602 1991-02-28
JP03-055605 1991-02-28
JP5560991 1991-02-28
JP5561191 1991-02-28
JP03-055607 1991-02-28
JP03-055608 1991-02-28
JP03-055601 1991-02-28
JP03-085755 1991-03-27
JP8575591 1991-03-27
JP3148164A JPH04346418A (en) 1991-05-24 1991-05-24 Manufacture of semiconductor substrate
JP03-148164 1991-05-24
JP14816391 1991-05-24
JP14816191 1991-05-24
JP14816091 1991-05-24
JP03-148163 1991-05-24
JP03-148161 1991-05-24
JP03-148160 1991-05-24
JP03-149297 1991-05-27
JP14930991 1991-05-27
JP3149297A JPH04349621A (en) 1991-05-27 1991-05-27 Manufacture of semiconductor substrate
JP03-149299 1991-05-27
JP03-149301 1991-05-27
JP14930791 1991-05-27
JP14929891 1991-05-27
JP14931091 1991-05-27
JP14931191 1991-05-27
JP14930191 1991-05-27
JP14930891 1991-05-27
JP14930691 1991-05-27
JP14930291 1991-05-27
JP03-149300 1991-05-27
JP03-149298 1991-05-27
JP14929991 1991-05-27
JP03-149302 1991-05-27
JP14930091 1991-05-27
JP15098391 1991-05-28
JP15098191 1991-05-28
JP15098591 1991-05-28
JP03-150992 1991-05-28
JP03-150981 1991-05-28
JP03-150980 1991-05-28
JP15099091 1991-05-28
JP15098291 1991-05-28
JP03-150989 1991-05-28
JP03-150990 1991-05-28
JP03-150991 1991-05-28
JP15099491 1991-05-28
JP15098091 1991-05-28
JP15099391 1991-05-28
JP15099291 1991-05-28
JP03-150984 1991-05-28
JP15098491 1991-05-28
JP03-150994 1991-05-28
JP15098991 1991-05-28
JP03-150983 1991-05-28
JP15099191 1991-05-28
JP03-150985 1991-05-28
JP03-150982 1991-05-28
JP3-150993 1991-05-29
JP3-149307 1991-05-29
JP3-152250 1991-05-29
JP3-152251 1991-05-29
JP03-152249 1991-05-29
JP3-149308 1991-05-29
JP03-152248 1991-05-29
JP15224891 1991-05-29
JP3-149310 1991-05-29
JP3-149311 1991-05-29
JP3-149309 1991-05-29
JP15225091 1991-05-29
JP15225191 1991-05-29
JP15224991 1991-05-29
JP3-149306 1991-05-29

Publications (2)

Publication Number Publication Date
CA2061264A1 true CA2061264A1 (en) 1992-08-16
CA2061264C CA2061264C (en) 1999-11-16

Family

ID=27586982

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002061264A Expired - Fee Related CA2061264C (en) 1991-02-15 1992-02-14 Etching solution for etching porous silicon, etching method using the etching solution and method of preparing semiconductor member using the etching solution

Country Status (8)

Country Link
US (1) US5767020A (en)
EP (2) EP0499488B9 (en)
KR (1) KR960007640B1 (en)
CN (1) CN1099905A (en)
AT (1) ATE244931T1 (en)
CA (1) CA2061264C (en)
MY (1) MY114349A (en)
SG (2) SG93197A1 (en)

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US20130019918A1 (en) 2011-07-18 2013-01-24 The Regents Of The University Of Michigan Thermoelectric devices, systems and methods
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Also Published As

Publication number Publication date
ATE244931T1 (en) 2003-07-15
EP1347505A3 (en) 2004-10-20
KR960007640B1 (en) 1996-06-07
EP0499488B1 (en) 2003-07-09
EP0499488B9 (en) 2004-01-28
CN1099905A (en) 1995-03-08
EP1347505A2 (en) 2003-09-24
CA2061264C (en) 1999-11-16
SG47089A1 (en) 1998-03-20
SG93197A1 (en) 2002-12-17
EP0499488A2 (en) 1992-08-19
EP0499488A3 (en) 1995-03-01
US5767020A (en) 1998-06-16
MY114349A (en) 2002-10-31

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