CA2064746A1 - Modular input/output system for supercomputers - Google Patents
Modular input/output system for supercomputersInfo
- Publication number
- CA2064746A1 CA2064746A1 CA002064746A CA2064746A CA2064746A1 CA 2064746 A1 CA2064746 A1 CA 2064746A1 CA 002064746 A CA002064746 A CA 002064746A CA 2064746 A CA2064746 A CA 2064746A CA 2064746 A1 CA2064746 A1 CA 2064746A1
- Authority
- CA
- Canada
- Prior art keywords
- data
- channel
- buffer
- high speed
- iop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0656—Data buffering arrangements
Abstract
An input-output subsystem for a supercomputer is disclosed.
Peripheral devices are coupled to the system through channel adaptor interfaces, while communication with the CPU is through a high speed data channels. A circular memory is provided to buffer data transfers between the peripherals and the CPU's.
Peripheral devices are coupled to the system through channel adaptor interfaces, while communication with the CPU is through a high speed data channels. A circular memory is provided to buffer data transfers between the peripherals and the CPU's.
Description
2 ~ 6 ~ 7 4 6 PCl['/US90/04279 .;
MODULAR INPUT/O~TPUT SYSTEM FOR S~JPERCOMPUTERS
Technical Yield of the Invention The present invention relates generally to the field of input/output svstems used with digital computlng systems, and more particularly to a peripheral interface control subsystem used with a supercomputer.
Background of the Invention 10 Mainframe digital supercomputers are composed of functional subsystems. These subsystems may include one or more central processing units (CPUs); central memory, which is directly addressable by the CPUs; a solid state storage device (SSD) which is accessed through high speed data channels; and input-output subsystems.
The input/output subsystems (IOS) have been traditionall~ used to transfer data into and out of the supercomputer system. As such, a number of peripheral devices have been coupled to the supercomputer through the IOS subsystem. Two of the most common peripherals include magne~ic tape transports and magnetic disk storage units.
, . . . .. .
In operation the IOS normalizes transactions between commercially available peripheral devices and the CPU.
This permits the CPU to communicate in a standard fashion with peripheral devices, with the necessary translation being provided by the IOS subsystem. This translation activity is accomplished in two steps.
First, each peripheral device, a disk;drive for example, usually has circuitry which converts standard command signals into data storage or retrieval operations. This circuitry is referred to as a disk controller. Second, a channel adapter has electricah-circuitry-sufficient to translate hig~ lev,el control instructions from the IOS
into the basi~ controller command signals necessary to perform the instruction. This type of IOS has a large buffer memory, one or more input-output processors, and communicates ~_o the other components of the computer system through various channel interfaces.
WO9l/~2312, ' ~ PCT/US90/04279 20~7~ -The inclusion of SSD devices in supercomputing systems as taught by U.S. Patent 4,630,230 to Sundet has placed increased demands on the performance of the IOS
subsystem. The distribution of additional fast memory throughout the system makes the performance of the system strongly dependant on the IOS data paths and performance.
Summary of the Invention ,,, lo In contrast to the architecture of the prior art IOS, the IOS of the present invention includes a circular memory buffer which is coupled to a high speed multiplexor. The multiplexor is coupled to two high speed data channels (HISPs).
In one illustrative configuration, the IOS is connected to ~oth the CPU and the SSD. The connection to the CPU is through one HISP data channel and the connection to the SSD is through the other HISP data channel. In this configuration, the IOS can transfer data to and f;rom the SSD independently of data transfers between the IOS and the CPU.
The illustrative example demonstrates that the IOS
can be considered conceptually as a data coupler which can match the bandwidth of the logical devices which it interconnects.
This architecture improves the overall performance of the computing system and is readily scaled"to various hardware configurations.
,~ The preferred partitioning of the IOS subsystem divides the s~stem into modules. Each moduIe has one IOP processor to supervise four-peripherals.'' Each ~ peripheral-:is coupIed to one of four channél adapters.
- -~Each channel:adaptor'-is connected to its own''circular ,~ memory buffer. rA'single"mult~plexor structure ~S
3S provided to couple~'any''of'the buffers with either'of the high speed'data channels. - - `;
-The multiplexor'function and the circular memory WO91/02312 2 0 5 ~ 7 ~ ~ PCT/US90/04279 .;
MODULAR INPUT/O~TPUT SYSTEM FOR S~JPERCOMPUTERS
Technical Yield of the Invention The present invention relates generally to the field of input/output svstems used with digital computlng systems, and more particularly to a peripheral interface control subsystem used with a supercomputer.
Background of the Invention 10 Mainframe digital supercomputers are composed of functional subsystems. These subsystems may include one or more central processing units (CPUs); central memory, which is directly addressable by the CPUs; a solid state storage device (SSD) which is accessed through high speed data channels; and input-output subsystems.
The input/output subsystems (IOS) have been traditionall~ used to transfer data into and out of the supercomputer system. As such, a number of peripheral devices have been coupled to the supercomputer through the IOS subsystem. Two of the most common peripherals include magne~ic tape transports and magnetic disk storage units.
, . . . .. .
In operation the IOS normalizes transactions between commercially available peripheral devices and the CPU.
This permits the CPU to communicate in a standard fashion with peripheral devices, with the necessary translation being provided by the IOS subsystem. This translation activity is accomplished in two steps.
First, each peripheral device, a disk;drive for example, usually has circuitry which converts standard command signals into data storage or retrieval operations. This circuitry is referred to as a disk controller. Second, a channel adapter has electricah-circuitry-sufficient to translate hig~ lev,el control instructions from the IOS
into the basi~ controller command signals necessary to perform the instruction. This type of IOS has a large buffer memory, one or more input-output processors, and communicates ~_o the other components of the computer system through various channel interfaces.
WO9l/~2312, ' ~ PCT/US90/04279 20~7~ -The inclusion of SSD devices in supercomputing systems as taught by U.S. Patent 4,630,230 to Sundet has placed increased demands on the performance of the IOS
subsystem. The distribution of additional fast memory throughout the system makes the performance of the system strongly dependant on the IOS data paths and performance.
Summary of the Invention ,,, lo In contrast to the architecture of the prior art IOS, the IOS of the present invention includes a circular memory buffer which is coupled to a high speed multiplexor. The multiplexor is coupled to two high speed data channels (HISPs).
In one illustrative configuration, the IOS is connected to ~oth the CPU and the SSD. The connection to the CPU is through one HISP data channel and the connection to the SSD is through the other HISP data channel. In this configuration, the IOS can transfer data to and f;rom the SSD independently of data transfers between the IOS and the CPU.
The illustrative example demonstrates that the IOS
can be considered conceptually as a data coupler which can match the bandwidth of the logical devices which it interconnects.
This architecture improves the overall performance of the computing system and is readily scaled"to various hardware configurations.
,~ The preferred partitioning of the IOS subsystem divides the s~stem into modules. Each moduIe has one IOP processor to supervise four-peripherals.'' Each ~ peripheral-:is coupIed to one of four channél adapters.
- -~Each channel:adaptor'-is connected to its own''circular ,~ memory buffer. rA'single"mult~plexor structure ~S
3S provided to couple~'any''of'the buffers with either'of the high speed'data channels. - - `;
-The multiplexor'function and the circular memory WO91/02312 2 0 5 ~ 7 ~ ~ PCT/US90/04279 .;
buffer function are controlled by the input/output processor (IOP). This processor operates under the control of software which resides in a local memory contained in the module. Two important tasks for the IOP
are; monitoring the buffer operation and;.defining the , data path by controlling the routing function of the multiplexor.
.
. B~ief Description of the Drawings Figure l shows a high level functional blocX diagram o~ an illustr~tive super computer data processing , system..
Figure 2 ,hows a functional block diagram of the ., IOS.
. Figure 3 shows a functional block relationship diagram of the elements of the IOS interacting with a CPU .
Figure 4 shows a functional block diagram of relationships between a CPU and'elements of the IOS.
Figure 5 shows a detailed diagram of the circular IO
buffer functions.
Figure 6 shows a detailed diagram of the functional elements of a circular IO buffer and its relationship to other elements of the system.
~etailed Descriptio~ of the_Preferred Embodiment In.the following detailed description of the preferred embodiment, reference is made to the ,, accompanying draw,ings which form-a part hereof, and in which is shown by way of illustration.a specific embodiment.in which the,invention may.be-practice. This embodiment is described,in sufficient detail to enable those skilled;in ~the.art to practice the invention, and , it~is to be.understood that.other embodiments may be utilized.and that structural changes may be made withoùt . departing,fro.n the scope of the present invention. ~he following detniled description-is, therefore, not to be WO91/02312 ~ PCT/US90/04279 2~47~
~, taken in a limiting sense, and the scope of' the present invention is defined by the appended claims.
..
GENERAL DESCRIPTION
Referring to Figure 1, there is shown a simplified supercomputing system comprising a CPU subsystem 2. The CPU is connected to the IOS 3 through a high speed bi-directional communication link or HISP 20. The system also includes an SSD 4 of the type disclosed in U.S.
Patent 4,630,230 to Sundet which is incorporated by reference herein. The SSD 4 is connected to the IOS 3 through another HISP 21. The CPU 2 and the SSD 4 also have an interconnection through VHISP 22. Command inf'ormation is delivered to the IOS through low speed data channels which are shown in the~figure as LOSP 23 and LOSP 24. The IOS itself is-connected to a variety of peripheral devices 9. These devices may be magnetic storage units or other peripheral devices.
In operation the IOS accepts n'read" or "'write"
commands issued by the CPU over the low speed data communication paths 23. The IOS will then retrieve or store identified data from the appropriate peripheral.
The identified data is transmitted to or'from'the requesting device at high speed over the'appropriate HISP.
In general the HISP will exhibit a data bandwidth of 100-200 million bytes.per second. The LOSP data bandwidth is approximately 6 million bytes per~second.
Peripherals will exhibit a wide'rangè o'f data-bandwiths ,from approximately 1 to 100 million bytes per second.
This,,disparity in dàta bandwith requirës that a buffer ! j ~function be provided:in the IOS.~
,Referring to Figure;2'there t is;shown a'~ '' - representativa single level IOP' cluster. Each module 3 is expected to service one CPU in a'multiprocèssor configuration. Connection to the CPU for data transfer is through the HISP'20.'Connection to thè CPU for W091/02312 2 ~ 6 ~ 7 ~ ~ PCT/US90/04279 "
command and s,atus information is through the LOSP 24.
The peripheral 9 is cabled to the IOS and connected to a channel adapter 13 (CA~. Up to four channel adaptor are available on ,~ach IOS module.
A function of the channel adaptor is to perform format con~ersion on the data between the peripheral format and the circular memory buffer format. Typically data stored on the peripheral will be assembled into 64 bit data-words in latches located in the channel - lo adaptor. Once the data word is assembled in the latch, an error recovery byte is added to it forming a 72 bit data word. It is preferred to manipulate data in the IOS
with an error recovery byte integrated'with the data even though this consumes available data bandwidth.
Each channel adaptor is linked-to a circular memory buffer 6. This structure is preferably 65K words long.
This memory is connected to the data multiplexor 10.
This allows the memory to be shared by the channel adaptor, the IOP processor and either of the ~ISP
channels. Competition for access to the memory buffer is avoided by allowing the channel adapter and the HISP to access the memory on different memory clock cycles.
Access to the memory address space is allocated through the assignment of pointers.'~he IOP 14 monitors the memory for overflow and underflow conditions and assigns pointers to avoid data underflow and data overflow.
. ~ , . , , , . . ~ - .
CPU Read from Peripheral Referring now to Figure 3, there is shown a functional block relationship diagram of the`elements of the IOS interacting with a CPU. A CPU read from peripheral is initiated by the CPU~ by asserting-a read message 103 to the'IOS.~ Th'e'read message is~directed by the IOP multiplexor:10 to'the appropriate IOP'5 as a read message 104. The IOP S then sets up 105 access pointers and circuitry 101 within the circular buffers WO91/02312 ~ , PCT/US90/04279 2Q6 ~7 4~ 6 100. Next, the IOP 5 functions 106 the channel adaptor 8 to perform a read on a particular address on the disk 9. Depending on the particular application which is running, the disk data may be requested as sectors, multiple sectors or multiple tracks. Throughout the description an illustrative and non-limiting example of a track request is described.
The channel adaptor 8 performs the read on the peripheral 9 ~y asserting the necessary command signals through the peripheral interface 107. The data from the read is loade~ in multiple tracks 108 into the storage portion I02 of the circular buffer lOO based on pointers lOl within the circular buffer. After the data has been transferred by the channel adaptor 8, it signals lO9 the IOP 5 that the read operation has completed.
The IOP 5 interprets the done message from the channel adaptor 8 and responds by signaling llO through the IOP MUX to the HISP MUX 53. This signal includes an address within main memory to write the data stored in the circular ~uffer and a channel on which to transmit `
the data in the circular~buffer lOO. The HISP MUX 53, through its channel control circuitry 99, initiates and controls a transfer 111 of data within the storage area of the circular buffer 102 through the high speed data channel ll to its destination address. When the channel control circuitry,99,has completed the transfer, it responds with a done mes~age 112 to the IOP MUX 10.
The IOP MUX transfers the done message to the IOP 5 which responds with an appropriate completion message 113 through the IOP MUX 10 to the CPU 1 with the approprlate low speed (LOSP) completion message 114.
CPU Write to a P~ripheral- ,,- , , ,Referr,ing;~now to~Fig,ure 4, there;is shown a ;~
functional block diagram of relationships between a CPU
and elements of the IOS. -A CPU 1 initiates a write to a peripheral by asserting a write messa~e to an IOP
.
WO91/02312 2 ~ 6 4 7 ~ ~ PCT/US90/04279 address 200 through the IOP MUX 10. The IOP MUX 10 transfers the message 201 to the appropriate IOP 5. The IOP 5 sets up 202 buffer pointers 101 and control circuitry wit~in the circular buffer 100 for the write operation.
The IOP then signals the HISP MUX 53 by asserting a message containing an address and a channel 204 through the IOP MUX 10. The message is routed to the channel control circuitry 99 within ~ISP MUX 53. Ths channel control circuitry 99 then initiates and controls 205 a data transfer through the HISP channel 11 from the CPU
into the circular buffer from the CPU 1 through the HISP
channel 11 to the circular buffer 100. It accesses control circuitry and pointers 101 to address storage 102 within the circular buffer.
When the ~hannel control circuitry 99 completes the transfer, it responds with a done message 206 to the IOP
MUX through t~e IOP MUX 10 to the IOP 5.
The IOP 5i upon receiving a transfer completion message 206 from the HISP MUX 53 functions a write signal 207 to the channel adaptor 8. The channel adaptor 8 then transfers tracks of data previously set up 203 in the circular buffer storage area 102. It transfers them 211 to its attached peripheral 9. When the channel adaptor 8 completes the transfer, it responds with a done message 208 to the attached IOP 5.
The IOP transfers the done message 209 through the IOP
MUX 10 onto t!le LOSP channel'210 as a write completion message 210.
~O Bufer ~ ~ Referring now~to Figure 5, there is shown-a detailed diagram of the circular IO buffer~functions. 'Each ~ buffer 100 is comprised of random-:access'~memory 'devices arranged in an orthogonally addressed'array of 65,536 72-bit words.~ Four registers 501, 502, 503, and 504-hold addresses within the buffer address space. The IOP
WO91J023~2 . ` PCT/US90/04279 7 ~ ~ 8 sets the values in these registers as discussed above.
The buffer address is used to form a circular data structure.
The lower portion 510 of Figure 5 shows the relationship of buffer access through the address pointers. As time progresses, alternate cycles of HISP
511 and CA 512 access are-performed. Reads and writes are performed on the buffer by accessing the orthogonal array,through addresses contained either in the ~A" or "B" registers on the one hand or the "a" or "b"
registers on ~he other.
Referring now to Figure 5, there is shown a detailed diagram of th2 functional elements of a circular IO
buffer in this relationship to other elements of the system. The HISP MUX controller 99 controls the function of the pointers during data transfer on the HISP channel. The circular buffer address space 102 is pointed to by a dual level addressing MUX within the pointers 101 area the circular IO buffer 100. Addresses are stored in the control registers ~a~ 503, nbN 504, nA" 501, "B" 502 during transfer set-up performed by the IOP discussed above. Based on HISP control signals from the HISP MUX oontroller 99, the pointers 101 control circuitry closks an address onto the address bus 600.
The data bus is latched into a data latch 602 which is clocked onto the HISP channel 11, or in the channel . adaptor 8., All clocking is governed by a single clock source 45 within the IOS..;
As shown in Figures 5 and 6 the address which is clocked onto the address bus 600 is determined through a buffer cycle selector 604. The buffer cycle~-selèctor loads.Lthe~nA~ 501..or.nBn:.502 register contents onto the address~bus_if~,the.HISP lI is accessing the buffer. If ;.;the.pointer,.,,circuitry.~is.infa CA cyclej~ the address is 35 .-taken.from~seLect circuitry.:605:which~determines an address-out o~ the,,na~ 503, or nb" 504~:registers.
Depending on which buffer cycle is active the buffer may WO91/02312 2 0 ~ ~ 7 4 ~ PCT/US90/04279 be coupled to either the HISP or the channel adaptor.
This architecture permits reads, from a disk, for example, wherein the "a" register is loaded with a beginning address for track 0, and the "b" register is loaded with an address for data from track 1. The IOP
functions the channel adaptor to read tracks O and 1 from the disk into the buffer at the respective addresses. The IOP can then set nA" and nB" equal to ~an and "b". It then functions the HISP MUX controller 99 to transfer data onto the HISP channel from locations "A" and "B" while initiating a simultaneous read or write from the disk through the channel adaptor. It is this circular IO buffering architecture which permits multiple simultaneous reads and writes to and from the IOS.
While the present invention has been described in connection with the preferred embodiment thereof, it should be understood that many modifications will be readily apparsnt to those of ordinary skill in the art, and this application is intended to cover any adaptations or variations thereof. Therefore, it is manifestly intended that the invention is limited only by the claims and equivalents thereof.
.. . ~ . .., -: .
.. . . . . .
.. . . . . .
are; monitoring the buffer operation and;.defining the , data path by controlling the routing function of the multiplexor.
.
. B~ief Description of the Drawings Figure l shows a high level functional blocX diagram o~ an illustr~tive super computer data processing , system..
Figure 2 ,hows a functional block diagram of the ., IOS.
. Figure 3 shows a functional block relationship diagram of the elements of the IOS interacting with a CPU .
Figure 4 shows a functional block diagram of relationships between a CPU and'elements of the IOS.
Figure 5 shows a detailed diagram of the circular IO
buffer functions.
Figure 6 shows a detailed diagram of the functional elements of a circular IO buffer and its relationship to other elements of the system.
~etailed Descriptio~ of the_Preferred Embodiment In.the following detailed description of the preferred embodiment, reference is made to the ,, accompanying draw,ings which form-a part hereof, and in which is shown by way of illustration.a specific embodiment.in which the,invention may.be-practice. This embodiment is described,in sufficient detail to enable those skilled;in ~the.art to practice the invention, and , it~is to be.understood that.other embodiments may be utilized.and that structural changes may be made withoùt . departing,fro.n the scope of the present invention. ~he following detniled description-is, therefore, not to be WO91/02312 ~ PCT/US90/04279 2~47~
~, taken in a limiting sense, and the scope of' the present invention is defined by the appended claims.
..
GENERAL DESCRIPTION
Referring to Figure 1, there is shown a simplified supercomputing system comprising a CPU subsystem 2. The CPU is connected to the IOS 3 through a high speed bi-directional communication link or HISP 20. The system also includes an SSD 4 of the type disclosed in U.S.
Patent 4,630,230 to Sundet which is incorporated by reference herein. The SSD 4 is connected to the IOS 3 through another HISP 21. The CPU 2 and the SSD 4 also have an interconnection through VHISP 22. Command inf'ormation is delivered to the IOS through low speed data channels which are shown in the~figure as LOSP 23 and LOSP 24. The IOS itself is-connected to a variety of peripheral devices 9. These devices may be magnetic storage units or other peripheral devices.
In operation the IOS accepts n'read" or "'write"
commands issued by the CPU over the low speed data communication paths 23. The IOS will then retrieve or store identified data from the appropriate peripheral.
The identified data is transmitted to or'from'the requesting device at high speed over the'appropriate HISP.
In general the HISP will exhibit a data bandwidth of 100-200 million bytes.per second. The LOSP data bandwidth is approximately 6 million bytes per~second.
Peripherals will exhibit a wide'rangè o'f data-bandwiths ,from approximately 1 to 100 million bytes per second.
This,,disparity in dàta bandwith requirës that a buffer ! j ~function be provided:in the IOS.~
,Referring to Figure;2'there t is;shown a'~ '' - representativa single level IOP' cluster. Each module 3 is expected to service one CPU in a'multiprocèssor configuration. Connection to the CPU for data transfer is through the HISP'20.'Connection to thè CPU for W091/02312 2 ~ 6 ~ 7 ~ ~ PCT/US90/04279 "
command and s,atus information is through the LOSP 24.
The peripheral 9 is cabled to the IOS and connected to a channel adapter 13 (CA~. Up to four channel adaptor are available on ,~ach IOS module.
A function of the channel adaptor is to perform format con~ersion on the data between the peripheral format and the circular memory buffer format. Typically data stored on the peripheral will be assembled into 64 bit data-words in latches located in the channel - lo adaptor. Once the data word is assembled in the latch, an error recovery byte is added to it forming a 72 bit data word. It is preferred to manipulate data in the IOS
with an error recovery byte integrated'with the data even though this consumes available data bandwidth.
Each channel adaptor is linked-to a circular memory buffer 6. This structure is preferably 65K words long.
This memory is connected to the data multiplexor 10.
This allows the memory to be shared by the channel adaptor, the IOP processor and either of the ~ISP
channels. Competition for access to the memory buffer is avoided by allowing the channel adapter and the HISP to access the memory on different memory clock cycles.
Access to the memory address space is allocated through the assignment of pointers.'~he IOP 14 monitors the memory for overflow and underflow conditions and assigns pointers to avoid data underflow and data overflow.
. ~ , . , , , . . ~ - .
CPU Read from Peripheral Referring now to Figure 3, there is shown a functional block relationship diagram of the`elements of the IOS interacting with a CPU. A CPU read from peripheral is initiated by the CPU~ by asserting-a read message 103 to the'IOS.~ Th'e'read message is~directed by the IOP multiplexor:10 to'the appropriate IOP'5 as a read message 104. The IOP S then sets up 105 access pointers and circuitry 101 within the circular buffers WO91/02312 ~ , PCT/US90/04279 2Q6 ~7 4~ 6 100. Next, the IOP 5 functions 106 the channel adaptor 8 to perform a read on a particular address on the disk 9. Depending on the particular application which is running, the disk data may be requested as sectors, multiple sectors or multiple tracks. Throughout the description an illustrative and non-limiting example of a track request is described.
The channel adaptor 8 performs the read on the peripheral 9 ~y asserting the necessary command signals through the peripheral interface 107. The data from the read is loade~ in multiple tracks 108 into the storage portion I02 of the circular buffer lOO based on pointers lOl within the circular buffer. After the data has been transferred by the channel adaptor 8, it signals lO9 the IOP 5 that the read operation has completed.
The IOP 5 interprets the done message from the channel adaptor 8 and responds by signaling llO through the IOP MUX to the HISP MUX 53. This signal includes an address within main memory to write the data stored in the circular ~uffer and a channel on which to transmit `
the data in the circular~buffer lOO. The HISP MUX 53, through its channel control circuitry 99, initiates and controls a transfer 111 of data within the storage area of the circular buffer 102 through the high speed data channel ll to its destination address. When the channel control circuitry,99,has completed the transfer, it responds with a done mes~age 112 to the IOP MUX 10.
The IOP MUX transfers the done message to the IOP 5 which responds with an appropriate completion message 113 through the IOP MUX 10 to the CPU 1 with the approprlate low speed (LOSP) completion message 114.
CPU Write to a P~ripheral- ,,- , , ,Referr,ing;~now to~Fig,ure 4, there;is shown a ;~
functional block diagram of relationships between a CPU
and elements of the IOS. -A CPU 1 initiates a write to a peripheral by asserting a write messa~e to an IOP
.
WO91/02312 2 ~ 6 4 7 ~ ~ PCT/US90/04279 address 200 through the IOP MUX 10. The IOP MUX 10 transfers the message 201 to the appropriate IOP 5. The IOP 5 sets up 202 buffer pointers 101 and control circuitry wit~in the circular buffer 100 for the write operation.
The IOP then signals the HISP MUX 53 by asserting a message containing an address and a channel 204 through the IOP MUX 10. The message is routed to the channel control circuitry 99 within ~ISP MUX 53. Ths channel control circuitry 99 then initiates and controls 205 a data transfer through the HISP channel 11 from the CPU
into the circular buffer from the CPU 1 through the HISP
channel 11 to the circular buffer 100. It accesses control circuitry and pointers 101 to address storage 102 within the circular buffer.
When the ~hannel control circuitry 99 completes the transfer, it responds with a done message 206 to the IOP
MUX through t~e IOP MUX 10 to the IOP 5.
The IOP 5i upon receiving a transfer completion message 206 from the HISP MUX 53 functions a write signal 207 to the channel adaptor 8. The channel adaptor 8 then transfers tracks of data previously set up 203 in the circular buffer storage area 102. It transfers them 211 to its attached peripheral 9. When the channel adaptor 8 completes the transfer, it responds with a done message 208 to the attached IOP 5.
The IOP transfers the done message 209 through the IOP
MUX 10 onto t!le LOSP channel'210 as a write completion message 210.
~O Bufer ~ ~ Referring now~to Figure 5, there is shown-a detailed diagram of the circular IO buffer~functions. 'Each ~ buffer 100 is comprised of random-:access'~memory 'devices arranged in an orthogonally addressed'array of 65,536 72-bit words.~ Four registers 501, 502, 503, and 504-hold addresses within the buffer address space. The IOP
WO91J023~2 . ` PCT/US90/04279 7 ~ ~ 8 sets the values in these registers as discussed above.
The buffer address is used to form a circular data structure.
The lower portion 510 of Figure 5 shows the relationship of buffer access through the address pointers. As time progresses, alternate cycles of HISP
511 and CA 512 access are-performed. Reads and writes are performed on the buffer by accessing the orthogonal array,through addresses contained either in the ~A" or "B" registers on the one hand or the "a" or "b"
registers on ~he other.
Referring now to Figure 5, there is shown a detailed diagram of th2 functional elements of a circular IO
buffer in this relationship to other elements of the system. The HISP MUX controller 99 controls the function of the pointers during data transfer on the HISP channel. The circular buffer address space 102 is pointed to by a dual level addressing MUX within the pointers 101 area the circular IO buffer 100. Addresses are stored in the control registers ~a~ 503, nbN 504, nA" 501, "B" 502 during transfer set-up performed by the IOP discussed above. Based on HISP control signals from the HISP MUX oontroller 99, the pointers 101 control circuitry closks an address onto the address bus 600.
The data bus is latched into a data latch 602 which is clocked onto the HISP channel 11, or in the channel . adaptor 8., All clocking is governed by a single clock source 45 within the IOS..;
As shown in Figures 5 and 6 the address which is clocked onto the address bus 600 is determined through a buffer cycle selector 604. The buffer cycle~-selèctor loads.Lthe~nA~ 501..or.nBn:.502 register contents onto the address~bus_if~,the.HISP lI is accessing the buffer. If ;.;the.pointer,.,,circuitry.~is.infa CA cyclej~ the address is 35 .-taken.from~seLect circuitry.:605:which~determines an address-out o~ the,,na~ 503, or nb" 504~:registers.
Depending on which buffer cycle is active the buffer may WO91/02312 2 0 ~ ~ 7 4 ~ PCT/US90/04279 be coupled to either the HISP or the channel adaptor.
This architecture permits reads, from a disk, for example, wherein the "a" register is loaded with a beginning address for track 0, and the "b" register is loaded with an address for data from track 1. The IOP
functions the channel adaptor to read tracks O and 1 from the disk into the buffer at the respective addresses. The IOP can then set nA" and nB" equal to ~an and "b". It then functions the HISP MUX controller 99 to transfer data onto the HISP channel from locations "A" and "B" while initiating a simultaneous read or write from the disk through the channel adaptor. It is this circular IO buffering architecture which permits multiple simultaneous reads and writes to and from the IOS.
While the present invention has been described in connection with the preferred embodiment thereof, it should be understood that many modifications will be readily apparsnt to those of ordinary skill in the art, and this application is intended to cover any adaptations or variations thereof. Therefore, it is manifestly intended that the invention is limited only by the claims and equivalents thereof.
.. . ~ . .., -: .
.. . . . . .
.. . . . . .
Claims (5)
1. An input/output subsystem for use with a supercomputer comprising:
a) channel adaptor means for interfacing with at least one peripheral;
b) high speed data channel means for coupling with said supercomputer;
c) circular memory buffer means coupled to said channel adaptor means for storing data;
d) multiplexor means coupled to said buffer means for transferring data to said high speed data channel means;
e) timing means for permitting said channel adaptor means access and high speed data channel means access to said buffer means on alternate memory access cycles.
a) channel adaptor means for interfacing with at least one peripheral;
b) high speed data channel means for coupling with said supercomputer;
c) circular memory buffer means coupled to said channel adaptor means for storing data;
d) multiplexor means coupled to said buffer means for transferring data to said high speed data channel means;
e) timing means for permitting said channel adaptor means access and high speed data channel means access to said buffer means on alternate memory access cycles.
2. The input/output subsystem according to claim 1 wherein said circular buffer means further includes first pointer means for indicating the location of data received from said channel adapter means and second pointer means for indicating the location of data to be transferred to said high speed data channel means.
3. The input/output subsystem according to claim 4 wherein said circular buffer means further includes means for preventing said first and second pointer means from overwriting data in said circular buffer.
4. The input/output subsystem according to claim 1 wherein said multiplexor means is further coupled to said buffer means for transferring data from said high speed data channel means.
5. The input/output subsystem according to claim 1 further including:
control means coupled to said multiplexor means for directing data from a plurality of said circular buffer means onto said high speed channel means; and low speed channel means coupled between said supercomputer and said control means for receiving control information from said supercomputer.
control means coupled to said multiplexor means for directing data from a plurality of said circular buffer means onto said high speed channel means; and low speed channel means coupled between said supercomputer and said control means for receiving control information from said supercomputer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US390,722 | 1989-08-08 | ||
| US07/390,722 US5347637A (en) | 1989-08-08 | 1989-08-08 | Modular input/output system for supercomputers |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2064746A1 true CA2064746A1 (en) | 1991-02-09 |
Family
ID=23543656
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002064746A Abandoned CA2064746A1 (en) | 1989-08-08 | 1990-07-31 | Modular input/output system for supercomputers |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5347637A (en) |
| EP (1) | EP0485507B1 (en) |
| AT (1) | ATE124553T1 (en) |
| CA (1) | CA2064746A1 (en) |
| DE (1) | DE69020569T2 (en) |
| WO (1) | WO1991002312A1 (en) |
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-
1990
- 1990-07-31 DE DE69020569T patent/DE69020569T2/en not_active Expired - Fee Related
- 1990-07-31 WO PCT/US1990/004279 patent/WO1991002312A1/en active IP Right Grant
- 1990-07-31 CA CA002064746A patent/CA2064746A1/en not_active Abandoned
- 1990-07-31 EP EP90912832A patent/EP0485507B1/en not_active Expired - Lifetime
- 1990-07-31 AT AT90912832T patent/ATE124553T1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| DE69020569D1 (en) | 1995-08-03 |
| ATE124553T1 (en) | 1995-07-15 |
| DE69020569T2 (en) | 1995-11-30 |
| WO1991002312A1 (en) | 1991-02-21 |
| EP0485507B1 (en) | 1995-06-28 |
| US5347637A (en) | 1994-09-13 |
| EP0485507A1 (en) | 1992-05-20 |
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