CA2064987C - A synchronous control method in a plurality of channel units - Google Patents
A synchronous control method in a plurality of channel unitsInfo
- Publication number
- CA2064987C CA2064987C CA002064987A CA2064987A CA2064987C CA 2064987 C CA2064987 C CA 2064987C CA 002064987 A CA002064987 A CA 002064987A CA 2064987 A CA2064987 A CA 2064987A CA 2064987 C CA2064987 C CA 2064987C
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- Canada
- Prior art keywords
- synchronous control
- channel unit
- signal
- self
- channel
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
- H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
- H04J3/0629—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators in a network, e.g. in combination with switching or multiplexing, slip buffers
Abstract
A synchronous control method in a plurality of channel units for synchronously transmitting each transmission signal in response to a synchronous control signal by a plurality of channel units comprising the process steps of providing synchronous control circuits for outputting a synchronous control signal to each channel unit; and supplying the synchronous control signal from the synchronous control circuit corresponding to a high order channel unit to the self-channel unit and the synchronous control circuit corresponding to a low order channel unit in response to the synchronous signal in the transmission signal.
Description
2~649~7 SYNCHRONOUS CONTROL METHOD IN PLURALITY OF
CHANNEL UNITS AND CIRCUIT USING SAID METHOD
BACKGROUND OF THE INVENTION
1. Field of the Invention The present invention relates to a synchronous control method in a plurality of channel units and a circuit using said method for synchronously controlling a transmission operation of the plurality of channel units.
In a synchronous transmission system, each frame of the transmission signal of a plurality of channels is synchronized thereamong. To execute the frame synchronization, transmission operation in each channel unit by which a transmission signal is transmitted, is controlled synchronizedly. In the synchronous control of the channel units, a necessary synchronous control method is executed corresponding to combinations of the channel units.
2. Description of the Related Art The synchronous transmission system, for example, receives 150 Mb/s inputs having three 50 Mb/s signals by three channel units in a transmission process circuit, multiplexes the same to 150 Mb/s to transmit by a multiplex circuit, separates the multiplex signal to three 50 Mb/s signals by a separation circuit of a reception process circuit, and the separated signals are output from three channel units.
In this synchronous transmission, since frame positioning of the transmission signals are carried out in the three channel units of the transmission process circuit and the three channel unit of the reception process circuit, synchronous control circuits are provided in the transmission process circuit and the reception process circuit, and the synchronous control circuit supplies the synchronous control signal to the channel units of the transmission process circuit and the ~ ~4~87 .
channel units of the reception process circuit to synchronously control.
When the plurality of channel units are transmitted and synchronized, since applied channel numbers and combinations of the channel units are already determined, the necessary synchronous control circuit is used in response to the combination.
While, for effective utilization of lines, particularly at a high speed condition of transmission, there is a request for arbitrary synchronized channel numbers by various combinations of the channel units.
In this constitution, hitherto, since the synchronous control circuit is used corresponding to a combination of the channel units, the synchronous control circuits that are the same number as the channel units combination, must be provided, and moreover, there is a problem in that all the combinations are not always carried out.
Also there is another problem in that when 150 Mb/s circuit is added to another 150 Mb/s circuit to expand the system, the synchronous control cannot be carried out among the system, the expansion of the system is difficult, and the circuitry must be changed in response to the application aspects.
SUMMARY OF THE INVENTION
In accordance with an embodiment of the present invention there is provided in a synchronous control method, in a plurality of channel units including a high order channel unit and a low order channel unit, for synchronously transmitting transmission signals in response to a synchronous control signal by the plurality of channel units, the improvement characterized in the following process steps: providing a plurality of synchronous control circuits in cooperation with the plurality of channel units, each of the synchronous control circuits outputting a synchronous control signal; and supplying the synchronous control signal from the synchronous control ~ ~4~
circuit of the high order channel unit to a self-channel unit and the synchronous control circuit of the low order channel unit in response to a synchronous signal in a transmission signal.
In accordance with another embodiment of the present invention there is provided a synchronous control circuit in a plurality of channel units using a synchronous control method for synchronously transmitting each transmission signal in response to a synchronous control signal by the plurality of channel units, comprising: a logical operation circuit wherein a synchronous control signal for a self-channel unit and a synchronous control signal for a low order channel unit are output; the synchronous control signals are determined by a conjunction of a synchronous control signal corresponding to a high order channel unit and a synchronous control flag in a transmission signal from the self-channel unit; or by a conjunction of a synchronous control signal from the self-channel unit and an inverted signal of the synchronous control flag from the self-channel unit.
Other features and advantages of the invention will be apparent from the following description with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a block diagram for explaining a related art;
Fig. 2 is a block diagram for explaining another related art;
Fig. 3 is a block diagram for explaining problems in a related art;
Fig. 4 is a block diagram for explaining a summary of an embodiment according to the present invention;
Fig. 5 is a block diagram for illustrating a 1' 206~7 transmission process circuit of a system executing a synchronous control method in a plurality of channel units according to the embodiment of the invention;
Fig. 6 is an example of a circuit diagram of a synchronous control circuit in Fig. 5; and Fig. 7 is an explanatory diagram for illustrating an operation of a synchronous control in the synchronous control circuit in Fig. 6.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Prior to the explanation of an embodiment, a related art of this invention is explained with reference to drawings.
Figure 1 and Fig. 2 are block diagrams for illustrating the related art. In Fig. 1, a synchronous transmission is explained and in Fig. 2, a synchronous control is explained.
As shown in Fig. 1, a synchronous transmission system receives, for example, three inputs of 50 Mb/s (Megabit/second) at channel units 10 to 12 of a transmission process circuit, the three inputs multiplexed by a multiplex circuit (MUX) 22 to 150 Mb/s, are transmitted to a reception process circuit, separated by a separation circuit (DMUX) 24 to three outputs of 50 Mb/s, and output from channel units 16 to 18.
In the above synchronous transmission, since the respective channel units 10 to 12 and 16 to 18 carry out frame synchronization of the transmission signals, as shown in Fig. 2, a synchronous control circuit 3 is provided in the transmission process circuit and the reception process circuit, respectively, the synchronous control circuit 3 supplies the synchronous control signal to the respective channel unit 10 to 12 and 16 to 18, and the system is controlled synchronizedly.
When the plurality of channels are transmitted synchronizedly, since the applied number of the channel, a combination of the channels, or the like have already been determined, the synchronous control circuit 206~87 corresponding to the combination is used.
In Fig. 3, problems in the related art are explained. To utilize lines effectively at high speed transmission by various combinations of the channels, arbitrary acquisition of the synchronized number of channels is requested.
In this case, hitherto, since the synchronous control circuit corresponding to the combination of the channels is used, there is a problem wherein the synchronous control circuits being the same number as the number of the channel combinations must be provided.
Moreover, the provided synchronous control circuits cannot respond to all the combinations.
Further as shown in Fig. 3, in the case when the system is expanded by providing another 150 Mb/s system to a 150 Mb/s system, the synchronous control is not carried out, the expansion of the system is difficult, and the circuit constitution must change in response to the application aspect.
Next, the summary of an embodiment is explained. In the embodiment of this invention, a synchronous control circuit 3 outputting a synchronous control signal is provided in each channel units 10 to 12, since the synchronous control signal from the synchronous control circuit 3 of a high order channel unit is output to a self-channel unit and to the synchronous control circuit 3 of a low order channel unit, in response to the synchronous signal in the transmission signal; the low order channel unit is synchronized with the high order channel unit, an arbitrary channel synchronization is possible by single circuitry and only the necessary channel can be synchronized.
In a working aspect of this invention, the synchronous control signal is an address signal of a memory of the channel units 10 to 12, and a frame synchronization of the transmission signal is realized by the memory control.
- 6 - ~0~987 In another working aspect of this invention, when the synchronous control circuit 3 is in a synchronous control state, an alarm signal from the high order or low order is output to the self-channel unit and transmits the same to the low order or high order channel unit, and the alarm can be despatched to all the channels at a synchronous state to process. When not in a synchronous state, an unnecessary alarm is not imparted to the other channel units.
Next, an embodiment of this invention is explained with reference to Fig. 5 wherein an example in a transmission process circuit is shown. Fig. 6 and Fig. 7 are explanatory diagrams of the synchronous control circuit according to the embodiment of the invention.
The identical reference numerals shown in Figs. 1 and 4 designate the same articles.
In Fig. 5, six 50 MbJs lines are connected to six channel units 10 to 15 and multiplexers (MUX) 22 and 23 multiplex the six channel to two 150 Mb/s channel. To synchronously control the above six channels 10 to 15, the synchronous control circuits 3 are provided in the respective channel units 10 to 15.
The synchronous control circuit 3, as shown in Fig. 6, comprises an AND gate 30 for supplying a conjunction ~etween a synchronous control flag by a synchronous signal detected from the transmission signal by the channel unit and an ES (elastic memory) control signal (memory address) from the synchronous control circuit 3 of a high order channel unit; an inverter 31 inverting the synchronous control flag; an AND gate 32 for supplying a conjunction between an ES control signal (memory address) of the self-channel unit and the inverted synchronous control flag; and an OR gate 33 for supplying a logical add between outputs of AND gates 30 and 32 and outputting the ES control signal (memory address) to the self-channel unit and to the low order channel unit.
206~9~7 Further, the synchronous control circuit 3 comprises an OR gate 34 for supplying a logical add between an alarm of the self-channel unit and an alarm of the low order channel unit; an AND gate 35 for supplying a conjunction between the synchronous control flag and the alarm output of the OR gate 34; an AND gate 36 for supplying a con~unction between the synchronous control flag and the alarm of the high order channel unit; and an OR gate 37 for supplying a logical add between the alarm output of the OR gate 34 and the alarm output of the AN~
gate 36 and for outputting the alarm output to the self-channel unit and the low order channel unit.
The synchronous control operation is explained with reference to Fig. 7. When the synchronous control flag is not detected, the AND gate 32 opens (ON) and the AND
gate 30 closes (OFF), then, the memory address of the self-channel unit is output from the OR gate 33 to the self-channel unit and the low order channel unit. Thus, the self-channel unit writes or reads the transmission signal to or from an elastic memory in accordance with the memory address of the self-channel unit.
On the other hand, if the self-channel unit detects the synchronous signal from the transmission signal, the synchronous control flag turns ON, the AND gate 32 closes (OFF) and the AND gate 30 opens (ON), and thus the memory address of the high order channel unit is output from the OR gate 33 to the self-channel unit and the low order channel unit.
Therefore, the self-channel unit writes or reads the 3~ transmission signal to or from the elastic memory in accordance with the memory address of the high order channel unit.
As mentioned above, the low order channel unit is synchronized and controlled depending on the high order channel unit, and in spite of the combination of the channel units, only a single synchronous control circuit can be synchronized and control the low order channel 206~98 ~
unit.
While, in the alarm signal, when the synchronous control flag is not detected, the AND gate 35 closes (OFF) and the AND gate 36 closes (OFF), and thus the alarm signal of the self-channel unit is not transmitted to both the high order channel unit and low order channel unit, accordingly at the asynchronous state, the unnecessary alarm signal is not transmitted.
On the other hand, when the self-channel unit detects the synchronous signal from the transmission signal, the synchronous control flag turns ON, the AND
gate 35 opens (ON), the AND gate 36 opens (ON), the alarm signal of the self-channel unit and the alarm signal of the low order channel unit can be transmitted to the high order channel unit, and the alarm signal of the high order channel unit can be transmitted to the self-channel unit and the low order channel unit. Thus, in the synchronizing state, an alarm of one channel can be transmitted to all the channels, and when asynchronous state occurs, a countermeasure can be carried out.
In addition to the above embodiment, the following modifications are possible. In the above embodiment, the synchronous control signal is explained by using an address of an elastic memory, however, instead, the other synchronous control signal such as a timing signal or the like can be used.
In the embodiment, an example wherein all the channel units are synchronously controlled is shown, however, in the circuit comprising 12 channels, for example, the following aspect can be applied. Namely, the 3 channels are synchronized as a circuit, the 4 channels are synchronized as another circuit, and the 5 channels are further synchronized as the other circuit, or the like.
Also, in this embodiment, the invention is explained using an example of the multiplex unit, this may be applied to a separation unit, a cross connect unit or the 2~61~87 g like.
sesides the above, various modifications are possible, in the scope of the subject matter of this invention. These modifications also should not be excluded.
In this invention, the synchronous control circuits 3 outputting the synchronous control signal are provided in the respective channel units 10 to 12, and the synchronous control signal from the synchronous control circuit 3 of the high order channel unit is output to the self-channel unit and transmitted to the synchronous control circuit 3 of the low order channel unit in response to the synchronized signal in the transmission signal. Thus, the lower channel units are synchronized with the high order channel unit, the synchronization of the arbitrary channel is possible by single circuitry, and the many synchronous control circuits corresponding to combinations of the channels are not needed.
Further, since the synchronization of the arbitrary channel is possible by single circuitry, only the necessary channel can be easily synchronized.
CHANNEL UNITS AND CIRCUIT USING SAID METHOD
BACKGROUND OF THE INVENTION
1. Field of the Invention The present invention relates to a synchronous control method in a plurality of channel units and a circuit using said method for synchronously controlling a transmission operation of the plurality of channel units.
In a synchronous transmission system, each frame of the transmission signal of a plurality of channels is synchronized thereamong. To execute the frame synchronization, transmission operation in each channel unit by which a transmission signal is transmitted, is controlled synchronizedly. In the synchronous control of the channel units, a necessary synchronous control method is executed corresponding to combinations of the channel units.
2. Description of the Related Art The synchronous transmission system, for example, receives 150 Mb/s inputs having three 50 Mb/s signals by three channel units in a transmission process circuit, multiplexes the same to 150 Mb/s to transmit by a multiplex circuit, separates the multiplex signal to three 50 Mb/s signals by a separation circuit of a reception process circuit, and the separated signals are output from three channel units.
In this synchronous transmission, since frame positioning of the transmission signals are carried out in the three channel units of the transmission process circuit and the three channel unit of the reception process circuit, synchronous control circuits are provided in the transmission process circuit and the reception process circuit, and the synchronous control circuit supplies the synchronous control signal to the channel units of the transmission process circuit and the ~ ~4~87 .
channel units of the reception process circuit to synchronously control.
When the plurality of channel units are transmitted and synchronized, since applied channel numbers and combinations of the channel units are already determined, the necessary synchronous control circuit is used in response to the combination.
While, for effective utilization of lines, particularly at a high speed condition of transmission, there is a request for arbitrary synchronized channel numbers by various combinations of the channel units.
In this constitution, hitherto, since the synchronous control circuit is used corresponding to a combination of the channel units, the synchronous control circuits that are the same number as the channel units combination, must be provided, and moreover, there is a problem in that all the combinations are not always carried out.
Also there is another problem in that when 150 Mb/s circuit is added to another 150 Mb/s circuit to expand the system, the synchronous control cannot be carried out among the system, the expansion of the system is difficult, and the circuitry must be changed in response to the application aspects.
SUMMARY OF THE INVENTION
In accordance with an embodiment of the present invention there is provided in a synchronous control method, in a plurality of channel units including a high order channel unit and a low order channel unit, for synchronously transmitting transmission signals in response to a synchronous control signal by the plurality of channel units, the improvement characterized in the following process steps: providing a plurality of synchronous control circuits in cooperation with the plurality of channel units, each of the synchronous control circuits outputting a synchronous control signal; and supplying the synchronous control signal from the synchronous control ~ ~4~
circuit of the high order channel unit to a self-channel unit and the synchronous control circuit of the low order channel unit in response to a synchronous signal in a transmission signal.
In accordance with another embodiment of the present invention there is provided a synchronous control circuit in a plurality of channel units using a synchronous control method for synchronously transmitting each transmission signal in response to a synchronous control signal by the plurality of channel units, comprising: a logical operation circuit wherein a synchronous control signal for a self-channel unit and a synchronous control signal for a low order channel unit are output; the synchronous control signals are determined by a conjunction of a synchronous control signal corresponding to a high order channel unit and a synchronous control flag in a transmission signal from the self-channel unit; or by a conjunction of a synchronous control signal from the self-channel unit and an inverted signal of the synchronous control flag from the self-channel unit.
Other features and advantages of the invention will be apparent from the following description with reference to the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a block diagram for explaining a related art;
Fig. 2 is a block diagram for explaining another related art;
Fig. 3 is a block diagram for explaining problems in a related art;
Fig. 4 is a block diagram for explaining a summary of an embodiment according to the present invention;
Fig. 5 is a block diagram for illustrating a 1' 206~7 transmission process circuit of a system executing a synchronous control method in a plurality of channel units according to the embodiment of the invention;
Fig. 6 is an example of a circuit diagram of a synchronous control circuit in Fig. 5; and Fig. 7 is an explanatory diagram for illustrating an operation of a synchronous control in the synchronous control circuit in Fig. 6.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Prior to the explanation of an embodiment, a related art of this invention is explained with reference to drawings.
Figure 1 and Fig. 2 are block diagrams for illustrating the related art. In Fig. 1, a synchronous transmission is explained and in Fig. 2, a synchronous control is explained.
As shown in Fig. 1, a synchronous transmission system receives, for example, three inputs of 50 Mb/s (Megabit/second) at channel units 10 to 12 of a transmission process circuit, the three inputs multiplexed by a multiplex circuit (MUX) 22 to 150 Mb/s, are transmitted to a reception process circuit, separated by a separation circuit (DMUX) 24 to three outputs of 50 Mb/s, and output from channel units 16 to 18.
In the above synchronous transmission, since the respective channel units 10 to 12 and 16 to 18 carry out frame synchronization of the transmission signals, as shown in Fig. 2, a synchronous control circuit 3 is provided in the transmission process circuit and the reception process circuit, respectively, the synchronous control circuit 3 supplies the synchronous control signal to the respective channel unit 10 to 12 and 16 to 18, and the system is controlled synchronizedly.
When the plurality of channels are transmitted synchronizedly, since the applied number of the channel, a combination of the channels, or the like have already been determined, the synchronous control circuit 206~87 corresponding to the combination is used.
In Fig. 3, problems in the related art are explained. To utilize lines effectively at high speed transmission by various combinations of the channels, arbitrary acquisition of the synchronized number of channels is requested.
In this case, hitherto, since the synchronous control circuit corresponding to the combination of the channels is used, there is a problem wherein the synchronous control circuits being the same number as the number of the channel combinations must be provided.
Moreover, the provided synchronous control circuits cannot respond to all the combinations.
Further as shown in Fig. 3, in the case when the system is expanded by providing another 150 Mb/s system to a 150 Mb/s system, the synchronous control is not carried out, the expansion of the system is difficult, and the circuit constitution must change in response to the application aspect.
Next, the summary of an embodiment is explained. In the embodiment of this invention, a synchronous control circuit 3 outputting a synchronous control signal is provided in each channel units 10 to 12, since the synchronous control signal from the synchronous control circuit 3 of a high order channel unit is output to a self-channel unit and to the synchronous control circuit 3 of a low order channel unit, in response to the synchronous signal in the transmission signal; the low order channel unit is synchronized with the high order channel unit, an arbitrary channel synchronization is possible by single circuitry and only the necessary channel can be synchronized.
In a working aspect of this invention, the synchronous control signal is an address signal of a memory of the channel units 10 to 12, and a frame synchronization of the transmission signal is realized by the memory control.
- 6 - ~0~987 In another working aspect of this invention, when the synchronous control circuit 3 is in a synchronous control state, an alarm signal from the high order or low order is output to the self-channel unit and transmits the same to the low order or high order channel unit, and the alarm can be despatched to all the channels at a synchronous state to process. When not in a synchronous state, an unnecessary alarm is not imparted to the other channel units.
Next, an embodiment of this invention is explained with reference to Fig. 5 wherein an example in a transmission process circuit is shown. Fig. 6 and Fig. 7 are explanatory diagrams of the synchronous control circuit according to the embodiment of the invention.
The identical reference numerals shown in Figs. 1 and 4 designate the same articles.
In Fig. 5, six 50 MbJs lines are connected to six channel units 10 to 15 and multiplexers (MUX) 22 and 23 multiplex the six channel to two 150 Mb/s channel. To synchronously control the above six channels 10 to 15, the synchronous control circuits 3 are provided in the respective channel units 10 to 15.
The synchronous control circuit 3, as shown in Fig. 6, comprises an AND gate 30 for supplying a conjunction ~etween a synchronous control flag by a synchronous signal detected from the transmission signal by the channel unit and an ES (elastic memory) control signal (memory address) from the synchronous control circuit 3 of a high order channel unit; an inverter 31 inverting the synchronous control flag; an AND gate 32 for supplying a conjunction between an ES control signal (memory address) of the self-channel unit and the inverted synchronous control flag; and an OR gate 33 for supplying a logical add between outputs of AND gates 30 and 32 and outputting the ES control signal (memory address) to the self-channel unit and to the low order channel unit.
206~9~7 Further, the synchronous control circuit 3 comprises an OR gate 34 for supplying a logical add between an alarm of the self-channel unit and an alarm of the low order channel unit; an AND gate 35 for supplying a conjunction between the synchronous control flag and the alarm output of the OR gate 34; an AND gate 36 for supplying a con~unction between the synchronous control flag and the alarm of the high order channel unit; and an OR gate 37 for supplying a logical add between the alarm output of the OR gate 34 and the alarm output of the AN~
gate 36 and for outputting the alarm output to the self-channel unit and the low order channel unit.
The synchronous control operation is explained with reference to Fig. 7. When the synchronous control flag is not detected, the AND gate 32 opens (ON) and the AND
gate 30 closes (OFF), then, the memory address of the self-channel unit is output from the OR gate 33 to the self-channel unit and the low order channel unit. Thus, the self-channel unit writes or reads the transmission signal to or from an elastic memory in accordance with the memory address of the self-channel unit.
On the other hand, if the self-channel unit detects the synchronous signal from the transmission signal, the synchronous control flag turns ON, the AND gate 32 closes (OFF) and the AND gate 30 opens (ON), and thus the memory address of the high order channel unit is output from the OR gate 33 to the self-channel unit and the low order channel unit.
Therefore, the self-channel unit writes or reads the 3~ transmission signal to or from the elastic memory in accordance with the memory address of the high order channel unit.
As mentioned above, the low order channel unit is synchronized and controlled depending on the high order channel unit, and in spite of the combination of the channel units, only a single synchronous control circuit can be synchronized and control the low order channel 206~98 ~
unit.
While, in the alarm signal, when the synchronous control flag is not detected, the AND gate 35 closes (OFF) and the AND gate 36 closes (OFF), and thus the alarm signal of the self-channel unit is not transmitted to both the high order channel unit and low order channel unit, accordingly at the asynchronous state, the unnecessary alarm signal is not transmitted.
On the other hand, when the self-channel unit detects the synchronous signal from the transmission signal, the synchronous control flag turns ON, the AND
gate 35 opens (ON), the AND gate 36 opens (ON), the alarm signal of the self-channel unit and the alarm signal of the low order channel unit can be transmitted to the high order channel unit, and the alarm signal of the high order channel unit can be transmitted to the self-channel unit and the low order channel unit. Thus, in the synchronizing state, an alarm of one channel can be transmitted to all the channels, and when asynchronous state occurs, a countermeasure can be carried out.
In addition to the above embodiment, the following modifications are possible. In the above embodiment, the synchronous control signal is explained by using an address of an elastic memory, however, instead, the other synchronous control signal such as a timing signal or the like can be used.
In the embodiment, an example wherein all the channel units are synchronously controlled is shown, however, in the circuit comprising 12 channels, for example, the following aspect can be applied. Namely, the 3 channels are synchronized as a circuit, the 4 channels are synchronized as another circuit, and the 5 channels are further synchronized as the other circuit, or the like.
Also, in this embodiment, the invention is explained using an example of the multiplex unit, this may be applied to a separation unit, a cross connect unit or the 2~61~87 g like.
sesides the above, various modifications are possible, in the scope of the subject matter of this invention. These modifications also should not be excluded.
In this invention, the synchronous control circuits 3 outputting the synchronous control signal are provided in the respective channel units 10 to 12, and the synchronous control signal from the synchronous control circuit 3 of the high order channel unit is output to the self-channel unit and transmitted to the synchronous control circuit 3 of the low order channel unit in response to the synchronized signal in the transmission signal. Thus, the lower channel units are synchronized with the high order channel unit, the synchronization of the arbitrary channel is possible by single circuitry, and the many synchronous control circuits corresponding to combinations of the channels are not needed.
Further, since the synchronization of the arbitrary channel is possible by single circuitry, only the necessary channel can be easily synchronized.
Claims (6)
1. A synchronous control method, in a plurality of channel units including a high order channel unit and a low order channel unit, for synchronously transmitting transmission signals in response to a synchronous control signal by said plurality of channel units, the improvement characterized in the following process steps:
providing a plurality of synchronous control circuits in cooperation with said plurality of channel units, each of said synchronous control circuits outputting a synchronous control signal; and supplying the synchronous control signal from the synchronous control circuit of said high order channel unit to a self-channel unit and the synchronous control circuit of said low order channel unit in response to a synchronous signal in a transmission signal.
providing a plurality of synchronous control circuits in cooperation with said plurality of channel units, each of said synchronous control circuits outputting a synchronous control signal; and supplying the synchronous control signal from the synchronous control circuit of said high order channel unit to a self-channel unit and the synchronous control circuit of said low order channel unit in response to a synchronous signal in a transmission signal.
2. A synchronous control method as set forth in claim 1, wherein each channel unit is provided with at least one memory and wherein said synchronous control signal is an address signal of said memory.
3. A synchronous control method as set forth in claim 1, wherein when said plurality of synchronous control circuits are in a synchronous control state, the synchronous control circuits supply an alarm signal from said high order channel unit to the self-channel unit and to said low order channel unit or from said low order channel unit to the self-channel unit and to said high order channel unit.
4. A synchronous control circuit in a plurality of channel units using a synchronous control method for synchronously transmitting each transmission signal in response to a synchronous control signal by said plurality of channel units, comprising:
a logical operation circuit wherein a synchronous control signal for a self-channel unit and a synchronous control signal for a low order channel unit are output; the synchronous control signals are determined by a conjunction of a synchronous control signal corresponding to a high order channel unit and a synchronous control flag in a transmission signal from the self-channel unit; or by a conjunction of a synchronous control signal from the self-channel unit and an inverted signal of the synchronous control flag from the self-channel unit.
a logical operation circuit wherein a synchronous control signal for a self-channel unit and a synchronous control signal for a low order channel unit are output; the synchronous control signals are determined by a conjunction of a synchronous control signal corresponding to a high order channel unit and a synchronous control flag in a transmission signal from the self-channel unit; or by a conjunction of a synchronous control signal from the self-channel unit and an inverted signal of the synchronous control flag from the self-channel unit.
5. A synchronous control circuit as set forth in claim 4, wherein each channel unit is provided with at least one memory and wherein said synchronous control signal is an address signal of said memory.
6. A synchronous control circuit as set forth in claim 4, further comprising an alarm circuit for supplying as an alarm input to the high order channel unit a conjunction of the synchronous control flag from the self-channel unit in the transmission signal and a logical add between an alarm signal from the self-channel unit and an alarm signal from the low order channel unit; and for supplying outputs determined to be either a conjunction of an alarm signal from the high order channel unit and the synchronous control flag or a logical add of an alarm signal from the self-channel unit and an alarm signal from the low order channel unit as an alarm output of the self-channel unit and an alarm output of the low order channel unit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03-109,864 | 1991-04-15 | ||
| JP3109864A JP2968369B2 (en) | 1991-04-15 | 1991-04-15 | Synchronous control method for multiple channels |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2064987A1 CA2064987A1 (en) | 1992-10-16 |
| CA2064987C true CA2064987C (en) | 1999-03-30 |
Family
ID=14521135
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002064987A Expired - Fee Related CA2064987C (en) | 1991-04-15 | 1992-04-02 | A synchronous control method in a plurality of channel units |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5319637A (en) |
| EP (1) | EP0509448B1 (en) |
| JP (1) | JP2968369B2 (en) |
| CA (1) | CA2064987C (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5689535A (en) * | 1992-08-25 | 1997-11-18 | Dsc Communications Corporation | Method and apparatus for processing multiple facility datalinks |
| JP2938294B2 (en) * | 1992-12-29 | 1999-08-23 | 富士通株式会社 | Subrate control channel switching method |
| WO1997001140A1 (en) * | 1995-06-23 | 1997-01-09 | Philips Electronics N.V. | A circuit for coordinating the timing of operations of asynchronously operating sub-circuits |
| US5940456A (en) * | 1996-06-20 | 1999-08-17 | Ut Starcom, Inc. | Synchronous plesiochronous digital hierarchy transmission systems |
| DE19800619A1 (en) * | 1998-01-12 | 1999-07-15 | Lucent Tech Network Sys Gmbh | Circuit for transmitting plesiochronic signals in Synchronous Digital Hierarchy transmission system |
| DE10005793A1 (en) * | 2000-02-10 | 2001-08-16 | Siemens Ag | Data transmission system |
| CN101919186A (en) * | 2008-01-15 | 2010-12-15 | 爱立信电话股份有限公司 | Telecom multiplexer for variable rate composite bit stream |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58182932A (en) * | 1982-04-20 | 1983-10-26 | Fujitsu Ltd | Inspection system of quality of transmission line |
| JPS60173992A (en) * | 1984-02-17 | 1985-09-07 | Fujitsu Ltd | Subordinate address switching system in subordinate synchronizing network |
| JPS61177834A (en) * | 1985-02-04 | 1986-08-09 | Hitachi Ltd | Multiplexed signal transmitting system |
| JPH0752987B2 (en) * | 1986-02-28 | 1995-06-05 | 株式会社日立製作所 | Multi-dimensional information order storage time slot selection method |
| US4933934A (en) * | 1986-12-22 | 1990-06-12 | Nec Corporation | Time division multiplexing method with channel compression and a device therefor |
| JPS63236432A (en) * | 1987-03-25 | 1988-10-03 | Fujitsu Ltd | System for multiplexing bsi-ed bit interleave |
-
1991
- 1991-04-15 JP JP3109864A patent/JP2968369B2/en not_active Expired - Fee Related
-
1992
- 1992-04-02 CA CA002064987A patent/CA2064987C/en not_active Expired - Fee Related
- 1992-04-10 US US07/867,141 patent/US5319637A/en not_active Expired - Lifetime
- 1992-04-14 EP EP92106432A patent/EP0509448B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US5319637A (en) | 1994-06-07 |
| EP0509448B1 (en) | 1996-03-13 |
| JP2968369B2 (en) | 1999-10-25 |
| CA2064987A1 (en) | 1992-10-16 |
| EP0509448A2 (en) | 1992-10-21 |
| EP0509448A3 (en) | 1993-01-13 |
| JPH04316233A (en) | 1992-11-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed | ||
| MKLA | Lapsed |
Effective date: 20020402 |