CA2066443C - Parallel i/o newtork file server architecture - Google Patents

Parallel i/o newtork file server architecture Download PDF

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Publication number
CA2066443C
CA2066443C CA002066443A CA2066443A CA2066443C CA 2066443 C CA2066443 C CA 2066443C CA 002066443 A CA002066443 A CA 002066443A CA 2066443 A CA2066443 A CA 2066443A CA 2066443 C CA2066443 C CA 2066443C
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Prior art keywords
network
data
requests
file
storage device
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CA2066443A1 (en
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Edward John Row
Laurence B. Boucher
William M. Pitts
Stephen E. Blightman
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NetApp Inc
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Auspex Systems Inc
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/10File systems; File servers
    • G06F16/18File system types
    • G06F16/1858Parallel file systems, i.e. file systems supporting multiple processors
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00Network arrangements or protocols for supporting network services or applications
    • H04L67/01Protocols
    • H04L67/133Protocols for remote procedure calls [RPC]
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00Network arrangements or protocols for supporting network services or applications
    • H04L67/01Protocols
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/40Network security protocols
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H04L69/329Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the application layer [OSI layer 7]

Abstract

A file server architecture is disclosed, comprising as separate processors, a network controller unit (110), a file controller unit (112) and a storage processor unit (114). These units incorporate their own processors, and operate in parallel with a local Unix host processor (118). All networks are connected to the network controller unit (110), which performs all protocol process-ing up through the NFS layer. The virtual file system is implemented in the file controller unit (112) and the storage processor (114) provides high-speed multiplexed access to an array of mass storage devices. The file controller unit (112) controls file infor-mation caching through its own local cache buffer, and controls disk data caching through a large system memory which is acces-sible on a bus by any of the processors.

Description

.sY5 i5, l 7 0.
w ~ ~1 ~ .~ ~#- :-7'~

10 The present application is related to the following U.S. Patent Applications, all filed concurrently herewith:
1. MULTIPLE FACILITY OPERATING SYSTEM
ARCHITECTURE, invented by David Hitz, Allan Schwartz, James Lau and Guy Harris;
2. ENHANCED VMEBUS PROTOCOL UTILIZING
PSEUDOSYNCHRONOUS HANDSHAKING AND BLOCK MODE DATA
TRANSFER, invented by Daryl Starr; and 3. BUS LOCKING FIFO MULTI-PROCESSOR COMMUNICATIONS
SYSTEM UTILIZING PSEUDOSYNCHRONOUS HANDSHAKING AND
BLOCK MODE DATA TRANSFER invented by Daryl D. Starr, William Pitts and Stephen Blightman.
The above applications are all assigned to the assignee of the present invention and are all expressly incorporated herein by reference.
SUBSTITUTE SHEET

WO 91/03788 ~ ~.~ ~ ~~ ':~ ..:~ PCT/US90/04711 BACKGROUND OF THE INVENTION
Field of the Invention The invention relates to computer data networks, and more particularly, to network file server architectures for computer networks.
Description of the Related Art Over the past ten years, remarkable increases in hardware price/performance ratios have caused a startling shift in both technical and office computing environments. Distributed workstation-server networks are displacing the once pervasive dumb terminal attached to mainframe or minicomputer. To date, however, network I/O limitations have constrained the potential performance available to workstation users.
This situation has developed in part because dramatic jumps in microprocessor performance have exceeded increases in network I/0 performance.
In a computer network, individual user workstations are referred to as clients, and shared resources for filing, printing, data storage and wide-area communications are referred to as servers. Clients and servers are all considered nodes of a network.
Client nodes use standard communications protocols to exchange service requests and responses with server nodes.
Present-day network clients and servers usually run the DOS, Macintosh OS, OS/2, or Unix operating systems. Local networks are usually Ethernet or Token Ring at the high end, Arcnet in the midrange, or LocalTalk or StarLAN at the low end. The client-server communication protocols are fairly strictly dictated by the operating system environment --usually one of several proprietary schemes for PCs (NetWare, 3Plus, Vines, LANManager, LANServer);
AppleTalk for Macintoshes; and TCP/IP with NFS or RFS
SUBSTIT~Tt ~H~Ej WO 91/03788 -~~ '" ~ ~ ~.~ :~ '~ ,.~ PCT/US90/04711 for Unix. These protocols are all well-known in the industry.
Unix client nodes typically feature a 16- or 32-bit microprocessor with 1-8 MB of primary memory, a 640 x 1024 pixel display, and a built-in network interface. A 40-100 MB local disk is often optional.
Low-end examples are 80286-based PCs or 68000-based Macintosh I's; mid-range machines include 80386 PCs, Macintosh II's, and 680X0-based Unix workstations;
high-end machines include RISC-based DEC, HP, and Sun Unix workstations. Servers are typically nothing more than repackaged client nodes, configured in 19-inch racks rather than desk sideboxes. The extra space of a 19-inch rack is used for additional backplane slots, disk or tape drives, and power supplies.
Driven by RISC and CISC microprocessor developments, client workstation performance has increased by more than a factor of ten in the last few years. Concurrently, these extremely fast clients have also gained an appetite for data that remote servers are unable to satisfy. Because the I/O
shortfall is most dramatic in the Unix environment, the description of the preferred embodiment of the present invention will focus on Unix file servers.
The architectural principles that solve the Unix server I/O problem, however, extend easily to server performance bottlenecks in other operating system environments as well. Similarly, the description of the preferred embodiment will focus on Ethernet . 30 implementations, though the principles extend easily to other types of networks.
In most Unix environments, clients and servers exchange file data using the Network File System ("NFS"), a standard promulgated by Sun Microsystems and now widely adopted by the Unix community. NFS is defined in a document entitled, "NFS: Network File SUBSTI1U1~ Sn~Er r,, .~ r WO 91/03788 '~ ~ ~ ~ ~'~ ~" '~ PCT/US90/04711 System Protocol Specification," Request For Comments (RFC) 1094, by Sun Microsystems, Inc. (March 1989).
This document is incorporated herein by reference in its entirety.
While simple and reliable, NFS is not optimal.
Clients using NFS place considerable demands upon both networks and NFS servers supplying clients with NFS
data. This demand is particularly acute for so-called diskless clients that have no local disks and therefore depend on a file server for application binaries and virtual memory paging as well as data .
For these Unix client-server configurations, the ten to-one increase in client power has not been matched by a ten-to-one increase in Ethernet capacity, in disk speed, or server disk-to-network I/O throughput.
The result is that the number of diskless clients that a single modern high-end server can adequately support has dropped to between 5-10, depending on client power and application workload. For clients containing small local disks for applications and paging, referred to as dataless clients, the client-to-server ratio is about twice this, or between 10-20.
Such low client/server ratios cause piecewise network configurations in which each local Ethernet contains isolated traffic for its own 5-10 (diskless) clients and dedicated server. For overall connectivity, these local networks are usually joined together with an Ethernet backbone or, in the future, with an FDDI backbone. These backbones are typically connected to the local networks either by IP routers or MAC-level bridges, coupling the local networks together directly, or by a second server functioning as a network interface, coupling servers for all the local networks together.
~ll6STITUT~ SHEET

WO 91/03788 ~, h;' ~~ ~, .~ ;~ ~_~ PCT/US90/04711 In addition to performance considerations, the low client-to-server ratio creates computing problems in several additional ways:
1. Sharing. Development groups of more than 5 10 people cannot share the same server, and thus cannot easily share files without file replication and manual, multi-server updates. Bridges or routers are a partial solution but inflict a performance penalty due to more network hops.
2. Administration. System administrators must maintain many limited-capacity servers rather than a few more substantial servers. This burden includes network administration, hardware maintenance, and user account administration.
3. File System Backup. System administrators or operators must conduct multiple file system backups, which can be onerously time consuming tasks . It is also expensive to duplicate backup peripherals on each server (or every few servers if slower network backup is used).
4. Price Per Seat. With only 5-10 clients per server, the cost of the server must be shared by only a small number of users. The real cost of an entry-level Unix workstation is therefore significantly greater, often as much as 140% greater, than the cost of the workstation alone.
The widening I/O gap, as well as administrative and economic considerations, demonstrates a need for higher-performance, larger-capacity Unix file servers.
Conversion of a display-less workstation into a server may address disk capacity issues, but does nothing to address fundamental I/O limitations. As an NFS
server, the one-time workstation must sustain 5-10 or more times the network, disk, backplane, and file system throughput than it was designed to support as a client. Adding larger disks, more network adaptors, sI~~STITUTE SHEET

WO 91 /03788 w PCT/US9~/04711 extra primary memory, or even a faster processor do not resolve basic architectural I/O constraints; I/O
throughput does not increase sufficiently.
Other prior art computer architectures, while not specifically designed as file servers, may potentially be used as such. In one such well-known architecture, a CPU, a memory unit, and two I/O processors are connected to a single bus. One of the I/O processors operates a set of disk drives, and if the architecture is to be used as a server, the other I/O processor would be connected to a network. This architecture is not optimal as a file server, however, at least because the two I/O processors cannot handle network file requests without involving the CPU. All network file requests that are received by the network I/O
processor are first transmitted to the CPU, which makes appropriate requests to the disk-I/O processor for satisfaction of the network request.
In another such computer architecture, a disk controller CPU manages access to disk drives, and several other CPUs, three for example, may be clustered around the disk controller CPU. Each of the other CPUs can be connected to its own network. The network CPUs are each connected to the disk controller CPU as well as to each other for interprocessor communication. One of the disadvantages of this computer architecture is that each CPU in the system runs its own complete operating system. Thus, network file server requests must be handled by an operating system which is also heavily loaded with facilities and processes for performing a large number of other, non file-server tasks. Additionally, the interprocessor communication is not optimized for file server type requests.
In yet another computer architecture, a plurality of CPUs, each having its own cache memory for data and s~~tSTtTUTE SHEET

WO 91/03788 .5 :. ' r~ ~~ ,:~ , PCT/US90/04711 a;...~ "t.i _7_ instruction storage, are connected to a common bus with a system memory and a disk controller. The disk controller and each of the CPUs have direct memory access to the system memory, and one or more of the CPUs can be connected to a network. This architecture is disadvantageous as a file server because, among other things, both file data and the instructions for the CPUs reside in the same system memory. There will be instances, therefore, in which the CPUs must stop running while they wait for large blocks of file data to be transferred between system memory and the network CPU. Additionally, as with both of the previously described computer architectures, the entire operating system runs on each of the CPUs, including the network CPU.
In yet another type of computer architecture, a large number of CPUs are connected together in a hypercube topology. One of more of these CPUs can be connected to networks, while another can be connected to disk drives. This architecture is also disadvantageous as a file server because, among other things, each processor runs the entire operating system. Interprocessor communication is also not optimal for file server applications.
SUMMARY OF THE INVENTION
The present invention involves a new, server-specific I/O architecture that is optimized for a Unix file server's most common actions -- file operations.
. Roughly stated, the invention involves a file server architecture comprising one or more network controllers, one or more file controllers, one or more storage processors, and a system or buffer memory, all connected over a message passing bus and operating in parallel with the Unix host processor. The network controllers each connect to one or more network, and ~~$ST1TUT~ SHEET

WO 91 /03788 . ~ "; a t 3 ~; PGT/US90/04711 ~:~r~~.l.,~~l~~~~~
_g_ provide all protocol processing between the network layer data format and an internal file server format for communicating client requests to other processors in the server. Only those data packets which cannot be interpreted by the network controllers, for example client requests to run a client-defined program on the server, are transmitted to the Unix host for processing. Thus the network controllers, file controllers and storage processors contain only small parts of an overall operating system, and each is optimized for the particular type of work to which it is dedicated.
Client requests for file operations are transmitted to one of the file controllers which, independently of the Unix host, manages the virtual file system of a mass storage device which is coupled to the storage processors. The file controllers may also control data buffering between the storage processors and the network controllers, through the system memory. The file controllers preferably each include a local buffer memory for caching file control information, separate from the system memory for caching file data.
Additionally, the network controllers, file processors and storage processors are all designed to avoid any instruction fetches from the system memory, instead keeping all instruction memory separate and local.
This arrangement eliminates contention on the backplane between microprocessor instruction fetches and transmissions of message and file data.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention will be described with respect to particular embodiments thereof, and reference will be made to the drawings, in which:
Fig. 1. is a block diagram of a prior art file server architecture;
s~SSTITUTE SHEET

3 ~~-~''~ !~ ~. ' ~ PCT/US90/04711 _g_ Fig. 2 is a block diagram of a file server architecture according to the invention;
Fig. 3 is a block diagram of one of the network controllers shown in Fig. 2;
Fig. 4 is a block diagram of one of the file controllers shown in Fig. 2;
Fig. 5 is a block diagram of one of the storage processors shown in Fig. 2;
Fig. 6 is a block diagram of one of the system memory cards shown in Fig. 2;
Figs. 7A-C are a flowchart illustrating the operation of a fast transfer protocol BLOCK WRITE
cycle; and Figs. 8A-C are a flowchart illustrating the operation of a fast transfer protocol BLOCK READ
cycle.
DETAILED DESCRIPTION
For comparison purposes and background, an illustrative prior-art file~server architecture will first be described with respect to Fig. 1. Fig. 1 is an overall block diagram of a conventional prior-art Unix-based file server for Ethernet networks. It consists of a host CPU card 10 with a single microprocessor on board. The host CPU card 10 connects to an Ethernet #1 12, and it connects via a memory management unit (MMU) 11 to a large memory array 16. The host CPU card 10 also drives a keyboard, a video display, and two RS232 ports (not * 30 shown). It also connects via the MMU 1l and a standard 32-bit VME bus 20 to various peripheral devices, including an SMD disk controller 22 controlling one or two disk drives 24, a SCSI host adaptor 26 connected to a SCSI bus 28, a tape controller 30 connected to a quarter-inch tape drive 32, and possibly a network #2 controller 34 connected SU~$TITUTE SHEET

WO 91/03788 ~" ~~ ~~ ~ ;A ~~.s~, P~ PCT/US90/04711 to a second Ethernet 36. The SMD disk controller 22 can communicate with memory array 16 by direct memory access via bus 20 and MMU 11, with either the disk controller or the MMU acting as a bus master. This configuration is illustrative; many variations are available.
The system communicates over the Ethernets using industry standard TCP/IP and NFS protocol stacks. A
description of protocol stacks in general can be found in Tanenbaum, "Computer Networks" (Second Edition, Prentice Hall: 1988). File server protocol stacks are described at pages 535-546. The Tanenbaum reference is incorporated herein by reference.
Basically, the following protocol layers are implemented in the apparatus of Fig. 1:
Network Layer. The network layer converts data packets between a formal specific to Ethernets and a format which is independent of the particular type of network used. the Ethernet-specific format which is used in the apparatus of Fig. 1 is described in Hornig, "A Standard For The Transmission of IP
Datagrams Over Ethernet Networks," RFC 894 (April 1984), which is incorporated herein by reference.
The Internet Protocol f IP ) Layer . Th i s 1 a y a r provides the functions necessary to deliver a package of bits (an Internet datagram) from a source to a destination over an interconnected system of networks.
For messages to be sent from the file server to a client, a higher level in the server calls the IP
module, providing the Internet address of the destination client and the message to transmit. The IP module performs any required fragmentation of the message to accommodate packet size limitations of any intervening gateway, adds Internet headers to each fragment, and calls on the network layer to transmit the resulting Internet datagrams. The Internet header S~SSTITUTr SHE I

.-, v .i ~,r ~~~~ ,~'F,, .',7 includes a local network destination address (translated from the Internet address) as well as other parameters.
For messages received by the IP layer from the network layer, the IP module determines from the Internet address whether the datagram is to be forwarded to another host on another network, for example on a second Ethernet such as 36 in Fig. 1, or whether it is intended for the server itself. If it is intended for another host on the second network, the IP module determines a local net address for the destination and calls on the local network layer for that network to send the datagram. If the datagram is intended for an application program within the server, the IP layer strips off the header and passes the remaining portion of the message to the appropriate next higher layer. The Internet protocol standard used in the illustrative apparatus of Fig. 1 is specified in Information Sciences Institute, "Internet Protocol, DARPA Internet Program Protocol Specification," RFC 791 (September 1981), which is incorporated herein by reference.
TCP/UDP Layer. This layer is a datagram service with more elaborate packaging and addressing options than the IP layer. For example, whereas an IP
datagram can hold about 1,500 bytes and be addressed to hosts, UDP datagrams can hold about 64KB and be addressed to a particular port within a host. TCP and UDP are alternative protocols at this layer;
applications requiring ordered reliable delivery of streams of data may use TCP, whereas applications (such as NFS) which do nat require ordered and reliable delivery may use UDP.
The prior art file server of Fig. 1 uses both TCP
and UDP. It uses UDP for file server-related services, and uses TCP for certain other services SI~BSTITs~'f Sr»T

WO 91/03788 q;, ~'y ~ !~ ,y ~~ j_~ PCT/US90/04711 which the server provides to network clients. The UDP
is specified in Postel, "User Datagram Protocol," RFC
768 (August 28, 1980), which is incorporated herein by reference. TCP is specified in Postel, "Transmission Control Protocol," RFC 761 (January 1980) and RFC 793 (September 1981 ) , which is also incorporated herein by reference.
XD~/RPC Layer. This layer provides functions callable from higher level programs to run a designated procedure on a remote machine. It also provides the decoding necessary to permit a client machine to execute a procedure on the server. For example, a caller process in a client node may send a call message to the server of Fig. 1. The call message includes a specification of the desired procedure, and its parameters. The message is passed up the stack to the RPC layer, which calls the appropriate procedure within the server. When the procedure is complete, a reply message is generated and RPC passes it back down the stack and over the network to the caller client. RPC is described in Sun Microsystems, Inc., "RPC: Remote Procedure Call Protocol Specification, Version 2," RFC 1057 (June 1988), which is incorporated herein by reference.
RPC uses the XDR external data representation standard to represent information passed to and from the underlying UDP layer. XDR is merely a data encoding standard, useful for transferring data between different computer architectures. Thus, on the network side of the XDR/RPC layer, information is machine-independent; on the host application side, it may not be. XDR is described in Sun Microsystems, Inc., "XDR: External Data Representation Standard,"
RFC 1014 (June 1987), which is incorporated herein by reference.
~~iBSTITIii~c SHs~;' WO 91/03788 ~ w -~ ~ ~ r -PCT/US90/04711 m,a . ~.

~1FS Laver. The NFS ("network file system") layer is one of the programs available on the server which an RPC request can call. The combination of host address, program number, and procedure number in an RPC request can specify one remote NFS procedure to be called.
Remote procedure calls to NFS on the file server of Fig. 1 provide transparent, stateless, remote access to shared files on the disks 24. NFS assumes a file system that is hierarchical, with directories as all but the bottom level of files. Client hosts can call any of about 20 NFS procedures including such procedures as reading a specified number of bytes from a specified file; writing a specified number of bytes to a specified file; creating, renaming and removing specified files; parsing directory trees; creating and removing directories; and reading and setting file attributes . The location on disk to which and from which data is stored and retrieved is always specified in logical terms, such as by a file handle or Inode designation and a byte offset. The details of the actual data storage are hidden from the client. The NFS procedures, together with possible higher level modules such as Unix VFS and UFS, perform all conversion of logical data addresses to physical data addresses such as drive, head, track and sector identification. NFS is specified in Sun Microsystems, Inc., "NFS: Network File System Protocol Specification," RFC 1094 (March 1989), incorporated herein by reference.
With the possible exception of the network layer, . all the protocol processing described above is done in software, by a single processor in the host CPU card 10. That is, when an Ethernet packet arrives on Ethernet 12, the host CPU 10 performs all the protocol processing in the NFS stack, as well as the protocol SU~S~'~TUTE SHEET

_,°. ~~ ~ ~ ~~ ,~~ i ~ PCT/US90/04711 processing for any other application which may be running on the host 10. NFS procedures are run on the host CPU 10, with access to memory 16 for both data and program code being provided via MMU 11. Logically specified data addresses are converted to a much more physically specified form and communicated to the SMD
disk controller 22 or the SCSI bus 28, via the VME bus 20, and all disk caching is done by the host CPU 10 through the memory 16. The host CPU card 10 also runs procedures for performing various other functions of the file server, communicating with tape controller 30 via the VME bus 20. Among these are client-defined remote procedures requested by client workstations.
If the server serves a second Ethernet 36, packets from that Ethernet are transmitted to the host CPU 10 over the same VME bus 20 in the form of IP datagrams.
Again, all protocol processing except for the network layer is performed by software processes running on the host CPU 10. In addition, the protocol processing for any message that is to b~ sent from the server out on either of the Ethernets 12 or 36 is also done by processes running on the host CPU 10.
It can be seen that the host CPU 10 performs an enormous amount of processing of data, especially if 5-10 clients on each of the two Ethernets are making file server requests and need to be sent responses on a frequent basis. The host CPU 10 runs a multitasking Unix operating system, so each incoming request need not wait for the previous request to be completely processed and returned before being processed.
Multiple processes are activated on the host CPU 10 for performing different stages of the processing of different requests, so many requests may be in process at the same time. But there is only one CPU on the card 10, so the processing of these requests is not accomplished in a truly parallel manner. The SlI~ST(TI;T~ SN~ET

WO 91/03788 ~ ~ ~' ' ' ~ 'r PGT/US90/04711 W, v~~ ": ~) ~.~ 's ;3 processes are instead merely time sliced. The CPU 10 therefore represents a major bottleneck in the processing of file server requests.
Another bottleneck occurs in MMU 11, which must transmit both instructions and data between the CPU
card 10 and the memory 16. All data flowing between the disk drives and the network passes through this interface at least twice.
Yet another bottleneck can occur on the VME bus 20, which must transmit data among the SMD disk controller 22, the SCSI host adaptor 26, the host CPU card 10, and possibly the network #2 controller 24.
PREFERRED EMBODIMENT-OVERALL HARDi~IARE ARCHITECTURE
In Fig. 2 there is shown a block diagram of a network file server 100 according to the invention.
It can include multiple network controller (NC) boards, one or more file controller (FC) boards, one or more storage processor (SP) boards, multiple system memory boards, and one or more host processors. The particular embodiment shown in Fig. 2 includes four network controller boards 110a-110d, two file controller boards 112a-112b, two storage processors 114a-114b, four system memory cards 116a-116d for a total of 192MB of memory, and one local host processor 118. The boards 110, 112, 114, 116 and 118 are connected together over a VME bus 120 on which an enhanced block transfer mode as described in the ENHANCED VMEBUS PROTOCOL application identified above may be used. Each of the four network controllers 110 shown in Fig. 2 can be connected to up to two Ethernets 122, for a total capacity of 8 Ethernets 122a-122h. Each of the storage processors 114 operates ten parallel SCSI busses, nine of which can each support up to three SCSI disk drives each. The tenth SCSI channel on each of the storage processors ~i13ST1TUT~ SHEET

,. ,.~ .-. v ; . ~ a WO 91/03788 w~ ~ ~: ~~ ~.~3 '~ w~'y <v:' PCT/US90/04711 114 is used for tape drives and other SCSI
peripherals.
The host 118 is essentially a standard SunOs Unix processor, providing all the standard Sun Open Network Computing (ONC) services except NFS and IP routing.
Importantly, all network requests to run a user defined procedure are passed to the host for execution. Each of the NC boards 110, the FC boards 112 and the SP boards 114 includes its own independent 32-bit microprocessor. These boards essentially off-load from the host processor 118 virtually all of the NFS and disk processing. Since the vast majority of messages to and from clients over the Ethernets 122 involve NFS requests and responses, the processing of these requests in parallel by the NC, FC and SP
processors, with minimal involvement by the local host 118, vastly improves file server performance. Unix is explicitly eliminated from virtually all network, file, and storage processing.
OVERALL SOFTWARE ORGANIZATION AND DATA FLOW
Prior to a detailed discussion of the hardware subsystems shown in Fig. 2, an overview of the software structure will now be undertaken. The software organization is described in more detail in the above-identified application entitled MULTIPLE
FACILITY OPERATING SYSTEM ARCHITECTURE.
Most of the elements of the software are well known in the field and are found in most networked Unix systems, but there are two components which are not:
Local NFS ("LNFS") and the messaging kernel ("MK") operating system kernel. These two components will be explained first.
The Messaging Kernel. The various processors in file server 100 communicate with each other through the use of a messaging kernel running on each of the SUBSTITU~",~ SHEET

WO 91/0378$ r:;i 'i:.' ~.) k ~ '~:~ ':r ~.,~ PCT/US90/04711 processors 110, 112, 114 and 118. These processors do not share any instruction memory, so task-level communication cannot occur via straightforward procedure calls as it does in conventional Unix.
Instead, the messaging kernel passes messages over VME
bus 120 to accomplish all necessary inter-processor communication. Message passing is preferred over remote procedure calls for reasons of simplicity and speed.
Messages passed by the messaging kernel have a fixed 128-byte length. Within a single processor, messages are sent by reference; between processors, they are copied by the messaging kernel and then delivered to the destination process by reference.
The processors of Fig. 2 have special hardware, discussed below, that can expediently exchange and buffer inter-processor messaging kernel messages.
The LNFS Local NFS interface. The 22-function NFS
standard was specifically designed for stateless operation using unreliable communication. This means that neither clients nor server can be sure if they hear each other when they talk (unreliability). In practice, an in an Ethernet environment, this works well.
Within the server 100, however, NFS level datagrams are also used for communication between processors, in particular between the network controllers 1I0 and the file controller 112, and between the host processor 118 and the file controller 112. For this internal communication to be both efficient and convenient, it is undesirable and impractical to have complete statelessness or unreliable communications.
Consequently, a modified form of NFS, namely LNFS, is used for internal communication of NFS requests and responses. LNFS is used only wit in the file server 100; the external network protocol supported by the $~SSTITUTE SHEET

'~'~~.'>'~ i!
l~.J ~. v "~,~ Y v .~i ' server is precisely standard, licensed NFS. LNFS is described in more detail below.
The Network Controllers 110 each run an NFS server which, after all protocol processing is done up to the NFS layer, converts between external NFS requests and responses and internal LNFS requests and responses.
For example, NFS requests arrive as RPC requests with XDR and enclosed in a UDP datagram. After protocol processing, the NFS server translates the NFS request into LNFS form and uses the messaging kernel to send the request to the file controller 112.
The file controller runs an LNFS server which handles LNFS requests both from network controllers and from the host 118. The LNFS server translates LNFS requests to a form appropriate for a file system server, also running on the file controller, which manages the system memory file data cache through a block I/0 layer.
An overview of the software in each of the processors will now be set forth.
Network Controller 110 The optimized dataflow of the server 100 begins with the intelligent network controller 110. This processor receives Ethernet packets from client workstations. It quickly identifies NFS-destined packets and then performs full protocol processing on them to the NFS level, passing the resulting LNFS
requests directly to the file controller 112. This protocol processing includes IP routing and reassembly, UDP demultiplexing, XDR decoding, and NFS
request dispatching. The reverse steps are used to send an NFS reply back to a client. Importantly, these time-consuming activities are performed directly in the Network Controller 110, not in the host 118.
SUBSTITUTE ~I~~E T

WO 91/03788 t~ ~a ~~ ~ ,:~ y ~ PCT/US90/04711 The server 100 uses conventional NFS ported from Sun Microsystems, Inc., Mountain View, CA, and is NFS
protocol compatible.
Non-NFS network traffic is passed directly to its destination host processor 118.
The NCs 110 also perform their own IP routing.
Each network controller 110 supports two fully parallel Ethernets. There are four network controllers in the embodiment of the server 100 shown in Fig. 2, so that server can support up to eight Ethernets. For the two Ethernets on the same network controller 110, IP routing occurs completely within the network controller and generates no backplane traffic. Thus attaching two mutually active Ethernets to the same controller not only minimizes their Inter net transit time, but also significantly reduces backplane contention on the VME bus 120. Routing table updates are distributed to the network controllers from the host processor 118, which runs either the gated or routed~Unix demon.
While the network controller described here is designed for Ethernet LANs, it will be understood that the invention can be used just as readily with other network types, including FDDI.
File Controller 112 In addition to dedicating a separate processor for NFS protocol processing and IP routing, the server 100 also dedicates a separate processor, the intelligent file controller 112, to be responsible for all file system processing. It uses conventional Berkeley Unix 4.3 file system code and uses a binary-compatible data representation on disk. These two choices allow all standard file system utilities (particularly block-level tools) to run unchanged.
SUBSTITUTE SI-aEET

WO 91/03788 ~ ~,, ;-~ ,s .;. PCT/US90/04711 t~aa~lJ~::. y as The file controller 112 runs the shared file system used by all NCs 110 and the host processor 118. Both the NCs and the host processor communicate with the file controller 112 using the LNFS interface. The NCs 110 use LNFS as described above, while the host processor 118 uses LNFS as a plug-in module to SunOs's standard Virtual File System ("VFS") interface.
When an NC receives an NFS read request from a client workstation, the resulting LNFS request passes to the FC 112. The FC 112 first searches the system memory 116 buffer cache for the requested data. If found, a reference to the buffer is returned to the NC
110. If not found, the LRU (least recently used) cache buffer in system memory 116 is freed and reassigned for the requested block. The FC then directs the SP 114 to read the block into the cache buffer from a disk drive array. When complete, the SP
so notifies the FC, which in turn notifies the NC 100.
The NC 110 then sends an NFS reply, with the data from the buffer, back to the NFS client workstation out on the network. Note that the SP 114 transfers the data into system memory 116, if necessary, and the NC 110 transferred the data from system memory 116 to the networks. The process takes place without any involvement of the host 118.
Storage Processor The intelligent storage processor 114 manages all disk and tape storage operations. While autonomous, storage processors are primarily directed by the file controller 112 to move file data between system memory 116 and the disk subsystem. The exclusion of both the host 118 and the FC 112 from the actual data path helps to supply the performance needed to service many remote clients.
S~BSTIT(ITE ~fIEE T

WO 91/03788 .. ~fi, ~T> ' ;.t '.;
Pte/ US90/04711 ~.. a _r Additionally, coordinated by a Server Manager in the host 118, storage processor 114 can execute server backup by moving data between the disk subsystem and tape or other archival peripherals on the SCSI
channels. Further, if directly accessed by host processor 118, SP 114 can provide a much higher performance conventional disk interface for Unix, virtual memory, and databases. In Unix nomenclature, the host processor 118 can mount boot, storage swap, and raw partitions via the storage processors 114.
Each storage processor 114 operates ten parallel, fully synchronous SCSI channels (busses) simultaneously. Nine of these channels support three arrays of nine SCSI disk drives each, each drive in an array being assigned to a different SCSI channel. The tenth SCSI channel hosts up to seven tape and other SCSI peripherals. In addition to performing reads and writes, SP 114 performs device-level optimizations such as disk seek queue sorting, directs device error recovery, and controls DMA transfers between the devices and system memory 116.
Host Processor 118 The local host 118 has three main purposes: to run Unix, to provide standard ONC network services for clients, and to run a Server Manager. Since Unix and ONC are ported from the standard SunCJs Release 4 and ONC Services Release 2, the server 100 can provide identically compatible high-level ONC services such as the Yellow Pages, Lock Manager, DES Key Authenticator, Auto Mounter, and Port Mapper. Sun/2 Network disk booting and more general IP Internet services such as Telnet, FTP, SMTP, SNMP, and reverse ARP are also supported. Finally, print spoolers and similar Unix demons operate transparently.
S~~STI1~~T~ ~~~~T

WO 91/03788 , a ,~~ ~~ , ~~, ~ ~ PCT/US90/04711 The host processor 118 runs the following software modules:
TCP and socket layers. The Transport Control Protocol ("TCP"), which is used for certain server functions other than NFS, provides reliable bytestream communication between two processors. Socket are used to establish TCP connections.
VFS interface. The Virtual File System ("VFS") interface is a standard SunOs file system interface.
It paints a uniform file-system picture for both users and the non-file parts of the Unix operating system, hiding the details of the specific file system. Thus standard NFS, LNFS, and any local Unix file system can coexist harmoniously.
yFS interface. The Unix File System ("UFS") interface is the traditional and well-known Unix interface for communication with local-to-the-processor disk drives. In the server 100, it is used to occasionally mount storage processor volumes directly, without going through the file controller 112. Normally, the host 118 uses LNFS and goes through the file controller.
Device layer. The device layer is a standard software interface between the Unix device model and different physical device implementations. In the server 100, disk devices are not attached to host processors directly, so the disk driver in the host's device layer uses the messaging kernel to communicate with the storage processor 114.
Route and Port Mapper Demons. The Route and Port Mapper demons are Unix user-level background processes that maintain the Route and Port databases for packet routing. They are mostly inactive and not in any performance path.
Yell,~wPaaes and Authentication Demon. The Yellow Pages and Authentication services are Sun-ONC standard ~JdSTITUT~ SUB?' WO91/03788 ~~ ''. <° ~ ~ ,~~ ':> PCT/US90/04711 network services. Yellow Pages is a widely used multipurpose name-to-name directory lookup service.
The Authentication service uses cryptographic keys to authenticate, or validate, requests to insure that requestors have the proper privileges for any actions or data they desire.
Server Manager. The Server Manager is an administrative application suite that controls configuration, logs error and performance reports, and provides a monitoring and tuning interface for the system administrator. These functions can be exercised from either system console connected to the host 118, or from a system administrator's workstation.
The host processor 118 is a conventional OEM Sun central processor card, Model 3E/120. It incorporates a Motorola 68020 microprocessor and 4MB of on-board memory. Other processors, such as a SPARC-based processor, are also possible.
The structure and operation of each of the hardware components of server 100 will now be described in detail.
NETWORK CONTROLLER HARDWARE ARCHITECTURE
Fig. 3 is a block diagram showing the data path and some control paths for an illustrative one of the network controllers 110a. It comprises a 20 MHz 68020 microprocessor 210 connected to a 32-bit microprocessor data bus 212. Also connected to the microprocessor data bus 212 is a 256K byte CPU memory 214. The low order 8 bits of the microprocessor data bus 212 are connected through a bidirectional buffer 216 to an 8-bit slow-speed data bus 218. On the slow-speed data bus 218 is a 128K byte EPROM 220, a 32 byte PROM 222, and a multi-function peripheral (MFP) 224.
The EPROM 220 contains boot code for the network F''UeST~TUTE Sf..~EET

I '~.,' ~~ ~'a ~;L

controller 110a, while the PROM 222 stores various operating parameters such as the Ethernet addresses assigned to each of the two Ethernet interfaces on the board. Ethernet address information is read into the corresponding interface control block in the CPU
memory 214 during initialization. The MFP 224 is a Motorola 68901, and performs various local functions such as timing, interrupts, and general purpose I/O.
The MFP 224 also includes a UART for interfacing to an RS232 port 226. These functions are not critical to the invention and will not be further described herein.
The low order 16 bits of the microprocessor data bus 212 are also coupled through a bidirectional buffer 230 to a 16-bit LAN data bus 232. A LAN
controller chip 234, such as the Am7990 LANCE Ethernet controller manufactured by Advanced Micro Devices, Inc. Sunnyvale, CA., interfaces the LAN data bus 232 with the first Ethernet 122a shown in Fig. 2. Control and data for the LAN contrbller 234 are stored in a 512K byte LAN memory 236, which is also connected to the LAN data bus 232. A specialized 16 to 32 bit FIFO
chip 240, referred to herein as a parity FIFO chip and described below, is also connected to the LAN data bus 232. Also connected to the LAN data bus 232 is a LAN
DMA controller 242, which controls movements of packets of data between the LAN memory 236 and the FIFO chip 240. The LAN DMA controller 242 may be a Motorola M68440 DMA controller using channel zero only.
The second Ethernet 122b shown in Fig. 2 connects to a second LAN data bus 252 on the network controller card 110a shown in Fig. 3. The LAN data bus 252 connects to the low order 16 bits of the microprocessor data bus 212 via a bidirectional buffer 250, and has similar components to those appearing on SUBSTITUTE SHEET

W0 91/03788 ~ «,, ~' a ~ ~, PCT/US90/04711 a,, s~ °~ ~ '.z. '.~ p ~

the LAN data bus 232. In particular, a LAN controller 254 interfaces the LAN data bus 252 with the Ethernet 122b, using LAN memory 256 for data and control, and a LAN DMA controller 262 controls DMA transfer of data between the LAN memory 256 and the 16-bit wide data port A of the parity FIFO 260.
The low order 16 bits of microprocessor data bus 212 are also connected directly to another parity FIFO
270, and also to a control port of a VME/FIFO DMA
controller 272. The FIFO 270 is used for passing messages between the CPU memory 214 and one of the remote boards 110, 112, 114, 116 or 118 (Fig. 2) in a manner described below. The VME/FIFO DMA controller 272, which supports three round-robin non-prioritized channels for copying data, controls all data transfers between one of the remote boards and any of the FIFOs 240, 260 or 270, as well as between the FIFOs 240 and 260.
32-bit data bus 274, which is connected to the 32 bit port H of each of the FIFOs 240, 260 and 270, is the data bus over which these transfers take place.
Data bus 274 communicates with a local 32-bit bus 276 via a bidirectional pipelining latch 278, which is also controlled by VME/FIFO DMA controller 727, which in turn communicates with the VME bus 120 via a bidirectional buffer 280.
The local data bus 276 is also connected to a set of control registers 282, Which are directly addressable across the VME bus 120. The registers 282 are used mostly for system initialization and diagnostics.
The local data bus 276 is also coupled to the microprocessor data bus 212 via a bidirectional buffer 284. When the NC 110a operates in slave mode, the CPU
memory 214 is directly addressable from VME bus 120.
One of the remote boards can copy data directly from ~U~STITU'1'E S~EET

WO 91/03788 ; ~~ ~~ ~$ l,,? .a PCT/US90/04711 =,t ~. .i ~ -..:

the CPU memory 214 via the bidirectional buffer 284.

LAN memories 236 and 256 are not directly addressed over VME bus 120.

The parity FIFOs 240, 260 and 270 each consist of an ASIC, the functions and operation of which are described in the Appendix. The FIFOs 240 and 260 are configured for packet data transfer and the FIFO 270 is configured for massage pas sing. Referring to the Appendix, the FIFOs 240 and 260 are programmed with the following bit settings in the Data Transfer Configuration Register:

Bit Definition Setting 0 WD Mode N/A

1 Parity Chip N/A

2 Parity Correct Mode N/A

3 8/16 bits CPU & PortA interface 16 bits(1) 4 Invert Port A address 0 no (0) 5 Invert Port A address 1 yes (1) 6 Checksum Carry Wrap yes (1) 7 Reset no (0) The Data Transfer Control R egister is programmed as follows:

Bit Def inition Settincr 0 Enable PortA Req/Ack yes (1) 1 Enable PortB Req/Ack yes (1) 2 Data Transfer Direction (as desired) 3 CPU parity enable no (0) 4 PortA parity enable no (0) 5 PortB parity enable no (O) 6 Checksum Enable yes (1) 7 PortA Master yes (1) Unlike the configuration used on FIFOs 240 and 260, the microprocessor 210 is responsible for loading and unloading Port A directly. The microprocessor 210 reads an entire 32-bit word from port A with a single instruction using two port A access cycles. Port A
SUBSTITUTE SHEET
i-1 ;:

data transfer is disabled by upsetting bits 0 (Enable PortA~ Req/Ack) and 7 (PortA Master) of the Data Transfer Control Register.
The remainder of the control settings in FIFO 270 are the same as those in FIFOs 240 and 260 described above.
The NC 110a also includes a command FIFO 290. The command FIFO 290 includes an input port coupled to the local data bus 276, and which is directly addressable across the VME bus 120, and includes an output port connected to the microprocessor data bus 212. As explained in more detail below, when one of the remote boards issues a command or response to the NC 110a, it does so by directly writing a 1-word (32-bit) message descriptor into NC 110a's command FIFO 290. Command FIFO 290 generates a "FIFO not empty" status to the microprocessor 210, which then reads the message descriptor off the top of FIFO 290 and processes it.
If the message is a command, then it includes a VME
address at which the message is located (presumably an address in a shared memory similar to 214 on one of the remote boards). The microprocessor 210 then programs the FIFO 270 and the VME/FIFO DMA controller 272 to copy the message from the remote location into the CPU memory 214.
Command FIFO 290 is a conventional two-port FIFO, except that additional circuitry is included for generating a Bus Error signal on VME bus 120 if an attempt is made to write to the data input port while the FIFO is full. Command FIFO 290 has space for 256 entries.
A noteworthy feature of the architecture of NC 110a is that the LAN buses 232 and 252 are independent of the microprocessor data bus 212. Data packets being 3 5 routed to or from an Ethernet are stored in LAN memory 236 on the LAN data bus 232 (or 256 on the LAN data SU~',.r~'' TITUTE SHEET

t a ~ ~ ~ z~ ~;~ ;-~ . ,~ PCT/US90/04711 bus 252), and not in the CPU memory 214. Data transfer between the LAN memories 236 and 256 and the Ethernets 122a and 122b, are controlled by LAN
controllers 234 and 254, respectively, while most data trans f er between LAN memory 2 3 6 or 2 5 6 and a remote port on the VME bus 120 are controlled by LAN DMA
controllers 242 and 262, FIFOs 240 and 260, and VME/FIFO DMA controller 272. An exception to this rule occurs when the size of the data transfer is small, e.g., less than 64 bytes, in which case microprocessor 210 copies it directly without using DMA. The microprocessor 210 is not involved in larger transfers except in initiating them and in receiving notification when they are complete.
The CPU memory 214 contains mostly instructions for microprocessor 210, messages being transmitted to or from a remote board via FIFO 270, and various data blocks for controlling the FIFOs, the DMA controllers and the LAN controllers. The microprocessor 210 accesses the data packets in the LAN memories 236 and 256 by directly addressing them through the bidirectional buffers 230 and 250, respectively, for protocol processing. The local high-speed static RAM
in CPU memory 214 can therefore provide zero wait state memory access for microprocessor 210 independent of network traffic. This is in sharp contrast to the prior art architecture shown in Fig. 1, in which all data and data packets, as well as microprocessor instructions for host CPU card 10, reside in the memory 16 and must communicate with the host CPU card 10 via the MMU 11.
While the LAN data buses 232 and 252 are shown as separate buses in Fig. 3, it will be understood that they may instead be implemented as a single combined bus.

WO 91/03788 ~ ~.~. r, ~r, :, ,~ .~~ PCT/US90/04711 .. , ~ ~.~ y ~~ '_~.. ., NETWORK CON'~L'ROLLER OPERATION
In operation, when one of the LAN controllers (such as 234) receives a packet of information over its Ethernet 122a, it reads in the entire packet and stores it in corresponding LAN memory 236. The LAN
controller 234 then issues an interrupt to microprocessor 210 via MFP 224, and the microprocessor 210 examines the status register on LAN controller 234 (via bidirectional buffer 230) to determine that the event causing the interrupt was a "receive packet completed." In order to avoid a potential lockout of the second Ethernet 122b caused by the prioritized interrupt handling characteristic of MFP 224, the microprocessor 210 does not at this time immediately process the received packet; instead, such processing is scheduled for a polling function.
When the polling function reaches the processing of the received packet, control over the packet is passed to a software link level receive module. The link level receive module then decodes the packet according to either of two different frame formats: standard Ethernet format or SNAP (IEEE 802 LCC) format. An entry in the header in the packet specifies which frame format was used. The link level driver then determines which of three types of messages is contained in the received packet: (1) IP, (2) ARP
packets which can be handled by a local ARP module, or (3) ARP packets and other packet types which must be forwarded to the local host 118 (Fig. 2) for processing. If the packet is an ARP packet which can be handled by the NC 110a, such as a request for the address of server 100, then the microprocessor 210 assembles a response packet in LAN memory 236 and, in a conventional manner, causes LAN controller 234 to transmit that packet back over Ethernet 122a. It is noteworthy that the data manipulation for $Ut~iSTITt,iT~' $HE~T

WO 91103788 ~ .-,, n -a ~5 ~x ~;, PCT/US90/04711 accomplishing this task is performed almost completely in LAN memory 236, directly addressed by microprocessor 210 as controlled by instructions in CPU memory 214. The function is accomplished also without generating any traffic on the VME backplane 120 at all, and without disturbing the local host 118.
If the received packet is either an ARP packet which cannot be processed completely in the NC 110a, or is another type of packet which requires delivery to the local host 118 (such as a client request for the server 100 to execute a client-defined procedure) , then the microprocessor 210 programs LAN DMA
controller 242 to load the packet from LAN memory 236 into FIFO 240, programs FIFO 240 with the direction of data transfer, and programs DMA controller 272 to read the packet out of FIFO 240 and across the VME bus 120 into system memory 116. In particular, the microprocessor 210 first programs the LAN DMA
controller 242 with the starting address and length of the packet in LAN memory 236, and programs the controller to begin transferring data from the LAN
memory 236 to port A of parity FIFO 240 as soon as the FIFO is ready to receive data. Second, microprocessor 210 programs the VME/FIFO DMA controller 272 with the destination address in system memory 116 and the length of the data packet, and instructs the controller to begin transferring data from port B of the FIFO 260 onto VME bus 120. Finally, the microprocessor 210 programs FIFO 240 with the direction of the transfer to take place. The transfer then proceeds entirely under the control of DMA
controllers 242 and 272, without any further involvement by microprocessor 210.
The microprocessor 210 then sends a message to host 118 that a packet is available at a specified system memory address. The microprocessor 210 sends such a SUBSTITUTE SHEET

message by writing a message descriptor to a software-emulated command FIFO on the host, which copies the message from CPU memory 214 on the NC via buffer 284 and into the host's local memory, in ordinary VME
block transfer mode. The host then copies the packet from system memory 116 into the host's own local memory using ordinary VME transfers.
If the packet received by NC 110a from the network is an IP packet, then the microprocessor 210 determines whether it is (1) an IP packet for the server 100 which is not an NFS packet; (2) an IP
packet to be routed to a different network; or (3) an NFS packet. If it is an IP packet for the server 100, but not an NFS packet, then the microprocessor 210 causes the packet to be transmitted from the LAN
memory 236 to the host 118 in the same manner described above with respect to certain ARP packets.
If the IP packet is not intended for the server 100, but rather is to be routed to a client on a different network, then the packet is copied into the LAN memory associated with the Ethernet to which the destination client is connected. If the destination client is on the Ethernet 122b, which is on the same NC board as the source Ethernet_ 122a, then the microprocessor 210 causes the packet to be copied from LAN memory 236 into LAN 256 and then causes LAN
controller 254 to transmit it over Ethernet 122b. (Of course, if the two LAN data buses 232 and 252 are combined, then copying would be unnecessary; the microprocessor 210 would simply cause the LAN
controller 254 to read the packet out of the same locations in LAN memory to which the packet was written by LAN controller 234.) The copying of a packet from LAN memory 236 to LAN
memory 256 takes place similarly to the copying described above from LAN memory to system memory. For SUBSTITUTE SHEET

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transfer sizes of 64 bytes or more, the microprocessor 210 first programs the LAN DMA controller 242 with the starting address and length of the packet in LAN
memory 236, and programs the controller to begin transferring data from the LAN memory 236 into port A
of parity FIFO 240 as soon as the FIFO is ready to receive data. Second, microprocessor 210 programs the LAN DMA controller 262 with a destination address in LAN memory 256 and the length of the data packet, and instructs that controller to transfer data from parity FIFO 260 into the LAN memory 256. Third, microprocessor 210 programs the VME/FIFO DMA
controller 272 to clock words of data out of port B of the FIFO 240, over the data bus 274, and into port B
of FIFO 260. Finally, the microprocessor 210 programs the two FIFOs 240 and 260 with the direction of the transfer to take place. The transfer then proceeds entirely under the control of DMA controllers 242, 262 and 272, without any further involvement by the microprocessor 210. Like the copying from LAN memory to system memory, if the transfer size is smaller than 64 bytes, the microprocessor 210 performs the transfer directly, without DMA.
When each of the LAN DMA controllers 242 and 262 complete their work, they so notify microprocessor 210 by a respective interrupt provided through MFP 224.
When the microprocessor 210 has received both interrupts, it programs LAN controller 254 to transmit the packet on the Ethernet 122b in a conventional manner.
Thus, IP routing between the two Ethernets in a single network controller 110 takes place over data bus 274, generating no traffic over VME bus 120. Nor is the host processor 118 disturbed for such routing, in contrast to the prior art architecture of Fig. 1.
Moreover, all but the shortest copying work is SUBSTITUTE SHEET

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performed by controllers outside microprocessor 210, requiring the involvement of the microprocessor 210, and bus traffic on microprocessor data bus 212, only for the supervisory functions of programming the DMA
controllers and the parity FIFOs and instructing them to begin. The VME/FIFO DMA controller 272 is programmed by loading control registers via microprocessor data bus 212; the LAN DMA controllers 242 and 262 are programmed by loading control registers on the respective controllers via the microprocessor data bus 212, respective bidirectional buffers 230 and 250, and respective LAN data buses 232 and 252, and the parity FIFOs 240 and 260 are programmed as set forth in the Appendix.
If the destination workstation of the IP packet to be routed is on an Ethernet connected to a different one of the network controllers 110, then the packet is copied into the appropriate LAN memory on the NC 110 to which that Ethernet is connected. Such copying is accomplished by first copying the packet into system memory 116, in the manner described above with respect to certain ARP packets, and then notifying the destination NC that a packet is available. When an NC
is so notified, it programs its own parity FIFO and DMA controllers to copy the packet from system memory 116 into the appropriate LAN memory. It is noteworthy that though this type of IP routing does create VME
bus traffic, it still does not involve the host CPU
118.
If the IP packet received over the Ethernet 122a and now stored in LAN memory 236 is an NFS packet intended for the server 100, then the microprocessor 210 performs all necessary protocol preprocessing to extract the NFS message and convert it to the local NFS (LNFS) format. This may well involve the logical concatenation of data extracted from a large number of SUBSTITUTE SHEET

WO 91/03788 ~"~ '~' '~' .~~ "'' '=~ PCT/US90/04711 .j u'h Sr; . ;~ :~ r.:
~J t~. ~~ y individual IP packets stored' in LAN memory 236, resulting in a linked list, in CPU memory 214, pointing to the different blocks of data in LAN memory 236 in the correct sequence.
The exact details of the LNFS format are not important for an understanding of the invention, except to note that it includes commands to maintain a directory of files which are stored on the disks attached to the storage processors 114, commands for reading and writing data to and from a file on the disks, and various configuration management and diagnostics control messages. The directory maintenance commands which are supported by LNFS
include the following messages based on conventional NFS: get attributes of a file (GETATTR); set attributes of a file (SETATTR); look up a file (LOOKUP); created a file (CREATE); remove a file (REMOVE); rename a file (RENAME); created a new linked file (LINK); create a symlink (SYMLINK); remove a directory (RMDIR); and return file system statistics (STATFS). The data transfer commands supported by LNFS include read from a file (READ); write to a file (WRITE); read from a directory (READDIR); and read a link (READLINK). LNFS also supports a buffer release command (RELEASE), for notifying the file controller that an NC is finished using a specified buffer in system memory. It also supports a VOP-derived access command, for determining whether a given type access is legal for specified credential on a specified file.
If the LNFS request includes the writing of file data from the LAN memory 236 to disk, the NC 110a first requests a buffer in system memory 116 to be allocated by the appropriate FC 112. When a pointer to the buffer is returned, microprocessor 210 programs LAN DMA controller 242, parity FIFO 240 and VME/FIFO
DMA controller 272 to transmit the entire block of SIJ~STIIGTE SHEET

:.
WO 91/03788 , :;". ~~ '~> ' ,~ ' PCT/US90/04711 .~ '',s.~ ~~<< , . ; a ~:f ~: y file data to system memory 116. The only difference between this transfer and the transfer described above for transmitting IP packets and ARP packets to system memory 116 is that these data blocks will typically have portions scattered throughout LAN memory 236.
The microprocessor 210 accommodates that situation by programming LAN DMA controller 242 successively for each portion of the data, in accordance with the linked list, after receiving notification that the previous portion is complete. The microprocessor 210 can program the parity FIFO 240 and the VME/FIFO DMA
controller 272 once for the entire message, as long as the entire data block is to be placed contiguously in system memory I16. If it is not, then the microprocessor 210 can program the DMA controller 272 for successive blocks in the same manner LAN DMA
controller 242.
If the network controller 110a receives a message from another processor in server 100, usually from file controller 112 , that file data is available in system memory 116 for transmission on one of the Ethernets, for example Ethernet 122a, then the network controller 110a copies the file data into LAN memory 236 in a manner similar to the copying of file data in the opposite direction. In particular, the microprocessor 210 first programs VME/FIFO DMA
controller 272 with the starting address and length of the data in system memory 116, and programs the controller to begin transferring data over the VME bus 120 into port B of parity FIFO 240 as soon as the FIFO
is ready to receive data. The microprocessor 210 then programs the LAN DMA controller 242 with a destination address in LAN memory 236 and then length of the file data, and instructs that controller to transfer data from the parity FIFO 240 into the LAN memory 236.
Third, microprocessor 210 programs the parity FIFO 240 SUBSTITUTE SHEET

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WO 91103788 . PCT/US90/04711 ~,... !r, .y'::
~'9'-~ ~ _mQa ~::a with the direction of the transfer to take place. The transfer then proceeds entirely under the control of DMA controllers 242 and 272, without any further involvement by the microprocessor 210. Again, if the file data is scattered in multiple blocks in system memory 116, the microprocessor 210 programs the VME/FIFO DMA controller 272 with a linked list of the blocks to transfer in the proper order.
When each of the DMA controllers 242 and 272 complete their work, they so notify microprocessor 210 through MFP 224. The microprocessor 210 then performs all necessary protocol processing on the LNFS message in LAN memory 236 in order to prepare the message for transmission over the Ethernet 122a in the form of Ethernet IP packets. As set forth above, this protocol processing is performed entirely in network controller 110a, without any involvement of the local host 118.
It should be noted that the parity FIFOs are designed to move multiples of 128-byte blocks most efficiently. The data transfer size through port B is always 32-bits wide, and the VME address corresponding to the 32-bit data must be quad-byte aligned. The data transfer size for port A can.be either 8 or 16 bits. For bus utilization reasons, it is set to 16 bits when the corresponding local start address is double-byte aligned, and is set at 8 bits otherwise.
The TCP/IP checksum is always computed in the 16 bit mode. Therefore, the checksum word requires byte swapping if the local start address is not double-byte aligned.
Accordingly, for transfer from port B to port A of any of the FIFOs 240, 260 or 270, the microprocessor 210 programs the VME/FIFO DMA controller to pad the transfer count to the next 128-byte boundary. The extra 32-bit word transfers do not involve the VME
SUBSTITUTE SI-BEET

..~ , ~ ~,,, ~ .:-a , bus, and only the desired number of 32-bit words will be unloaded from port A.
For transfers from port A to port B of the parity FIFO 270, the microprocessor 210 loads port A word s by-word and forces a FIFO full indication when it is finished. The FIFO full indication enables unloading from port B. The same procedure also takes place fox transfers from port A to port B of either of the parity FIFOs 240 or 260, since transfers of fewer than 128 bytes are performed under local microprocessor control rather than under the control of LAN DMA
controller 242 or 262. For all of the FIFOs, the VME/FIFO DMA controller is programmed to unload only the desired number of 32-bit words.
FILE CONTROLLER HARDWARE ARCHTTF_.C'.Ti~
The file controllers (FC) 112 may each be a standard off-the-shelf microprocessor board, such as one manufactured by Motorola Inc. Preferably, however, a more specialized~board is used such as that shown in block diagram form in Fig. 4.
Fig. 4 shows one of the FCs 112a, and it will be understood that the other FC can be identical. In many aspects it is simply a scaled-down version of the NC 110a shown in Fig. 3, and in some respects it is scaled up. Like the NC 110a, FC 112a comprises a 20MHz 68020 microprocessor 310 connected to a 32-bit microprocessor data bus 312. Also connected to the microprocessor data bus 312 is a 256K byte shared CPU
memory 314. The low order 8 bits of the microprocessor data bus 312 are connected through a bidirectional buffer 316 to an 8-bit slow-speed data bus 318. On slow-speed data bus 318 are a 128K byte PROM 320, and a multifunction peripheral (MFP) 324.
The functions of the PROM 320 and MFP 324 are the same as those described above with respect to EPROM 220 and SUBSTITUTE SHEET

WO 91103788 ° ., f, ~ ~ p ,~ ~, PCT/US90104711 f:~~~ ~~v~~=~' MFP 224 on NC 110a. FC 112a does not include PROM
like the PROM 222 on NC 110a, but does include a parallel port 392. The parallel port 392 is mainly for testing and diagnostics.
Like the NC 110a, the FC 112a is connected to the VME bus 120 via a bidirectional buffer 380 and a 32-bit local data bus 376. A set of control registers 382 are connected to the local data bus 376, and directly addressable across the VME bus 120. The local data bus 376 is also coupled to the microprocessor data bus 312 via a bidirectional buffer 384. This permits the direct addressability of CPU
memory 314 from VME bus 120.
FC 112a also includes a command FIFO 390, which includes an input port coupled to the local data bus 376 and which is directly addressable across the VME
bus 120. The command FIFO 390 also includes an output port connected to the microprocessor data bus 312.
The structure, operation and purpose of command FIFO
390 are the same as those described above with respect to command FIFO 290 on NC 110a.
The FC 112a omits the LAN data buses 323 and 352 which are present in NC 110a, but instead includes a 4 megabyte 32-bit wide FC memory 396 coupled to the microprocessor data bus 312 via a bidirectional buffer 394. As will be seen, FC memory 396 is used as a cache memory for file control information, separate from the file data information cached in system memory 116.
The file controller embodiment shown in Fig. 4 does not include any DMA controllers, and hence cannot act as a master for transmitting or receiving data in any block transfer mode, over the VME bus 120. Block transfers do occur with the CPU memory 314 and the FC
memory 396, however, with the FC 112a acting as an VME
bus slave. In such transfers, the remote master SUBSTITUTE SI-MEET

WO 91/03788 F;',, ~ ,~ i~ t;~ ~~ . P~'/US90/04711 addresses the CPU memory 314 or the FC memory 396 directly over the VME bus 120 through the bidirectional buffers 384 and, if appropriate, 394.
FILE Cf~]~tTROLLER'OPERATIC,~
The purpose of the FC 112a is basically to provide virtual file system services in response to requests provided in LNFS format by remote processors on the VME bus 120. Most requests will come from a network controller 110, but requests may also come from the local host 118.
The file related commands supported by LNFS are identified above. They are all specified to the FC
112a in terms of logically identified disk data blocks. For example, the LNFS command for reading data from a file includes a specification of the file from which to read (file system ID (FSID) and file ID
(inode)), a byte offset, and a count of the number of bytes to read. The FC 112a converts that identification into physical form, namely disk and sector numbers, in order to satisfy the command.
The FC 112a runs a conventional Fast File System (FFS or UFS), which is based on the Berkeley 4.3 VAX
release. This code performs the conversion and also performs all disk data caching and control data caching. However, as previously mentioned, control data caching is performed using the FC memory 396 on FC 112a, whereas disk data caching is performed using the system memory 116 (Fig. 2). Caching this file control information within the FC 112a avoids the VME
bus congestion and speed degradation which would result if file control information was cached in system memory 116. The memory on the FC 112a is directly accessed over the VME bus 120 for three main purposes. First, and by far the most frequent, are accesses to FC memory 396 by an SP 114 to read or suessiT~u-r~ sMF~~

q ,,~ « ~ a ~~ ,;~ ~~ PCT/US90/04711 ', ~1,: x~~ w~ : $, 'x. .;r. e., write cached file control information. These are accesses requested by FC 112a to write locally modified file control structures through to disk, or to read file control structures from disk. Second, the FC's CPU memory 314 is accessed directly by other processors for message transmissions from the FC 112a to such other processors. For example, if a data block in system memory is to be transferred to an SP
114 for writing to disk, the FC 112a first assembles a message in its local memory 314 requesting such a transfer. The FC 112a then notifies the SP 114, which copies the message directly from the CPU memory 314 and executes the requested transfer.
A third type of direct access to the FC~s local memory occurs when an LNFS client reads directory entries. When FC 112a receives an LNFS request to read directory entries, the FC 112a formats the requested directory entries in FC memory 396 and notifies the requestor of their location. The requestor then directly accesses FC memory 396 to read the entries.
The version of the UFS code on FC 112a includes some modifications in order to separate the two caches. In particular, two sets of buffer headers are maintained, one for the FC memory 396 and one for the system memory 116. Additionally, a second set of the system buffer routines (GETBLK(), BRELSE(), BREAD(), BWRITE( ) , and BREADA( ) ) exist, one for buffer accesses to FC Mem 396 and one for buffer accesses to system memory 116. The UFS code is further modified to call the appropriate buffer routines for FC memory 396 for accesses to file control information, and to call the appropriate buffer routines for the system memory 116 for the caching of disk data. A description of UFS
may be found in chapters 2, 6, 7 and 8 of ~~Kernel Structure and Flow,~~ by Rieken and Webb of .sh $UBSTITUTE SHEET

WO 91/03788 i ~.' V~ i~~' ~a ;'~ '.~ PCT/US90/Oa711 t".J ..Y ~P~ u~j ~.a~, w:. ~".,!~

consulting (Santa Clara, California: 1988), incorporated herein by reference.
When a read command is sent to the FC by~ a requestor such as a network controller, the FC first converts the file, offset and count information into disk and sector information. It then locks the system memory buffers which contain that information, instructing the storage processor 114 to read them from disk if necessary. When the buffer is ready, the FC returns a message to the requestor containing both the attributes of the designated file and an array of buffer descriptors that identify the locations in system memory 116 holding the data.
After the requestor has read the data out of the buffers, it sends a release request back to the FC.
The release request is the same message that was returned by the FC in response to the read request;
the FC 112a uses the information contained therein to determine which buffers to free.
A write command is processed by FC 112a similarly to the read command, but the caller is expected to write to (instead of read from) the locations in system memory 116 identified by the buffer descriptors returned by the FC 112a. Since FC 112a employs write-through caching, when it receives the release command from the requestor, it instructs storage processor 114 to copy the data from system memory 116 onto the appropriate disk sectors before freeing the system memory buffers for possible reallocation.
The READDIR transaction is similar to read and write, but the request is satisfied by the FC 112a directly out of its own FC memory 396 after formatting the requested directory information specifically for this purpose. The FC 112a causes the storage processor read the requested directory information from disk if it is not already locally cached. Also, SUBSTITUTE SHEET

fa ~ ~ ~: PCT/US90/04711 v ~ d &,-~ ~~ 1'~ I.~ ~,~
r-., . _ .,.

the specified offset is a "magic cookie" instead of a byte offset, identifying directory entries instead of an absolute byte offset into the file. No file attributes are returned.
The READLINR transaction also returns no file attributes, and since links are always read in their entirety, it does not require any offset or count.
For all of the disk data caching performed through system memory 116, the FC 112a acts as a central authority for dynamically allocating, deallocating and keeping track of buffers. If there are two or more FCs 112, each has exclusive control over its own assigned portion of system memory 116. In all of these transactions, the requested buffers are locked during the period between the initial request and the release request. This prevents corruption of the data by other clients.
Also in the situation where there are two or more FCs, each file system on the disks is assigned to a particular one of the FCs~ FC #0 runs a process called FC VICE PRESIDENT, which maintains a list of which file systems are assigned to which FC. When a client processor (for example an NC 110) is about to make an LNFS request designating a particular file system, it first sends the fsid in a message to the FC VICE PRESIDENT asking which FC controls the specified file system. The FC VICE PRESIDENT
responds, and the~client processor sends the LNFS
request to the designated FC. The client processor also maintains its own list of fsid/FC pairs as it discovers them, so as to minimize the number of such requests to the FC VICE PRESIDENT.
STORAGE PROCESSOR HARDWARE ARCHITECTUBE
In the file server 100, each of the storage processors 114 can interface the VME bus 120 with up SUBSTITUTE SHEET

....w.. . ~ . /'A ~-!
E,%
.., .., to 10 different SCSI buses. Additionally, it can do so at the full usage rate of an enhanced block transfer protocol of 55MB per second.
Fig. 5 is a block diagram of one of the SPs 114a.
SP 114b is identical. SP 114a comprises a microprocessor 510, which may be a Motorola 68020 microprocessor operating at 20MHz. The microprocessor 510 is coupled over a 32-bit microprocessor data bus 512 with CPU memory 514, which may include up to 1MB
of static RAM. The microprocessor 510 accesses instructions, data and status on its own private bus 512, with no contention from any other source. The microprocessor 510 is the only master of bus 512.
The low order 16 bits of the microprocessor data bus 512 interface with a control bus 516 via a bidirectional buffer 518. The low order 8 bits of the control bus 516 interface with a slow speed bus 520 via another bidirectional buffer 522. The slow speed bus 520 connects to an MFP 524, similar to the MFP 224 in NC 110a (Fig. 3), and with a PROM 526, similar to PROM 220 on NC 110a. The PROM 526 comprises 128K
bytes of EPROM which contains the functional code for SP 114a. Due to the width and speed of the EPROM 526, the functional code is copied to CPU memory 514 upon reset for faster execution.
MFP 524, like the MFP 224 on NC 110a, comprises a Motorola 68901 multifunction peripheral device. It provides the functions of a vectored interrupt controller, individually programmable I/0 pins, four timers and a DART. The DART functions provide serial communications across an RS 232 bus (not shown in Fig.
5) for debug monitors and diagnostics. Two of the four timing functions may be used as general-purpose timers by the microprocessor 510, either independently or in cascaded fashion. A third timer function provides the refresh clock for a DMA controller WO 91 /03788 , , , ,r, a ; ~ ,.

described below, and the fourth timer generates the DART clock. Additional information on the MFP 524 can be found in "MC 68901 Multi-Function Peripheral Specification," by Motorola, Inc., which is incorporated herein by reference. T h a a i g h t general-purpose I/O bits provided by MFP 524 are configured according to the following table:
7 input Power Failure is Imminent - This functions as an early warning.
6 input SCSI Attention - A composite of the SCSI.
Attentions from all 10 SCSI channels.

5 input Channel Operation Done - A composite of the channel done bits from all 13 channels of the DMA controller, described below.
4 output DMA Controller Enable. Enables the DMA
Controller to run.
3 input VMEbus Interrupt Done - Indicates the completion of a VMEbus Interrupt.
2 input Command Available - Indicates that the BP'S Command Fifo, described below, contains one or more command pointers.
1 output External Interrupts Disable. Disables externally generated interrupts to the microprocessor 510.
0 output Command Fifo Enable. Enables operation of the BP'S Command Fifo. Clears the Command Fifo when reset.
Commands are provided to the SP 114a from the VME
bus 120 via a bidirectional buffer 530, a local data bus 532, and a command FIFO 534. The command FIFO 534 is similar to the command FIFOs 290 and 390 on NC 110a and FC 112a, respectively, and has a depth of 256 32-bit entries. The command FIFO 534 is a write-only register as seen on the VME bus 120, and as a read-only register as seen by microprocessor 510. If the SUBSTITUTE SHEET

,.' , f~~ r~> .w ~~ ~ ; ';~, ;.a FIFO is full at the beginning of a write from the VME
bus, a VME bus error is generated. Pointers are removed from the command FIFO 534 in the order received, and only by the microprocessor 510. Command available status is provided through I/O bit 4 of the MFP 524, and as a long as one or more command pointers are still within the command FIFO 534, the command available status remains asserted.
As previously mentioned, the SP 114a supports up to 10 SCSI buses or channels 540a-540j. In the typical configuration, buses 540a-5401 support up to 3 SCSI
disk drives each, and channel 540j supports other SCSI
peripherals such as tape drives, optical disks, and so on. Physically, the SP 114a connects to each of the SCSI buses with an ultra-miniature D sub connector and round shielded cables. Six 50-pin cables provide 300 conductors which carry 18 signals per bus and 12 grounds. The cables attach at the front panel of the SP 114a and to a commutator board at the disk drive array. Standard 50-pin cables connect each SCSI
device to the commutator board. Termination resistors are installed on the SP 114a.
The SP 114a supports synchronous parallel data transfers up to 5MB per second on each of the SCSI
buses 540, arbitration, and disconnect/reconnect services. Each SCSI bus 540 is connected to a respective SCSI adaptor 542, which in the present embodiment is an AIC 6250 controller IC manufactured by Adapter Inc., Milpitas, California, operating in the non-multiplexed address bus mode. The AIC 6250 is described in detail in ~~AIC-6250 Functional Specification," by Adapter Inc., which is incorporated herein by reference. The SCSI adaptors 542 each provide the necessary hardware interface and low-level electrical protocol to implement its respective SCSI channel.
SUBSTITUTE SHEET

., , ..

The 8-bit data port of each of the SCSI adaptors 542 is connected to port A of a respective one of a set of ten parity FIFOs 544a-544j. The FIFOs 544 are the same as FIFOs 240, 260 and 270 on NC 110a, and are connected and configured to provide parity covered data transfers between the 8-bit data port of the respective SCSI adaptors 542 and a 36-bit (32-bit plus 4 bits of parity) common data bus 550. The FIFOs 544 provide handshake, status, word assembly/disassembly and speed matching FIFO buffering for this purpose.
The FIFOs 544 also generate and check parity for the 32-bit bus, and for RAID 5 implementations they accumulate and check redundant data and accumulate recovered data.
All of the SCSI adaptors 542 reside at a single location of the address space of the microprocessor 510, as do all of the parity FIFOs 544. The microprocessor 510 selects individual controllers and FIFOs for access in pairs, by first programming a pair select register (not shown) to point to the desired pair and then reading from or writing to the control register address of the desired chip in the pair. The microprocessor 510 communicates with the control registers on the SCSI adaptors 542 via the control bus 516 and an additional bidirectional buffer 546, and communicates with the control registers on FIFOs 544 via the control bus 516 and a bidirectional buffer 552. Both the SCSI adaptors 542 and FIFOs 544 employ 8-bit control registers, and register addressing of the FIFOs 544 is arranged such that such registers alias in consecutive byte locations. This allows the microprocessor 510 to write to the registers as a single 32-bit register, thereby reducing instruction overhead.
The parity FIFOs 544 are each configured in their Adaptec 6250 mode. Referring to the Appendix, the SG~ST~T(I i t ~~~~

~,;;, <5 ;~ ~~ y ,' .: a FIFOs 544 are programmed with the following bit settings in the Data Transfer Configuration Register:
Bit Definition Setting 0 WD Mode (0) 1 Parity Chip (1) 2 Parity Correct Mode (0) 3 8/16 bits CPU & PortA interface (0) 4 Invert Port A address 0 (1) 5 Invert Port A address 1 (1) 6 Checksum Carry Wrap (0) 7 Reset (0) The Data Transfer Control Register is programmed as follows:

Bit Definition Setting 0 Enable PortA Req/Ack (1) 1 Enable PortB Req/Ack (1) 2 Data Transfer Direction as desired 3 CPU parity enable (0) 4 PortA parity enables (1) 5 PortB parity enable (1) 6 Checksum Enable (0) 7 PortA Master (0) In addition, bit 4 of the RAM Access Control Register (Long Burst) is programmed for 8- byte bursts.

SCSI adaptors 542 each generate a respective interrupt signal, the status of which are provided to microprocessor 510 as 10 bits of a 16-bit SCSI

interrupt register 556. The SCSI interr upt register 556 is connected to the control bus 516.

Additionally, a composite SCSI interrupt is provided through the MFP 524 whenever any one of the SCSI

adaptors 542 needs servicing, An additional parity FIFO 554 is also provided in the SP 114a, for message passing. Again referring to the Appendix, the parity FIFO 554 is programmed with S~BSTITU T ~ SHE' .. ,~ ~ ~~ ~'. ',, the following bit settings in the Data Transfer Configuration Register:

Bit Definition ,~ettina 0 WD Mode (0) 1 Parity Chip (1) 2 Parity Correct Mode (0) 3 8/16 bits CPU & PortA interface (1) 4 Invert Port A address 0 (1) 5 Invert Port A address 1 (1) 6 Checksum Carry Wrap (0) 7 Reset (0) The Data Transfer Control Register programmed as is follows:

Bit Definition Setting 0 Enable PortA Req/Ack (0) 1 Enable PortB Req/Ack (1) 2 Data Transfer Direction as desired 3 CPU parity enable (0) 4 PortA parity enable (0) 5 PortB parity enable (1) 6 Checksum Enable (0) 7 PortA Master (0) In addition, bit 4 of the RAM Access Control Register 8-byte bursts. ' (Long Burst) is programmed for Port A to the 16-bit of FIFO
554 is connected control bus 516, and port B is connected to the common data bus 550. FIFO 554 provides one means by which the microprocessor 510 can communicate directly with the VME bus 120, as is described in more detail below.
The microprocessor 510 manages data movement using a set of 15 channels, each of which has an unique status which indicates its current state. Channels are implemented using a channel enable register 560 and a channel status register 562, both connected to the control bus 516. The channel enable register 560 SUBSTITUTE SHEET

h, - ~ , ,~ H ~~ ~~ is <% :~? ..~ r.:~

is a 16-bit write-only register, whereas the channel status register 562 is a 16-bit read-only register.
The two registers reside at the same address to microprocessor 510. The microprocessor 510 enables a particular channel by setting its respective bit in channel enable register 560, and recognizes completion of the specified operation by testing for a "done" bit in the channel status register 562. The microprocessor 510 then resets the enable bit, which causes the respective "done" bit in the channel status register 562 to be cleared.
The channels are defined as follows:
0:9 These channels control data movement to and from the respective FIFOe 544 via the common data bus 550. When a FIFO is enabled and a request is received from it, the channel becomes ready. Once the channel has been serviced a status of done is generated.
11:10 These channels control data movement between a local data buffer 564, described below, and the VME bus 120. When enabled the channel becomes ready. Once the channel has been serviced a status of done is generated.
12 When enabled, this channel causes the DRAM in local data buffer 564 to be refreshed based on a clock which is generated by the MFP 524.
The refresh consists of a burst of 16 rows.
This channel does not generate a status of done.
13 The microprocessor's communication FIFO 554 is serviced by this channel. When enable is set and the FIFO 554 asserts a request then the channel becomes ready. This channel generates a status of done.
14 Low latency writes from microprocessor 510 onto the VME bus 120 are controlled by this channel. When this channel is enabled data is moved from a special 32 bit register, described below, onto the VME bus 120. This channel generates a done status.
$DESTITUTE SHEET

t,~ ~p e_..
°~~~b x=x 15 This is a null channel for which neither a ready status nor done status is generated.
Channels are prioritized to allow servicing of the more critical requests first. Channel priority is assigned in a descending order starting at channel 14.
That is, in the event that all channels are requesting service, channel 14 will be the first one served.
The common data bus 550 is coupled via a bidirectional register 570 to a 36-bit junction bus 572. A second bidirectional register 574 connects the junction bus 572 with the local data bus 532. Local data buffer 564, which comprises 1MB of DRAM, with parity, is coupled bidirectionally to the junction bus 572. It is organized to provide 256K 32-bit words with byte parity. The SP 114a operates the DRAMS in page mode to support a very high data rate, which requires bursting of data instead of random single-word accesses. It will be seen that the local data buffer 564 is used to implement a RAID (redundant array of inexpensive disks) algorithm, and is not used for direct reading and writing between the VME bus 120 and a peripheral on one of the SCSI buses 540.
A read-only register 576, containing all zeros, is also connected to the junction bus 572. This register is used mostly for diagnostics, initialization, and clearing of large blocks of data in system memory 116.
The movement of data between the FIFOs 544 and 554, the local data buffer 564, and a remote entity such as the system memory 116 on the VME bus 120, is all controlled by a VME/FIFO DMA controller 580. The VME/FIFO DMA controller 580 is similar to the VME/FIFO
DMA controller 272 on network controller 110a (Fig.
3), and is described in the Appendix. Briefly, it includes a bit slice engine 582 and a dual-port static RAM 584. One port of the dual-port static RAM X84 communicates over the 32-bit microprocessor data bus SUBSTITUTE SHEET

rr ~, .x :.y ., 512 with microprocessor 510, and the other port communicates over a separate 16-bit bus with the bit slice engine 582. The microprocessor 510 places command parameters in the dual-port RAM 584, and uses the channel enables 560 to signal the VME/FIFO DMA
controller 580 to proceed with the command. The VME/FIFO DMA controller is responsible for scanning the channel status and servicing requests, and returning ending status in the dual-port RAM 584. The dual-port RAM 584 is organized as 1K x 32 bits at the 32-bit port and as 2K x 16 bits at the 16-bit port.
example showing the method by which the microprocessor 510 controls the VME/FIFO DMA controller 580 is as follows. First, the microprocessor 510 writes into the dual-port RAM 584 the desired command and associated parameters for the desired channel. For example, the command might be, "copy a block of data from FIFO 544h out into a block of system memory 116 beginning at a specified VME address." Second, the microprocessor sets the channel enable bit in channel enable register 560 for the desired channel.
At the time the channel enable bit is set, the appropriate FIFO may not yet be ready to send data.
Only when the VME/FIFO DMA controller 580 does receive a "ready" status from the channel, will the controller 580 execute the command. In the meantime, the DMA
controller 580 is free to execute commands and move data to or from other channels.
When the DMA controller 580 does receive a status of "ready" from the specified channel, the controller fetches the channel command and parameters from the dual-ported RAM 584 and executes. When the command is complete, for example all the requested data has been copied, the DMA controller writes status back into the dual-port RAM 584 and asserts "done" for the channel in channel status register 562. The microprocessor SUBlSTITUTE SHEET

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r r ',.,~ J'~ V~~ ~4 " ~..

510 is then interrupted, at which time it reads channel status register 562 to determine which channel interrupted. The microprocessor 510 then clears the channel enable for the appropriate channel and checks the ending channel status in the dual-port RAM 584.
In this way a high-speed data transfer can take place under the control of DMA controller 580, fully in parallel with other activities being performed by microprocessor 510. The data transfer takes place over busses different from microprocessor data bus 512, thereby avoiding any interference with microprocessor instruction fetches.
The SP 114a also includes a high-speed register 590, which is coupled between the microprocessor data bus 512 and the local data bus 532. The high-speed register 590 is used to write a single 32-bit word to an VME bus target with a minimum of overhead. The register is write only as viewed from the microprocessor 510. In order to write a word onto the VME bus 120, the microprocessor 510 first writes the word into the register 590, and the desired VME target address into dual-port RAM 584. When the microprocessor 510 enables the appropriate channel in channel enable register 560, the DMA controller 580 transfers the data from the register 590 into the VME
bus address specified in the dual-port RAM 584. The DMA controller 580 then writes the ending status to the dual-port RAM and sets the channel "done" bit in channel status register 562.
This procedure is very efficient for transfer of a single word of data, but becomes inefficient for large blocks of data. Transfers of greater than one word of data, typically for message passing, are usually performed using the FIFO 554.
The SP 114a also includes a series of registers 592, similar to the registers 282 on NC 110a (Fig. 3) SUSSTlTUTE SHEET

Fn ~ , .,.
.~ =.:. , and the registers 382 on FC 112a (Fig. 4). The details of these registers are not important for an understanding of the present invention.
STORAGE PROCESSOR OPERATION
The 30 SCSI disk drives supported by each of the SPs 114 are visible to a client processor, for example one of the file controllers 112, either as three large, logical disks or as 30 independent SCSI drives, depending on configuration. When the drives are visible as three logical disks, the SP uses RAID 5 design algorithms to distribute data for each logical drive on nine physical drives to minimize disk arm contention. The tenth drive is left as a spare. The RAID 5 algorithm (redundant array of inexpensive drives, revision 5) is described in "A Case For a Redundant Arrays of Inexpensive Disks (RAID)", by Patterson et al., published at ACM SIGMOD Conference, Chicago, I11., June 1-3, 1988, incorporated herein by reference.
In the RAID 5 design, disk data are divided into stripes. Data stripes are recorded sequentially on eight different disk drives. A ninth parity stripe, the exclusive-or of eight data stripes, is recorded on a ninth drive. If a stripe size is set to 8K bytes, a read of 8K of data involves only one drive. A write of 8K of data involves two drives: a data drive and a parity drive. Since a write requires the reading back of old data to generate a new parity stripe, writes are also referred to as modify writes. The SP 114a supports nine small reads to nine SCSI drives concurrently. When stripe size is set to 8K, a read of 64K of data starts all eight SCSI drives , with each drive reading one 8K stripe worth of data. The parallel operation is transparent to the caller client. $UE~STtTUTE SHEET

WO 91/03788 ., ~ .-a ,~ ~ ' PCT/US90/04711 ~~~ ~~ a~ i~ i t. ,. ".
y'3 ~_~

The parity stripes are rotated among the nine drives in order to avoid drive contention during write operations. The parity stripe is used to improve availability of data. When one drive is down, the SP
114a can reconstruct the missing data from a parity stripe. In such case, the SP 114a is running in error recovery mode. When a bad drive is repaired, the SP
114a can be instructed to restore data on the repaired drive while the system is on-line.
When the SP 114a is used to attach thirty independent SCSI drives, no parity stripe is created and the client addresses each drive directly.
The SP 114a processes multiple messages (transactions, commands) at one time, up to 200 messages per second. The SP 114a does not initiate any messages after initial system configuration. The following SP 114a operations are defined:
O1 No Op 02 Send Configuration Data 03 Receive Configuration Data 05 Read and Write Sectors 06 Read and Write Cache Pages 07 IOCTL Operation 08 Dump SP 114a Local Data Buffer 09 Start/Stop A SCSI Drive OC Inquiry OE Read Message Log Buffer OF Set SP 114a Interrupt The above transactions are described in detail in the above-identified application entitled MULTIPLE
FACILITY OPERATING SYSTEM ARCHITECTURE. For and understanding of the invention, it will be useful to describe the function and operation of only two of these commands: read and write sectors, and read and write cache pages.
StJ6tSTITUTE SHEET

WO 91/03788 r P ~,.~ ~ ' , =, PCT/US90/04711 .... .~ :.~ dJ a .~r t~e~d~.d Write Sectors This command, issued usually by an FC 112, causes the SP 114a to transfer data between a specified block of system memory and a specified series of contiguous sectors on the SCSI disks. As previously described in connection with the file controller 112, the particular sectors are identified in physical terms.
In particular, the particular disk sectors are identified by SCSI channel number (0-9), SCSI ID on that channel number (0-2), starting sector address on the specified drive, and a count of the number of sectors to read or write. The SCSI channel number is zero if the SP 114a is operating under RAID 5.
The SP 114a can execute up to 30 messages on the 30 SCSI drives simultaneously. Unlike most of the commands to an SP 114, which are processed by microprocessor 510 as soon as they appear on the command FIFO 534, read and write sectors commands (as well as read and write cache memory commands) are first sorted and queued. Hence, they are not served in the order of arrival.
When a disk access command arrives, the microprocessor 510 determines which disk drive is targeted and inserts the message in a queue for that disk drive sorted by the target sector address. The microprocessor 510 executes commands on all the queues simultaneously, in the order present in the queue for each disk drive. In order to minimize disk arm movements, the microprocessor 510 moves back and forth among queue entries in an elevator fashion.
If no error conditions are detected from the SCSI
disk drives, the command is completed normally. When a data check error condition occurs and the SP 114a is configured for RAID 5, recovery actions using 3S redundant data begin automatically. When a drive is down while the SP 114a is configured for RAID 5, SUBSTfTUTE SHEET

a ;a.~ : .~, .~: ;~> '' recovery actions similar to data check recovery take place.
~eadlWrite Cache Pages This command is similar to read and write sectors, except that multiple VME addresses are provided for transferring disk data to and from system memory 116.
Each VME address points to a cache page in system memory 116, the size of which is also specified in the command. When transferring data from a disk to system memory 116, data are scattered to different cache pages; when writing data to a disk, data are gathered from different cache pages in system memory 116.
Hence, this operation is referred to as a scatter gather function.
The target sectors on the SCSI disks are specified in the command in physical terms, in the same manner that they are specified for the read and write sectors command. Termination of the command with or without error conditions is the same as for the read and write sectors command.
The dual-port RAM 584 in the DMA controller 580 maintains a separate set of commands for each channel controlled by the bit slice engine 582. As each channel completes its previous operation, the microprocessor 510 writes a new DMA operation into the dual-port RAM 584 for that channel in order to satisfy the next operation on a disk elevator queue.
The commands written to the DMA controller 580 include an operation code and a code indicating whether the operation is to be performed in non-block mode, in standard VME block mode, or in enhanced block mode. The operation codes supported by DMA controller 580 are as follows:
SUBSTITUTE SHEET

WO 91/03788 ~ a ~ R ' PCT/US90/04711 OP CODE OPERATION

1 ZEROES -> BUFFER Move zeros from zeros register 576 to local data buffer 564.
2 ZEROES -> FIFO Move zeros from zeros register 576 to the currently selected FIFO on common data bus 550.
3 ZEROES -> VMEbus Move zeros from zeros register 576 out onto the VME bus 120.

Used for initializing cache buffers in system memory 116.

4 VMEbus -> BUFFER Move data from the VME bus 120 to the local data buffer 564. This operation is used during a write, to move target data intended for a down drive into the b a f f a r f o r participation in r a d a n d a n c y generation. Used only for RAID 5 application.

5 VMEbus -> FIFO New data to be written from VME bus onto a drive. Since RAID 5 requires redundancy data to be generated from data that is buffered in local data buffer 564, this operation will be used only if the SP 114a is not configured for RAID

5.

6 VMEbus -> BUFFER & FIFO
Target data is moved from VME bus 120 to a SCSI
SUBSTITUTE S~-,9EET

W091/03788 ,~ f~ !, a d -~ :; PCT/US90/04711 ~ ~~ ~3 ~~~;

device and is also captured in the local data buffer 564 for participation in redundancy generation.
Used only if SP 114a is configured for RAID 5 operation.
7 BUFFER -> VMEbus This operation is not used.
8 BUFFER -> FIFO Participating data is transferred to create redundant data or recovered data on a disk drive. Used only in RAID 5 applications.
9 FIFO -> VMEbus This operation is used to move target data directly from a disk drive onto the VME bus 120.
A FIFO -> BUFFER Used to move participating data for recovery and modify operations.
Used only in RAID 5 applications.
B FIFO -> VMEbus & BUFFER
This operation is used to save target data for participation in data recovery. Used only in RAID 5 applications.
SYSTEM MEMORY
Fig. 6 provides a simplified block diagram of the preferred architecture of one of the system memory cards 116a. Each of the other system memory cards are the same. Each memory card 116 operates as a slave on the enhanced VME bus 120 and therefore requires no on-board CPU. Rather, a timing control block 610 is sufficient to provide the necessary slave control operations. In particular, the timing control block SUBSTITUTE SHEET

n ,.-> ,'~ ''",a ?~ : 't~ '~ ~ y r, A

610, in response to control signals from the control portion of the enhanced VME bus 120, enables a 32-bit wide buffer 612 for an appropriate direction transfer of 32-bit data between the enhanced VME bus 120 and a multiplexer unit 614. The multiplexer 614 provides a multiplexing and demultiplexing function, depending on data transfer direction, for a six megabit by seventy-two bit word memory array 620. An error correction code (ECC) generation and testing unit 622 is also connected to the multiplexer 614 to generate or verify, again depending on transfer direction, eight bits of ECC data. The status of ECC verification is provided back to the timing control block 610.
ENHANCED VME BUS PROTOCOL
VME bus 120 is physically the same as an ordinary VME bus, but each of the NCs and SPs include additional circuitry and firmware for transmitting data using an enhanced VME block transfer protocol.
The enhanced protocol is described in detail in the above-identified application entitled ENHANCED VMEBUS
PROTOCOL UTILIZING PSEUDOSYNCHRONOUS HANDSHAKING AND
BLOCK MODE DATA TRANSFER, and summarized in the Appendix hereto. Typically transfers of LNFS file data between NCs and system memory, or between SPs and system memory, and transfers of packets being routed from one NC to another through system memory, are the only types of transfers that use the enhanced protocol in server 100. All other data transfers on VME bus 120 use either conventional VME block transfer protocols or ordinary non-block transfer protocols.
MESSAGE PA,~SING
As is evident from the above description, the different processors in the server 100 communicate with each other via certain types of messages. In SUBSTITUTE SHIEET

w« ,-~ s ,~
' ~. ~ x ~1 i Ail ~', t;s ,~

software, these messages are all handled by the messaging kernel, described in detail in the MULTIPLE
FACILITY OPERATING SYSTEM ARCHITECTURE application cited above. In hardware, they are implemented as follows.
Each of the NCs 110, each of the FCs 112, and each of the SPs 114 includes a command or communication FIFO such as 290 on NC 110a. The host 118 also includes a command FIFO, but since the host is an unmodified purchased processor board, the FIFO is emulated in software. The write port of the command FIFO in each of the processors is directly addressable from any of the other processors over VME bus 120.
Similarly, each of the processors except SPs 114 also includes shared memory such as CPU memory 214 on NC 110a. This shared memory is also directly addressable by any of the other processors in the server 100.
If one processor, for example network controller 110a, is to send a message or command to a second processor, for example file controller 112a, then it does so as follows. First, it forms the message in its own shared memory (e.g., in CPU memory 214 on NC
110a). Second, the microprocessor in the sending processor directly writes a message descriptor into the command FIFO in the receiving processor. For a command being sent from network controller 110a to file controller 112a, the microprocessor 210 would perform the write via buffer 284 on NC 110a, VME bus 120, and buffer 384 on file controller 112a.
The command descriptor is a single 32-bit word containing in its high order 30 bits a VME address indicating the start of a quad-aligned message in the sender's shared memory. The low order two bits indicate the message type as follows:
SUBSTITUTE SHEET

1-~ r s g :, . .. ".,' i.~ ~,~ ~~ '.v:~ e.,?

Tvre ~yscription 0 Pointer to a new message being sent 1 Pointer to a reply message 2 Pointer to message to be forwarded 3 Pointer to message to be freed; also message acknowledgment All messages are 128-bytes long.
When the receiving processor reaches the command descriptor on its command FIFO, it directly accesses the sender's shared memory and copies it into the receiver's own local memory. For a command issued from network controller 110a to file controller 112a, this would be an ordinary VME block or non-block mode transfer from NC CPU memory 214, via buffer 284, VME
bus 120 and buffer 384, into FC CPU memory 314. The FC microprocessor 310 directly accesses NC CPU memory 214 for this purpose over the VME bus 120.
When the receiving processor has received the command and has completed its work, it sends a reply message back to the sending processor. The reply message may be no more than the original command message unaltered, or it may be a modified version of that message or a completely new message. If the reply message is not identical to the original command message, then the receiving processor directly accesses the original sender's shared memory to modify the original command message or overwrite it completely. For replies from the FC 112a to the NC
110a, this involves an ordinary VME block or non-block mode transfer from the FC 112a, via buffer 384, VME bus 120, buffer 284 and into NC CPU memory 214.
Again, the FC microprocessor 310 directly accesses NC
CPU memory 214 for this purpose over the VME bus 120.
Whether or not the original command message has been changed, the receiving processor then writes a reply message descriptor directly into the original sender's command FIFO. The reply message descriptor a~~~STI'ti~'~t S~~'t .~ ~.~ ifi ~~ ,~ :~ :., ~n rs, .-~ , x contains the same VME address as~the original command message descriptor, and the low order two bits of the word are modified to indicate that this is a reply message. For replies from the FC 112a to the NC 110a, the message descriptor write is accomplished by microprocessor 310 directly accessing command FIFO 290 via buffer 384, VME bus 120 and buffer 280 on the NC.
Once this is done, the receiving processor can free the buffer in its local memory containing the copy of the command message.
When the original sending processor reaches the reply message descriptor on its command FIFO, it wakes up the process that originally sent the message and permits it to continue. After examining the reply message, the original sending processor can free the original command message buffer in its own local shared memory.
As mentioned above, network controller 110a uses the buffer 284 data path in order to write message descriptors onto the VME bus 120, and uses VME/FIFO
DMA controller 272 together with parity FIFO 270 in order to copy messages from the VME bus 120 into CPU
memory 214. Other processors read from CPU memory 214 using the buffer 284 data path.
File controller 112a writes message descriptors onto the VME bus 120 using the buffer 384 data path, and copies messages from other processors' shared memory via the same data path. Both take place under the control of microprocessor 310. Other processors copy messages from CPU memory 314 also via the buffer 384 data path.
Storage processor 114a writes message descriptors onto the VME bus using high-speed register 590 in the manner described above, and copies messages from other processors using DMA controller 580 and FIFO 554. The SP 114a has no shared memory, however, so it uses a $UBStITUTE SHEET

.* ..
!W , j ~ ry. p 1,r3 buffer in system memory 116 to emulate that function.
That is, before it writes a message descriptor into another processor's command FIFO, the SP 114a first copies the message into its own previously allocated buffer in system memory 116 using DMA controller 580 and FIFO 554. The VME address included in the message descriptor then reflects the VME address of the message in system memory 116.
In the host 118, the command FIFO and shared memory are both emulated in software.
The invention has been described with respect to particular embodiments thereof, and it will be understood that numerous modifications and variations are possible within the scope of the invention.
SUBSTITUTE SHEET

f r 't '? ;~J ~-fc.' ~.i ~ '~' NDIX A
In storage processor 114a, DMA controller 580 manages the data path under the direction of the microprocessor 510. The DMA controller 580 is a microcoded 16-bit bit-slice implementation executing pipelined instructions at a rate of one each 62.5ns.
It is responsible for scanning the channel status 562 and servicing request with parameters stored in the dual-ported ram 584 by the microprocessor 510. Ending status is returned in the ram 584 and interrupts are generated for the microprocessor 510.
Control Store. The control store contains the microcoded instructions which control the DMA
controller 580. The control store consists of 6 1K x 8 proms configured to yield a 1K x 48 bit microword.
Locations within the control store are addressed by the sequencer and data is presented at the input of the pipeline registers.
Sequencer. The sequencer controls program flow by generating control store addresses based upon pipeline data and various status bits. The control store address consists of 10 bits. Bits 8:0 of the control store address derive from a multiplexer having as its inputs either an ALU output or the output of an incrementer. The incrementer can be preloaded with pipeline register bits 8:0, or it can be incremented as a result of a test condition. The 1K address range is divided into two pages by a latched flag such that the microprogram can execute from either page.
Branches, however remain within the selected page.
Conditional sequencing is performed by having the test condition increment the pipeline provided address. A
false condition allows execution from the pipeline address while a true condition causes execution from SUBSTITUTE SHEET

,i .:v 7rA n..1 :q 1 4.
.. 4 ~ h l., ,.,; l,. :.
.n. ,'.'. Y...' the address + 1. The alu output is selected as an address source in order to directly vector to a routine or in order to return to a calling routine.
Note that when calling a subroutine the calling routine must reside within the same page as the subroutine or the wrong page will be selected on the return.
ALU. The alu comprises a single IDT49C402A
integrated circuit. It is 16 bits in width and most closely resembles four 2901s with 64 registers. The alu is used primarily for incrementing, decrementing, addition and bit manipulation. All necessary control signals originate in the control store. The IDT HIGH
PERFORMANCE CMOS 1988 DATA BOOK, incorporated by reference herein, contains additional information about the alu.
Mi~roword. The 48 bit microword comprises several fields which control various functions of the DMA
controller 580. The format of the microword is defined below along with mnemonics end a description of each function.
AI<8:0> 47:39 (Alu Instruction bits 8:0) The AI
bits provide the instruction for the 49C402A alu. Refer to the IDT data book for a complete definition of the alu instructions. Note that the I9 signal input of the 49C402A is always low.
CIN 38 (Carry INput) This bit forces the carry input to the alu.
RA<5:0> 37:32 (Register A address bits 5:0) These bits select one of 64 registers as the "A" operand for the alu. These bits also provide literal bits 15: 10 for the alu bus.
R8<5:0> 31:26 (Register B address bits 5:0) These bits select one of 64 registers as the "B" operand for the alu. These bits also provide literal bits 9:4 for the alu bus.
SUBSTITUTE Sf~EET

,,_~~~~la r r ;~~ f~ ;,-~eb LFD 25 (Latched Flag Data') When set this bit causes the selected latched flag to be set. When reset this bit causes the selected latched flag to be cleared. This bits also functions as literal bit 3 for the alu bus.
LFS<2:0> 24:22 (Latched Flag Select bits 2:0) The meaning of these bits is dependent upon the selected source for the alu bus. In the event that the literal field is selected as the bus source then LFS<2:0> function as literal bits <2:0> otherwise the bits are used to select one of the latched flags.
LFS<2:0> SELECTED FLAG
0 This value selects a null f lag .
1 When set this bit enables the buffer clock. When reset this bit disables the buffer clock.

2 When this bit is cleared VME

bus transfers, buffer operations and RAS are all disabled.

4 When set this bit enables VME

bus transfers.

5 When set this bit enables buffer operations.

6 When set this bit asserts the row address strobe to the dram buffer.

7 When set this bit selects page 0 of the control store.

SRC<1,0> 20,21 (alu bus SouRCe select bits 1,0) These bits select the data source to be enabled onto the alu bus.

SUBSTiTUtE SHEE1 ' .
.,a ~ ~, ' ~

4,_ r,.a ~.k y ,~

C' d S
l c ource SR _0>
0 ecte e alu 1 dual ported ram 2 literal 3 reserved-not defined PF<2:0> 19:17 (Pulsed Flag select bits 2:0) These bits select a flag/signal to be pulsed.

PF<2:0> Flaa 0 null CLK

_ generates a single transition of buffer clock.

2 SET_VB

forces vme and buffer enable to be set.

PERR

_ clears buffer parity error status.

DN

_ set channel done status for the currently selected channel.

ADR

_ increment dual ported ram address.

6:7 RESERVED - NOT
DEFINED

DEST<3:0> 16:13 (DESTination select bits 3:0) These bits select one of 10 destinations to be loaded from the alu bus.

DEST<3:0> Destination 0 null WR

_ causes the data on the alu bus to be written to the dual ported ram.

D<15:0> -> ram<15:0>

~'sU~STITUTE SHEET

loads the data f rom the alu bus into the dram address counters .

D<14:7> -> mux addr<8:0>

loads the data from the alu bus into the least significant 2 bytes of the VME address register.

D<15:2> -> VME addr<15:2>

tional registers D1 -> ENB

_ D<15:2> -> VME addr<15:2>

D1 -> ENB ENH

DO -> ENB BLK

loads the most significant 2 bytes of the VME address register.

D<15:0> -> VME addr<31:16>

RADD

_ loads the dual ported ram address counters.

D<10:0> -> ram addr <10:0>

WCNT
WR

_ loads the word counters.

D15 -> count enable*

D<14:8> -> count <6:0>

CO
WR

_ loads the co-channel select register.

D<7:4> -> CO<3:0>

g WR_NXT
loads the next-channel select register.
D<3:0> -> NEXT<3:0>

loads the current-channel select register.
D<3:0> -> CURR <3:0>
10:14 RESERVED - NOT DEFINED

causes the control store sequencer to select the alu data bus.
D<8:0> -> CS A<8:0>
SUBSTITUTE SNEET

.. ~. ,. ~;, ~,~, TEST<3:0> 12:9 (TEST condition select bits 3:0) Select one of 16 inputs to the test multiplexor to be used as the carry input to the incrementer.
TEST<3:0> Condition 0 FALSE -always false 1 TRUE -always true 2 ALU COUT -carry output of alu 3 ALU EQ -equals output of alu 4 ALU OVR -alu overflow 5 ALU NEG -alu negative 6 XFR DONE -transfer complete 7 PAR_ERR -buffer parity error 8 TIMOUT -bus operation timeout 9 ANY ERR -any error status 14:10 RESERVED -NOT DEFINED
15 CH RDY -next channel ready NEXT_A<8:0> 8:0 (NEXT Address bits 8:0) Selects an instructions from the current page of the control store for execution.
Dual Ported Ram. The dual ported ram is the medium by which command, parameters and status are communicated between the DMA controller 580 and the microprocessor 510. The ram is organized as 1K x 32 at the master port and as 2K x 16 at the DMA port. The ram may be both written and read at either port.
The ram is addressed by the DMA controller 580 by loading an 11 bit address into the address counters.
Data is then read into bidirectional registers and the address counter is incremented to allow read of the next location.
SUBSTITUTE SHEET

j ~ ?'.e :'-~ j a ( . r, F :: : k~:' . .. ...., , _70_ Writing the ram is accomplished by loading data from the processor into the registers after loading the ram address. Successive writes may be performed on every other processor cycle.
The ram contains current block pointers, ending status, high speed bus address and parameter blocks.
The following i5 the format of the ram:

0 ;CURR POINTER 0 ; STATUS 0 ;
4 ; INITIAL POINTER 0 ;
58 ;CURR POINTER ; STATUS B ;
B

5C ; INITIAL POINTER B ;

_______________ ________________ 60 ; not used ; not used ;

64 ; not used ; not used ;

68 ;CURR POINTER ; STATUS D ;
D

__________________1____________ 6C ; INITIAL POINTER D ;

70 ; not used ; STATUS E ;

_______________ ________________ 74 ;HIGH SPEED BUS ADDRESS 31:2;0;0;

78 ; PARAMETER BLOCK
0 ;

?? ; PARAMETER BLOCK n ;
The Initial Pointer is a 32 bit value which points the first command block of a chain. The current pointer is a sixteen bit value used by the DMA
controller 580 to point to the current command block.
The current command block pointer should be initialized to 0x0000 by the microprocessor 510 before enabling the channel. Upon detecting a value of 0x0000 SUBSTITUTE SNEET

~.~ '~ h~ :i' ~ .
4~:: ,.: ~_ J~

in the current block pointer the DMA controller 580 will copy the lower 16 bits from the initial pointer to the current pointer. Once the DMA controller 580 has completed the specified operations for the parameter block the current pointer will be updated to point to the next block. In the event that no further parameter blocks are available the pointer will be set to 0x0000.
The status byte indicates the ending status for the last channel operation performed. The following status bytes are defined:
STATUS MEANING

The format of the parameter block is:

0 ; FORWARD LINK ' 4 ; NOT USED ; WORD COUNT ;
8 ; - VME ADDRESS 31:2, ENH, BLK ;
C ; TERM 0 ; OP 0 ; BUF ADDR 0 , C+(4Xn) ; TERM n ; OP n ' ~ BUF ADDR n;
FORWARD LINK - The forward link points to the first word of the next parameter block for execution. It allows several parameter blocks to be initialized and chained to create a sequence of operations for execution. The forward pointer has the following format SUBSTITUTE SHEET

H'' ~' ~ ~ r_ ~.: :v r: 3 A31:A2,0,0 The format dictates that the parameter block must start on a quad byte boundary. A pointer of 0x00000000 is a special case which indicates no forward link exists.
WORD COUNT - The word count specifies the number of quad byte words that are to be transferred to or from each buffer address or to/from the VME address. A word count of 64K words may be specified by initializing the word count with the value of 0. The word count has the following format:
(D15(D14(D13(D12(D11(D10(D9(D8(D7(D6(D5(D4(D3(D2(D1(DO( The word count is updated by the DMA controller 580 at the completion of a transfer to/from the last specified buffer address. Word count is not updated after transferring to/from each buffer address and is therefore not an accurate indicator of the total data moved to/from the buffer. Word count represents the amount of data transferred to the VME bus or one of the FIFOs 544 or 554.
VME ADDRESS - The VME address specifies the starting address for data transfers. Thirty bits allows the address to start at any quad byte boundary.
ENH - This bit when set selects the enhanced block transfer protocol described in the above-cited ENHANCED VMEBUS PROTOCOL UTILIZING PSEUDOSYNCHRONOUS
HANDSHAKING AND BLOCK MODE DATA TRANSFER application, to be used during the VME bus transfer. Enhanced protocol will be disabled automatically when performing any transfer to or from 24 bit or 16 bit address space, when the starting address is not 8 byte aligned or when the word count is not even.
BLK - This bit when set selects the conventional VME block mode protocol to be used during the VME bus transfer. Block mode will be disabled automatically SUBSTITUTE SHEET

.. ~' -. ~ ',4 i 4~,: ~t a . ..

when performing any transfer to or from 16 bit address space.
BUF ADDR - The buffer address specifies the starting buffer address for the adjacent operation.
Only 16 bits are available for a 1M byte buffer and as a result the starting address always falls on a 16 byte boundary. The programmer must ensure that the starting address is on a modulo 128 byte boundary. The buffer address is updated by the DMA controller 580 after completion of each data burst.
~A19~A18~A17~A16~A15~A14~A13~A12~A11~A10~A9~A8~A7~A6~A5~A4~
TERM - The last buffer address and operation within a parameter block is identified by the terminal bit.
The DMA controller 580 continues to fetch buffer addresses and operations to perform until this bit is encountered. Once the last operation within the parameter block is executed the word counter is updated and if not equal to zero the series of operations is repeated. Once the word counter reaches zero the forward link pointer is used to access the next parameter block.
i0i0i0i0i0i0i0i0iTi OP - Operations are specified by the op code. The op code byte has the following format:
;O;O;O;O;OP3;OP2;OP1;OP0;
The op codes are listed below ("FIFO" refers to any of the FIFOs 544 or 554):
SUUSTITUTE SHEET

-, :? ~3 ~ '.I
s _ ~~.~ ~r~. ~ 'E: P b OP CODE OpER~TION

1 ZEROES -> BUFFER

ZEROES -> FIFO

3 ZEROES -> VMEbus 4 VMEbus -> BUFFER

VMEbus -> FIFO

VMEbus -> BUFFER & FIFO

BUFFER -> VMEbus 8 BUFFER -> FIFO

9 FIFO -> VMEbus p, FIFO -> BUFFER

B FIFO -> VMEbus & BUFFER

C RESERVED

1~ D RESERVED

E RESERVED

F RESERVED

SuBSTiTUr~ ~~~T

APPENDIX B
Enhanced VME Block Transfer Protocol The enhanced VME block transfer protocol is a VMEbus compatible pseudo-synchronous fast transfer handshake protocol for use on a VME backplane bus having a master functional module and a slave functional module logically interconnected by a data transfer bus. The data transfer bus includes a data strobe signal line and a data transfer acknowledge signal line. To accomplish the handshake, the master transmits a data strobe signal of a given duration on the data strobe line. The master then awaits the reception of a data transfer acknowledge signal from the slave module on the data transfer acknowledge signal line. The slave then responds by transmitting data transfer acknowledge signal of a given duration on the data transfer acknowledge signal line.
Consistent with the pseudo-synchronous nature of the handshake protocol, the data to be transferred is referenced to only one signal depending upon whether the transfer operation is a READ or WRITE operation.
In transferring data from the master functional unit to the slave, the master broadcasts the data to be transferred, The master asserts a data strobe signal and the slave, in response to the data strobe signal, captures the data broadcast by the master.
Similarly, in transferring data from the slave to the master, the slave broadcasts the data to be transferred to the master unit. The slave then asserts a data transfer acknowledge signal and the master, in response to the data transfer acknowledge signal, captures the data broadcast by the slave.
The fast transfer protocol, while not essential to the present invention, facilitates the rapid transfer of large amounts of data across a VME backplane bus by substantially increasing the data transfer rate.
~UBSTITUtr S~iEET

a.<
t ~ ~'~ z ~ ' :.:a ,..
~:..r :.a These data rates are achieved by using a handshake wherein the data strobe and data transfer acknowledge signals are functionally decoupled and by specifying high current drivers for all data and control lines.
The enhanced pseudo-synchronous method of data transfer (hereinafter referred to as "fast transfer mode") is implemented so as to comply and be compatible with the IEEE VME backplane bus standard.
The protocol utilizes user-defined address modifiers, defined in the VMEbus standard, to indicate use of the fast transfer mode. Conventional VMEbus functional units, capable only of implementing standard VMEbus protocols, will ignore transfers made using the fast transfer mode and, as a result, are fully compatible with functional units capable of implementing the fast transfer mode.
The fast transfer mode reduces the number of bus propagations required to accomplish a handshake from four propagations, as required under conventional VMEbus protocols, to only two bus propagations.
Likewise, the number of bus propagations required to ef f ect a BLOCK READ or BLOCR WRITE data trans f er i s reduced. Consequently, by reducing the propagations across the VMEbus to accomplish handshaking and data transfer functions, the transfer rate is materially increased.
The enhanced protocol is described in detail in the above-cited ENHANCED VMEBUS PROTOCOL application, and will only be summarized here. Familiarity with the conventional VME bus standards is assumed.
In the fast transfer mode handshake protocol, only two bus propagations are used to accomplish a handshake, rather than four as required by the conventional protocol. At the initiation of a data transfer cycle, the master will assert and deassert DSO* in the form of a pulse of a given duration. The SUBSTI1UTE S~1EET

.,. ,. ' ~ <,) '~,~,~ ix ~. ~:a deassertion of DSO* is accomplished without regard as to whether a response has been received from the slave. The master then waits for an acknowledgement from the slave. Subsequent pulsing of DSO* cannot occur until a responsive DTACK* signal is received from the slave. Upon receiving the slave's assertion of DTACK*, the master can then immediately reassert data strobe, if so desired. The fast transfer mode protocol does not require the master to wait for the deassertion of DTACK* by the slave as a condition precedent to subsequent assertions of DSO*. In the fast transfer mode, only the leading edge (i.e., the assertion) of a signal is significant. Thus, the deassertion of either DSO* or DTACK* is completely irrelevant for completion of a handshake. The fast transfer protocol does not employ the DS1* line for data strobe purposes at all.
The fast transfer mode protocol may be characterized as pseudo-synchronous as it includes both synchronous and asynchronous aspects. The fast transfer mode protocol is synchronous in character due to the fact that DSO* is asserted and deasserted without regard to a response from the slave. The asynchronous aspect of the fast transfer mode protocol is attributable to the fact that the master may not subsequently assert DSO* until a response to the prior strobe is received from the slave. Consequently, because the protocol includes both synchronous and asynchronous components, it is most accurately classified as "pseudo-synchronous."
The transfer of data during a BLOCK WRITE cycle in the fast transfer protocol is referenced only to DSO* .
The master first broadcasts valid data to the slave, and then asserts DSO to the slave. The slave is given a predetermined period of time after the assertion of DSO* in which to capture the data. Hence, slave ~a Fr , ~ ~., h ~..

modules must be prepared to capture data at any time, as DTACK* is not referenced during the transfer cycle.
Similarly, the transfer of data during a BLOCK READ
cycle in the fast transfer protocol is referenced only to DTACK*. The master first asserts DSO*. The slave then broadcasts data to the master and then asserts DTACK*. The master is given a predetermined period of time after the assertion of DTACK in which to capture the data. Hence, master modules must be prepared to capture data at any time as DSO is not referenced during the transfer cycle.
Fig. 7, parts A through C, is a flowchart illustrating the operations involved in accomplishing the fast transfer protocol BLOCK WRITE cycle. To initiate a BLOCK WRITE cycle, the master broadcasts the memory address of the data to be transferred and the address modifier across the DTB bus. The master also drives interrupt acknowledge signal (IACK*) high and the LWORD* signal low 701. A special address modifier, for example "1F," broadcast by the master indicates to the slave module that the fast transfer protocol will be used to accomplish the BLOCK WRITE.
The starting memory address of the data to be transferred should reside on a 64-bit boundary and the size of block of data to be transferred should be a multiple of 64 bits. In order to remain in compliance with the VMEbus standard, the block must not cross a 256 byte boundary without performing a new address cycle.
The slave modules connected to the DTB receive the address and the address modifier broadcast by the master across the bus and receive LWORD* low and IACK*
high 703. Shortly after broadcasting the address and address modifier 701, the master drives the AS* signal low 705. The slave modules receive the AS* low signal 707. Each slave individually determines whether it ~UBSTiTUT~ SI~~T

~. ~~e i .~C , ~ '' a i ~..
_79_ will participate in the data transfer by determining whether the broadcasted address is valid for the slave in question 709. If the address is not valid, the data transfer does not involve that particular slave and it ignores the remainder of the data transfer cycle.
The master drives WRITE* low to indicate that the transfer cycle about to occur is a WRITE operation 711. The slave receives the WRITE* low signal 713 and, knowing that the data transfer operation is a WRITE operation, awaits receipt of a high to low transition on the DSO* signal line 715. The master will wait until both DTACK* and BERR* are high 718, which indicates that the previous slave is no longer driving the DTB.
The master proceeds to place the first segment of the data to be transferred on data lines D00 through D31, 719. After placing data on D00 through D31, the master drives DSO* low 721 and, after a predetermined interval, drives DSO* high 723.
In response to the transition of DSO* from high to low, respectively 721 and 723, the slave latches the data being transmitted by the master over data lines D00 through D31, 725. The master places the next segment of the data to be transferred on data lines D00 through D31, 727, and awaits receipt of a DTACK*
signal in the form of a high to low transition signal, 729 in Fig. 7B.
Referring to Fig. 7B, the slave then drives DTACK*
low, 731, and, after a predetermined period of time, drives DTACK high, 733. The data latched by the slave, 725, is written to a device, which has been selected to store the data 735. The slave also increments the device address 735. The slave then waits for another transition of DSO* from high to low 737.
aUBSTITUTE SNEET

9 ,I
!'a Vii' a Y y i~ ~ ,r Y.;' o . .n ...J

To commence the transfer of the next segment of the block of data to be transferred, the master drives DSO* low 739 and, after a predetermined period of time, drives DSO* high 741. In response to the transition of DSO* from high to low, respectively 739 and 741, the slave latches the data being broadcast by the master over data lines D00 through D31, 743. The master places the next segment of the data to be transferred on data lines D00 through D31, 745, and awaits receipt of a DTACK* signal in the form of a high to low transition, 747.
The slave then drives DTACK* low, 749, and, after a predetermined period of time, drives DTACK* high, 751. The data latched by the slave, 743, is written to the device selected to store the data and the device address is incremented 753. The slave waits for another transition of DSO* from high to low 737.
The transfer of data will continue in the above described manner until all of the data has been transferred from the master ~to the slave. After all of the data has been transferred, the master will release the address lines, address modifier lines, data lines, IACK* line, LWORD* line and DSO* line, 755. The master will then wait for receipt of a DTACK* high to low transition 757. The slave will drive DTACK* low, 759 and, after a predetermined period of time, drive DTACK* high 761. In response to the receipt of the DTACK* high to low transition, the master will drive AS* high 763 and then release the AS* line 765.
Fig. 8, parts A through C, is a flowchart illustrating the operations involved in accomplishing the fast transfer protocol BLOCK READ cycle. To initiate a BLOCK READ cycle, the master broadcasts the memory address of the data to be transferred and the address modifier across the DTB bus 801. The master S~BSTITUTc SHEET

_~..
i. S~ ~" P ~ r ~' . , ~. m drives the LWORD* signal low and the IACK* signal high 801. As noted previously, a special address modifier indicates to the slave module that the fast transfer protocol will be used to accomplish the BLOCK READ.
The slave modules connected to the DTB receive the address and the address modifier broadcast by the master across the bus and receive LWORD* low and IACK*
high 803. Shortly after broadcasting the address and address modifier 801, the master drives the AS* signal low 805. The slave modules receive the AS* low signal 807. Each slave individually determines whether it will participate in the data transfer by determining whether the broadcasted address is valid for the slave in question 809. If the address is not valid, the data transfer does not involve that particular slave and it ignores the remainder of the data transfer cycle.
The master drives WRITE* high to indicate that the transfer cycle about to occur is a READ operation 811.
The slave receives the WRITE* high signal 813 and, knowing that the data transfer operation is a READ
operation, places the first segment of the data to be transferred on data lines D00 through D31 819. The master will wait until both DTACK* and BERR* are high 818, which indicates that the previous slave is no longer driving the DTB.
The master then drives DSO* low 821 and, after a predetermined interval, drives DSO* high 823. The master then awaits a high to low transition on the DTACK* signal line 824. As shown in Fig. 8B, the slave then drives the DTACK* signal low 825 and, after a predetermined period of time, drives the DTACK*
signal high 827.
In response to the transition of DTACK* from high to low, respectively 825 and 827, the master latches the data being transmitted by the slave over data SUBSTITUTE SHfET

lines D00 through D31, 831. The data latched by the master, 831, is written to a device, which has been selected to store the data the device address is incremented 833.
The slave places the next segment of the data to be transferred on data lines D00 through D31, 829, and then waits for another transition of DSO* from high to low 837.
To commence the transfer of the next segment of the block of data to be transferred, the master drives DSO* low 839 and, after a predetermined period of time, drives DSO* high 841. The master then waits for the DTACK* line to transition from high to low, 843.
The slave drives DTACR* low, 845, and, after a predetermined period of time, drives DTACK* high, 847.
In response to the transition of DTACK* from high to low, respectively 839 and 841, the master latches the data being transmitted by the slave over data lines D00 through D31, 845. The data latched by the master, 845, is written to the device selected to store the data, 851 in Fig. 8C, and the device address is incremented. The slave places the next segment of the data to be transferred on data lines D00 through D31, 849.
The transfer of data will continue in the above-described manner until all of the data to be transferred from the slave to the master has been written into the device selected to store the data.
After all of the data to be transferred has been written into the storage device, the master will release the address lines, address modifier lines, data lines, the IACK* line, the LWORD line and DSO*
line 852. The master will then wait for receipt of a DTACK* high to low transition 853. The slave will drive DTACK* low 855 and, after a predetermined period of time, drive DTACK* high 857. In response to the SUBSTITUTE SHEET

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receipt of the DTACK* high to low transition, the master will drive AS* high 859 and release the AS*
line 861.
To implement the fast transfer protocol, a conventional 64 mA tri-state driver is substituted for the 48 mA open collector driver conventionally used in VME slave modules to drive DTACK*. Similarly, the conventional VMEbus data drivers are replaced with 64 mA tri-state drivers in SO-type packages. The latter modification reduces the ground lead inductance of the actual driver package itself and, thus, reduces "ground bounce" effects which contribute to skew between data, DSO* and DTACK*. In addition, signal return inductance along the bus backplane is reduced by using a connector system having a greater number of ground pins so as to minimize signal return and mated-pair pin inductance. One such connector system is the "High Density Plus" connector, Model No. 420-8015-000, manufactured by Teradyne Corporation.
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APPENDIX C
Parity FIFO
The parity FIFOs 240, 260 and 270 (on the network controllers 110), and 544 and 554 (on storage processors 114) are each implemented as an ASIC. All the parity FIFOs are identical, and are configured on power-up or during normal operation for the particular function desired. The parity FIFO is designed to allow speed matching between buses of different speed, and to perform the parity generation and correction for the parallel SCSI drives.
The FIFO comprises two bidirectional data ports, Port A and Port B, with 36 x 64 bits of RAM buffer between them. Port A is 8 bits wide and Port B is 32 bits wide. The RAM buffer is divided into two parts, each 36 x 32 bits, designated RAM X and RAM Y. The two ports access different halves of the buffer alternating to the other half when available. When the chip is configured as a parallel parity chip (e. g.
one of the FIFOs 544 on SP 114a), all accesses on Port B are monitored and parity is accumulated in RAM X
and RAM Y alternately.
The chip also has a CPU interface, which may be 8 or 16 bits wide. In 16 bit mode the Port A pins are used as the most significant data bits of the CPU
interface and are only actually used when reading or writing to the Fifo Data Register inside the chip.
A REQ, ACK handshake is used for data transfer on both Ports A and B. The chip may be configured as either a master or a slave on Port A in the sense that, in master mode the Port A ACK / RDY output signifies that the chip is ready to transfer data on Port A, and the Port A REQ input specifies that the slave is responding. In slave mode, however, the Port A REQ input specifies that the master requires a data SUBSiitUTE SHEET

WO 91/03788 _ PCT/US90/04711 a, ~ ~' ~f ~,i; j ''~ ~ , transfer, and the chip responds with Port A ACK / RDY
when data is available. The chip is a master on Port B since it raises Port B REQ and waits for Port B ACK
to indicate completion of the data transfer.
SIGNAL DESCRIPTIONS
Port A 0-7, P
Port A is the 8 bit data port. Port A P, if used, is the odd parity bit for this port.
A Req, A Ack/Rdy These two signals are used in the data transfer mode to control the handshake of data on Port A.
uP Data 0-7, uP Data P, uPAdd 0-2, CS
These signals are used by a microprocessor to address the programmable registers within the chip.
The odd parity signal uP Data P is only checked when data is written to the Fifo Data or Checksum Registers and microprocessor parity is enabled.
Clk The clock input is used to generate some of the chip timing. It is expected to be in the 10-20 Mhz range.
Read En, Write En During microprocessor accesses, while CS is true, these signals determine the direction of the microprocessor accesses. During data transfers in the WD mode these signals are data strobes used in conjunction with Port A Ack.
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Port B 00-07, 10-17, 20-27, 30-3'7, OP-3P
Port B is a 32 bit data port. There is one odd parity bit for each byte. Port B OP is the parity of bits 00-07, PortB 1P is the parity of bits 10-17, Port B 2P is the parity of bits 20-27, and Port B 3P is the parity of bits 30-37.
B Select, B Req, B Ack, Parity Sync, B Output Enable These signals are used in the data transfer mode to control the handshake of data on Port B. Port B Req and Port B Ack are both gated with Port B Select.
The Port B Ack signal is used to strobe the data on the Port B data lines. The parity sync signal is used to indicate to a chip conf figured as the parity chip to indicate that the last words of data involved in the parity accumulation are on Port B. The Port B
data lines will only be driven by the Fifo chip if all of the following conditions are met:
a. the data transfer is from Port A to Port B;
b. the Port B select signal is true;
c. the Port B output enable signal is true; and d. the chip is not configured as the parity chip or it is in parity correct mode and the Parity Sync signal is true.
Reset This signal resets all the registers within the chip and causes all bidirectional pins to be in a high impedance state.
DESCRIPTION OF OPERATION
Normal Operation. Normally the chip acts as a simple FIFO chip. A FIFO is simulated by using two RAM buffers in a simple ping-pong mode. It is intended, but not mandatory, that data is burst into or out of the FIFO on Port B. This is done by holding Port B Sel signal low and pulsing the Port B Ack signal. When transferring data from Port B to Port A, ~OBSTITUTE SHEET

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_87_ data is first written into RAM X and when this is full, the data paths will be switched such that Port B may start writing to RAM Y. Meanwhile the chip will begin emptying RAM X to Port A. When RAM Y is full and RAM X empty the data paths will be switched again such that Port B may reload RAM X and Port A may empty RAM Y.
Port A Slave Mor~,Q. This is the default mode and the chip is reset to this condition. In this mode the chip waits for a master such as one of the SCSI
adapter chips 542 to raise Port A Request for data transfer. If data is available the Fifo chip will respond with Port A Ack/Rdy.
Port A WD Mode. The chip may be configured to run in the WD or Western Digital mode. In this mode the chip must be configured as a slave on Port A. It differs from the default slave mode in that the chip responds with Read Enable or Write Enable as appropriate together with Port A Ack/Rdy. This mode is intended to allow the chip to be interfaced to the Western Digital 33C93A SCSI chip or the NCR 53C90 SCSI
chip.
Port A Master Mode. When the chip is configured as a master, it will raise Port A Ack/Rdy when it is ready for data transfer. This signal is expected to be tied to the Request input of a DMA controller which will respond with Port A Req when data is available.
In order to allow the DMA controller to burst, the Port A Ack/Rdy signal will only be negated after every 8 or 16 bytes transferred.
Pert B Parallel Write Mode. In parallel write mode, the chip is configured to be the parity chip for a parallel transfer from Port B to Port A. In this mode, when Port B Select and Port B Request are asserted, data is written into RAM X or RAM Y each time the Port 8 Ack signal is received. For the first SUBSTITUTE SHEET

- 8 8 - ~s "r ~ ~ .~ : : __ block of 128 bytes data is simply copied into the selected RAM. The next 128 bytes driven on Port B will be exclusive-ORed with the first 128 bytes. This procedure will be repeated for all drives such that the parity is accumulated in this chip. The Parity Sync signal should be asserted to the parallel chip together with the last block of 128 bytes. This enables the chip to switch access to the other RAM and start accumulating a new 128 bytes of parity.
Port B Parallel Read Mode - Check Data. This mode is set if all drives are being read and parity is to be checked. In this case the Parity Correct bit in the Data Transfer Configuration Register is not set.
The parity chip will first read 128 bytes on Port A as in a normal read mode and then raise Port B Request.
While it has this signal asserted the chip will monitor the Port B Ack signals and exclusive-or the data on Port B with the data in its selected RAM. The Parity Sync should again be asserted with the last block of 128 bytes. In this mode the chip will not drive the Port B data lines but will check the output of its exclusive-or logic for zero. If any bits are set at this time a parallel parity error will be flagged.
Port B Parallel Read Mode Correct Data. This mode is set by setting the Parity Correct bit in the Data Transfer Configuration Register. In this case the chip will work exactly as in the check mode except that when Port B Output Enable, Port B Select and Parity Sync are true the data is driven onto the Port B data lines and a parallel parity check for zero is not performed.
Bvte Swag. In the normal mode it is expected that Port B bits 00-07 are the first byte, bits 10-17 the second byte, bits 20-27 the third byte, and bits 30-37 the last byte of each word. The order of these bytes SUBSTITUTE SNEET

" ", -a may be changed by writing to the byte swap bits in the configuration register such that the byte address bits are inverted. The way the bytes are written and read also depend on whether the CPU interface is configured S as 16 or 8 bits. The following table shows the byte alignments for differe nt possibiliti es for data the transfer using A Request Acknowledge the Port /

handshake:

CPU Invert Invert Port B Port Port Port B
B B

I/F Addr 1 Addr 00-07 10-17 20-27 30-37 8 False False Port A Port Port Port A
A A

byte 0 byte byte byte 1 8 False True Port A Port Port Port A
A A

byte 1 byte byte byte 2 8 True False Port A Port Port Port A
A A

byte 2 byte byte byte 1 2 8 True True Port A Port Port Port A

byte 3 byte byte byte 0 16 False False Port A uProc Port uProc A

byte 0 byte byte byte 1 2 16 False True uProc Port uProc Port A

byte 0 byte byte byte 1 16 True False Port A uProc Port uProc A

byte 1 byte byte byte 0 30 16 True True uProc Port uProc Port A
A

byte 1 byte byte byte 0 When the Fifo accessed writing the is by reading or Fifo Data Register through the microprocessor port in 35 8 bit mode, the in the same bytes order are as the table above but uProc is d instead the data use of port Port A. In 16 bit mode the pplies.
table above a Odd Leng th Transfers. f the I data transfer is not a multiple of 32 words, 128 bytes, the or 40 microprocessor internal must manipulate registers the of the chip to ensure all data is transferred. Port A Ack and Port B Req are normally not asserted until SUBSTITUTE SHEET

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a '~' .' i~..S'. ;~ ~~

all 32 words of the selected RAM are available. These signals may be forced by writing to the appropriate RAM status bits of the Data Transfer Status Register.
When an odd length transfer has taken place the microprocessor must wait until both ports are quiescent before manipulating any registers. It should then reset both of the Enable Data Transfer bits for Port A and Port B in the Data Transfer Control Register. It must then determine by reading their Address Registers and the RAM Access Control Register whether RAM X or RAM Y holds the odd length data. It should then set the corresponding Address Register to a value of 20 hexadecimal, forcing the RAM
full bit and setting the address to the first word.
Finally the microprocessor should set the Enable Data Transfer bits to allow the chip to complete the transfer.
At this point the Fifo chip will think that there are now a full 128 bytes of data in the RAM and will transfer 128 bytes if allowed to do so. The fact that some of these 128 bytes are not valid must be recognized externally to the FIFO chip.
PROGRAMMABLE REGISTERS
Data Transfer Configuration Register (Read/Write) Register Address 0. This register is cleared by the reset signal.
Bit 0 WD Mode. Set if data transfers are to use the Western Digital WD33C93A
protocol, otherwise the Adaptec 6250 protocol will be used.
Bit 1 Parity Chig. Set if this chip is to accumulate Port B parities.
Bit 2 Parity Correct Mode. Set if the parity chip is to correct parallel parity on Port B. _ SCBSTITUTE SHEEP

r) , ~ ~ %-.
~~ "~, :. ' ~. F 3 Bit 3 CpU InterfacQ 16 bits wide. If set, the microprocessor data bits are combined with the Port A data bits to effectively produce a 16 bit Port. All accesses by the microprocessor as well as all data transferred using the Port A Request and Acknowledge handshake will transfer 16 bits.

Bit 4 Invert Port A byte address 0. Set to invert the least significant bit of Port A byte address.

Bit 5 Invert ~o~t A yte address 1. Set to invert the most significant bit of Port A byte address.

Bit 6 Checksum Carry Wrap. Set to enable the carry out of the 16 bit checksum adder to carry back into the least significant bit of the adder.

Bit 7 Reset. Writing a 1 to this bit will reset the other registers. This bit resets itself after a maximum of 2 clock cycles and will therefore normally be read as a 0. No other register should be written for a minimum of 4 clock cycles after writing to this bit.
Data Transfer Control Register fRead/Write) Register Address 1. This register is cleared by the reset signal or by writing to the reset bit.
Bit 0 Enable Data Transfer on Port A. Set to enable the Port A Req/Ack handshake.
Bit 1 Enable Data Transfer on Port B. Set to enable the Port B Req/Ack handshake.
Bit 2 Port A to Port B. If set, data transfer is from Port A to Port B. If reset, data transfer is from Port B to Port A. In order to avoid any glitches on the request lines, the state of this bit should not be altered at the same time as the enable data transfer bits 0 or 1 above.
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Bit- 3 uProcessor Parity Enable. Set if parity is to be checked on the microprocessor interface. It will only be checked when writing to the Fifo Data Register or reading from the Fifo Data or Checksum Registers, or during a Port A
Request/Acknowledge transfer in 16 bit mode. The chip will, however, always re-generate parity ensuring that correct parity is written to the RAM or read on the microprocessor interface.
Bit 4 Port A Parity Enable. Set if parity is to be checked on Port A. It is checked when accessing the Fifo Data Register in 16 bit mode, or during a Port A
Request/Acknowledge transfer. The chip will, however, always re-generate parity ensuring that correct parity is written to the RAM or read on the Port A
interface.
Bit 5 Port B Paritv Enablg. Set if Port B
data has valid byte parities. If it is not set, byte parity is generated internally to the chip when writing to the RAMs. Byte parity is not checked when writing from Port B, but always checked when reading to Port B.
Bit 6 Checksum Enable. Set to enable writing to the 16 bit checksum register. This register accumulates a 16 bit checksum for all RAM accesses, including accesses to the Fifo Data Register, as well as all writes to the checksum register. This bit must be reset before reading from the Checksum Register.
Bit 7 Port A Master. Set if Port A is to operate in the master mode on Port A
during the data transfer.
Data Transfer Status Register (Read Only) Register Address 2. This register is cleared by the reset signal or by writing to the reset bit.
Bit 0 Data in RAM X or RAM Y. Set if any bits are true in the RAM X, RAM Y, or Port A
byte address registers.
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a i~ ,:
f r.a ,. ~.a - ax -";' n Bit 1 uProc Port Parity Error. Set if the uProc Parity Enable bit is set and a parity error is detected on the microprocessor interface during any RAM

access or write to the Checksum Register in 16 bit mode.

Bit 2 Port A Parity Error. Set if the Port A

Parity Enable bit is set and a parity error is detected on the Port A interface during any RAM access or write to the Checksum Register.

Bit 3 Pn_rt B Parallel Parity. Error Set if the chip is configured as the parity chip, is not in parity correct mode, and a non zero result is detected when the Parity Sync signal is true. It is also set whenever data is read out onto Port B and the data being read back through the bidirectional buffer does not compare.

Bits 4-7 Port B Bytes 0-3 Parity Error. Set whenever the data being read out of the RAMS on the Port B side has bad parity.

Ram Access Control Register (Read/Write) Register Address 3. This register is cleared by the reset signal or by writing to the reset bit. The Enable Data Transfer bits in the Data Transfer Control Register must be reset before attempting to write to this register, else the write will be ignored.
Bit 0 Port A by.~e address 0. This bit is the least significant byte address bit. It is read directly bypassing any inversion done by the invert bit in the Data Transfer Configuration Register.
Bit 1 Port A byte address 1. This bit is the most significant byte address bit. It is read directly bypassing any inversion done by the invert bit in the Data Transfer Configuration Register.
Bit 2 Port A to RAM Y. Set if Port A is accessing RAM Y, and reset if it is accessing RAM X .
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Bit 3 Port B to RAM Y. Set if Port B is accessing RAM Y, and reset if it is accessing RAM X .
Bit 4 Long Burst. If the chip is configured to transfer data on Port A as a master, and this bit is reset, the chip will only negate Port A Ack/Rdy after every 8 bytes, or 4 words in 16 bit mode, have been transferred. If this bit is set, Port A Ack/Rdy will be negated every 16 bytes, or 8 words in 16 bit mode.
Bits 5-7 Not Used.
RAM X Address Reaister (Read/Write) Register Address 4. This register is cleared by the reset signal or by writing to the reset bit. The Enable Data Transfer bits in the Data Transfer Control Register must be reset before attempting to write to this register, else the write will be ignored.
Bits 0-4 RAM X word address Bit 5 RAM X full Bits 6-7 Not Used RAM Y Address Reaister (ReadlWrite) Register Address 5. This register is cleared by the reset signal or by writing to the reset bit. The Enable Data Transfer bits in the Data Transfer Control Register must be reset before attempting to write to this register, else the write will be ignored.
Bits 0-4 RAM Y word address Bit 5 RAM Y full Bits 6-7 Not Used l:ifo Data Register (Read/Writel Register Address 6. The Enable Data Transfer bits in the Data Transfer Control Register must be reset before attempting to write to this register, else the write will be ignored. The Port A to Port B bit in S~~STITUT~ SHEET

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the Data Transfer Control register must also be set before writing this register. If it is not, the RAM
controls will be incremented but no data will be written to the RAM. For consistency, the Port A to PortB should be reset prior to reading this register.
Bits 0-7 are Fifo Data. The microprocessor may access the FIFO by reading or writing this register.
The RAM control registers are updated as if the access was using Port A. If the chip is configured with a 16 bit CPU Interface the most significant byte will use the Port A 0-7 data lines, and each Port A access will increment the Port A byte address by 2.
Port A Checksum Register (Read/Write) Register Address 7. This register is cleared by the reset signal or by writing to the reset bit.
Bits 0-7 are Checksum Data. The chip will accumulate a 16 bit checksum for all Port A accesses.
If the chip is configured with a 16 bit CPU interface, the most significant byte is read on the Port A 0-7 data lines. If data is written directly to this register it is added to the current contents rather than overwriting them. It is important to note that the Checksum Enable bit in the Data Transfer Control Register must be set to write this register and reset to read it.
PROGRAMMING THE FIFO CHIP
In general the fifo chip is programmed by writing to the data transfer configuration and control registers to enable a data transfer, and by reading the data transfer status register at the end of the transfer to check the completion status. Usually the data transfer itself will take place with both the Port A and the Port B handshakes enabled, and in this case the data transfer itself should be done without SUBSTtTUI'E SHEET

. ; '#

any other microprocessor interaction. In some applications, however, the Port A handshake may not be enabled, and it will be necessary for the microprocessor to fill or empty the fifo by repeatedly writing or reading the Fifo Data Register.
Since the fifo chip has no knowledge of any byte counts, there is no way of telling when any data transfer is complete by reading any register within this chip itself. Determination of whether the data transfer has been completed must therefore be done by some other circuitry outside this chip.
The following C language routines illustrate how the parity FIFO chip may be programmed. The routines assume that both Port A and the microprocessor port are connected to the system microprocessor, and return a size code of 16 bits, but that the hardware addresses the Fifo chip as long 32 bit registers.
struct FIFO regs {
unsigned char config,al,a2,a3 ;
unsigned char control,bl,b2,b3;
unsigned char status,cl,c2,c3;
unsigned char ram access control,dl,d2,d3;
unsigned char ram X addr,el,e2,e3;
unsigned char ram Y_addr,fl ,f2,f3;
2 5 unsigned long data;
unsigned int checksum,hl;
#define FIF01 ((struct FIFO-regs*) FIFO-BASE ADDRESS) #define FIFO RESET 0x80 #define FIFO 16 BITS 0x08 #define FIFO CARRY WRAP 0x40 #define FIFO PORT A ENABLE 0x01 #define FIFO PORT B ENABLE 0x02 3 5 #define FIFO PORT ENABLES 0x03 #define FIFO PORT A TO
B 0x04 #define FIFO _ CHECKSUM ENABLE
0x40 #define FIFO DATA IN RAM 0x01 #define FIFO FORCE RAM FULL 0x20 #define PORT A TO PORT B(fifo) ((fifo-> control ) & 0x04) #define PORT A BYTE ADDRESS(fifo) ((fifo->ram access control) &
0x03) #define PORT A TO RAM Y(fifo) ((fifo->ram access control ) & 0x04) #define PORT B TO RAM Y(fifo) ((fifo-> ram access control ) & 0x08) SUBSTITUTE Si~EET

~' ~ 91/03788 PCT/US90/04711 f.;s '' ~ g: ~ i; ~~ ,l'~ ~ ;i; ~i 'tJ .J .J1 .i». ,.

/***********************************************************
The following routine initiates a Fifo data transfer using two values passed to it.
config data This is the data to be written to the configuration register.
control_data This is the data to be written to the Data Transfer Control Register. If the data transfer is to take place automatically using both the Port Aand Port B
handshakes, both data transfer enables bits should be set in this parameter.
x**********************************************************/
FIFO initiate data transfer(config data, control data) unsigned char config data, control data;
FIF01->config = config data ~ FIFO_RESET; /* Set Configuration value & Reset */
FIF01->control = control data & (--FIFO PORT ENABLES); /* Set 2 0 everything but enables *%
FIF01->control = control data ; /* Set data transfer enables */
}
2 5 /***********************************************************
The following routine forces the transfer of any odd bytes that have been left in the Fifo at the end of a data transfer.
It first disables both ports, then forces the Ram Full bits, and then re-enables the appropriate Port.
30 ***********************************************************/
FIFO force odd length transferQ
FIF01->control &_ FIFO PORT ENABLES; /* Disable Ports A & B
3 5 *%
if (PORT A TO PORT B(FIF01)) if (P~R'~ A TO RAM Y(FIF01 )) ~{
FIF01-> ram_Y_addr = FIFO_FORCE_RAM_FULL; /*
Set RAM Y full */
40 }
else FIF01->ram X addr = FIFO FORCE_RAM FULL ; /* Set RAM X full *~
FIFO1->control ~ = FIFO_PORT B_ENABLE ; /*
Re-Enable Port B */
45 }
else ~( if (PORT B TO RAM Y(FIF01)) FIF61->ram Y addr = FIFO FORCE RAM FULL ; /*
Set RAM Y full *%
50 }
else FIF01->ram X addr = FIFO_FORCE-RAM_FULL ; /* Set RAM X full */
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., > ~, ; i ;.:a ~,.. ',i ~r~, a . ~,,~
_98_ FIFO1->control ~ = FIFO_PORT A-ENABLE ; /*
Re-Enable Port A */
}
}
/***********************************************************
The following routine returns how many odd bytes have been left in the Fifo at the end of a data transfer.
***********************************************************/
i0 int FIFO count odd bytesQ
f int number odd bytes;
number odd bytes=0;
if (FIF01->status & FIFO DATA IN RAM) {
if (PORT A TO PART B~FIF01)) {
number odd bytes =
(PORT A BYTE ADDRES~(FIF~1)) ;
if (PORT A TO RAM Y(FIF01)) number odd bytes +_ (FIF01->ram Y addr) 4 ;
else number odd bytes + _ (FIF01->ram X addr) * 4 ;
else {
if (PORT B TO RAM Y(FIF01)) number odd bytes = (FIF01->ram Y addr) * 4 ;
else number odd bytes = (FIF01->ram X addr) * 4 ;
}
return (number odd bytes);
}
/***********************************************************
The following routine tests the microprocessor intertace of the chip. It first writes and reads the first 6 registers. It then writes 1 s, Os, and 3 5 an address pattern to the RAM, reading the data back and checking it.
The test returns a bit significant error code where each bit represents the address of the registers that failed.
4 0 Bit 0 = config register failed Bit 1 = control register failed Bit 2 = status register failed Bit 3 = ram access control register failed Bit 4 = ram X address register failed 4 5 Bit 5 = ram Y address register failed Bit 6 = data register failed Bit 7 = checksum register failed ***********************************************************/
50 #define RAM_DEPTH 64 /* number of long words in Fifo Ram */
reg expected data[6J = { Ox7F, OxFF, 0x00, 0x1 F, Ox3F, Ox3F };
>.
~UBSTITU'fE SN~ET

_99_ char FIFO uprocessor interface testQ
unsigned long test data;
char *register adds;
s int i;
char j,error;
FIF01->config = FIFO_RESET; /* reset the chip */
error = 0;
register addr =(char *) FIF01;
1o j=1;
/* first test registers 0 thru 5 */
for (i=0; i<6; i++) {
15 *register addr = OxFF; /* write test data */
if (*register addr ! = reg expected data[i]) error ~ = j;
*register aadr = 0; /* write Os to register */
if (*register addr) error ~ = j;
*register addr = OxFF; /* write test data again */
2o if (*register addr != reg expected_data[iJ) error ~ = j;
FIF01->config = FIFO RESET; /* reset the chip */
if (*register addr) errors = j; /* register should be 0 */
register addr+ +; /* go to next register */
1 «=1;
/* now test Ram data & checksum registers test 1 s throughout Ram & then test Os */
3 o for (test data = -1; test_data ! = 1; test_data+ + ) { /* test for 1 s & Os */
FIF01->config = FIFO RESET ~ FIFO 16 BITS ;
FIF01->control = FIFO PORT_A_TO_~;
for (i=O;i<RAM_DEPTH;i++) /* write data to RAM
3 5 */
FI FO 1- > data = test_data;
FIF01->control = 0;
for (i=O;i < RAM DEPTH;i+ +) if (FIF01- > data ! = test data) error ~ = j; /* read &
check data */
if (FIF01->checksum) error ~ = 0x80; /* checksum should = 0 */
4 5 /* now test Ram data with address pattern uses a different pattern for every byte */
test data=0x00010203; /* address pattern start */
FIF~1->config = FIFO RESET ~ FIFO_16 BITS ~
FIFO CARRY WRAP;
f=IF01->control = FIFO PORT A TO B ~
FIFO CHECKSUM ENABLE;
for (i=O;i<RAM DEPTH;i++) {
FIF01->data = test data; /* write address pattern */
SUBSTITUTE SNEET

WO 91/03'788 PCT/US90/04711 test data + = 0x04040404;
test data=0x00010203; /* address pattern start */
FIF~1->control = FIFO CHECKSUM_ENABLE;
for (i=O;i<RAM DEPTH;i++) {
if (FIF01->status != FIFO_DATA_IN RAM) error ~ = 0x04; T* should be data in ram */
if (FIF01->data != test_data) error ~ = j; /* read & check address pattern */
1 o test data + = 0x04040404;
if (FIF01- > checksum 1= 0x0102) error ~ = 0x80; /* test checksum of address pattern */
FIF01->config = FIFO RESET ~ FIFO_16 BITS ; /* inhibit carry wrap *~
FIF01->checksum = OxFEFE; /* writing adds to checksum */
if (FIF01->checksum) error ~ =0x80; /* checksum should be 0 */
if (FIF01->status) error ~ = 0x04; /* status should be 0 */
2 0 return (error);
S~IBSTITU i r SHcET

Claims (142)

Claims:
1. Network server apparatus for use with a data network and a mass storage device, comprising:
an interface processor unit coupleable to said network and to said mass storage device;
a host processor unit capable of running remote procedures defined by a client node on said network;
means in said interface processor unit for satisfying requests from said network to store data from said network on said mass storage device;
means in said interface processor unit for satisfying requests from said network to retrieve data from said mass storage device to said network; and means in said interface processor unit for transmitting predefined categories of messages from said network to said host processor unit for processing in said host processor unit, said transmitted messages including all requests by a network client to run client-defined procedures on said network server apparatus.
2. Apparatus according to claim 1, wherein said interface processor unit comprises:
a network control unit coupleable to said network;
a data control unit coupleable to said mass storage device;
a buffer memory;
means in said network control unit for transmitting to said data control unit requests from said network to store specified storage data from said network on said mass storage device;
means in said network control unit for transmitting said specified storage data from said network to said buffer memory and from said buffer memory to said data control unit;
means in said network control unit for transmitting to said data control unit requests from said network to retrieve specified retrieval data from said mass storage device to said network;

means in said network control unit for transmitting said specified retrieval data from said data control unit to said buffer memory and from said buffer memory to said network; and means in said network control unit for transmitting said predefined categories of messages from said network to said host processing unit for processing by said host processing unit.
3. Apparatus according to claim 2, wherein said data control unit comprises:
a storage processor unit coupleable to said mass storage device;
a file processor unit;
means on said file processor unit for translating said file system level storage requests from said network into requests to store data at specified physical storage locations in said mass storage device;
means on said file processor unit for instructing said storage processor unit to write data from said buffer memory into said specified physical storage locations in said mass storage device;
means on said file processor unit for translating file system level retrieval requests from said network into requests to retrieve data from specified physical retrieval locations in said mass storage device;
means on said file processor unit for instructing said storage processor unit to retrieve data from said specified physical retrieval locations in said mass storage device to said buffer memory if said data from said specified physical locations is not already in said buffer memory; and means in said storage processor unit for transmitting data between said buffer memory and said mass storage device.
4. Network server apparatus for use with a data network and a mass storage device, comprising:
a network control unit coupleable to said network;
a data control unit coupleable to said mass storage device;

a buffer memory;
means for transmitting from said network control unit to said data control unit requests from said network to store specified storage data from said network on said mass storage device;
means for transmitting said specified storage data by DMA from said network control unit to said buffer memory and by DMA from said buffer memory to said data control unit;
means for transmitting from said network control unit to said data control unit requests from said network to retrieve specified retrieval data from said mass storage device to said network; and means for transmitting said specified retrieval data by DMA from said data control unit to said buffer memory and by DMA from said buffer memory to said network control unit.
5. Apparatus according to claim 1, for use further with a buffer memory, and wherein said requests from said network to store and retrieve data include file system level storage and retrieval requests respectively, and wherein said interface processor unit comprises:
a storage processor unit coupleable to said mass storage device;
a file processor unit;
means on said file processor unit for translating said file system level storage requests into requests to store data at specified physical storage locations in said mass storage device;
means on said file processor unit for instructing said storage processor unit to write data from said buffer memory into said specified physical storage locations in said mass storage device;
means on said file-processor unit for translating said file system level retrieval requests into requests to retrieve data from specified physical retrieval locations in said mass storage device;
means on said file processor unit for instructing said storage processor unit to retrieve data from said specified physical retrieval locations in said mass storage device to said buffer memory if said data from said specified physical locations is not already in said buffer memory; and means in said storage processor unit for transmitting data between said buffer memory and said mass storage device.
6. A data control unit for use with a data network and a mass storage device, and in response to file system level storage and retrieval requests from said data network, comprising:
a data bus different from said network;
a buffer memory bank coupled to said bus;
storage processor apparatus coupled to said bus and coupleable to said mass storage device;
file processor apparatus coupled to said bus, said file processor apparatus including a local memory bank first means on said file processor apparatus for translating said file system level storage requests into requests to store data at specified physical storage locations in said mass storage device; and second means on said file processor apparatus for translating said file system level retrieval requests into requests to retrieve data from specified physical retrieval locations in said mass storage device, said first and second means for translating collectively including means for caching file control information through said local memory bank in said file processor unit, said data control unit further comprising means for caching the file data, to be stored or retrieved according to said storage and retrieval requests, through said buffer memory bank.
7. A network node for use with a data network and a mass storage device, comprising:
a system buffer memory;
a host processor unit having direct memory access to said system buffer memory;

a network control unit coupleable to said network and having direct memory access to said system buffer memory;
a data control unit coupleable to said mass storage device and having direct memory access to said system buffer memory;
first means for satisfying requests from said network to store data from said network on said mass storage device;
second means for satisfying requests from said network to retrieve data from said mass storage device to said network; and third means for transmitting predefined categories of messages from said network to said host processor unit for processing in said host processor unit, said first, second and third means collectively including means for transmitting from said network control unit to said system memory bank by direct memory access file data from said network for storage on said mass storage device, means for transmitting from said system memory bank to said data control unit by direct memory access said file data from said network for storage on said mass storage device, means for transmitting from said data control unit to said system memory bank by direct memory access file data for retrieval from said mass storage device to said network, and means for transmitting from said system memory bank to said network control unit said file data for retrieval from said mass storage device to said network;
at least said network control unit including a microprocessor and local instruction storage means distinct from said system buffer memory, all instructions for said microprocessor residing in said local instruction storage means.
8. A network file server for use with a data network and a mass storage device, comprising:
a host processor unit running a Unix operating system;

an interface processor unit coupleable to said network and to said mass storage device, said interface processor unit including means for decoding all NFS
requests from said network, means for performing all procedures for satisfying said NFS requests, means for encoding any NFS reply messages for return transmission on said network, and means for transmitting predefined non-NFS categories of messages from said network to said host processor unit for processing in said host processor unit.
9. Network server apparatus for use with a data network, comprising:
a network controller coupleable to said network to receive incoming information packets over said network, said incoming information packets including certain packets which contain part or all of a request to said server apparatus, said request being in either a first or a second class of requests to said server apparatus;
a first additional processor;
an interchange bus different from said network and coupled between said network controller and said first additional processor;
means in said network controller for detecting and satisfying requests in said first class of requests contained in said certain incoming information packets, said network controller lacking means in said network controller for satisfying requests in said second class of requests;
means in said network controller for detecting and assembling into assembled requests, requests in said second class of requests contained in said certain incoming information packets;
means for delivering said assembled requests from said network controller to said first additional processor over said interchange bus; and means in said first additional processor for further processing said assembled requests in said second class of requests.
10. Apparatus according to claim 9, wherein said packets each include a network node destination address, and wherein said means in said network controller for detecting and assembling into assembled requests, assembles said assembled requests in a format which omits said network node destination addresses.
11. Apparatus according to claim 9, wherein said means in said network controller for detecting and satisfying requests in said first class of requests, assembles said requests in said first class of requests into assembled requests before satisfying said requests in said first class of requests.
12. Apparatus according to claim 9, wherein said packets each include a network node destination address, wherein said means in said network controller for detecting and assembling into assembled requests, assembles said assembled requests in a format which omits said network node destination addresses, and wherein said means in said network controller for detecting and satisfying requests in said first class of requests, assembles said requests in said first class of requests, in a format which omits said network node destination addresses, before satisfying said requests in said first class of requests.
13. Apparatus according to claim 9, wherein said means in said network controller for detecting and satisfying requests in said first class includes means for preparing an outgoing message in response to one of said first class of requests, means for packaging said outgoing message in outgoing information packets suitable for transmission over said network, and means for transmitting said outgoing information packets over said network.
14. Apparatus according to claim 9, further comprising a buffer memory coupled to said interchange bus, and wherein said means for delivering said assembled requests comprises:
means for transferring the contents of said assembled requests over said interchange bus into said buffer memory; and means for notifying said first additional processor of the presence of said contents in said buffer memory.
15. Apparatus according to claim 9, wherein said means in said first additional processor for further processing said assembled requests includes means for preparing an outgoing message in response to one of said second class of requests, said apparatus further comprising means for delivering said outgoing message from said first additional processor to said network controller over said interchange bus, said network controller further comprising means in said network controller for packaging said outgoing message in outgoing information packets suitable for transmission over said network, and means in said network controller for transmitting said outgoing information packages over said network.
16. Apparatus according to claim 9, wherein said first class of requests comprises requests for an address of said server apparatus, and wherein said means in said network controller for detecting and satisfying requests in said first class comprises means for preparing a response packet to such an address request and means for transmitting said response packet over said network.
17. Apparatus according to claim 9, for use further with a second data network, said network controller being coupleable further to said second network, wherein said first class of requests comprises requests to route a message to a destination reachable over said second network, and wherein said means in said network controller for detecting and satisfying requests in said first class comprises means for detecting that one of said certain packets comprises a request to route a message contained in said one of said certain packets to a destination reachable over said second network, and means for transmitting said message over said second network.
18. Apparatus according to claim 17, for use further with a third data network, said network controller further comprising means in said network controller for detecting particular requests in said incoming information packets to route a message contained in said particular requests, to a destination reachable over said third network, said apparatus further comprising:

a second network controller coupled to said interchange bus and couplable to said third data network;

means for delivering said message contained in said particular requests to said second network controller over said interchange bus; and means in said second network controller for transmitting said message contained in said particular requests over said third network.
19. Apparatus according to claim 9, for use further with a third data network, said network controller further comprising means in said network controller for detecting particular requests in said incoming information packets to route a message contained in said particular requests, to a destination reachable over said third network, said apparatus further comprising:

a second network controller coupled to said interchange bus and couplable to said third data network;

means for delivering said message contained in said particular requests to said second network controller over said interchange bus; and means in said second network controller for transmitting said message contained in said particular requests over said third network.
20. Apparatus according to claim 9, for use further with a mass storage device, wherein said first additional processor comprises a data control unit couplable to said mass storage device, wherein said second class of requests comprises remote calls to procedures for managing a file system in said mass storage device, and wherein said means in said first additional processor for further processing said assembled requests in said second class of requests comprises means for executing file system procedures on said mass storage device in response to said assembled requests.
21. Apparatus according to claim 20, wherein said file system procedures include a read procedure for reading data from said mass storage device, said means in said first additional processor for further processing said assembled requests including means for reading data from a specified location in said mass storage device in response to a remote call to said read procedure, said apparatus further including means for delivering said data to said network controller, said network controller further comprising means on said network controller for packaging said data in outgoing information packets suitable for transmission over said network, and means for transmitting said outgoing information packets over said network.
22. Apparatus according to claim 21, wherein said means for delivering comprises:

a system buffer memory coupled to said interchange bus;

means in said data control unit for transferring said data over said interchange bus into said buffer memory; and means in said network controller for transferring said data over said interchange bus from said system buffer memory to said network controller.
23. Apparatus according to claim 20, wherein said file system procedures include a read procedure for reading a specified number of bytes of data from said mass storage device beginning at an address specified in logical terms including a file system ID and a file ID, said means for executing file system procedures comprising:

means for converting the logical address specified in a remote call to said read procedure to a physical address; and means for reading data from said physical address in said mass storage device.
24. Apparatus according to claim 23, wherein said mass storage device comprises a disk drive having a numbered tracks and sectors, wherein said logical address specifies said file system ID, said file ID, and a byte offset, and wherein said physical address specifies a corresponding track and sector number.
25. Apparatus according to claim 20, wherein said file system procedures include a read procedure for reading a specified number of bytes of data from said mass storage device beginning at an address specified in logical terms including a file system ID and a file ID, said data control unit comprising a file processor coupled to said interchange bus and a storage processor coupled to said interchange bus and couplable to said mass storage device, said file processor comprising means for converting the logical address specified in a remote call to said read procedure to a physical address, said apparatus further comprising means for delivering said physical address to said storage processor, said storage processor comprising means for reading data from said physical address in said mass storage device and for transferring said data over said interchange bus into said buffer memory; and means in said network controller for transferring said data over said interchange bus from said system buffer memory to said network controller.
26. Apparatus according to claim 20, wherein said file system procedures include a write procedure for writing data contained in an assembled request, to said mass storage device, said means in said first additional processor for further processing said assembled requests including means for writing said data to a specified location in said mass storage device in response to a remote call to said read procedure.
27. Apparatus according to claim 9, wherein said first additional processor comprises a host computer coupled to said interchange bus, wherein said second class of requests comprises remote calls to procedures other than procedures for managing a file system, and wherein said means in said first additional processor for further processing said assembled requests in said second class of requests comprises means for executing remote procedure calls in response to said assembled requests.
28. Apparatus according to claim 27, for use further with a mass storage device and a data control unit couplable to said mass storage device and coupled to said interchange bus, wherein said network controller further comprises means in said network controller for detecting and assembling remote calls, received over said network, to procedures for managing a file system in said mass storage device, and wherein said data control unit comprises means for executing file system procedures on said mass storage device in response to said remote calls to procedures for managing a file system in said mass storage device.
29. Apparatus according to claim 27, further comprising means for delivering all of said incoming information packets not recognized by said network controller to said host computer over said interchange bus.
30. Apparatus according to claim 9, wherein said network controller comprises:

a microprocessor;

a local instruction memory containing local instruction code;

a local bus coupled between said microprocessor and said local instruction memory;

bus interface means for interfacing said microprocessor with said interchange bus at times determined by said microprocessor in response to said local instruction code; and network interface means for interfacing said microprocessor with said data network, said local instruction memory including all instruction code necessary for said microprocessor to perform said function of detecting and satisfying requests in said first class of requests, and all instruction code necessary for said microprocessor to perform said function of detecting and assembling into assembled requests, requests in said second class of requests.
31. Network server apparatus for use with a data network, comprising:
a network controller coupleable to said network to receive incoming information packets over said network, said incoming information packets including certain packets which contain part or all of a message to said server apparatus, said message being in either a first or a second class of messages to said server apparatus, said messages in said first class or messages including certain messages containing requests;

a host computer;

an interchange bus different from said network and coupled between said network controller and said host computer;

means in said network controller for detecting and satisfying said requests in said first class of messages;

means for delivering messages in said second class of messages from said network controller to said host computer over said interchange bus; and means in said host computer for further processing said messages in said second class of messages.
32. Apparatus according to claim 31, wherein said packets each include a network node destination address, and wherein said means for delivering messages in said second class of messages comprises means in said network controller for detecting said messages in said second class of messages and assembling them into assembled messages in a format which omits said network node destination addresses.
33. Apparatus according to claim 31, wherein said means in said network controller for detecting and satisfying requests in said first class includes means for preparing an outgoing message in response to one of said requests in said first class of messages, means for packaging said outgoing message in outgoing information packets suitable for transmission over said network, and means for transmitting said outgoing information packets over said network.
34. Apparatus according to claim 31, for use further with a second data network, said network controller being coupleable further to said second network, wherein said first class of messages comprises messages to be routed to a destination reachable over said second network, and wherein said means in said network controller for detecting and satisfying requests in said first class comprises means for detecting that one of said certain packets includes a request to route a message contained in said one of said certain packets to a destination reachable over said second network, and means for transmitting said message over said second network.
35. Apparatus according to claim 31, for use further with a third data network, said network controller further comprising means in said network controller for detecting particular messages in said incoming information packets to be routed to a destination reachable over said third network, said apparatus further comprising:

a second network controller coupled to said interchange bus and couplable to said third data network;

means for delivering said particular messages to said second network controller over said interchange bus, substantially without involving said host computer; and means in said second network controller for transmitting said message contained in said particular requests over said third network, substantially without involving said host computer.
36. Apparatus according to claim 31, for use further with a mass storage device, further comprising a data control unit coupleable to said mass storage device, said network controller further comprising means in said network controller for detecting ones of said incoming information packets containing remote calls to procedures for managing a file system in said mass storage device, and means in said network controller for assembling said remote calls from said incoming packets into assembled calls, substantially without involving said host computer, said apparatus further comprising means for delivering said assembled file system calls to said data control unit over said interchange bus substantially without involving said host computer, and said data control unit comprising means in said data control unit for executing file system procedures on said mass storage device in response to said assembled file system calls, substantially without involving said host computer.
37. Apparatus according to claim 31, further comprising means for delivering all of said incoming information packets not recognized by said network controller to said host computer over said interchange bus.
38. Apparatus according to claim 31, wherein said network controller comprises:

a microprocessor;
a local instruction memory containing local instruction code;
a local bus coupled between said microprocessor and said local instruction memory;

bus interface means for interfacing said microprocessor with said interchange bus at times determined by said microprocessor in response to said local instruction code; and network interface means for interfacing said microprocessor with said data network, said local instruction memory including all instruction code necessary for said microprocessor to perform said function of detecting and satisfying requests in said first class of requests.
39. File server apparatus for use with a mass storage device, comprising:
a requesting unit capable of issuing calls to file system procedures in a device-independent form;

a file controller including means for converting said file system procedure calls from said device-independent form to a device-specific form and means for issuing device-specific commands in response to at least a subset of said procedure calls, said file controller operating in parallel with said requesting unit; and a storage processor including means for executing said device-specific commands on said mass storage device, said storage processor operating in parallel with said requesting unit and said file controller.
40. Apparatus according to claim 39, further comprising:
an interchange bus;

first delivery means for delivering said file system procedure calls from said requesting unit to said file controller over said interchange bus; and second delivery means for delivering said device-specific commands from said file controller to said storage processor over said interchange bus.
41. Apparatus according to claim 39, further comprising:
an interchange bus coupled to said requesting unit and to said file controller;
first memory means in said requesting unit and addressable over said interchange bus;

second memory means in said file controller;
means in said requesting unit for preparing in said first memory means one of said calls to file system procedures;

means for notifying said file controller of the availability of said one of said calls in said first memory means; and means in said file controller for controlling an access to said first memory means for reading said one of said calls over said interchange bus into said second memory means in response to said notification.
42. Apparatus according to claim 41, wherein said means for notifying said file controller comprises:
a command FIFO in said file controller addressable over said interchange bus;
and means in said requesting unit for controlling an access to said FIFO for writing a descriptor into said FIFO over said interchange bus, said descriptor describing an address in said first memory means of said one of said calls and an indication that said address points to a message being sent.
43. Apparatus according to claim 41, further comprising:
means in said file controller for controlling an access to said first memory means over said interchange bus for modifying said one of said calls in said first memory means to prepare a reply to said one of said calls; and means for notifying said requesting unit of the availability of said reply in said first memory.
44. Apparatus according to claim 41, further comprising:
a command FIFO in said requesting processor addressable over said interchange bus; and means in said file controller for controlling an access to said FIFO for writing a descriptor into said FIFO over said interchange bus, said descriptor describing said address in said first memory and an indication that said address points to a reply to said one of said calls.
45. Apparatus according to claim 39, further comprising:
an interchange bus coupled to said file controller and to said storage processor;

second memory means in said file controller and addressable over said interchange bus;
means in said file controller for preparing one of said device-specific commands in said second memory means;
means for notifying said storage processor of the availability of said one of said commands in said second memory means; and means in said storage processor for controlling an access to said second memory means for reading said one of said commands over said interchange bus in response to said notification.
46. Apparatus according to claim 45, wherein said means for notifying said storage processor comprises:
a command FIFO in said storage processor addressable over said interchange bus; and means in said file controller for controlling an access to said FIFO for writing a descriptor into said FIFO over said interchange bus, said descriptor describing an address in said second memory of said one of said calls and an indication that said address points to a message being sent.
47. Apparatus according to claim 39, wherein said means for converting said file system procedure calls comprises:
a file control cache in said file controller, storing device-independent to device-specific conversion information; and means for performing said conversions in accordance with said conversion information in said file control cache.
48. Apparatus according to claim 39, wherein said mass storage device includes a disk drive having numbered sectors, wherein one of said file system procedure calls is a read data procedure call, said apparatus further comprising an interchange bus and a system buffer memory addressable over said interchange bus, said means for converting said file system procedure calls including means for issuing a read sectors command in response to one of said read data procedure calls, said read sectors command specifying a starting sector on said disk drive, a count indicating the amount of data to read, and a pointer to a buffer in said system buffer memory, and said means for executing device-specific commands including means for reading data from said disk drive beginning at said starting sector and continuing for the number of sectors indicated by said count, and controlling an access to said system buffer memory for writing said data over said interchange bus to said buffer in said system buffer memory.
49. Apparatus according to claim 48, wherein said file controller further includes means for determining whether the data specified in said one of said read data procedure calls is already present in said system buffer memory, said means for converting issuing said read sectors command only if said data is not already present in said system buffer memory.
50. Apparatus according to claim 48, further comprising:
means in said storage processor for controlling a notification of said file controller when said read sectors command has been executed;
means in said file controller, responsive to said notification from said storage processor, for controlling a notification of said requesting unit that said read data procedure call has been executed; and means in said requesting unit, responsive to said notification from said file controller, for controlling an access to said system buffer memory for reading said data over said interchange bus from said buffer in said system buffer memory to said requesting unit.
51. Apparatus according to claim 39, wherein said mass storage device includes a disk drive having numbered sectors, wherein one of said file system procedure calls is a write data procedure call, said apparatus further comprising an interchange bus and a system buffer memory addressable over said interchange bus, said means for converting said file system procedure calls including means for issuing a write sectors command in response to one of said write data procedure calls, said write data procedure call including a pointer to a buffer in said system buffer memory containing data to be written, and said write sectors command including a starting sensor on said disk drive, a count indicating the amount of data to write, and said pointer to said buffer in said buffer memory, and said means for executing device-specific commands including means for controlling an access to said buffer memory for reading said data over said interchange bus from said buffer in said system buffer memory, and writing said data to said disk drive beginning at said starting sector and continuing for the number of sectors indicated by said count.
52. Apparatus according to claim 51, further comprising:
means in said requesting unit for controlling an access to said system buffer memory for writing said data over said interchange bus to said buffer in said system buffer memory; and means in said requesting unit for issuing said one of said write data procedure calls when said data has been written to said buffer in said system buffer memory.
53. Apparatus according to claim 52, further comprising:
means in said requesting unit for issuing a buffer allocation request; and means in said file controller for allocating said buffer in said system buffer memory in response to said buffer allocation request, and for providing said pointer, before said data is written to said buffer in said system buffer memory.
54. Network controller apparatus for use with a first data network carrying signals representing information packets encoded according to a first physical layer protocol, comprising:

a first network interface unit, a first packet bus and first packet memory addressable by said first network interface unit over said first packet bus, said first network interface unit including means for receiving signals over said first network representing incoming information packets, extracting said incoming information packets and writing said incoming information packets into said first packet memory over said first packet bus;
a first packet bus port;
first packet DMA means for reading data over said first packet bus from said first packet memory to said first packet bus port; and a local processor including means for accessing said incoming information packets in said first packet memory and, in response to the contents of said incoming information packets, controlling said first packet DMA means to read selected data over said first packet bus from said first packet memory to said first packet bus port, said local processor including a CPU, a CPU bus and CPU memory containing CPU
instructions, said local processor operating in response to said CPU
instructions, said CPU instructions being received by said CPU over said CPU bus independently of any of said writing by said first network interface unit of incoming information packets into said first packet memory over said first packet bus and independently of any of said reading by said first packet DMA means of data over said first packet bus from said first packet memory to said first packet bus port.
55. Apparatus according to claim 54, wherein said first network interface unit further includes means for reading outgoing information packets from said first packet memory over said first packet bus, encoding said outgoing information packets according to said first physical layer protocol, and transmitting signals over said first network representing said outgoing information packets, said local processor further including means for preparing said outgoing information packets in said first packet memory, and for controlling said first network interface unit to read, encode and transmit said outgoing information packets, said receipt of CPU instructions by said CPU over said CPU bus being independent further of any of said reading by said first network interface unit of outgoing information packets from said first packet memory over said first packet bus.
56. Apparatus according to claim 54, further comprising a first FIFO
having first and second ports, said first port of said first FIFO being said first packet bus port.
57. Apparatus according to claim 56, for use further with an interchange bus, further comprising interchange bus DMA means for reading data from said second port of said first FIFO onto said interchange bus, said local processor further including means for controlling said interchange bus DMA means to read said data from said second port of said first FIFO onto said interchange bus.
58. Apparatus according to claim 54, for use further with a second data network carrying signals representing information packets encoded according to a second physical layer protocol, further comprising:
a second network interface unit, a second packet bus and second packet memory addressable by said second network interface unit over said second packet bus, said second network interface unit including means for reading outgoing information packets from said second packet memory over said second packet bus, encoding said outgoing information packets according to said second physical layer protocol, and transmitting signals over said second network representing said outgoing information packets;
a second packet bus port; and second packet DMA means for reading data over said second packet bus from said second packet bus port to said second packet memory, said local processor further including means for controlling said second packet DMA means to read data over said second packet bus from said second packet bus port to said second packet memory, and for controlling said second network interface unit to read, encode and transmit outgoing information packets from said data in said second packet memory, said receipt of CPU instructions by said CPU over said CPU bus being independent further of any of said reading by said second packet DMA means of data over said second packet bus from said second packet bus port to said second packet memory, and independent further of any of said reading by said second network interface unit of outgoing information packets from said second packet memory over said second packet bus, and all of said accesses to said first packet memory over said first packet bus being independent of said accesses to said second packet memory over said second packet bus.
59. Apparatus according to claim 58, wherein said second physical layer protocol is the same as said first physical layer protocol.
60. Apparatus according to claim 58, further comprising means, responsive to signals from said processor, for coupling data from said first packet bus port to said second packet bus port.
61. Apparatus according to claim 61, further comprising:
first and second FIFOs, each having first and second ports, said fist port of said first FIFO being said first packet bus port and said first port of said second FIFO
being said second packet bus port;
an interchange bus; and interchange bus DMA means for transferring data between said interchange bus and either said second port of said first FIFO or said second port of said second FIFO, selectably in response to DMA control signals from said local processor.
62. Apparatus according to claim 58, wherein said interchange bus DMA
means comprises:

a transfer bus coupled to said second port of said first FIFO and to said second port of said second FIFO;
coupling means coupled between said transfer bus and said interchange bus;
and a controller coupled to receive said DMA control signals from said processor and coupled to said first and second FIFOs and to said coupling means to control data transfers over said transfer bus.
63. Storage processing apparatus for use with a plurality of storage devices on a respective plurality of channel buses, and an interchange bus, said interchange bus capable of transferring data at a higher rate than any of said channel buses, comprising:
data transfer means coupled to each of said channel buses and to said interchange bus, for transferring data in parallel between said data transfer means and each of said channel buses at the data transfer rates of each of said channel buses, respectively, and for transferring data between said data transfer means and said interchange bus at a data transfer rate higher than said data transfer rates of any of said channel buses; and a local processor including transfer control means for controlling said data transfer means to transfer data between said data transfer means and specified ones of said channel buses and for controlling said data transfer means to transfer data between said data transfer means and said interchange bus, said local processor including a CPU, a CPU bus and CPU memory containing CPU instructions, said local processor operating in response to said CPU
instructions, said CPU instructions being received by said CPU over said CPU
bus independently of any of said data transfers between said channel buses and said data transfer means and independently of any of said data transfers between said data transfer means and said interchange bus.
64. Apparatus according to claim 63, wherein the highest data transfer rate of said interchange bus is substantially equal to the sum of the highest data transfer rates of all of said channel buses.
65. Apparatus according to claim 63, wherein said data transfer means comprises:
a FIFO corresponding to each of said channel buses, each of said FIFOs having a first port and a second port;
a channel adapter coupled between the first port of each of said FIFOs and a respective one of said channels; and DMA means coupled to the second port of each of said FIFOs and to said interchange bus, for transferring data between said interchange bus and one of said FIFOs as specified by said local processor, said transfer control means in said local processor comprising means for controlling each of said channel adapters separately to transfer data between the channel bus coupled to said channel adapter and the FIFO coupled to said channel adapter, and for controlling said DMA controller to transfer data between separately specified ones of said FIFOs and said interchange bus, said DMA means performing said transfers sequentially.
66. Apparatus according to claim 65, wherein said DMA means comprises a command memory and a DMA processor, said local processor having means for writing FIFO/interchange bus DMA commands into said command memory, each of said commands being specific to a given one said FIFOs and including an indication of the direction of data transfer between said interchange bus and said given FIFO, each of said FIFOs generating a ready status indication, said DMA processor controlling the data transfer specified in each of said commands sequentially after the corresponding FIFO indicates a ready status, and notifying said local processor upon completion of the data transfer specified in each of said commands.
67. Apparatus according to claim 65 further comprising an additional FIFO
coupled between said CPU bus and said DMA memory, said local processor further having means for transferring data between said CPU and said additional FIFO, and said DMA means being further for transferring data between said interchange bus and said additional FIFO in response to commands issued by said local processor.
68. Network server apparatus for use with a data network and a mass storage device, comprising:
an interface processor unit coupleable to said network and to said mass storage device;
a host processor unit coupleable to said interface processor unit by a second path different from said network;
means in said interface processor unit for satisfying requests from said network to store data from said network on said mass storage device;
means in said interface processor unit for satisfying requests from said network to retrieve data from said mass storage device to said network;
means in said interface processor unit for satisfying requests received from said host processor unit over said second path to store data from said host processor unit on said mass storage device; and means in said interface processor unit for satisfying requests received from said host processor unit over said second path to retrieve data from said mass storage device to said host processor unit.
69. Apparatus according to claim 68, wherein said interface processor unit comprises:
a network control unit coupleable to said network;
a data control unit coupleable to said mass storage device;
a buffer memory;
means in said network control unit for transmitting to said data control unit requests from said network to store specified storage data from said network on said mass storage device;

means in said network control unit for transmitting said specified storage data from said network to said buffer memory and from said buffer memory to said data control unit;
means in said network control unit for transmitting to said data control unit requests from said network to retrieve specified retrieval data from said mass storage device to said network; and means in said network control unit for transmitting said specified retrieval data from said data control unit to said buffer memory and from said buffer memory to said network.
70. Apparatus according to claim 69, wherein said data control unit comprises:
a storage processor unit coupleable to said mass storage device;
a file processor unit;
means on said file processor unit for translating said file system level storage requests from said network into requests to store data at specified physical storage locations in said mass storage device;
means on said file processor unit for instructing said storage processor unit to write data from said buffer memory into said specified physical storage locations in said mass storage device;
means on said file processor unit for translating file system level retrieval requests from said network into requests to retrieve data from specified physical retrieval locations in said mass storage device;
means on said file processor unit for instructing said storage processor unit to retrieve data from said specified physical retrieval locations in said mass storage device to said buffer memory if said data from said specified physical locations is not already in said buffer memory; and means in said storage processor unit for transmitting data between said buffer memory and said mass storage device.
71. Apparatus according to claim 68, for use further with a buffer memory, and wherein said requests from said network to store and retrieve data include file system level storage and retrieval requests respectively, and wherein said interface processor unit comprises:
a storage processor unit coupleable to said mass storage device;
a file processor unit;
means on said file processor unit for translating said file system level storage requests into requests to store data at specified physical storage locations in said mass storage device;
means on said file processor unit for instructing said storage processor unit to write data from said buffer memory into said specified physical storage locations in said mass storage device;
means on said file processor unit for translating said file system level retrieval requests into requests to retrieve data from specified physical retrieval locations in said mass storage device;
means on said file processor unit for instructing said storage processor unit to retrieve data from said specified physical retrieval locations in said mass storage device to said buffer memory if said data from said specified physical locations is not already in said buffer memory; and means in said storage processor unit for transmitting data between said buffer memory and said mass storage device.
72. A network node for use with a data network and a mass storage device, comprising:
a system buffer memory;
a network control unit coupleable to said network and having direct memory access to said system buffer memory;
a data control unit coupleable to said mass storage device and having direct memory access to said system buffer memory;
first means for satisfying requests from said network to store data from said network on said mass storage device; and second means for satisfying requests from said network to retrieve data from said mass storage device to said network, said first and second means collectively including means for transmitting from said network control unit to said system memory bank by direct memory access file data from said network for storage on said mass storage device, means for transmitting from said system memory bank to said data control unit by direct memory access said file data from said network for storage on said mass storage device, means for transmitting from said data control unit to said system memory bank by direct memory access file data for retrieval from said mass storage device to said network, and means for transmitting from said system memory bank to said network control unit said file data for retrieval from said mass storage device to said network;
at least said network control unit including a microprocessor and local instruction storage means distinct from said system buffer memory, all instructions for said microprocessor residing in said local instruction storage means.
73. A network file server for use with a data network and a mass storage device, comprising:
a host processor unit; and an interface processor unit coupleable to said network, to said mass storage device and, over a second path different from said network, to said host processor unit, said interface processor unit including means for decoding all NFS
requests from said network, means for performing all procedures for satisfying said NFS
requests, means for encoding any NFS reply messages for return transmission on said network, and means for satisfying file system requests from said host processor unit over said second path.
74. Network server apparatus for use with a data network, comprising:
a network controller coupleable to said network to receive incoming information packets over said network, said incoming information packets including certain packets which contain part or all of a request to said server apparatus, said request being in either a first or a second class of requests to said server apparatus;
a first additional processor;
an interchange bus different from said network and coupled between said network controller and said first additional processor;
means in said network controller for detecting and satisfying requests in said first class of requests contained in said certain incoming information packets, said network controller lacking means in said network controller for satisfying requests in said second class of requests; and means in said network controller for satisfying requests received over said interchange bus from said first additional processor.
75. Apparatus according to claim 74, wherein said means in said network controller for detecting and satisfying requests in said first class of requests, assembles said requests in said first class of requests into assembled requests before satisfying said requests in said first class of requests.
76. Apparatus according to claim 74, wherein said packets each include a network node destination address, wherein said means in said network controller for detecting and satisfying requests in said first class of requests, assembles said requests in said first class of requests, in a format which omits said network node destination addresses, before satisfying said requests in said first class of requests.
77. Apparatus according to claim 74, wherein said means in said network controller for detecting and satisfying requests in said first class includes means for preparing an outgoing message in response to one of said first class of requests, means for packaging said outgoing message in outgoing information packets suitable for transmission over said network, and means for transmitting said outgoing information packets over said network.
78. Apparatus according to claim 74, wherein said first class of requests comprises requests for an address of said server apparatus, and wherein said means in said network controller for detecting and satisfying requests in said first class comprises means for preparing a response packet to such an address request and means for transmitting said response packet over said network.
79. Apparatus according to claim 74, for use further with a second data network, said network controller being coupleable further to said second network, wherein said first class of requests comprises requests to route a message to a destinationreachable over said second network, and wherein said means in said network controller for detecting and satisfying requests in said first class comprises means for detecting that one of said certain packets comprises a request to route a message contained in said one of said certain packets to a destination reachable over said second network, and means for transmitting said message over said second network.
80. Apparatus according to claim 79, for use further with a third data network, said network controller further comprising means in said network controller for detecting particular requests in said incoming information packets to route a message contained in said particular requests, to a destination reachable over said third network, said apparatus further comprising:
a second network controller coupled to said interchange bus and coupleable to said third data network;
means for delivering said message contained in said particular requests to said second network controller over said interchange bus; and means in said second network controller for transmitting said message contained in said particular requests over said third network.
81. Apparatus according to claim 74, for use further with a third data network, said network controller further comprising means in said network controller for detecting particular requests in said incoming information packets to route a message contained in said particular requests, to a destination reachable over said third network, said apparatus further comprising:
a second network controller coupled to said interchange bus and coupleable to said third data network;
means for delivering said message contained in said particular requests to said second network controller over said interchange bus; and means in said second network controller;for transmitting said message contained in said particular requests over said third network.
82. Apparatus according to claim 74, for use further with amass storage device, wherein said first additional processor comprises a data control unit coupleable to said mass storage device, wherein said second class of requests comprises remote calls to procedures for managing a file system in said mass storage device, and wherein said means in said first additional processor for further processing said assembled requests in said second class of requests comprises means for executing file system procedures on said mass storage device in response to said assembled requests.
83. Apparatus according to claim 82, wherein said file system procedures include a read procedure for reading data from said mass storage device, said means in said first additional processor for further processing said assembled requests including means for reading data from a specified location in said mass storage device in response to a remote call to said read procedure, said apparatus further including means for delivering said data to said network controller, said network controller further comprising means on said network controller for packaging said data in outgoing information packets suitable for transmission over said network, and means for transmitting said outgoing information packets over said network.
84. Apparatus according to claim 83, wherein said means for delivering comprises:
a system buffer memory coupled to said interchange bus;
means in said data control unit for transferring said data over said interchange bus into said buffer memory; and means in said network controller for transferring said data over said interchange bus from said system buffer memory to said network controller.
85. Apparatus according to claim 82, wherein said file system procedures include a read procedure for reading a specified number of bytes of data from said mass storage device beginning at an address specified in logical terms including a file system ID and a file ID, said means for executing file system procedures comprising:
means for converting the logical address specified in a remote call to said read procedure to a physical address; and means for reading data from said physical address in said mass storage device.
86. Apparatus according to claim 85, wherein said mass storage device comprises a disk drive having a numbered tracks and sectors, wherein said logical address specifies said file system ID, said file ID, and a byte offset, and wherein said physical address specifies a corresponding track and sector number.
87. Apparatus according to claim 82, wherein said file system procedures include a read procedure for reading a specified number of bytes of data from said mass storage device beginning at an address specified in logical terms including a file system ID and a file ID, said data control unit comprising a file processor coupled to said interchange bus and a storage processor coupled to said interchange bus and coupleable to said mass storage device, said file processor comprising means for converting the logical address specified in a remote call to said read procedure to a physical address, said apparatus further comprising means for delivering said physical address to said storage processor, said storage processor comprising means for reading data from said physical address in said mass storage device and for transferring said data over said interchange bus into said buffer memory; and means in said network controller for transferring said data over said interchange bus from said system buffer memory to said network controller.
88. Apparatus according to claim 82, wherein said file system procedures include a write procedure for writing data contained in an assembled request, to said mass storage device, said means in said first additional processor for further processing said assembled requests including means for writing said data to a specified location in said mass storage device in response to a remote call to said read procedure.
89. Apparatus according to claim 74, wherein said network controller comprises:
a microprocessor;
a local instruction memory containing local instruction code;
a local bus coupled between said microprocessor and said local instruction memory;
bus interface means for interfacing said microprocessor with said interchange bus at times determined by said microprocessor in response to said local instruction code; and network interface means for interfacing said microprocessor with said data network, said local instruction memory including all instruction code necessary for said microprocessor to perform said function of detecting and satisfying requests in said first class of requests.
90. Network server apparatus for use with a data network, comprising:
a network controller coupleable to said network to receive incoming information packets over said network, said incoming information packets including certain packets which contain part or all of a message to said server apparatus, said message being in either a first or a second class of messages to said server apparatus, said messages in said first class of messages including certain messages containing requests;
a host computer;
an interchange bus different from said network and coupled between said network controller and said host computer;
means in said network controller for detecting and satisfying said requests in said first class of messages; and means for satisfying requests received over said interchange bus from said host computer.
91. Apparatus according to claim 90, wherein said means in said network controller for detecting and satisfying requests in said first class includes means for preparing an outgoing message in response to one of said requests in said first class of messages, means for packaging said outgoing message in outgoing information packets suitable for transmission over said network, and means for transmitting said outgoing information packets over said network.
92. Apparatus according to claim 90, for use further with a second data network, said network controller being coupleable further to said second network, wherein said first class of messages comprises messages to be routed to a destination reachable over said second network, and wherein said means in said network controller for detecting and satisfying requests in said first class comprises means for detecting that one of said certain packets includes a request to route a message contained in said one of said certain packets to a destination reachable over said second network, and means for transmitting said message over said second network.
93. Apparatus according to claim 90, for use further with a third data network, said network controller further comprising means in said network controller for detecting particular messages in said incoming information packets to be routed to a destination reachable over said third network, said apparatus further comprising:
a second network controller coupled to said interchange bus and coupleable to said third data network;
means for delivering said particular messages to said second network controller over said interchange bus, substantially without involving said host computer; and means in said second network controller for transmitting said message contained in said particular requests over said third network, substantially without involving said host computer.
94. Apparatus according to claim 90, for use further with a mass storage device, further comprising a data control unit coupleable to said mass storage device, said network controller further comprising means in said network controller for detecting ones of said incoming information packets containing remote calls to procedures for managing a file system in said mass storage device, and means in said network controller for assembling said remote calls from said incoming packets into assembled calls, substantially without involving said host computer, said apparatus further comprising means for delivering said assembled file system calls to said data control unit over said interchange bus substantially without involving said host computer, and said data control unit comprising means in said data control unit for executing file system procedures on said mass storage device in response to said assembled file system calls, substantially without involving said host computer.
95. Apparatus according to claim 90, wherein said network controller comprises:
a microprocessor;
a local instruction memory containing local instruction code;

a local bus coupled between said microprocessor and said local instruction memory;
bus interface means for interfacing said microprocessor with said interchange bus at times determined by said microprocessor in response to said local instruction code; and network interface means for interfacing said microprocessor with said data network, said local instruction memory including all instruction code necessary for said microprocessor to perform said function of detecting and satisfying requests in said first class of requests.
96. A network file server for use with a data network and a mass storage device, comprising:
means for decoding NFS requests from said network;
means for performing procedures for satisfying said NFS requests, including accessing said mass storage device if required; and means for encoding any NFS reply messages for return transmission on said network, said network file server for satisfying only-NFS requests from said network.
97. A network file server for use with a data network and a mass storage device, said network file server including a first unit comprising:
means for decoding file system requests from said network;
means for performing procedures for satisfying said file system requests, including accessing said mass storage device if required; and means for encoding any file system reply messages for return transmission on said network, said first unit for executing any programs other than programs which make calls to any general purpose operating system.
98. A network file server according to claim 97, further including a second unit comprising means for executing programs which make calls to a general purpose operating system.
99. A network file server according to claim 97, wherein said file system requests from said network comprise NFS requests.
100. A network file server for use with a data network and a mass storage device, said network file server including a first unit comprising:
means for decoding file system requests from said network;
means for performing procedures for satisfying said file system requests, including accessing said mass storage device if required; and means for encoding any file system reply messages for return transmission on said network, said first unit for executing any application programs other than user-provided application programs on said first unit.
101. A network file server according to claim 100, further including a second unit running a user-provided application program.
102. A network file server according to claim 100, wherein said file system requests from said network comprise NFS requests.
103. A network file server for use with a data network and a mass storage device, said network file server comprising:
a network control module, including a network interface coupled to receive file system requests from said network;
a file system control module, including a mass storage device interface coupled to said mass storage device; and a communication path coupled directly between said network control module and said file system control module, said communication path carrying file retrieval requests prepared by said network control module in response to received file system requests to retrieve specified retrieval data from said mass storage device, said file system control module retrieving said specified retrieval data from said mass storage device in response to said file retrieval requests and returning said specified retrieval data to said network control module, and said network control module preparing reply messages containing said specified retrieval data from said file system control module for return transmission on said network.
104. A network file server according to claim 103, wherein said file system control module returns said specified retrieval data directly to said network control module.
105. A network file server according to claim 103, wherein said network control module further prepares file storage requests in response to received file system requests to store specified storage data on said mass storage device, said network control module communicating said file storage requests to said file system control module, and wherein said file system control module further stores said specified storage data on said mass storage device in response to said file storage requests.
106. A network file server according to claim 105, wherein said file storage requests are communicated to said file system control module via said communication path.
107. A network file server according to claim 103, wherein said received file system requests to retrieve specified retrieval data comprise NFS requests.
108. A method for processing requests from a data network, for use by a network file server including a network control module coupled to receive file system requests from said network and a file system control module coupled to said mass storage device, comprising the steps of:

said network control module preparing file retrieval requests in response to received file system requests to retrieve specified retrieval data from said mass storage device;
said network control module communicating said file retrieval requests directly to said file system control module;
said file system control module retrieving said specified retrieval data from said mass storage device in response to said file retrieval requests and returning said specified retrieval data to said network control module; and said network control module preparing reply messages containing said specified retrieval data from said file system control module for return transmission on said network.
109. A method according to claim 108, wherein said file system control module returns said specified retrieval data directly to said network control module.
110. A method according to claim 108, further comprising the steps of:
said network control module preparing file storage requests in response to received file system requests to store specified storage data on said mass storage device said network control module communicating said file storage requests to said file system control module; and said file system control module storing said specified storage data on said mass storage device in response to said file storage requests.
111. A method according to claim 110, wherein said file storage requests are communicated directly to said file system control module.
112. A method according to claim 108, wherein said received file system requests to retrieve specified retrieval data comprise NFS requests.
113. Apparatus for use with a data network and a mass storage device, comprising the combination of first and second processing units, said first processing unit processing all requests from said network which are addressed to said apparatus and which are within a predefined non-NFS class of requests, and said second processing unit being coupleable to said network and to said mass storage device and decoding all NFS requests from said network which are addressed to said apparatus, performing procedures for satisfying said NFS
requests, and encoding NFS reply messages for return transmission on said network, said second processing unit not satisfying any of said requests from said network which are addressed to said apparatus and which are within said predefined non-NFS class of requests.
114. Apparatus according to claim 113, wherein said predefined non-NFS
class of requests includes all requests to perform client-defined procedures on said combination.
115. Apparatus according to claim 113, wherein said first processing unit includes a UNIX kernel and wherein said second processing unit does not include a UNIX kernel.
116. Apparatus according to claim 113, wherein said second processing unit comprises:
a network control unit coupleable to said network;
a data control unit coupleable to said mass storage device;
a buffer memory;
means in said network control unit for decoding said NFS requests and for encoding said NFS reply messages;
means for transmitting to said data control unit requests responsive to NFS
requests from said network to store specified data from said network on said mass storage device;
means for transmitting said specified storage data from said network to said buffer memory and from said buffer memory to said data control unit;

means for transmitting to said data control unit requests responsive to NFS
requests from said network to retrieve specified retrieval data from said mass storage device to said network;
means for transmitting said specified retrieval data from said data control unit to said buffer memory and from said buffer memory to said network.
117. A network file server for use with a data network and a mass storage device, said network file server including a first unit comprising:
means for decoding NFS requests from said network;
means for performing procedures for satisfying said NFS requests, including accessing said mass storage device if required; and means for encoding any NFS reply messages for return transmission on said network, said first unit for executing any programs which make UNIX operating system calls.
118. A network file server according to claim 117, further including a second unit comprising means for executing programs which make UNIX operating system calls.
119. A network file server for use with a data network and a mass storage device, said network file server including a first unit comprising:
means for decoding NFS requests from said network;
means for performing procedures for satisfying said NFS requests, including accessing said mass storage device if required; and means for encoding any NFS reply messages for return transmission on said network, said first unit lacking any UNIX kernel.
120. A network file server according to claim 119, further including a second unit running a UNIX kernel.
121. A network file server unit for use with a data network and a mass storage device, said network file server unit comprising:
means for decoding NFS requests from said network;
means for performing procedures for satisfying said NFS requests, including accessing said mass storage device if required; and means for encoding any NFS reply messages for return transmission on said network, said first unit lacking any UNIX application programs running on said first unit.
122. A network file server according to claim 121, further including a second unit running a UNIX application program.
123. Apparatus for use with a data network and a mass storage device, comprising the combination of first and second processing units, said first processing unit being coupled to said network and performing procedures for satisfying requests from said network which are within a predefined non-NFS class of requests, and said second processing unit being coupled to said network and to said mass storage device and decoding NFS requests from said network, performing procedures for satisfying said NFS requests, and encoding NFS reply messages for return transmission on said network, said second processing unit not satisfying any requests from said network which are within said predefined non-NFS class of requests.
124. Apparatus according to claim 123, wherein said predefined non-NFS
class of requests includes a predefined set of remote procedure calls.
125. Apparatus according to claim 123, wherein said first processing unit includes a general purpose operating system and wherein said second processing unit does not include a general purpose operating system.
126. Apparatus according to claim 123, wherein said second processing unit comprises:
a network control unit coupleable to said network;
a data control unit coupleable to said mass storage device;
a buffer memory;
means in said network control unit for decoding said NFS requests and for encoding said NFS reply messages;
means for transmitting to said data control unit requests responsive to NFS
requests from said network to store specified data from said network on said mass storage device;
means for transmitting said specified storage data from said network to said buffer memory and from said buffer memory to said data control unit;
means for transmitting to said data control unit requests responsive to NFS
requests from said network to retrieve specified retrieval data from said mass storage device to said network;
means for transmitting said specified retrieval data from said data control unit to said buffer memory and from said buffer memory to said network.
127. A network file server for use with a data network and a mass storage device, said network file server including a first unit comprising:
means for decoding NFS requests from said network;
means for performing procedures for satisfying said NFS requests, including accessing said mass storage device if required; and means for encoding any NFS reply messages for return transmission on said network, said first unit lacking means in said first unit for executing any programs which make calls to any general purpose operating system.
128. A network file server according to claim 127, further including a second unit comprising means for executing programs which make calls to a general purpose operating system.
129. A network file server according to claim 128, wherein said first unit lacks means in said first unit for executing any programs which make calls to a UNIX
operating system, and wherein said second unit comprises means for executing programs which make calls to a UNIX operating system.
130. A network file server for use with a data network and a mass storage device, said network file server including a first unit comprising:
means for decoding NFS requests from said network;
means for performing procedures for satisfying said NFS requests, including accessing said mass storage device if required; and means for encoding any NFS reply messages for return transmission on said network, said first unit lacking means to execute any user-provided application programs on said first unit.
131. A network file server according to claim 130, further including a second unit running a user-provided application program.
132. A network file server for use with a data network and a mass storage device, said network file server comprising;
a network control module, including a network interface coupled to receive NFS requests from said network;
a file system control module; including a mass storage device interface coupled to said mass storage device; and a communication path coupled directly between said network control module and said file system control module, said communication path carrying file retrieval requests prepared by said network control module in response to received NFS
requests to retrieve specified retrieval data from said mass storage device, said file system control module retrieving said specified retrieval data from said mass storage device in response to said file retrieval requests and returning said specified retrieval data to said network control module, and said network control module preparing reply messages containing said specified retrieval data from said file system control module for return transmission on said network.
133. A network file server according to claim 132, wherein said file system control module returns said specified retrieval data directly to said network control module.
134. A network file server according to claim 132, wherein said network control module further prepares file storage requests in response to received NFS
requests to store specified storage data on said mass storage device, said network control module communicating said file storage requests to said file system control module, and wherein said file system control module further stores said specified storage data on said mass storage device in response to said file storage requests.
135. A network file server according to claim 134, wherein said file storage requests are communicated to said file system control module via said communication path.
136. A method for processing requests from a data network, for use by a network file server including a network control module coupled to receive NFS
requests from said network and a file system control module coupled to said mass storage device, comprising the steps of:
said network control module preparing file retrieval requests in response to received NFS requests to retrieve specified retrieval data from said mass storage device;
said network control module communicating said file retrieval requests directly to said file system control module;
said file system control module retrieving said specified retrieval data from said mass storage device in response to said file retrieval requests and returning said specified retrieval data to said network control module; and said network control module preparing reply messages containing said specified retrieval data from said file system control module for return transmission on said network.
137. A method according to claim 136, wherein said file system control module returns said specified retrieval data directly to said network control module.
138. A method according to claim 136, further comprising the steps of:
said network control module preparing file storage requests in response to received NFS requests to store specified storage data on said mass storage device said network control module communicating said file storage requests to said file system control module; and said file system control module storing said specified storage data on said mass storage device in response to said file storage requests.
139. A method according to claim 138, wherein said file storage requests are communicated directly to said file system control module.
140. A network file server for use with a network and at least one mass storage device, said network file server including:
a network interface, coupleable to said network, for receiving NFS requests from said network;
a file server processor, coupled to the network interface and coupleable to said at least one mass storage device, for executing essentially only NFS
requests from said network interface, including accessing said at least one mass storage device if required.
141. A network file server for use with an Ethernet network and at least one mass storage device, said network file server including:
a network interface, coupleable to said Ethernet network, for receiving from said Ethernet network packets containing NFS requests to read data from or write data to said at least one mass storage device;

a parallel bus;
a dedicated file server processor, coupled to said network interface by means of said parallel bus, and coupleable to said at least one mass storage device, for executing essentially only NFS requests from said network interface, including accessing said at least one mass storage device if required.
142. A network file server for use with an Ethernet network, said network file server including:
a parallel bus;
at least one mass storage device coupled to said parallel bus;
a network interface, coupleable to said Ethernet network, and coupled to said parallel bus, for receiving from said Ethernet network packets containing NFS
requests to read data from or write data to said at least one mass storage device;
a dedicated file server processor, coupled to said network interface and to said at least one mass storage device by means of said parallel bus, for executing essentially only NFS requests from said network interface, including accessing said at least one mass storage device if required.
CA002066443A 1989-09-08 1990-08-20 Parallel i/o newtork file server architecture Expired - Lifetime CA2066443C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US07/404,959 US5163131A (en) 1989-09-08 1989-09-08 Parallel i/o network file server architecture
US404,959 1989-09-08
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7689754B2 (en) 1997-12-31 2010-03-30 Crossroads Systems, Inc. Storage router and method for providing virtual local storage
USRE42761E1 (en) 1997-12-31 2011-09-27 Crossroads Systems, Inc. Storage router and method for providing virtual local storage

Families Citing this family (905)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2945757B2 (en) * 1989-09-08 1999-09-06 オースペックス システムズ インコーポレイテッド Multi-device operating system architecture.
EP0428021B1 (en) * 1989-11-03 1998-09-02 Compaq Computer Corporation Method for data distribution in a disk array
US6389010B1 (en) * 1995-10-05 2002-05-14 Intermec Ip Corp. Hierarchical data collection network supporting packetized voice communications among wireless terminals and telephones
IL96808A (en) * 1990-04-18 1996-03-31 Rambus Inc Integrated circuit i/o using a high performance bus interface
US5611070A (en) * 1990-05-10 1997-03-11 Heidelberger; Philip Methods and apparatus for performing a write/load cache protocol
JPH0433139A (en) * 1990-05-30 1992-02-04 Fujitsu Ltd File accessing system
DE69121973T2 (en) * 1990-05-30 1997-01-30 Fujitsu Ltd Processing system for issuing the right to use the equipment
JPH0496830A (en) * 1990-08-15 1992-03-30 Hitachi Ltd Data management method for distributed processing system
US5673394A (en) * 1990-10-31 1997-09-30 Microsoft Corporation Method of sharing memory between an operating system and an application program
US5321844A (en) * 1990-12-20 1994-06-14 Siemens Aktiengesellschaft Method for error correction of software errors in a communication system
US5645815A (en) * 1991-02-08 1997-07-08 Diatide, Inc. Radiolabled compounds for thrombus imaging
US5333315A (en) * 1991-06-27 1994-07-26 Digital Equipment Corporation System of device independent file directories using a tag between the directories and file descriptors that migrate with the files
DE4227346C2 (en) * 1991-08-19 1999-09-09 Sequent Computer Systems Inc Device for data transmission between several units connected to a SCSI bus
US5410700A (en) * 1991-09-04 1995-04-25 International Business Machines Corporation Computer system which supports asynchronous commitment of data
EP0539782B1 (en) * 1991-10-28 1999-04-21 Eastman Kodak Company Circuit for controlling data transfer from VME bus to SCSI disk drive
US5410674A (en) * 1991-10-28 1995-04-25 Eastman Kodak Company Circuit for controlling data transfer from SCSI disk drive to VME bus
KR940004735B1 (en) * 1991-11-22 1994-05-28 삼성전자 주식회사 Graphic processing system
US5530899A (en) * 1991-12-18 1996-06-25 Dmi, Inc. Archival and retrieval system accessing an external storage by polling internal queues from remote terminals minimizing interruption of a host processor
GB9201949D0 (en) 1992-01-30 1992-03-18 Jenkin Michael Large-scale,touch-sensitive video display
DE69330655T2 (en) * 1992-02-10 2002-07-04 Canon Kk Dispensing procedure and unit
GB2264843B (en) * 1992-02-28 1995-09-20 Texas Instruments Ltd An interface device for coupling a host device having a network interface to a computer network having a predetermined communications medium
JPH07504527A (en) * 1992-03-09 1995-05-18 オースペックス システムズ インコーポレイテッド High performance non-volatile RAM protected write cache accelerator system
JP2868141B2 (en) * 1992-03-16 1999-03-10 株式会社日立製作所 Disk array device
JPH0619785A (en) * 1992-03-27 1994-01-28 Matsushita Electric Ind Co Ltd Distributed shared virtual memory and its constitution method
US5317739A (en) * 1992-03-30 1994-05-31 International Business Machines Corp. Method and apparatus for coupling data processing systems
US5444853A (en) * 1992-03-31 1995-08-22 Seiko Epson Corporation System and method for transferring data between a plurality of virtual FIFO's and a peripheral via a hardware FIFO and selectively updating control information associated with the virtual FIFO's
US5341499A (en) * 1992-04-02 1994-08-23 International Business Machines Corporation Method and apparatus for processing multiple file system server requests in a data processing network
US5642515A (en) * 1992-04-17 1997-06-24 International Business Machines Corporation Network server for local and remote resources
US5241670A (en) * 1992-04-20 1993-08-31 International Business Machines Corporation Method and system for automated backup copy ordering in a time zero backup copy session
JP3260813B2 (en) 1992-04-23 2002-02-25 株式会社日立製作所 Information processing system
US5305438A (en) * 1992-05-19 1994-04-19 Sony Electronics Inc. Video storage, processing, and distribution system using recording format independent hierarchical storages and processors
US6026452A (en) 1997-02-26 2000-02-15 Pitts; William Michael Network distributed site cache RAM claimed as up/down stream request/reply channel for storing anticipated data and meta data
CA2097564C (en) * 1992-06-16 2004-05-25 David L. Phillips Method of coupling open systems to a proprietary network
JPH0695986A (en) * 1992-06-19 1994-04-08 Westinghouse Electric Corp <We> Real-time data imaging network system and operating method thereof
US5307475A (en) * 1992-06-29 1994-04-26 The United States Of America As Represented By The Secretary Of The Navy Slave controller utilizing eight least/most significant bits for accessing sixteen bit data words
EP0582535A1 (en) * 1992-07-07 1994-02-09 International Business Machines Corporation Communication system and method utilizing picoprocessors for performing complex functions out of main communication data path
US5590372A (en) * 1992-07-14 1996-12-31 International Business Machines Corporation VME bus transferring system broadcasting modifiers to multiple devices and the multiple devices simultaneously receiving data synchronously to the modifiers without acknowledging the modifiers
US5309451A (en) * 1992-08-12 1994-05-03 Digital Equipment Corporation Data and parity prefetching for redundant arrays of disk drives
US5465351A (en) * 1992-08-14 1995-11-07 Noblenet Inc. Client-side memory management process for client-server computing
JPH07117929B2 (en) * 1992-08-14 1995-12-18 インターナショナル・ビジネス・マシーンズ・コーポレイション Connectionless session oriented protocol first message generation system and method
US5491812A (en) * 1992-09-28 1996-02-13 Conner Peripherals, Inc. System and method for ethernet to SCSI conversion
US5659690A (en) * 1992-10-15 1997-08-19 Adaptec, Inc. Programmably configurable host adapter integrated circuit including a RISC processor
US5841991A (en) * 1992-11-18 1998-11-24 Canon Information Systems, Inc. In an Interactive network board, a method and apparatus for storing a media access control address in a remotely alterable memory
US5568612A (en) * 1992-11-18 1996-10-22 Canon Kabushiki Kaisha Method and apparatus for advertising services of two network servers from a single network node
US5325527A (en) * 1993-01-19 1994-06-28 Canon Information Systems, Inc. Client/server communication system utilizing a self-generating nodal network
WO1994018634A1 (en) * 1993-02-01 1994-08-18 Lsc, Inc. Archiving file system for data servers in a distributed network environment
US5394526A (en) * 1993-02-01 1995-02-28 Lsc, Inc. Data server for transferring selected blocks of remote file to a distributed computer network involving only single data transfer operation
GB9302225D0 (en) * 1993-02-05 1993-03-24 Int Computers Ltd Data processing system
US5548724A (en) * 1993-03-22 1996-08-20 Hitachi, Ltd. File server system and file access control method of the same
US5367669A (en) * 1993-03-23 1994-11-22 Eclipse Technologies, Inc. Fault tolerant hard disk array controller
US5455934A (en) * 1993-03-23 1995-10-03 Eclipse Technologies, Inc. Fault tolerant hard disk array controller
US5463772A (en) * 1993-04-23 1995-10-31 Hewlett-Packard Company Transparent peripheral file systems with on-board compression, decompression, and space management
US6718399B1 (en) * 1993-05-21 2004-04-06 Candle Distributed Solutions, Inc. Communications on a network
US7174352B2 (en) 1993-06-03 2007-02-06 Network Appliance, Inc. File system image transfer
EP0701716B1 (en) * 1993-06-03 2002-08-14 Network Appliance, Inc. Method and file system for allocating blocks of files to storage space in a RAID disk system
US6604118B2 (en) 1998-07-31 2003-08-05 Network Appliance, Inc. File system image transfer
US6138126A (en) * 1995-05-31 2000-10-24 Network Appliance, Inc. Method for allocating files in a file system integrated with a raid disk sub-system
DE69425658T2 (en) * 1993-06-03 2001-04-19 Network Appliance Inc ARRANGEMENT OF A FILE SYSTEM FOR DESCRIBING ANY AREAS
WO1994029795A1 (en) * 1993-06-04 1994-12-22 Network Appliance Corporation A method for providing parity in a raid sub-system using a non-volatile memory
US5619690A (en) * 1993-06-21 1997-04-08 Hitachi, Ltd. Computer system including a computer which requests an access to a logical address in a secondary storage system with specification of a local address in the secondary storage system
US5490134A (en) * 1993-06-29 1996-02-06 Southern California Edison Company Versatile communications controller
US5530907A (en) * 1993-08-23 1996-06-25 Tcsi Corporation Modular networked image processing system and method therefor
US5500929A (en) * 1993-08-30 1996-03-19 Taligent, Inc. System for browsing a network resource book with tabs attached to pages
US5878280A (en) * 1993-09-23 1999-03-02 Philips Electronics North America Corp. Data buffering system for plural data memory arrays
US5671386A (en) * 1993-09-23 1997-09-23 Philips Electronics North America Corporation System for storing data and for providing simultaneous plural access to data by connecting each access channel to each and every one of storage arrays
US5539660A (en) * 1993-09-23 1996-07-23 Philips Electronics North America Corporation Multi-channel common-pool distributed data storage and retrieval system
US5671372A (en) * 1993-09-30 1997-09-23 International Business Machines Corporation Data processing system with microprocessor/cache chip set directly coupled to memory bus of narrower data width
US5603046A (en) * 1993-11-02 1997-02-11 Motorola Inc. Method for complex data movement in a multi-processor data processing system
US5495607A (en) * 1993-11-15 1996-02-27 Conner Peripherals, Inc. Network management system having virtual catalog overview of files distributively stored across network domain
US5999907A (en) 1993-12-06 1999-12-07 Donner; Irah H. Intellectual property audit system
US6154725A (en) 1993-12-06 2000-11-28 Donner; Irah H. Intellectual property (IP) computer-implemented audit system optionally over network architecture, and computer program product for same
US5987622A (en) * 1993-12-10 1999-11-16 Tm Patents, Lp Parallel computer system including parallel storage subsystem including facility for correction of data in the event of failure of a storage device in parallel storage subsystem
US5809527A (en) * 1993-12-23 1998-09-15 Unisys Corporation Outboard file cache system
US5450578A (en) * 1993-12-23 1995-09-12 Unisys Corporation Method and apparatus for automatically routing around faults within an interconnect system
US5495589A (en) * 1993-12-23 1996-02-27 Unisys Corporation Architecture for smart control of bi-directional transfer of data
US5572729A (en) * 1994-01-11 1996-11-05 Sun Microsystems, Inc. Method for stateless rename propagation between hierarchical file name spaces
US5535400A (en) * 1994-01-28 1996-07-09 Compaq Computer Corporation SCSI disk drive power down apparatus
US5737549A (en) * 1994-01-31 1998-04-07 Ecole Polytechnique Federale De Lausanne Method and apparatus for a parallel data storage and processing server
USRE38410E1 (en) * 1994-01-31 2004-01-27 Axs Technologies, Inc. Method and apparatus for a parallel data storage and processing server
AU1835895A (en) * 1994-01-31 1995-08-15 Lannet Inc. Application and method for communication switching
AU2093795A (en) * 1994-03-11 1995-09-25 Panda Project, The Modular architecture for high bandwidth computers
KR100387207B1 (en) * 1994-03-15 2003-10-04 디지 인터내셔날 인크. Communication system and communication method by remote network device
US5991829A (en) * 1994-03-29 1999-11-23 The United States Of America As Represented By The Secretary Of The Navy Method of sensing target status in a local area network
US5471634A (en) * 1994-03-29 1995-11-28 The United States Of America As Represented By The Secretary Of The Navy Network file server with automatic sensing means
US6047356A (en) * 1994-04-18 2000-04-04 Sonic Solutions Method of dynamically allocating network node memory's partitions for caching distributed files
US5673381A (en) * 1994-05-27 1997-09-30 Cheyenne Software International Sales Corp. System and parallel streaming and data stripping to back-up a network
US5590381A (en) * 1994-06-30 1996-12-31 Lucent Technologies Inc. Method and apparatus for buffered video playback of video content distributed on a plurality of disks
US6175571B1 (en) 1994-07-22 2001-01-16 Network Peripherals, Inc. Distributed memory switching hub
US5812792A (en) * 1994-07-22 1998-09-22 Network Peripherals, Inc. Use of video DRAM for memory storage in a local area network port of a switching hub
US5655140A (en) * 1994-07-22 1997-08-05 Network Peripherals Apparatus for translating frames of data transferred between heterogeneous local area networks
US5499341A (en) * 1994-07-25 1996-03-12 Loral Aerospace Corp. High performance image storage and distribution apparatus having computer bus, high speed bus, ethernet interface, FDDI interface, I/O card, distribution card, and storage units
US5598536A (en) * 1994-08-09 1997-01-28 Shiva Corporation Apparatus and method for providing remote users with the same unique IP address upon each network access
US5537533A (en) * 1994-08-11 1996-07-16 Miralink Corporation System and method for remote mirroring of digital data from a primary network server to a remote network server
US5729719A (en) * 1994-09-07 1998-03-17 Adaptec, Inc. Synchronization circuit for clocked signals of similar frequencies
US5687347A (en) * 1994-09-19 1997-11-11 Matsushita Electric Industrial Co., Ltd. Data providing device, file server device, and data transfer control method
JPH0887459A (en) * 1994-09-19 1996-04-02 Fujitsu Ltd Background communication system
US7424731B1 (en) 1994-10-12 2008-09-09 Touchtunes Music Corporation Home digital audiovisual information recording and playback system
US7188352B2 (en) 1995-07-11 2007-03-06 Touchtunes Music Corporation Intelligent digital audiovisual playback system
DE69422647T2 (en) 1994-10-12 2000-08-31 Touchtunes Music Corp INTELLIGENT SYSTEM FOR NUMERICAL AUDIO-VISUAL REPRODUCTION
US8661477B2 (en) 1994-10-12 2014-02-25 Touchtunes Music Corporation System for distributing and selecting audio and video information and method implemented by said system
US5829018A (en) * 1994-10-25 1998-10-27 International Business Machines Corporation Apparatus and method for writing data from a cache to a storage device
US5675741A (en) * 1994-10-25 1997-10-07 Cabletron Systems, Inc. Method and apparatus for determining a communications path between two nodes in an Internet Protocol (IP) network
CA2203378A1 (en) * 1994-10-26 1996-05-09 Flamepoint, Inc. Simultaneous processing by multiple components
US5845061A (en) * 1994-10-31 1998-12-01 Hitachi, Ltd. Redundant client server system
US5717952A (en) * 1994-11-16 1998-02-10 Apple Computer, Inc. DMA controller with mechanism for conditional action under control of status register, prespecified parameters, and condition field of channel command
US6061731A (en) * 1994-12-06 2000-05-09 Thunderwave, Inc. Read only linear stream based cache system
US5623699A (en) * 1994-12-06 1997-04-22 Thunderwave, Inc. Read only linear stream based cache system
EP0716370A3 (en) * 1994-12-06 2005-02-16 International Business Machines Corporation A disk access method for delivering multimedia and video information on demand over wide area networks
US5870621A (en) * 1994-12-22 1999-02-09 Texas Instruments Incorporated Quadrilateral multichip computer systems and printed circuit boards therefor
US5619497A (en) * 1994-12-22 1997-04-08 Emc Corporation Method and apparatus for reordering frames
US5757642A (en) * 1995-01-20 1998-05-26 Dell Usa L.P. Multi-function server input/output subsystem and method
JPH08234928A (en) * 1995-02-22 1996-09-13 Matsushita Electric Ind Co Ltd Information storage controller
US5758084A (en) * 1995-02-27 1998-05-26 Hewlett-Packard Company Apparatus for parallel client/server communication having data structures which stored values indicative of connection state and advancing the connection state of established connections
US5978577A (en) * 1995-03-17 1999-11-02 Csg Systems, Inc. Method and apparatus for transaction processing in a distributed database system
US6249822B1 (en) * 1995-04-24 2001-06-19 Microsoft Corporation Remote procedure call method
US5699500A (en) * 1995-06-01 1997-12-16 Ncr Corporation Reliable datagram service provider for fast messaging in a clustered environment
US5636371A (en) * 1995-06-07 1997-06-03 Bull Hn Information Systems Inc. Virtual network mechanism to access well known port application programs running on a single host system
US6940840B2 (en) 1995-06-30 2005-09-06 Interdigital Technology Corporation Apparatus for adaptive reverse power control for spread-spectrum communications
US7020111B2 (en) 1996-06-27 2006-03-28 Interdigital Technology Corporation System for using rapid acquisition spreading codes for spread-spectrum communications
US7123600B2 (en) 1995-06-30 2006-10-17 Interdigital Technology Corporation Initial power control for spread-spectrum communications
US6697350B2 (en) 1995-06-30 2004-02-24 Interdigital Technology Corporation Adaptive vector correlator for spread-spectrum communications
US7929498B2 (en) 1995-06-30 2011-04-19 Interdigital Technology Corporation Adaptive forward power control and adaptive reverse power control for spread-spectrum communications
ZA965340B (en) 1995-06-30 1997-01-27 Interdigital Tech Corp Code division multiple access (cdma) communication system
US6885652B1 (en) 1995-06-30 2005-04-26 Interdigital Technology Corporation Code division multiple access (CDMA) communication system
US7072380B2 (en) 1995-06-30 2006-07-04 Interdigital Technology Corporation Apparatus for initial power control for spread-spectrum communications
US5754803A (en) * 1996-06-27 1998-05-19 Interdigital Technology Corporation Parallel packetized intermodule arbitrated high speed control and data bus
US6788662B2 (en) 1995-06-30 2004-09-07 Interdigital Technology Corporation Method for adaptive reverse power control for spread-spectrum communications
US6816473B2 (en) 1995-06-30 2004-11-09 Interdigital Technology Corporation Method for adaptive forward power control for spread-spectrum communications
US5802297A (en) * 1995-07-03 1998-09-01 Sun Microsystems, Inc. Client-server computer system and method utilizing a local client disk drive as a data cache
US5812775A (en) * 1995-07-12 1998-09-22 3Com Corporation Method and apparatus for internetworking buffer management
US5796944A (en) * 1995-07-12 1998-08-18 3Com Corporation Apparatus and method for processing data frames in an internetworking device
US5748633A (en) * 1995-07-12 1998-05-05 3Com Corporation Method and apparatus for the concurrent reception and transmission of packets in a communications internetworking device
US5651002A (en) * 1995-07-12 1997-07-22 3Com Corporation Internetworking device with enhanced packet header translation and memory
US5825774A (en) * 1995-07-12 1998-10-20 3Com Corporation Packet characterization using code vectors
US5790794A (en) * 1995-08-11 1998-08-04 Symbios, Inc. Video storage unit architecture
US5917730A (en) * 1995-08-17 1999-06-29 Gse Process Solutions, Inc. Computer implemented object oriented visualization system and method
US5668958A (en) * 1995-09-12 1997-09-16 International Business Machines Corporation Heterogeneous filing system with common API and reconciled file management rules
US6098128A (en) 1995-09-18 2000-08-01 Cyberstorage Systems Corporation Universal storage management system
US5692182A (en) * 1995-10-05 1997-11-25 International Business Machines Corporation Bufferpool coherency for identifying and retrieving versions of workfile data using a producing DBMS and a consuming DBMS
US5774670A (en) 1995-10-06 1998-06-30 Netscape Communications Corporation Persistent client state in a hypertext transfer protocol based client-server system
US5729681A (en) * 1995-10-10 1998-03-17 Intel Corporation Method of communicating data from a host to a network controller
US5974502A (en) * 1995-10-27 1999-10-26 Lsi Logic Corporation Apparatus and method for analyzing and modifying data transfer reguests in a raid system
US5778180A (en) * 1995-11-06 1998-07-07 Sun Microsystems, Inc. Mechanism for reducing data copying overhead in protected memory operating systems
JPH103421A (en) * 1995-11-20 1998-01-06 Matsushita Electric Ind Co Ltd Virtual file management system
KR100385238B1 (en) * 1995-11-27 2004-02-25 삼성전자주식회사 Method for realizing segment cash buffer for group adaptation type
EP0777183B1 (en) * 1995-12-01 2002-07-31 Hewlett-Packard Company, A Delaware Corporation Computer cache system
US5742817A (en) * 1995-12-08 1998-04-21 Emc Corporation Method and apparatus for file server addressing
JPH09179820A (en) * 1995-12-26 1997-07-11 Mitsubishi Electric Corp Load distributing system and its method
IL116986A (en) * 1996-01-31 2000-01-31 Galileo Technology Ltd Switching ethernet controller providing packet routing
US5727218A (en) * 1996-03-05 1998-03-10 Unisys Corp. Controlling an apparatus disposed for adapting fiber channel transmissions to an industry standard data bus
US5832198A (en) * 1996-03-07 1998-11-03 Philips Electronics North America Corporation Multiple disk drive array with plural parity groups
US5764634A (en) * 1996-03-13 1998-06-09 International Business Machines Corporation Lan switch with zero latency
US5884098A (en) * 1996-04-18 1999-03-16 Emc Corporation RAID controller system utilizing front end and back end caching systems including communication path connecting two caching systems and synchronizing allocation of blocks in caching systems
US5806085A (en) * 1996-05-01 1998-09-08 Sun Microsystems, Inc. Method for non-volatile caching of network and CD-ROM file accesses using a cache directory, pointers, file name conversion, a local hard disk, and separate small database
US6055577A (en) * 1996-05-06 2000-04-25 Oracle Corporation System for granting bandwidth for real time processes and assigning bandwidth for non-real time processes while being forced to periodically re-arbitrate for new assigned bandwidth
US6175854B1 (en) * 1996-06-11 2001-01-16 Ameritech Services, Inc. Computer system architecture and method for multi-user, real-time applications
DE19625196A1 (en) * 1996-06-24 1998-01-02 Godi Meyer Gizella Data archiving system
US5996047A (en) * 1996-07-01 1999-11-30 Sun Microsystems, Inc. Method and apparatus for caching file control information corresponding to a second file block in a first file block
ATE536588T1 (en) * 1996-07-25 2011-12-15 Xcelera Inc WEB SERVER SYSTEM WITH PRIMARY AND SECONDARY SERVERS
US5774660A (en) * 1996-08-05 1998-06-30 Resonate, Inc. World-wide-web server with delayed resource-binding for resource-based load balancing on a distributed resource multi-node network
US5839088A (en) 1996-08-22 1998-11-17 Go2 Software, Inc. Geographic location referencing system and method
US5781703A (en) * 1996-09-06 1998-07-14 Candle Distributed Solutions, Inc. Intelligent remote agent for computer performance monitoring
FR2753868A1 (en) 1996-09-25 1998-03-27 Technical Maintenance Corp METHOD FOR SELECTING A RECORDING ON AN AUDIOVISUAL DIGITAL REPRODUCTION SYSTEM AND SYSTEM FOR IMPLEMENTING THE METHOD
US5884046A (en) * 1996-10-23 1999-03-16 Pluris, Inc. Apparatus and method for sharing data and routing messages between a plurality of workstations in a local area network
US5797016A (en) * 1996-10-29 1998-08-18 Cheyenne Software Inc. Regeneration agent for back-up software
US5991763A (en) * 1996-10-29 1999-11-23 Sun Microsystems, Inc. Method and apparatus for embedding concatenated data files into object files during runtime in a virtual file system
US6246975B1 (en) 1996-10-30 2001-06-12 American Board Of Family Practice, Inc. Computer architecture and process of patient generation, evolution, and simulation for computer based testing system
US6230193B1 (en) * 1996-10-31 2001-05-08 3Com Corporation Method and apparatus supporting network communications
US6065100A (en) * 1996-11-12 2000-05-16 Micro-Design International Caching apparatus and method for enhancing retrieval of data from an optical storage device
JP3217002B2 (en) * 1996-11-19 2001-10-09 株式会社日立製作所 Digital studio apparatus and control method thereof
US6289320B1 (en) * 1998-07-07 2001-09-11 Diebold, Incorporated Automated banking machine apparatus and system
US6035418A (en) * 1996-12-13 2000-03-07 International Business Machines Corporation System and method for improving resource utilization in a TCP/IP connection management system
US6505268B1 (en) 1996-12-20 2003-01-07 Compaq Computer Corporation Data distribution in a disk array
US5940826A (en) * 1997-01-07 1999-08-17 Unisys Corporation Dual XPCS for disaster recovery in multi-host computer complexes
US5949970A (en) * 1997-01-07 1999-09-07 Unisys Corporation Dual XPCS for disaster recovery
US5845285A (en) * 1997-01-07 1998-12-01 Klein; Laurence C. Computer system and method of data analysis
US5978379A (en) 1997-01-23 1999-11-02 Gadzoox Networks, Inc. Fiber channel learning bridge, learning half bridge, and protocol
US6141701A (en) * 1997-03-13 2000-10-31 Whitney; Mark M. System for, and method of, off-loading network transactions from a mainframe to an intelligent input/output device, including off-loading message queuing facilities
US5873074A (en) * 1997-04-18 1999-02-16 Informix Software, Inc. Applying distinct hash-join distributions of operators to both even and uneven database records
US6407752B1 (en) 1997-04-29 2002-06-18 International Business Machines Corporation Method and system for a user interface for remote FTP hosts
US6604998B1 (en) 1999-11-10 2003-08-12 Ptt, Llc Modified poker system with combination of multiple games using at least some common cards and method of playing the same
US6960133B1 (en) 2000-08-28 2005-11-01 Igt Slot machine game having a plurality of ways for a user to obtain payouts based on selection of one or more symbols (power pays)
US6081807A (en) * 1997-06-13 2000-06-27 Compaq Computer Corporation Method and apparatus for interfacing with a stateless network file system server
JP3817339B2 (en) * 1997-06-26 2006-09-06 株式会社日立製作所 File input / output control method
US5884313A (en) * 1997-06-30 1999-03-16 Sun Microsystems, Inc. System and method for efficient remote disk I/O
US5987477A (en) * 1997-07-11 1999-11-16 International Business Machines Corporation Parallel file system and method for parallel write sharing
US6032216A (en) * 1997-07-11 2000-02-29 International Business Machines Corporation Parallel file system with method using tokens for locking modes
US7574727B2 (en) 1997-07-23 2009-08-11 Touchtunes Music Corporation Intelligent digital audiovisual playback system
US6032219A (en) * 1997-08-01 2000-02-29 Garmin Corporation System and method for buffering data
US5988847A (en) * 1997-08-22 1999-11-23 Honeywell Inc. Systems and methods for implementing a dynamic cache in a supervisory control system
JPH1185710A (en) 1997-09-16 1999-03-30 Toshiba Corp Server device and file management method
FR2769165B1 (en) 1997-09-26 2002-11-29 Technical Maintenance Corp WIRELESS SYSTEM WITH DIGITAL TRANSMISSION FOR SPEAKERS
US6192408B1 (en) * 1997-09-26 2001-02-20 Emc Corporation Network file server sharing local caches of file access information in data processors assigned to respective file systems
US6381674B2 (en) 1997-09-30 2002-04-30 Lsi Logic Corporation Method and apparatus for providing centralized intelligent cache between multiple data controlling elements
US6389479B1 (en) 1997-10-14 2002-05-14 Alacritech, Inc. Intelligent network interface device and system for accelerated communication
US6434620B1 (en) 1998-08-27 2002-08-13 Alacritech, Inc. TCP/IP offload network interface device
US8621101B1 (en) 2000-09-29 2013-12-31 Alacritech, Inc. Intelligent network storage interface device
US6427173B1 (en) 1997-10-14 2002-07-30 Alacritech, Inc. Intelligent network interfaced device and system for accelerated communication
US7042898B2 (en) 1997-10-14 2006-05-09 Alacritech, Inc. Reducing delays associated with inserting a checksum into a network message
US7174393B2 (en) 2000-12-26 2007-02-06 Alacritech, Inc. TCP/IP offload network interface device
US6470415B1 (en) 1999-10-13 2002-10-22 Alacritech, Inc. Queue system involving SRAM head, SRAM tail and DRAM body
US8539112B2 (en) 1997-10-14 2013-09-17 Alacritech, Inc. TCP/IP offload device
US7237036B2 (en) 1997-10-14 2007-06-26 Alacritech, Inc. Fast-path apparatus for receiving data corresponding a TCP connection
US6697868B2 (en) 2000-02-28 2004-02-24 Alacritech, Inc. Protocol processing stack for use with intelligent network interface device
US7167927B2 (en) 1997-10-14 2007-01-23 Alacritech, Inc. TCP/IP offload device with fast-path TCP ACK generating and transmitting mechanism
US6226680B1 (en) * 1997-10-14 2001-05-01 Alacritech, Inc. Intelligent network interface system method for protocol processing
US6687758B2 (en) 2001-03-07 2004-02-03 Alacritech, Inc. Port aggregation for network connections that are offloaded to network interface devices
US7133940B2 (en) 1997-10-14 2006-11-07 Alacritech, Inc. Network interface device employing a DMA command queue
US7089326B2 (en) * 1997-10-14 2006-08-08 Alacritech, Inc. Fast-path processing for receiving data on TCP connection offload devices
US6757746B2 (en) 1997-10-14 2004-06-29 Alacritech, Inc. Obtaining a destination address so that a network interface device can write network data without headers directly into host memory
US7185266B2 (en) * 2003-02-12 2007-02-27 Alacritech, Inc. Network interface device for error detection using partial CRCS of variable length message portions
US6658480B2 (en) 1997-10-14 2003-12-02 Alacritech, Inc. Intelligent network interface system and method for accelerated protocol processing
US7284070B2 (en) * 1997-10-14 2007-10-16 Alacritech, Inc. TCP offload network interface device
US6591302B2 (en) 1997-10-14 2003-07-08 Alacritech, Inc. Fast-path apparatus for receiving data corresponding to a TCP connection
US6427171B1 (en) 1997-10-14 2002-07-30 Alacritech, Inc. Protocol processing stack for use with intelligent network interface device
US7076568B2 (en) 1997-10-14 2006-07-11 Alacritech, Inc. Data communication apparatus for computer intelligent network interface card which transfers data between a network and a storage device according designated uniform datagram protocol socket
US8782199B2 (en) 1997-10-14 2014-07-15 A-Tech Llc Parsing a packet header
US6807581B1 (en) 2000-09-29 2004-10-19 Alacritech, Inc. Intelligent network storage interface system
US5941969A (en) 1997-10-22 1999-08-24 Auspex Systems, Inc. Bridge for direct data storage device access
US6189101B1 (en) 1997-10-24 2001-02-13 Richard G. Dusenbury, Jr. Secure network architecture method and apparatus
US7225463B2 (en) 1997-10-24 2007-05-29 Dusenbury Jr Richard G Secure network architecture method and apparatus
US7581077B2 (en) 1997-10-30 2009-08-25 Commvault Systems, Inc. Method and system for transferring data in a storage operation
US6418478B1 (en) 1997-10-30 2002-07-09 Commvault Systems, Inc. Pipelined high speed data transfer mechanism
US6009478A (en) * 1997-11-04 1999-12-28 Adaptec, Inc. File array communications interface for communicating between a host computer and an adapter
US6219693B1 (en) * 1997-11-04 2001-04-17 Adaptec, Inc. File array storage architecture having file system distributed across a data processing platform
US6081883A (en) * 1997-12-05 2000-06-27 Auspex Systems, Incorporated Processing system with dynamically allocatable buffer memory
US6079000A (en) * 1997-12-30 2000-06-20 Unisys Corporation XPC backup for in-process audit
US6701330B1 (en) 1997-12-30 2004-03-02 Unisys Corporation Protecting duplicate/lost updates against host failures
US6735245B1 (en) 1998-01-09 2004-05-11 Panasonic Communications Co., Ltd. Activation of multiple XDSL modems with channel probe
US6560639B1 (en) 1998-02-13 2003-05-06 3565 Acquisition Corporation System for web content management based on server-side application
US7003528B2 (en) 1998-02-13 2006-02-21 3565 Acquisition, Llc Method and system for web management
US6457130B2 (en) 1998-03-03 2002-09-24 Network Appliance, Inc. File access control in a multi-protocol file server
US6317844B1 (en) 1998-03-10 2001-11-13 Network Appliance, Inc. File server storage arrangement
US6697846B1 (en) * 1998-03-20 2004-02-24 Dataplow, Inc. Shared file system
KR20030059343A (en) * 1998-04-01 2003-07-07 마쓰시타 덴소 시스템 가부시키가이샤 ACTIVATION OF MULTIPLE xDSL MODEMS WITH IMPLICIT CHANNEL PROBE
US6446206B1 (en) 1998-04-01 2002-09-03 Microsoft Corporation Method and system for access control of a message queue
US6205498B1 (en) 1998-04-01 2001-03-20 Microsoft Corporation Method and system for message transfer session management
US6529932B1 (en) 1998-04-01 2003-03-04 Microsoft Corporation Method and system for distributed transaction processing with asynchronous message delivery
US6873652B1 (en) 1998-04-01 2005-03-29 Panasonic Communications Co., Ltd. Activation of multiple xDSL modems with implicit channel probe
US6912588B1 (en) * 1998-04-02 2005-06-28 Intel Corporation System and method for managing client requests in client-server networks
US6473401B1 (en) 1998-04-06 2002-10-29 Iscale, Inc. Self-scaling method for exploiting cached resources across organizational boundaries to enhance user response time and to reduce server and network load
US6185607B1 (en) * 1998-05-26 2001-02-06 3Com Corporation Method for managing network data transfers with minimal host processor involvement
AU4839899A (en) * 1998-06-29 2000-01-17 Recording Industry Association Of America Security marking system and method for minimizing pirating of data on data media
US6848108B1 (en) 1998-06-30 2005-01-25 Microsoft Corporation Method and apparatus for creating, sending, and using self-descriptive objects as messages over a message queuing network
US6256634B1 (en) 1998-06-30 2001-07-03 Microsoft Corporation Method and system for purging tombstones for deleted data items in a replicated database
US6275912B1 (en) * 1998-06-30 2001-08-14 Microsoft Corporation Method and system for storing data items to a storage device
FR2781582B1 (en) 1998-07-21 2001-01-12 Technical Maintenance Corp SYSTEM FOR DOWNLOADING OBJECTS OR FILES FOR SOFTWARE UPDATE
US6311221B1 (en) * 1998-07-22 2001-10-30 Appstream Inc. Streaming modules
US7197570B2 (en) 1998-07-22 2007-03-27 Appstream Inc. System and method to send predicted application streamlets to a client device
US20010044850A1 (en) 1998-07-22 2001-11-22 Uri Raz Method and apparatus for determining the order of streaming modules
US8028318B2 (en) 1999-07-21 2011-09-27 Touchtunes Music Corporation Remote control unit for activating and deactivating means for payment and for displaying payment status
FR2781591B1 (en) 1998-07-22 2000-09-22 Technical Maintenance Corp AUDIOVISUAL REPRODUCTION SYSTEM
US6574618B2 (en) 1998-07-22 2003-06-03 Appstream, Inc. Method and system for executing network streamed application
FR2781580B1 (en) 1998-07-22 2000-09-22 Technical Maintenance Corp SOUND CONTROL CIRCUIT FOR INTELLIGENT DIGITAL AUDIOVISUAL REPRODUCTION SYSTEM
FR2781593B1 (en) 1998-07-22 2001-01-12 Technical Maintenance Corp REMOTE CONTROL FOR INTELLIGENT DIGITAL AUDIOVISUAL REPRODUCTION SYSTEM
US6119244A (en) 1998-08-25 2000-09-12 Network Appliance, Inc. Coordinating persistent status information with multiple file servers
US7664883B2 (en) 1998-08-28 2010-02-16 Alacritech, Inc. Network interface device that fast-path processes solicited session layer read commands
US6351812B1 (en) * 1998-09-04 2002-02-26 At&T Corp Method and apparatus for authenticating participants in electronic commerce
US6356863B1 (en) * 1998-09-08 2002-03-12 Metaphorics Llc Virtual network file server
US7013305B2 (en) 2001-10-01 2006-03-14 International Business Machines Corporation Managing the state of coupling facility structures, detecting by one or more systems coupled to the coupling facility, the suspended state of the duplexed command, detecting being independent of message exchange
US6622164B1 (en) * 1998-09-11 2003-09-16 Quantum Corp. Mass storage device with network interface
US6230190B1 (en) * 1998-10-09 2001-05-08 Openwave Systems Inc. Shared-everything file storage for clustered system
US7430171B2 (en) 1998-11-19 2008-09-30 Broadcom Corporation Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost
US6343984B1 (en) 1998-11-30 2002-02-05 Network Appliance, Inc. Laminar flow duct cooling system
US6434637B1 (en) 1998-12-31 2002-08-13 Emc Corporation Method and apparatus for balancing workloads among paths in a multi-path computer system based on the state of previous I/O operations
US6950459B1 (en) 1999-01-08 2005-09-27 Panasonic Communications Co., Ltd. Activation of multiple xDSL modems with half duplex and full duplex procedures
US7966078B2 (en) * 1999-02-01 2011-06-21 Steven Hoffberg Network media appliance system and method
US7529654B2 (en) * 1999-02-01 2009-05-05 International Business Machines Corporation System and procedure for controlling and monitoring programs in a computer network
US6442682B1 (en) * 1999-02-18 2002-08-27 Auspex Systems, Inc. Characterization of data access using file system
US8726330B2 (en) 1999-02-22 2014-05-13 Touchtunes Music Corporation Intelligent digital audiovisual playback system
US6230251B1 (en) * 1999-03-22 2001-05-08 Agere Systems Guardian Corp. File replication methods and apparatus for reducing port pressure in a clustered processor
US6640278B1 (en) * 1999-03-25 2003-10-28 Dell Products L.P. Method for configuration and management of storage resources in a storage network
US6324062B1 (en) 1999-04-02 2001-11-27 Unisys Corporation Modular packaging configuration and system and method of use for a computer system adapted for operating multiple operating systems in different partitions
US7107253B1 (en) * 1999-04-05 2006-09-12 American Board Of Family Practice, Inc. Computer architecture and process of patient generation, evolution and simulation for computer based testing system using bayesian networks as a scripting language
US6295578B1 (en) 1999-04-09 2001-09-25 Compaq Computer Corporation Cascaded removable media data storage system
EP1049029A3 (en) * 1999-04-28 2003-07-09 Emc Corporation File systems with versatile indirection
WO2000065985A2 (en) 1999-04-29 2000-11-09 University Of South Florida Method and system for knowledge guided hyperintensity detection and volumetric measurement
US6893342B1 (en) 1999-05-03 2005-05-17 Ptt, Llc Slot machine game having a plurality of ways for a user to intuitively obtain payouts
US6751254B1 (en) * 1999-05-05 2004-06-15 Panasonic Communications Co., Ltd. Activation of multiple xDSL modems with power control measurement
AU4990800A (en) * 1999-05-05 2000-11-17 Contact Networks, Inc. Method and system to automate the updating of personal information within a personal information management application and to synchronize such updated personalinformation across multiple personal information management applications
US6463465B1 (en) * 1999-05-07 2002-10-08 Sun Microsystems, Inc. System for facilitating remote access to parallel file system in a network using priviliged kernel mode and unpriviliged user mode to avoid processing failure
US6694470B1 (en) * 1999-05-21 2004-02-17 Panasonic Communications Co., Ltd. Retransmission procedure and apparatus for handshaking protocol
US7546263B2 (en) 1999-06-18 2009-06-09 Thomson Holdings Llc System, method and computer readable medium containing instructions for evaluating and disseminating securities analyst performance information
US7016872B1 (en) * 1999-06-18 2006-03-21 Thomson Financial Inc. System, method and computer readable medium containing instructions for evaluating and disseminating investor performance information
FR2796482B1 (en) 1999-07-16 2002-09-06 Touchtunes Music Corp REMOTE MANAGEMENT SYSTEM FOR AT LEAST ONE AUDIOVISUAL INFORMATION REPRODUCING DEVICE
US7159030B1 (en) * 1999-07-30 2007-01-02 Intel Corporation Associating a packet with a flow
US7634453B1 (en) 1999-08-13 2009-12-15 Storage Technology Corporation Distributed file data location
AU7060300A (en) 1999-08-16 2001-03-13 Iready Corporation Internet jack
US6499058B1 (en) 1999-09-09 2002-12-24 Motokazu Hozumi File shared apparatus and its method file processing apparatus and its method recording medium in which file shared program is recorded and recording medium in which file processing program is recorded
DE60038448T2 (en) 1999-10-14 2009-04-02 Bluearc Uk Ltd. DEVICE AND METHOD FOR HARDWARE DEVELOPMENT OR HARDWARE ACCELERATION OF OPERATING SYSTEM FUNCTIONS
US6876991B1 (en) 1999-11-08 2005-04-05 Collaborative Decision Platforms, Llc. System, method and computer program product for a collaborative decision platform
FR2805377B1 (en) 2000-02-23 2003-09-12 Touchtunes Music Corp EARLY ORDERING PROCESS FOR A SELECTION, DIGITAL SYSTEM AND JUKE-BOX FOR IMPLEMENTING THE METHOD
US20020013858A1 (en) * 2000-02-09 2002-01-31 Anderson Keith R. ARP caching apparatus and method
US6438498B1 (en) 2000-02-10 2002-08-20 I-Stat Corporation System, method and computer implemented process for assaying coagulation in fluid samples
US6757291B1 (en) 2000-02-10 2004-06-29 Simpletech, Inc. System for bypassing a server to achieve higher throughput between data network and data storage system
FR2805072B1 (en) 2000-02-16 2002-04-05 Touchtunes Music Corp METHOD FOR ADJUSTING THE SOUND VOLUME OF A DIGITAL SOUND RECORDING
FR2805060B1 (en) 2000-02-16 2005-04-08 Touchtunes Music Corp METHOD FOR RECEIVING FILES DURING DOWNLOAD
US6704730B2 (en) 2000-02-18 2004-03-09 Avamar Technologies, Inc. Hash file system and method for use in a commonality factoring system
US7194504B2 (en) * 2000-02-18 2007-03-20 Avamar Technologies, Inc. System and method for representing and maintaining redundant data sets utilizing DNA transmission and transcription techniques
US7509420B2 (en) 2000-02-18 2009-03-24 Emc Corporation System and method for intelligent, globally distributed network storage
US6826711B2 (en) 2000-02-18 2004-11-30 Avamar Technologies, Inc. System and method for data protection with multidimensional parity
US7062648B2 (en) * 2000-02-18 2006-06-13 Avamar Technologies, Inc. System and method for redundant array network storage
WO2001069405A1 (en) * 2000-03-14 2001-09-20 Joseph Robert Marchese Digital video system using networked cameras
US7139743B2 (en) 2000-04-07 2006-11-21 Washington University Associative database scanning and information retrieval using FPGA devices
US6845387B1 (en) 2000-04-07 2005-01-18 Advanced Digital Information Corporation Creating virtual private connections between end points across a SAN
US8095508B2 (en) * 2000-04-07 2012-01-10 Washington University Intelligent data storage and processing using FPGA devices
US6711558B1 (en) * 2000-04-07 2004-03-23 Washington University Associative database scanning and information retrieval
FR2808906B1 (en) 2000-05-10 2005-02-11 Touchtunes Music Corp DEVICE AND METHOD FOR REMOTELY MANAGING A NETWORK OF AUDIOVISUAL INFORMATION REPRODUCTION SYSTEMS
US6684270B1 (en) * 2000-06-02 2004-01-27 Nortel Networks Limited Accelerated file system that recognizes and reroutes uncontested read operations to a second faster path for use in high-capacity data transfer systems
FR2811175B1 (en) 2000-06-29 2002-12-27 Touchtunes Music Corp AUDIOVISUAL INFORMATION DISTRIBUTION METHOD AND AUDIOVISUAL INFORMATION DISTRIBUTION SYSTEM
FR2811114B1 (en) 2000-06-29 2002-12-27 Touchtunes Music Corp DEVICE AND METHOD FOR COMMUNICATION BETWEEN A SYSTEM FOR REPRODUCING AUDIOVISUAL INFORMATION AND AN ELECTRONIC ENTERTAINMENT MACHINE
US8281022B1 (en) 2000-06-30 2012-10-02 Emc Corporation Method and apparatus for implementing high-performance, scaleable data processing and storage systems
US6498937B1 (en) 2000-07-14 2002-12-24 Trw Inc. Asymmetric bandwidth wireless communication techniques
US7562028B1 (en) 2000-07-24 2009-07-14 Donner Irah H System and method for determining and/or transmitting and/or establishing communication with a mobile device user for providing, for example, concessions, tournaments, competitions, matching, reallocating, upgrading, selling tickets, and other event admittance mean
US7386517B1 (en) 2000-07-24 2008-06-10 Donner Irah H System and method for determining and/or transmitting and/or establishing communication with a mobile device user for providing, for example, concessions, tournaments, competitions, matching, reallocating, upgrading, selling tickets, other event admittance means, goods and/or services
US7562051B1 (en) 2000-07-24 2009-07-14 Donner Irah H System and method for reallocating and/or upgrading and/or selling tickets, other event admittance means, goods and/or services
US7280975B1 (en) 2000-07-24 2007-10-09 Donner Irah H System and method for determining and/or transmitting and/or establishing communication with a mobile device user for providing, for example, concessions, tournaments, competitions, matching, reallocating, upgrading, selling tickets, other event admittance means, goods and/or services
US7031945B1 (en) 2000-07-24 2006-04-18 Donner Irah H System and method for reallocating and/or upgrading and/or rewarding tickets, other event admittance means, goods and/or services
US7216109B1 (en) 2000-07-24 2007-05-08 Donner Irah H System and method for reallocating and/or upgrading and/or selling tickets, other event admittance means, goods and/or services
US7162454B1 (en) 2000-07-24 2007-01-09 Donner Irah H System and method for reallocating and/or upgrading and/or selling tickets, other even admittance means, goods and/or services
US6728897B1 (en) 2000-07-25 2004-04-27 Network Appliance, Inc. Negotiating takeover in high availability cluster
AU2001286449A1 (en) * 2000-08-11 2002-02-25 3Ware, Inc. Architecture for providing block-level storage access over computer network
US6728922B1 (en) 2000-08-18 2004-04-27 Network Appliance, Inc. Dynamic data space
US6636879B1 (en) * 2000-08-18 2003-10-21 Network Appliance, Inc. Space allocation in a write anywhere file system
US6842770B1 (en) * 2000-08-18 2005-01-11 Apple Computer, Inc. Method and system for seamlessly accessing remotely stored files
US7072916B1 (en) 2000-08-18 2006-07-04 Network Appliance, Inc. Instant snapshot
FR2814085B1 (en) 2000-09-15 2005-02-11 Touchtunes Music Corp ENTERTAINMENT METHOD BASED ON MULTIPLE CHOICE COMPETITION GAMES
US6757894B2 (en) 2000-09-26 2004-06-29 Appstream, Inc. Preprocessed applications suitable for network streaming applications and method for producing same
US20020087717A1 (en) 2000-09-26 2002-07-04 Itzik Artzi Network streaming of multi-application program code
US8019901B2 (en) * 2000-09-29 2011-09-13 Alacritech, Inc. Intelligent network storage interface system
US6654912B1 (en) * 2000-10-04 2003-11-25 Network Appliance, Inc. Recovery of file system data in file servers mirrored file system volumes
US6720074B2 (en) * 2000-10-26 2004-04-13 Inframat Corporation Insulator coated magnetic nanoparticulate composites with reduced core loss and method of manufacture thereof
US6810398B2 (en) * 2000-11-06 2004-10-26 Avamar Technologies, Inc. System and method for unorchestrated determination of data sequences using sticky byte factoring to determine breakpoints in digital sequences
US7039717B2 (en) 2000-11-10 2006-05-02 Nvidia Corporation Internet modem streaming socket method
US7596139B2 (en) * 2000-11-17 2009-09-29 Foundry Networks, Inc. Backplane interface adapter with error control and redundant fabric
US6716589B2 (en) 2000-11-20 2004-04-06 Alphabeta Ab Discordant helix stabilization for prevention of amyloid formation
EP1209638B1 (en) * 2000-11-24 2006-08-09 Caliel S.r.l. System for distributing files containing digital data using a computer network
US20020108115A1 (en) * 2000-12-11 2002-08-08 The Associated Press News and other information delivery system and method
US6868417B2 (en) 2000-12-18 2005-03-15 Spinnaker Networks, Inc. Mechanism for handling file level and block level remote file accesses using the same server
US7165096B2 (en) * 2000-12-22 2007-01-16 Data Plow, Inc. Storage area network file system
US6907457B2 (en) 2001-01-25 2005-06-14 Dell Inc. Architecture for access to embedded files using a SAN intermediate device
US7379475B2 (en) 2002-01-25 2008-05-27 Nvidia Corporation Communications processor
US6990667B2 (en) 2001-01-29 2006-01-24 Adaptec, Inc. Server-independent object positioning for load balancing drives and servers
US6990547B2 (en) * 2001-01-29 2006-01-24 Adaptec, Inc. Replacing file system processors by hot swapping
US20020138559A1 (en) * 2001-01-29 2002-09-26 Ulrich Thomas R. Dynamically distributed file system
US7054927B2 (en) 2001-01-29 2006-05-30 Adaptec, Inc. File system metadata describing server directory information
US6754773B2 (en) 2001-01-29 2004-06-22 Snap Appliance, Inc. Data engine with metadata processor
KR100372090B1 (en) * 2001-01-29 2003-02-14 한국과학기술원 Virtually Spanning 2D Array Architecture and Memory Mapping Method for Embedded 3D Graphics Accelerator
US6862692B2 (en) 2001-01-29 2005-03-01 Adaptec, Inc. Dynamic redistribution of parity groups
US7171494B2 (en) * 2001-01-31 2007-01-30 Hewlett-Packard Development Company, L.P. Extending a standard-based remote file access protocol and maintaining compatibility with a standard protocol stack
JP4700204B2 (en) * 2001-03-07 2011-06-15 株式会社日立製作所 Storage management data control system
US8244864B1 (en) 2001-03-20 2012-08-14 Microsoft Corporation Transparent migration of TCP based connections within a network load balancing system
US6836839B2 (en) 2001-03-22 2004-12-28 Quicksilver Technology, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US7653710B2 (en) 2002-06-25 2010-01-26 Qst Holdings, Llc. Hardware task manager
US7752419B1 (en) 2001-03-22 2010-07-06 Qst Holdings, Llc Method and system for managing hardware resources to implement system functions using an adaptive computing architecture
US7249242B2 (en) 2002-10-28 2007-07-24 Nvidia Corporation Input pipeline registers for a node in an adaptive computing engine
US7962716B2 (en) 2001-03-22 2011-06-14 Qst Holdings, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US6604740B1 (en) 2001-03-28 2003-08-12 Ptt, Llc Slot machine game having a plurality of ways to designate one or more wild symbols (select-a-wild)
US8218555B2 (en) * 2001-04-24 2012-07-10 Nvidia Corporation Gigabit ethernet adapter
US6577678B2 (en) * 2001-05-08 2003-06-10 Quicksilver Technology Method and system for reconfigurable channel coding
US20030037061A1 (en) * 2001-05-08 2003-02-20 Gautham Sastri Data storage system for a multi-client network and method of managing such system
US20060020688A1 (en) * 2001-05-14 2006-01-26 At&T Corp. System having generalized client-server computing
US7469295B1 (en) 2001-06-25 2008-12-23 Network Appliance, Inc. Modified round robin load balancing technique based on IP identifier
US6928478B1 (en) * 2001-06-25 2005-08-09 Network Appliance, Inc. Method and apparatus for implementing a MAC address pool for assignment to a virtual interface aggregate
US6643654B1 (en) 2001-06-25 2003-11-04 Network Appliance, Inc. System and method for representing named data streams within an on-disk structure of a file system
US6944785B2 (en) * 2001-07-23 2005-09-13 Network Appliance, Inc. High-availability cluster virtual server system
JP4156817B2 (en) * 2001-07-27 2008-09-24 株式会社日立製作所 Storage system
US7685126B2 (en) 2001-08-03 2010-03-23 Isilon Systems, Inc. System and methods for providing a distributed file system utilizing metadata to track information about data stored throughout the system
US7146524B2 (en) * 2001-08-03 2006-12-05 Isilon Systems, Inc. Systems and methods for providing a distributed file system incorporating a virtual hot spare
US6757695B1 (en) 2001-08-09 2004-06-29 Network Appliance, Inc. System and method for mounting and unmounting storage volumes in a network storage environment
US6851070B1 (en) 2001-08-13 2005-02-01 Network Appliance, Inc. System and method for managing time-limited long-running operations in a data storage system
US6965989B1 (en) 2001-08-14 2005-11-15 Network Appliance, Inc. System and method for fast reboot of a file server
US6920579B1 (en) 2001-08-20 2005-07-19 Network Appliance, Inc. Operator initiated graceful takeover in a node cluster
US7536495B2 (en) * 2001-09-28 2009-05-19 Dot Hill Systems Corporation Certified memory-to-memory data transfer between active-active raid controllers
US7437493B2 (en) * 2001-09-28 2008-10-14 Dot Hill Systems Corp. Modular architecture for a network storage controller
US7340555B2 (en) 2001-09-28 2008-03-04 Dot Hill Systems Corporation RAID system for performing efficient mirrored posted-write operations
US7315911B2 (en) * 2005-01-20 2008-01-01 Dot Hill Systems Corporation Method for efficient inter-processor communication in an active-active RAID system using PCI-express links
US7143227B2 (en) * 2003-02-18 2006-11-28 Dot Hill Systems Corporation Broadcast bridge apparatus for transferring data to redundant memory subsystems in a storage controller
US7146448B2 (en) * 2001-09-28 2006-12-05 Dot Hill Systems Corporation Apparatus and method for adopting an orphan I/O port in a redundant storage controller
US7062591B2 (en) * 2001-09-28 2006-06-13 Dot Hill Systems Corp. Controller data sharing using a modular DMA architecture
US7351146B2 (en) 2001-10-05 2008-04-01 Igt Gaming device and method for activating multiple paylines upon the wager of a single credit
US6996670B2 (en) * 2001-10-05 2006-02-07 International Business Machines Corporation Storage area network methods and apparatus with file system extension
US7716330B2 (en) 2001-10-19 2010-05-11 Global Velocity, Inc. System and method for controlling transmission of data packets over an information network
US6931501B1 (en) * 2001-10-26 2005-08-16 Adaptec, Inc. Method and apparatus for merging contiguous like commands
US7380115B2 (en) * 2001-11-09 2008-05-27 Dot Hill Systems Corp. Transferring data using direct memory access
US7346831B1 (en) 2001-11-13 2008-03-18 Network Appliance, Inc. Parity assignment technique for parity declustering in a parity array of a storage system
US6851082B1 (en) 2001-11-13 2005-02-01 Network Appliance, Inc. Concentrated parity technique for handling double failures and enabling storage of more than one parity block per stripe on a storage device of a storage array
US7046635B2 (en) 2001-11-28 2006-05-16 Quicksilver Technology, Inc. System for authorizing functionality in adaptable hardware devices
US6986021B2 (en) 2001-11-30 2006-01-10 Quick Silver Technology, Inc. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements
US8412915B2 (en) 2001-11-30 2013-04-02 Altera Corporation Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements
US7730153B1 (en) 2001-12-04 2010-06-01 Netapp, Inc. Efficient use of NVRAM during takeover in a node cluster
US7215701B2 (en) 2001-12-12 2007-05-08 Sharad Sambhwani Low I/O bandwidth method and system for implementing detection and identification of scrambling codes
US20030115350A1 (en) * 2001-12-14 2003-06-19 Silverback Systems, Inc. System and method for efficient handling of network data
US7159080B1 (en) 2001-12-20 2007-01-02 Network Appliance, Inc. System and method for storing storage operating system data in switch ports
US7146522B1 (en) 2001-12-21 2006-12-05 Network Appliance, Inc. System and method for allocating spare disks in networked storage
US7650412B2 (en) 2001-12-21 2010-01-19 Netapp, Inc. Systems and method of implementing disk ownership in networked storage
US6836832B1 (en) 2001-12-21 2004-12-28 Network Appliance, Inc. System and method for pre-selecting candidate disks based on validity for volume
US7296068B1 (en) * 2001-12-21 2007-11-13 Network Appliance, Inc. System and method for transfering volume ownership in net-worked storage
US8402346B2 (en) * 2001-12-28 2013-03-19 Netapp, Inc. N-way parity technique for enabling recovery from up to N storage device failures
US7640484B2 (en) * 2001-12-28 2009-12-29 Netapp, Inc. Triple parity technique for enabling efficient recovery from triple failures in a storage array
US7360034B1 (en) * 2001-12-28 2008-04-15 Network Appliance, Inc. Architecture for creating and maintaining virtual filers on a filer
US7613984B2 (en) * 2001-12-28 2009-11-03 Netapp, Inc. System and method for symmetric triple parity for failing storage devices
US6895429B2 (en) * 2001-12-28 2005-05-17 Network Appliance, Inc. Technique for enabling multiple virtual filers on a single filer to participate in multiple address spaces with overlapping network addresses
US7073115B2 (en) * 2001-12-28 2006-07-04 Network Appliance, Inc. Correcting multiple block data loss in a storage array using a combination of a single diagonal parity group and multiple row parity groups
US6993701B2 (en) 2001-12-28 2006-01-31 Network Appliance, Inc. Row-diagonal parity technique for enabling efficient recovery from double failures in a storage array
US20030121835A1 (en) * 2001-12-31 2003-07-03 Peter Quartararo Apparatus for and method of sieving biocompatible adsorbent beaded polymers
US7403981B2 (en) * 2002-01-04 2008-07-22 Quicksilver Technology, Inc. Apparatus and method for adaptive multimedia reception and transmission in communication environments
JP2005515556A (en) * 2002-01-15 2005-05-26 ネットワーク アプライアンス, インコーポレイテッド Active file change notification
US7523216B1 (en) 2002-02-01 2009-04-21 Network Appliance, Inc. System and method for using an endian-neutral data packet to define subsequent data packet byte-order
US6922757B2 (en) * 2002-02-15 2005-07-26 Exanet Inc. Flexible and adaptive read and write storage system architecture
US6968345B1 (en) * 2002-02-27 2005-11-22 Network Appliance, Inc. Technique to enable support for symbolic link access by windows clients
US7039828B1 (en) 2002-02-28 2006-05-02 Network Appliance, Inc. System and method for clustered failover without network support
US6748510B1 (en) 2002-02-28 2004-06-08 Network Appliance, Inc. System and method for verifying disk configuration
US7389315B1 (en) 2002-02-28 2008-06-17 Network Appliance, Inc. System and method for byte swapping file access data structures
US7373364B1 (en) 2002-03-05 2008-05-13 Network Appliance, Inc. System and method for creating a point-in-time restoration of a database file
US20030169742A1 (en) * 2002-03-06 2003-09-11 Twomey John M. Communicating voice payloads between disparate processors
US7535913B2 (en) 2002-03-06 2009-05-19 Nvidia Corporation Gigabit ethernet adapter supporting the iSCSI and IPSEC protocols
US7210068B1 (en) 2002-03-06 2007-04-24 Network Appliance, Inc. System and method for multipath I/O support for fibre channel devices
US7080278B1 (en) 2002-03-08 2006-07-18 Network Appliance, Inc. Technique for correcting multiple storage device failures in a storage array
US7194519B1 (en) 2002-03-15 2007-03-20 Network Appliance, Inc. System and method for administering a filer having a plurality of virtual filers
US7143307B1 (en) 2002-03-15 2006-11-28 Network Appliance, Inc. Remote disaster recovery and data migration using virtual appliance migration
US7313557B1 (en) 2002-03-15 2007-12-25 Network Appliance, Inc. Multi-protocol lock manager
US6993539B2 (en) 2002-03-19 2006-01-31 Network Appliance, Inc. System and method for determining changes in two snapshots and for transmitting changes to destination snapshot
US7467167B2 (en) * 2002-03-19 2008-12-16 Network Appliance, Inc. System and method for coalescing a plurality of snapshots
US7051050B2 (en) * 2002-03-19 2006-05-23 Netwrok Appliance, Inc. System and method for restoring a single file from a snapshot
US7010553B2 (en) * 2002-03-19 2006-03-07 Network Appliance, Inc. System and method for redirecting access to a remote mirrored snapshot
US7043485B2 (en) * 2002-03-19 2006-05-09 Network Appliance, Inc. System and method for storage of snapshot metadata in a remote file
US7039663B1 (en) 2002-04-19 2006-05-02 Network Appliance, Inc. System and method for checkpointing and restarting an asynchronous transfer of data between a source and destination snapshot
US7007046B2 (en) 2002-03-19 2006-02-28 Network Appliance, Inc. Format for transmission file system information between a source and a destination
US7475098B2 (en) * 2002-03-19 2009-01-06 Network Appliance, Inc. System and method for managing a plurality of snapshots
US7225204B2 (en) * 2002-03-19 2007-05-29 Network Appliance, Inc. System and method for asynchronous mirroring of snapshots at a destination using a purgatory directory and inode mapping
US7539991B2 (en) 2002-03-21 2009-05-26 Netapp, Inc. Method and apparatus for decomposing I/O tasks in a raid system
US7254813B2 (en) * 2002-03-21 2007-08-07 Network Appliance, Inc. Method and apparatus for resource allocation in a raid system
US7200715B2 (en) 2002-03-21 2007-04-03 Network Appliance, Inc. Method for writing contiguous arrays of stripes in a RAID storage system using mapped block writes
US7437727B2 (en) * 2002-03-21 2008-10-14 Network Appliance, Inc. Method and apparatus for runtime resource deadlock avoidance in a raid system
US6895413B2 (en) * 2002-03-22 2005-05-17 Network Appliance, Inc. System and method for performing an on-line check of a file system
US7072910B2 (en) * 2002-03-22 2006-07-04 Network Appliance, Inc. File folding technique
US7418500B1 (en) 2002-03-25 2008-08-26 Network Appliance, Inc. Mechanism for controlled sharing of files in a clustered application environment
WO2003082076A2 (en) 2002-03-25 2003-10-09 Nmt Medical, Inc. Patent foramen ovale (pfo) closure clips
US8095503B2 (en) * 2002-03-29 2012-01-10 Panasas, Inc. Allowing client systems to interpret higher-revision data structures in storage systems
US20030188031A1 (en) * 2002-03-29 2003-10-02 Alan Deikman Network controller with pseudo network interface device drivers to control remote network interfaces
US7155458B1 (en) 2002-04-05 2006-12-26 Network Appliance, Inc. Mechanism for distributed atomic creation of client-private files
KR20030080443A (en) * 2002-04-08 2003-10-17 (주) 위즈네트 Internet protocol system using hardware protocol processing logic and the parallel data processing method using the same
US6993733B2 (en) * 2002-04-09 2006-01-31 Atrenta, Inc. Apparatus and method for handling of multi-level circuit design data
US7543087B2 (en) 2002-04-22 2009-06-02 Alacritech, Inc. Freeing transmit memory on a network interface device prior to receiving an acknowledgement that transmit data has been received by a remote device
US7496689B2 (en) 2002-04-22 2009-02-24 Alacritech, Inc. TCP/IP offload device
US7707263B1 (en) 2002-05-03 2010-04-27 Netapp, Inc. System and method for associating a network address with a storage device
US7187687B1 (en) 2002-05-06 2007-03-06 Foundry Networks, Inc. Pipeline method and system for switching packets
US7660984B1 (en) 2003-05-13 2010-02-09 Quicksilver Technology Method and system for achieving individualized protected space in an operating system
US7328414B1 (en) 2003-05-13 2008-02-05 Qst Holdings, Llc Method and system for creating and programming an adaptive computing engine
US6976146B1 (en) 2002-05-21 2005-12-13 Network Appliance, Inc. System and method for emulating block appended checksums on storage devices by sector stealing
US7093023B2 (en) * 2002-05-21 2006-08-15 Washington University Methods, systems, and devices using reprogrammable hardware for high-speed processing of streaming data to find a redefinable pattern and respond thereto
US7010528B2 (en) * 2002-05-23 2006-03-07 International Business Machines Corporation Mechanism for running parallel application programs on metadata controller nodes
US7448077B2 (en) * 2002-05-23 2008-11-04 International Business Machines Corporation File level security for a metadata controller in a storage area network
US20030220943A1 (en) * 2002-05-23 2003-11-27 International Business Machines Corporation Recovery of a single metadata controller failure in a storage area network environment
US7073022B2 (en) 2002-05-23 2006-07-04 International Business Machines Corporation Serial interface for a data storage array
US8140622B2 (en) 2002-05-23 2012-03-20 International Business Machines Corporation Parallel metadata service in storage area network environment
US20040047519A1 (en) * 2002-09-05 2004-03-11 Axs Technologies Dynamic image repurposing apparatus and method
EP1538994A4 (en) 2002-06-05 2008-05-07 Nmt Medical Inc Patent foramen ovale (pfo) closure device with radial and circumferential support
US20030228071A1 (en) * 2002-06-05 2003-12-11 Axs Technologies Parallel resampling of image data
US8051213B2 (en) * 2002-06-06 2011-11-01 International Business Machines Corporation Method for server-directed packet forwarding by a network controller based on a packet buffer threshold
US7315896B2 (en) 2002-06-06 2008-01-01 International Business Machines Corporation Server network controller including packet forwarding and method therefor
US7783787B1 (en) 2002-06-13 2010-08-24 Netapp, Inc. System and method for reprioritizing high-latency input/output operations
US7584279B1 (en) 2002-07-02 2009-09-01 Netapp, Inc. System and method for mapping block-based file operations to file level protocols
US7386546B1 (en) 2002-07-09 2008-06-10 Network Appliance, Inc. Metadirectory namespace and method for use of the same
JP2004054721A (en) * 2002-07-23 2004-02-19 Hitachi Ltd Network storage virtualization method
US8417678B2 (en) 2002-07-30 2013-04-09 Storediq, Inc. System, method and apparatus for enterprise policy management
US7805449B1 (en) 2004-10-28 2010-09-28 Stored IQ System, method and apparatus for enterprise policy management
WO2004012379A2 (en) * 2002-07-30 2004-02-05 Deepfile Corporation Method and apparatus for managing file systems and file-based data storage
US8612404B2 (en) 2002-07-30 2013-12-17 Stored Iq, Inc. Harvesting file system metsdata
US7107385B2 (en) * 2002-08-09 2006-09-12 Network Appliance, Inc. Storage virtualization by layering virtual disk objects on a file system
US7873700B2 (en) * 2002-08-09 2011-01-18 Netapp, Inc. Multi-protocol storage appliance that provides integrated support for file and block access protocols
US7711539B1 (en) 2002-08-12 2010-05-04 Netapp, Inc. System and method for emulating SCSI reservations using network file access protocols
US6983296B1 (en) 2002-08-12 2006-01-03 Network Appliance, Inc. System and method for tracking modified files in a file system
US7711844B2 (en) 2002-08-15 2010-05-04 Washington University Of St. Louis TCP-splitter: reliable packet monitoring methods and apparatus for high speed networks
US7346701B2 (en) 2002-08-30 2008-03-18 Broadcom Corporation System and method for TCP offload
US8108656B2 (en) 2002-08-29 2012-01-31 Qst Holdings, Llc Task definition for specifying resource requirements
US7934021B2 (en) 2002-08-29 2011-04-26 Broadcom Corporation System and method for network interfacing
US7313623B2 (en) * 2002-08-30 2007-12-25 Broadcom Corporation System and method for TCP/IP offload independent of bandwidth delay product
US8180928B2 (en) 2002-08-30 2012-05-15 Broadcom Corporation Method and system for supporting read operations with CRC for iSCSI and iSCSI chimney
WO2004021626A2 (en) 2002-08-30 2004-03-11 Broadcom Corporation System and method for handling out-of-order frames
US8584175B2 (en) 2002-09-16 2013-11-12 Touchtunes Music Corporation Digital downloading jukebox system with user-tailored music management, communications, and other tools
GB2409553B (en) 2002-09-16 2007-04-04 Commvault Systems Inc System and method for optimizing storage operations
US10373420B2 (en) 2002-09-16 2019-08-06 Touchtunes Music Corporation Digital downloading jukebox with enhanced communication features
US8103589B2 (en) 2002-09-16 2012-01-24 Touchtunes Music Corporation Digital downloading jukebox system with central and local music servers
US8332895B2 (en) 2002-09-16 2012-12-11 Touchtunes Music Corporation Digital downloading jukebox system with user-tailored music management, communications, and other tools
US9646339B2 (en) 2002-09-16 2017-05-09 Touchtunes Music Corporation Digital downloading jukebox system with central and local music servers
US11029823B2 (en) 2002-09-16 2021-06-08 Touchtunes Music Corporation Jukebox with customizable avatar
US7822687B2 (en) 2002-09-16 2010-10-26 Francois Brillon Jukebox with customizable avatar
US8151304B2 (en) 2002-09-16 2012-04-03 Touchtunes Music Corporation Digital downloading jukebox system with user-tailored music management, communications, and other tools
US7426576B1 (en) 2002-09-20 2008-09-16 Network Appliance, Inc. Highly available DNS resolver and method for use of the same
US7337241B2 (en) 2002-09-27 2008-02-26 Alacritech, Inc. Fast-path apparatus for receiving data corresponding to a TCP connection
US7191241B2 (en) 2002-09-27 2007-03-13 Alacritech, Inc. Fast-path apparatus for receiving data corresponding to a TCP connection
US7707184B1 (en) 2002-10-09 2010-04-27 Netapp, Inc. System and method for snapshot full backup and hard recovery of a database
US7340486B1 (en) 2002-10-10 2008-03-04 Network Appliance, Inc. System and method for file system snapshot of a virtual logical disk
US7152069B1 (en) * 2002-10-15 2006-12-19 Network Appliance, Inc. Zero copy writes through use of mbufs
US7937591B1 (en) 2002-10-25 2011-05-03 Qst Holdings, Llc Method and system for providing a device which can be adapted on an ongoing basis
US7766820B2 (en) 2002-10-25 2010-08-03 Nmt Medical, Inc. Expandable sheath tubing
US7171452B1 (en) 2002-10-31 2007-01-30 Network Appliance, Inc. System and method for monitoring cluster partner boot status over a cluster interconnect
US7457822B1 (en) 2002-11-01 2008-11-25 Bluearc Uk Limited Apparatus and method for hardware-based file system
US8041735B1 (en) 2002-11-01 2011-10-18 Bluearc Uk Limited Distributed file system and method
US8276135B2 (en) 2002-11-07 2012-09-25 Qst Holdings Llc Profiling of software and circuit designs utilizing data operation analyses
AU2003291014A1 (en) * 2002-11-14 2004-06-15 Isilon Systems, Inc. Systems and methods for restriping files in a distributed file system
US7225301B2 (en) 2002-11-22 2007-05-29 Quicksilver Technologies External memory controller node
JP4186602B2 (en) * 2002-12-04 2008-11-26 株式会社日立製作所 Update data writing method using journal log
US9017373B2 (en) 2002-12-09 2015-04-28 W.L. Gore & Associates, Inc. Septal closure devices
US6944733B2 (en) * 2002-12-11 2005-09-13 Intel Corporation Data storage using wireless communication
US7254696B2 (en) * 2002-12-12 2007-08-07 Alacritech, Inc. Functional-level instruction-set computer architecture for processing application-layer content-service requests such as file-access requests
JP4542308B2 (en) * 2002-12-16 2010-09-15 株式会社ソニー・コンピュータエンタテインメント Signal processing device and information processing device
US7069307B1 (en) 2002-12-20 2006-06-27 Network Appliance, Inc. System and method for inband management of a virtual disk
US8041761B1 (en) 2002-12-23 2011-10-18 Netapp, Inc. Virtual filer and IP space based IT configuration transitioning framework
JP2004213435A (en) * 2003-01-07 2004-07-29 Hitachi Ltd Storage device system
US20040225730A1 (en) * 2003-01-17 2004-11-11 Brown Albert C. Content manager integration
JP2006516341A (en) * 2003-01-17 2006-06-29 タシット ネットワークス,インク. Method and system for storage caching with distributed file system
US20040216084A1 (en) * 2003-01-17 2004-10-28 Brown Albert C. System and method of managing web content
US8015266B1 (en) 2003-02-07 2011-09-06 Netapp, Inc. System and method for providing persistent node names
US7809693B2 (en) * 2003-02-10 2010-10-05 Netapp, Inc. System and method for restoring data on demand for instant volume restoration
US7197490B1 (en) 2003-02-10 2007-03-27 Network Appliance, Inc. System and method for lazy-copy sub-volume load balancing in a network attached storage pool
WO2004077211A2 (en) * 2003-02-28 2004-09-10 Tilmon Systems Ltd. Method and apparatus for increasing file server performance by offloading data path processing
US7231489B1 (en) 2003-03-03 2007-06-12 Network Appliance, Inc. System and method for coordinating cluster state information
US7809679B2 (en) * 2003-03-03 2010-10-05 Fisher-Rosemount Systems, Inc. Distributed data access methods and apparatus for process control systems
US7185144B2 (en) * 2003-11-24 2007-02-27 Network Appliance, Inc. Semi-static distribution technique
US7155460B2 (en) * 2003-03-18 2006-12-26 Network Appliance, Inc. Write-once-read-many storage system and method for implementing the same
US7231409B1 (en) 2003-03-21 2007-06-12 Network Appliance, Inc. System and method for reallocating blocks in checkpointing bitmap-based file systems
US7664913B2 (en) * 2003-03-21 2010-02-16 Netapp, Inc. Query-based spares management technique
US7111021B1 (en) 2003-03-21 2006-09-19 Network Appliance, Inc. System and method for efficient space accounting in a file system with snapshots
US7424637B1 (en) 2003-03-21 2008-09-09 Networks Appliance, Inc. Technique for managing addition of disks to a volume of a storage system
US7111147B1 (en) * 2003-03-21 2006-09-19 Network Appliance, Inc. Location-independent RAID group virtual block management
US7328364B1 (en) 2003-03-21 2008-02-05 Network Appliance, Inc. Technique for coherent suspension of I/O operations in a RAID subsystem
US7143235B1 (en) 2003-03-21 2006-11-28 Network Appliance, Inc. Proposed configuration management behaviors in a raid subsystem
US7383378B1 (en) 2003-04-11 2008-06-03 Network Appliance, Inc. System and method for supporting file and block access to storage object on a storage appliance
US7457982B2 (en) 2003-04-11 2008-11-25 Network Appliance, Inc. Writable virtual disk of read-only snapshot file objects
US7293203B1 (en) 2003-04-23 2007-11-06 Network Appliance, Inc. System and method for logging disk failure analysis in disk nonvolatile memory
US7191437B1 (en) 2003-04-23 2007-03-13 Network Appliance, Inc. System and method for reliable disk firmware update within a networked storage fabric
US7739543B1 (en) 2003-04-23 2010-06-15 Netapp, Inc. System and method for transport-level failover for loosely coupled iSCSI target devices
US7293152B1 (en) 2003-04-23 2007-11-06 Network Appliance, Inc. Consistent logical naming of initiator groups
US7260737B1 (en) 2003-04-23 2007-08-21 Network Appliance, Inc. System and method for transport-level failover of FCP devices in a cluster
US7275179B1 (en) 2003-04-24 2007-09-25 Network Appliance, Inc. System and method for reducing unrecoverable media errors in a disk subsystem
US7437530B1 (en) 2003-04-24 2008-10-14 Network Appliance, Inc. System and method for mapping file block numbers to logical block addresses
US7330862B1 (en) 2003-04-25 2008-02-12 Network Appliance, Inc. Zero copy write datapath
US7603553B1 (en) 2003-04-25 2009-10-13 Netapp, Inc. System and method to make file handles opaque to clients
US7577692B1 (en) 2003-04-25 2009-08-18 Netapp, Inc. System and method for reserving space to guarantee file writability in a file system supporting persistent consistency point images
US7437523B1 (en) 2003-04-25 2008-10-14 Network Appliance, Inc. System and method for on-the-fly file folding in a replicated storage system
US7181439B1 (en) * 2003-04-25 2007-02-20 Network Appliance, Inc. System and method for transparently accessing a virtual disk using a file-based protocol
US6901072B1 (en) 2003-05-15 2005-05-31 Foundry Networks, Inc. System and method for high speed packet transmission implementing dual transmit and receive pipelines
CA2523548C (en) 2003-05-23 2014-02-04 Washington University Intelligent data processing system and method using fpga devices
US10572824B2 (en) 2003-05-23 2020-02-25 Ip Reservoir, Llc System and method for low latency multi-functional pipeline with correlation logic and selectively activated/deactivated pipelined data processing engines
JP4329412B2 (en) * 2003-06-02 2009-09-09 株式会社日立製作所 File server system
GB0313012D0 (en) 2003-06-06 2003-07-09 Igt Uk Ltd Entertainment machines
US7523201B2 (en) * 2003-07-14 2009-04-21 Network Appliance, Inc. System and method for optimized lun masking
CA2532112C (en) 2003-07-14 2012-09-18 Nmt Medical, Inc. Tubular patent foramen ovale (pfo) closure device with catch system
US9861346B2 (en) 2003-07-14 2018-01-09 W. L. Gore & Associates, Inc. Patent foramen ovale (PFO) closure device with linearly elongating petals
US8480706B2 (en) 2003-07-14 2013-07-09 W.L. Gore & Associates, Inc. Tubular patent foramen ovale (PFO) closure device with catch system
US7716323B2 (en) * 2003-07-18 2010-05-11 Netapp, Inc. System and method for reliable peer communication in a clustered storage system
US7593996B2 (en) 2003-07-18 2009-09-22 Netapp, Inc. System and method for establishing a peer connection using reliable RDMA primitives
US8473693B1 (en) * 2003-07-29 2013-06-25 Netapp, Inc. Managing ownership of memory buffers (mbufs)
JP4297747B2 (en) * 2003-08-06 2009-07-15 株式会社日立製作所 Storage device
CA2535097A1 (en) * 2003-08-08 2005-02-17 Yottayotta, Inc. Method for embedding a server into a storage subsystem
US7055014B1 (en) 2003-08-11 2006-05-30 Network Applicance, Inc. User interface system for a multi-protocol storage appliance
DE602004017750D1 (en) 2003-08-19 2008-12-24 Nmt Medical Inc Expandable lock hose
US20050076091A1 (en) * 2003-09-11 2005-04-07 Duncan Missimer Data mirroring
US7865485B2 (en) * 2003-09-23 2011-01-04 Emc Corporation Multi-threaded write interface and methods for increasing the single file read and write throughput of a file server
JP4291664B2 (en) 2003-10-14 2009-07-08 株式会社日立製作所 Storage apparatus and system having communication buffer reservation function
US7590807B2 (en) 2003-11-03 2009-09-15 Netapp, Inc. System and method for record retention date in a write once read many storage system
US7328305B2 (en) * 2003-11-03 2008-02-05 Network Appliance, Inc. Dynamic parity distribution technique
US7721062B1 (en) 2003-11-10 2010-05-18 Netapp, Inc. Method for detecting leaked buffer writes across file system consistency points
US7783611B1 (en) 2003-11-10 2010-08-24 Netapp, Inc. System and method for managing file metadata during consistency points
US7401093B1 (en) 2003-11-10 2008-07-15 Network Appliance, Inc. System and method for managing file data during consistency points
GB2425199B (en) 2003-11-13 2007-08-15 Commvault Systems Inc System and method for combining data streams in pipelined storage operations in a storage network
US7647451B1 (en) 2003-11-24 2010-01-12 Netapp, Inc. Data placement technique for striping data containers across volumes of a storage system cluster
US7263629B2 (en) * 2003-11-24 2007-08-28 Network Appliance, Inc. Uniform and symmetric double failure correcting technique for protecting against two disk failures in a disk array
US7366837B2 (en) * 2003-11-24 2008-04-29 Network Appliance, Inc. Data placement technique for striping data containers across volumes of a storage system cluster
US7698289B2 (en) * 2003-12-02 2010-04-13 Netapp, Inc. Storage system architecture for striping data container content across volumes of a cluster
US7409497B1 (en) 2003-12-02 2008-08-05 Network Appliance, Inc. System and method for efficiently guaranteeing data consistency to clients of a storage system cluster
US6996070B2 (en) * 2003-12-05 2006-02-07 Alacritech, Inc. TCP/IP offload device with reduced sequential processing
US20050273119A1 (en) 2003-12-09 2005-12-08 Nmt Medical, Inc. Double spiral patent foramen ovale closure clamp
US8176545B1 (en) 2003-12-19 2012-05-08 Nvidia Corporation Integrated policy checking system and method
US7720801B2 (en) * 2003-12-19 2010-05-18 Netapp, Inc. System and method for supporting asynchronous data replication with very short update intervals
US8065439B1 (en) 2003-12-19 2011-11-22 Nvidia Corporation System and method for using metadata in the context of a transport offload engine
US8549170B2 (en) 2003-12-19 2013-10-01 Nvidia Corporation Retransmission system and method for a transport offload engine
US7624198B1 (en) 2003-12-19 2009-11-24 Nvidia Corporation Sequence tagging system and method for transport offload engine data lists
US7899913B2 (en) 2003-12-19 2011-03-01 Nvidia Corporation Connection management system and method for a transport offload engine
US7260631B1 (en) 2003-12-19 2007-08-21 Nvidia Corporation System and method for receiving iSCSI protocol data units
US8572289B1 (en) * 2003-12-19 2013-10-29 Nvidia Corporation System, method and computer program product for stateless offloading of upper level network protocol operations
US7478101B1 (en) 2003-12-23 2009-01-13 Networks Appliance, Inc. System-independent data format in a mirrored storage system environment and method for using the same
US7921110B1 (en) 2003-12-23 2011-04-05 Netapp, Inc. System and method for comparing data sets
US7249227B1 (en) * 2003-12-29 2007-07-24 Network Appliance, Inc. System and method for zero copy block protocol write operations
US7340639B1 (en) 2004-01-08 2008-03-04 Network Appliance, Inc. System and method for proxying data access commands in a clustered storage system
US7321982B2 (en) * 2004-01-26 2008-01-22 Network Appliance, Inc. System and method for takeover of partner resources in conjunction with coredump
US7266717B2 (en) * 2004-01-26 2007-09-04 Network Appliance, Inc. System and method of selection and communication of a disk for storage of a coredump
US8221206B2 (en) 2004-01-28 2012-07-17 Igt Gaming device having a partial selectable symbol matrix
US8041888B2 (en) 2004-02-05 2011-10-18 Netapp, Inc. System and method for LUN cloning
US7602785B2 (en) 2004-02-09 2009-10-13 Washington University Method and system for performing longest prefix matching for network address lookup using bloom filters
US7313720B1 (en) 2004-02-12 2007-12-25 Network Appliance, Inc. Technique for increasing the number of persistent consistency point images in a file system
JP2005234794A (en) * 2004-02-18 2005-09-02 Matsushita Electric Ind Co Ltd File system controller
US7249306B2 (en) 2004-02-20 2007-07-24 Nvidia Corporation System and method for generating 128-bit cyclic redundancy check values with 32-bit granularity
US7206872B2 (en) 2004-02-20 2007-04-17 Nvidia Corporation System and method for insertion of markers into a data stream
US7418646B2 (en) * 2004-03-02 2008-08-26 Intel Corporation Integrated circuit using wireless communication to store and/or retrieve data and/or check data
US7966293B1 (en) 2004-03-09 2011-06-21 Netapp, Inc. System and method for indexing a backup using persistent consistency point images
EP1577776B1 (en) * 2004-03-18 2007-05-02 Alcatel Lucent Method and apparatus for data synchronization in a distributed data base system
US7817659B2 (en) 2004-03-26 2010-10-19 Foundry Networks, Llc Method and apparatus for aggregating input data streams
US7698413B1 (en) 2004-04-12 2010-04-13 Nvidia Corporation Method and apparatus for accessing and maintaining socket control information for high speed network connections
US7739418B2 (en) * 2004-04-12 2010-06-15 Hewlett-Packard Development Company, L.P. Resource management system
US8230085B2 (en) * 2004-04-12 2012-07-24 Netapp, Inc. System and method for supporting block-based protocols on a virtual storage appliance executing within a physical storage appliance
US7409511B2 (en) * 2004-04-30 2008-08-05 Network Appliance, Inc. Cloning technique for efficiently creating a copy of a volume in a storage system
US7334094B2 (en) * 2004-04-30 2008-02-19 Network Appliance, Inc. Online clone volume splitting technique
US7409494B2 (en) 2004-04-30 2008-08-05 Network Appliance, Inc. Extension of write anywhere file system layout
US7430571B2 (en) 2004-04-30 2008-09-30 Network Appliance, Inc. Extension of write anywhere file layout write allocation
US7334095B1 (en) 2004-04-30 2008-02-19 Network Appliance, Inc. Writable clone of read-only volume
US7842053B2 (en) 2004-05-06 2010-11-30 Nmt Medical, Inc. Double coil occluder
US8308760B2 (en) 2004-05-06 2012-11-13 W.L. Gore & Associates, Inc. Delivery systems and methods for PFO closure device with two anchors
US7480749B1 (en) * 2004-05-27 2009-01-20 Nvidia Corporation Main memory as extended disk buffer memory
KR100579782B1 (en) 2004-06-02 2006-05-15 곽윤식 Group office system based on web storage and embodying method
US7353242B2 (en) * 2004-07-09 2008-04-01 Hitachi, Ltd. File server for long term data archive
CA2581677C (en) 2004-09-24 2014-07-29 Nmt Medical, Inc. Occluder device double securement system for delivery/recovery of such occluder device
US20060075281A1 (en) * 2004-09-27 2006-04-06 Kimmel Jeffrey S Use of application-level context information to detect corrupted data in a storage system
US7585219B2 (en) * 2004-09-30 2009-09-08 Igt Gaming device having a matching symbol game
US8248939B1 (en) 2004-10-08 2012-08-21 Alacritech, Inc. Transferring control of TCP connections between hierarchy of processing mechanisms
US8043155B2 (en) 2004-10-18 2011-10-25 Igt Gaming device having a plurality of wildcard symbol patterns
US7957379B2 (en) 2004-10-19 2011-06-07 Nvidia Corporation System and method for processing RX packets in high speed network applications using an RX FIFO buffer
US7730277B1 (en) 2004-10-25 2010-06-01 Netapp, Inc. System and method for using pvbn placeholders in a flexible volume of a storage system
US7984085B1 (en) 2004-10-25 2011-07-19 Network Appliance, Inc. Rate of change of data using on-the-fly accounting
US7844582B1 (en) 2004-10-28 2010-11-30 Stored IQ System and method for involving users in object management
US8510331B1 (en) 2004-10-28 2013-08-13 Storediq, Inc. System and method for a desktop agent for use in managing file systems
US8238350B2 (en) 2004-10-29 2012-08-07 Emc Corporation Message batching with checkpoints systems and methods
US8051425B2 (en) 2004-10-29 2011-11-01 Emc Corporation Distributed system with asynchronous execution systems and methods
US8055711B2 (en) 2004-10-29 2011-11-08 Emc Corporation Non-blocking commit protocol systems and methods
US7636744B1 (en) 2004-11-17 2009-12-22 Netapp, Inc. System and method for flexible space reservations in a file system supporting persistent consistency point images
US9165003B1 (en) 2004-11-29 2015-10-20 Netapp, Inc. Technique for permitting multiple virtual file systems having the same identifier to be served by a single storage system
US7707165B1 (en) 2004-12-09 2010-04-27 Netapp, Inc. System and method for managing data versions in a file system
US7506111B1 (en) 2004-12-20 2009-03-17 Network Appliance, Inc. System and method for determining a number of overwitten blocks between data containers
US7908080B2 (en) 2004-12-31 2011-03-15 Google Inc. Transportation routing
US7543096B2 (en) * 2005-01-20 2009-06-02 Dot Hill Systems Corporation Safe message transfers on PCI-Express link from RAID controller to receiver-programmable window of partner RAID controller CPU memory
US8019842B1 (en) 2005-01-27 2011-09-13 Netapp, Inc. System and method for distributing enclosure services data to coordinate shared storage
US7424497B1 (en) 2005-01-27 2008-09-09 Network Appliance, Inc. Technique for accelerating the creation of a point in time prepresentation of a virtual file system
US8180855B2 (en) 2005-01-27 2012-05-15 Netapp, Inc. Coordinated shared storage architecture
US7398460B1 (en) 2005-01-31 2008-07-08 Network Appliance, Inc. Technique for efficiently organizing and distributing parity blocks among storage devices of a storage array
US7757056B1 (en) 2005-03-16 2010-07-13 Netapp, Inc. System and method for efficiently calculating storage required to split a clone volume
JP4824085B2 (en) * 2005-04-25 2011-11-24 ネットアップ,インコーポレイテッド System and method for caching a network file system
WO2006116183A1 (en) * 2005-04-25 2006-11-02 Network Appliance, Inc. Architecture for supporting sparse volumes
US7962689B1 (en) 2005-04-29 2011-06-14 Netapp, Inc. System and method for performing transactional processing in a striped volume set
US7743210B1 (en) 2005-04-29 2010-06-22 Netapp, Inc. System and method for implementing atomic cross-stripe write operations in a striped volume set
US8073899B2 (en) * 2005-04-29 2011-12-06 Netapp, Inc. System and method for proxying data access commands in a storage system cluster
US7617370B2 (en) * 2005-04-29 2009-11-10 Netapp, Inc. Data allocation within a storage system architecture
US7904649B2 (en) * 2005-04-29 2011-03-08 Netapp, Inc. System and method for restriping data across a plurality of volumes
US7698501B1 (en) 2005-04-29 2010-04-13 Netapp, Inc. System and method for utilizing sparse data containers in a striped volume set
US7698334B2 (en) * 2005-04-29 2010-04-13 Netapp, Inc. System and method for multi-tiered meta-data caching and distribution in a clustered computer environment
US20060294300A1 (en) * 2005-06-22 2006-12-28 Seagate Technology Llc Atomic cache transactions in a distributed storage system
US20070022314A1 (en) * 2005-07-22 2007-01-25 Pranoop Erasani Architecture and method for configuring a simplified cluster over a network with fencing and quorum
US7653682B2 (en) * 2005-07-22 2010-01-26 Netapp, Inc. Client failure fencing mechanism for fencing network file system data in a host-cluster environment
US7581998B2 (en) * 2005-09-08 2009-09-01 Ngk Spark Plug Co., Ltd. Method for regulating aground electrode position in spark plug
US7650366B1 (en) 2005-09-09 2010-01-19 Netapp, Inc. System and method for generating a crash consistent persistent consistency point image set
US7707193B2 (en) * 2005-09-22 2010-04-27 Netapp, Inc. System and method for verifying and restoring the consistency of inode to pathname mappings in a filesystem
US7917537B2 (en) 2005-09-26 2011-03-29 Oracle International Corporation System and method for providing link property types for content management
US7818344B2 (en) 2005-09-26 2010-10-19 Bea Systems, Inc. System and method for providing nested types for content management
US20070073663A1 (en) * 2005-09-26 2007-03-29 Bea Systems, Inc. System and method for providing full-text searching of managed content
US20070088917A1 (en) * 2005-10-14 2007-04-19 Ranaweera Samantha L System and method for creating and maintaining a logical serial attached SCSI communication channel among a plurality of storage systems
US8484365B1 (en) 2005-10-20 2013-07-09 Netapp, Inc. System and method for providing a unified iSCSI target with a plurality of loosely coupled iSCSI front ends
US7797283B2 (en) 2005-10-21 2010-09-14 Isilon Systems, Inc. Systems and methods for maintaining distributed data
US7917474B2 (en) 2005-10-21 2011-03-29 Isilon Systems, Inc. Systems and methods for accessing and updating distributed data
US7788303B2 (en) 2005-10-21 2010-08-31 Isilon Systems, Inc. Systems and methods for distributed system scanning
US7386675B2 (en) * 2005-10-21 2008-06-10 Isilon Systems, Inc. Systems and methods for using excitement values to predict future access to resources
US7346720B2 (en) * 2005-10-21 2008-03-18 Isilon Systems, Inc. Systems and methods for managing concurrent access requests to a shared resource
US7551572B2 (en) * 2005-10-21 2009-06-23 Isilon Systems, Inc. Systems and methods for providing variable protection
US7873963B1 (en) 2005-10-25 2011-01-18 Netapp, Inc. Method and system for detecting languishing messages
EP1949214B1 (en) 2005-10-28 2012-12-19 Network Appliance, Inc. System and method for optimizing multi-pathing support in a distributed storage system environment
US7325111B1 (en) 2005-11-01 2008-01-29 Network Appliance, Inc. Method and system for single pass volume scanning for multiple destination mirroring
US7797570B2 (en) 2005-11-29 2010-09-14 Netapp, Inc. System and method for failover of iSCSI target portal groups in a cluster environment
US7751346B2 (en) * 2005-12-01 2010-07-06 Electronics And Telecommunications Research Institute Apparatus for searching TCP and UDP sockets
US7702629B2 (en) 2005-12-02 2010-04-20 Exegy Incorporated Method and device for high performance regular expression pattern matching
US7738500B1 (en) 2005-12-14 2010-06-15 Alacritech, Inc. TCP timestamp synchronization for network connections that are offloaded to network interface devices
US8448162B2 (en) 2005-12-28 2013-05-21 Foundry Networks, Llc Hitless software upgrades
US7693864B1 (en) 2006-01-03 2010-04-06 Netapp, Inc. System and method for quickly determining changed metadata using persistent consistency point image differencing
US7954114B2 (en) 2006-01-26 2011-05-31 Exegy Incorporated Firmware socket module for FPGA-based pipeline processing
US8560503B1 (en) 2006-01-26 2013-10-15 Netapp, Inc. Content addressable storage system
US7848261B2 (en) 2006-02-17 2010-12-07 Isilon Systems, Inc. Systems and methods for providing a quiescing protocol
US7734951B1 (en) 2006-03-20 2010-06-08 Netapp, Inc. System and method for data protection management in a logical namespace of a storage system environment
US7590660B1 (en) 2006-03-21 2009-09-15 Network Appliance, Inc. Method and system for efficient database cloning
US20070245060A1 (en) * 2006-03-27 2007-10-18 Lakkavalli Giridhar V Method and system for handling data by file-system offloading
US7937545B1 (en) * 2006-03-29 2011-05-03 Symantec Operating Corporation Method and apparatus for file-level restore from raw partition backups
US7756898B2 (en) 2006-03-31 2010-07-13 Isilon Systems, Inc. Systems and methods for notifying listeners of events
US8551135B2 (en) 2006-03-31 2013-10-08 W.L. Gore & Associates, Inc. Screw catch mechanism for PFO occluder and method of use
US9166883B2 (en) 2006-04-05 2015-10-20 Joseph Robert Marchese Network device detection, identification, and management
US8005793B1 (en) 2006-04-18 2011-08-23 Netapp, Inc. Retaining persistent point in time data during volume migration
US8090908B1 (en) 2006-04-26 2012-01-03 Netapp, Inc. Single nodename cluster system for fibre channel
US8165221B2 (en) * 2006-04-28 2012-04-24 Netapp, Inc. System and method for sampling based elimination of duplicate data
US7769723B2 (en) * 2006-04-28 2010-08-03 Netapp, Inc. System and method for providing continuous data protection
US7464238B1 (en) 2006-04-28 2008-12-09 Network Appliance, Inc. System and method for verifying the consistency of mirrored data sets
US7636703B2 (en) * 2006-05-02 2009-12-22 Exegy Incorporated Method and apparatus for approximate pattern matching
JP5204099B2 (en) 2006-05-05 2013-06-05 ハイバー インコーポレイテッド Group-based full and incremental computer file backup systems, processing and equipment
US9026495B1 (en) 2006-05-26 2015-05-05 Netapp, Inc. System and method for creating and accessing a host-accessible storage entity
US7921046B2 (en) 2006-06-19 2011-04-05 Exegy Incorporated High speed processing of financial information using FPGA devices
US7840482B2 (en) 2006-06-19 2010-11-23 Exegy Incorporated Method and system for high speed options pricing
US8412682B2 (en) * 2006-06-29 2013-04-02 Netapp, Inc. System and method for retrieving and using block fingerprints for data deduplication
US7921077B2 (en) * 2006-06-29 2011-04-05 Netapp, Inc. System and method for managing data deduplication of storage systems utilizing persistent consistency point images
US7536508B2 (en) * 2006-06-30 2009-05-19 Dot Hill Systems Corporation System and method for sharing SATA drives in active-active RAID controller system
US8010509B1 (en) 2006-06-30 2011-08-30 Netapp, Inc. System and method for verifying and correcting the consistency of mirrored data sets
US7571594B2 (en) * 2006-07-28 2009-08-11 Milliken & Company Composite yarn and process for producing the same
US8539056B2 (en) 2006-08-02 2013-09-17 Emc Corporation Systems and methods for configuring multiple network interfaces
US7987167B1 (en) 2006-08-04 2011-07-26 Netapp, Inc. Enabling a clustered namespace with redirection
US7590652B2 (en) 2006-08-18 2009-09-15 Isilon Systems, Inc. Systems and methods of reverse lookup
US7676691B2 (en) 2006-08-18 2010-03-09 Isilon Systems, Inc. Systems and methods for providing nonlinear journaling
US7680842B2 (en) 2006-08-18 2010-03-16 Isilon Systems, Inc. Systems and methods for a snapshot of data
US7953704B2 (en) 2006-08-18 2011-05-31 Emc Corporation Systems and methods for a snapshot of data
US7882071B2 (en) 2006-08-18 2011-02-01 Isilon Systems, Inc. Systems and methods for a snapshot of data
US7752402B2 (en) 2006-08-18 2010-07-06 Isilon Systems, Inc. Systems and methods for allowing incremental journaling
US7822932B2 (en) 2006-08-18 2010-10-26 Isilon Systems, Inc. Systems and methods for providing nonlinear journaling
US7680836B2 (en) * 2006-08-18 2010-03-16 Isilon Systems, Inc. Systems and methods for a snapshot of data
US7899800B2 (en) 2006-08-18 2011-03-01 Isilon Systems, Inc. Systems and methods for providing nonlinear journaling
US7747584B1 (en) 2006-08-22 2010-06-29 Netapp, Inc. System and method for enabling de-duplication in a storage system architecture
US7865741B1 (en) 2006-08-23 2011-01-04 Netapp, Inc. System and method for securely replicating a configuration database of a security appliance
US7610507B2 (en) * 2006-09-08 2009-10-27 Agere Systems Inc. High-speed redundant disk controller methods and systems
US8116455B1 (en) 2006-09-29 2012-02-14 Netapp, Inc. System and method for securely initializing and booting a security appliance
US7739546B1 (en) 2006-10-20 2010-06-15 Netapp, Inc. System and method for storing and retrieving file system log information in a clustered computer system
US8996487B1 (en) 2006-10-31 2015-03-31 Netapp, Inc. System and method for improving the relevance of search results using data container access patterns
US7822921B2 (en) 2006-10-31 2010-10-26 Netapp, Inc. System and method for optimizing write operations in storage systems
US7720889B1 (en) 2006-10-31 2010-05-18 Netapp, Inc. System and method for nearly in-band search indexing
US7685178B2 (en) * 2006-10-31 2010-03-23 Netapp, Inc. System and method for examining client generated content stored on a data container exported by a storage system
US8423731B1 (en) 2006-10-31 2013-04-16 Netapp, Inc. System and method for automatic scheduling and policy provisioning for information lifecycle management
US7660793B2 (en) 2006-11-13 2010-02-09 Exegy Incorporated Method and system for high performance integration, processing and searching of structured and unstructured data using coprocessors
US8326819B2 (en) 2006-11-13 2012-12-04 Exegy Incorporated Method and system for high performance data metatagging and data indexing using coprocessors
US8238255B2 (en) 2006-11-22 2012-08-07 Foundry Networks, Llc Recovering from failures without impact on data traffic in a shared bus architecture
US7613947B1 (en) 2006-11-30 2009-11-03 Netapp, Inc. System and method for storage takeover
US7711683B1 (en) 2006-11-30 2010-05-04 Netapp, Inc. Method and system for maintaining disk location via homeness
US7647526B1 (en) 2006-12-06 2010-01-12 Netapp, Inc. Reducing reconstruct input/output operations in storage systems
US7937641B2 (en) * 2006-12-21 2011-05-03 Smart Modular Technologies, Inc. Memory modules with error detection and correction
US8286029B2 (en) 2006-12-21 2012-10-09 Emc Corporation Systems and methods for managing unavailable storage devices
US7593938B2 (en) 2006-12-22 2009-09-22 Isilon Systems, Inc. Systems and methods of directory entry encodings
US8301673B2 (en) * 2006-12-29 2012-10-30 Netapp, Inc. System and method for performing distributed consistency verification of a clustered file system
US8489811B1 (en) 2006-12-29 2013-07-16 Netapp, Inc. System and method for addressing data containers using data set identifiers
US7509448B2 (en) 2007-01-05 2009-03-24 Isilon Systems, Inc. Systems and methods for managing semantic locks
US20080168226A1 (en) * 2007-01-05 2008-07-10 Accusys. Inc. Correction method for reading data of disk array system
US8155011B2 (en) 2007-01-11 2012-04-10 Foundry Networks, Llc Techniques for using dual memory structures for processing failure detection protocol packets
US9330529B2 (en) 2007-01-17 2016-05-03 Touchtunes Music Corporation Game terminal configured for interaction with jukebox device systems including same, and/or associated methods
US9171419B2 (en) 2007-01-17 2015-10-27 Touchtunes Music Corporation Coin operated entertainment system
US7853750B2 (en) * 2007-01-30 2010-12-14 Netapp, Inc. Method and an apparatus to store data patterns
US8190641B2 (en) 2007-02-13 2012-05-29 Netapp, Inc. System and method for administration of virtual servers
US7681089B2 (en) * 2007-02-20 2010-03-16 Dot Hill Systems Corporation Redundant storage controller system with enhanced failure analysis capability
US8868495B2 (en) * 2007-02-21 2014-10-21 Netapp, Inc. System and method for indexing user data on storage systems
US8312046B1 (en) 2007-02-28 2012-11-13 Netapp, Inc. System and method for enabling a data container to appear in a plurality of locations in a super-namespace
US9953481B2 (en) 2007-03-26 2018-04-24 Touchtunes Music Corporation Jukebox with associated video server
US8219821B2 (en) 2007-03-27 2012-07-10 Netapp, Inc. System and method for signature based data container recognition
US8312214B1 (en) 2007-03-28 2012-11-13 Netapp, Inc. System and method for pausing disk drives in an aggregate
US8533410B1 (en) 2007-03-29 2013-09-10 Netapp, Inc. Maintaining snapshot and active file system metadata in an on-disk structure of a file system
US8510524B1 (en) 2007-03-29 2013-08-13 Netapp, Inc. File system capable of generating snapshots and providing fast sequential read access
US7849057B1 (en) 2007-03-30 2010-12-07 Netapp, Inc. Identifying snapshot membership for blocks based on snapid
US9005242B2 (en) 2007-04-05 2015-04-14 W.L. Gore & Associates, Inc. Septal closure device with centering mechanism
US8209587B1 (en) 2007-04-12 2012-06-26 Netapp, Inc. System and method for eliminating zeroing of disk drives in RAID arrays
US7900015B2 (en) 2007-04-13 2011-03-01 Isilon Systems, Inc. Systems and methods of quota accounting
US7779048B2 (en) 2007-04-13 2010-08-17 Isilon Systems, Inc. Systems and methods of providing possible value ranges
US8966080B2 (en) 2007-04-13 2015-02-24 Emc Corporation Systems and methods of managing resource utilization on a threaded computer system
US9138562B2 (en) 2007-04-18 2015-09-22 W.L. Gore & Associates, Inc. Flexible catheter system
US8325633B2 (en) * 2007-04-26 2012-12-04 International Business Machines Corporation Remote direct memory access
US7987383B1 (en) 2007-04-27 2011-07-26 Netapp, Inc. System and method for rapid indentification of coredump disks during simultaneous take over
US8898536B2 (en) 2007-04-27 2014-11-25 Netapp, Inc. Multi-core engine for detecting bit errors
US7840837B2 (en) 2007-04-27 2010-11-23 Netapp, Inc. System and method for protecting memory during system initialization
US8219749B2 (en) * 2007-04-27 2012-07-10 Netapp, Inc. System and method for efficient updates of sequential block storage
US7827350B1 (en) 2007-04-27 2010-11-02 Netapp, Inc. Method and system for promoting a snapshot in a distributed file system
US7882304B2 (en) * 2007-04-27 2011-02-01 Netapp, Inc. System and method for efficient updates of sequential block storage
US7889657B2 (en) * 2007-05-04 2011-02-15 International Business Machines Corporation Signaling completion of a message transfer from an origin compute node to a target compute node
US7948999B2 (en) * 2007-05-04 2011-05-24 International Business Machines Corporation Signaling completion of a message transfer from an origin compute node to a target compute node
US7890670B2 (en) * 2007-05-09 2011-02-15 International Business Machines Corporation Direct memory access transfer completion notification
US7836331B1 (en) 2007-05-15 2010-11-16 Netapp, Inc. System and method for protecting the contents of memory during error conditions
US7779173B2 (en) * 2007-05-29 2010-08-17 International Business Machines Corporation Direct memory access transfer completion notification
US8037213B2 (en) 2007-05-30 2011-10-11 International Business Machines Corporation Replenishing data descriptors in a DMA injection FIFO buffer
US8762345B2 (en) * 2007-05-31 2014-06-24 Netapp, Inc. System and method for accelerating anchor point detection
US7797489B1 (en) 2007-06-01 2010-09-14 Netapp, Inc. System and method for providing space availability notification in a distributed striped volume set
US7765337B2 (en) * 2007-06-05 2010-07-27 International Business Machines Corporation Direct memory access transfer completion notification
US7734733B1 (en) * 2007-06-15 2010-06-08 Packeteer, Inc. WAFS disconnected-mode read-write access
US8018951B2 (en) 2007-07-12 2011-09-13 International Business Machines Corporation Pacing a data transfer operation between compute nodes on a parallel computer
US8478834B2 (en) * 2007-07-12 2013-07-02 International Business Machines Corporation Low latency, high bandwidth data communications between compute nodes in a parallel computer
US8346966B1 (en) 2007-07-19 2013-01-01 Blue Coat Systems, Inc. Transparent file system access for wide area network file system acceleration
US8301791B2 (en) * 2007-07-26 2012-10-30 Netapp, Inc. System and method for non-disruptive check of a mirror
US7890597B2 (en) * 2007-07-27 2011-02-15 International Business Machines Corporation Direct memory access transfer completion notification
US20090031001A1 (en) * 2007-07-27 2009-01-29 Archer Charles J Repeating Direct Memory Access Data Transfer Operations for Compute Nodes in a Parallel Computer
US8959172B2 (en) * 2007-07-27 2015-02-17 International Business Machines Corporation Self-pacing direct memory access data transfer operations for compute nodes in a parallel computer
US7975102B1 (en) 2007-08-06 2011-07-05 Netapp, Inc. Technique to avoid cascaded hot spotting
US7966289B2 (en) 2007-08-21 2011-06-21 Emc Corporation Systems and methods for reading objects in a file system
US7882068B2 (en) 2007-08-21 2011-02-01 Isilon Systems, Inc. Systems and methods for adaptive copy on write
US7949692B2 (en) 2007-08-21 2011-05-24 Emc Corporation Systems and methods for portals into snapshot data
US8392529B2 (en) 2007-08-27 2013-03-05 Pme Ip Australia Pty Ltd Fast file server methods and systems
US8793226B1 (en) 2007-08-28 2014-07-29 Netapp, Inc. System and method for estimating duplicate data
US7865475B1 (en) 2007-09-12 2011-01-04 Netapp, Inc. Mechanism for converting one type of mirror to another type of mirror on a storage system without transferring data
US8332887B2 (en) 2008-01-10 2012-12-11 Touchtunes Music Corporation System and/or methods for distributing advertisements from a central advertisement network to a peripheral device via a local advertisement server
US10290006B2 (en) 2008-08-15 2019-05-14 Touchtunes Music Corporation Digital signage and gaming services to comply with federal and state alcohol and beverage laws and regulations
US7996636B1 (en) 2007-11-06 2011-08-09 Netapp, Inc. Uniquely identifying block context signatures in a storage volume hierarchy
WO2009062029A1 (en) * 2007-11-09 2009-05-14 Carnegie Mellon University Efficient high performance system for writing data from applications to a safe file system
WO2011065929A1 (en) 2007-11-23 2011-06-03 Mercury Computer Systems, Inc. Multi-user multi-gpu render server apparatus and methods
US9904969B1 (en) 2007-11-23 2018-02-27 PME IP Pty Ltd Multi-user multi-GPU render server apparatus and methods
US9019287B2 (en) 2007-11-23 2015-04-28 Pme Ip Australia Pty Ltd Client-server visualization system with hybrid data processing
US10311541B2 (en) 2007-11-23 2019-06-04 PME IP Pty Ltd Multi-user multi-GPU render server apparatus and methods
US8548215B2 (en) 2007-11-23 2013-10-01 Pme Ip Australia Pty Ltd Automatic image segmentation of a volume by comparing and correlating slice histograms with an anatomic atlas of average histograms
US7984259B1 (en) 2007-12-17 2011-07-19 Netapp, Inc. Reducing load imbalance in a storage system
US8380674B1 (en) 2008-01-09 2013-02-19 Netapp, Inc. System and method for migrating lun data between data containers
US7996607B1 (en) 2008-01-28 2011-08-09 Netapp, Inc. Distributing lookup operations in a striped storage system
US20130165967A1 (en) 2008-03-07 2013-06-27 W.L. Gore & Associates, Inc. Heart occlusion devices
US9135284B1 (en) 2008-03-13 2015-09-15 Blue Coat Systems, Inc. Composite execution of rename operations in wide area file systems
US9442850B1 (en) 2008-03-25 2016-09-13 Blue Coat Systems, Inc. Efficient directory refresh operations in wide area file systems
US7953709B2 (en) 2008-03-27 2011-05-31 Emc Corporation Systems and methods for a read only mode for a portion of a storage system
US7949636B2 (en) 2008-03-27 2011-05-24 Emc Corporation Systems and methods for a read only mode for a portion of a storage system
US7984324B2 (en) 2008-03-27 2011-07-19 Emc Corporation Systems and methods for managing stalled storage devices
US7870345B2 (en) 2008-03-27 2011-01-11 Isilon Systems, Inc. Systems and methods for managing stalled storage devices
US9009350B2 (en) * 2008-04-01 2015-04-14 International Business Machines Corporation Determining a path for network traffic between nodes in a parallel computer
US8539513B1 (en) 2008-04-01 2013-09-17 Alacritech, Inc. Accelerating data transfer in a virtual computer system with tightly coupled TCP connections
US9225545B2 (en) * 2008-04-01 2015-12-29 International Business Machines Corporation Determining a path for network traffic between nodes in a parallel computer
US8725986B1 (en) 2008-04-18 2014-05-13 Netapp, Inc. System and method for volume block number to disk block number mapping
US8621154B1 (en) 2008-04-18 2013-12-31 Netapp, Inc. Flow based reply cache
US8161236B1 (en) 2008-04-23 2012-04-17 Netapp, Inc. Persistent reply cache integrated with file system
US8219564B1 (en) 2008-04-29 2012-07-10 Netapp, Inc. Two-dimensional indexes for quick multiple attribute search in a catalog system
US8374986B2 (en) 2008-05-15 2013-02-12 Exegy Incorporated Method and system for accelerated stream processing
KR101221551B1 (en) * 2008-07-01 2013-01-14 브로드콤 코포레이션 Network controller based pass-through communication mechanism between local host and management controller
WO2010005569A1 (en) 2008-07-09 2010-01-14 Touchtunes Music Corporation Digital downloading jukebox with revenue-enhancing features
US8341286B1 (en) 2008-07-31 2012-12-25 Alacritech, Inc. TCP offload send optimization
US8250043B2 (en) * 2008-08-19 2012-08-21 Netapp, Inc. System and method for compression of partially ordered data sets
US8706878B1 (en) 2008-08-21 2014-04-22 United Services Automobile Association Preferential loading in data centers
US8843522B2 (en) * 2008-09-15 2014-09-23 Thomson Reuters (Markets) Llc Systems and methods for rapid delivery of tiered metadata
US9306793B1 (en) 2008-10-22 2016-04-05 Alacritech, Inc. TCP offload device that batches session layer headers to reduce interrupts as well as CPU copies
US9158579B1 (en) 2008-11-10 2015-10-13 Netapp, Inc. System having operation queues corresponding to operation execution time
EP2189893A1 (en) 2008-11-21 2010-05-26 Thomson Licensing Data storage system and method of operation
CA2744746C (en) 2008-12-15 2019-12-24 Exegy Incorporated Method and apparatus for high-speed processing of financial market depth data
US8495417B2 (en) * 2009-01-09 2013-07-23 Netapp, Inc. System and method for redundancy-protected aggregates
US8793223B1 (en) 2009-02-09 2014-07-29 Netapp, Inc. Online data consistency checking in a network storage system with optional committal of remedial changes
US8171227B1 (en) 2009-03-11 2012-05-01 Netapp, Inc. System and method for managing a flow based reply cache
US9076155B2 (en) 2009-03-18 2015-07-07 Touchtunes Music Corporation Jukebox with connection to external social networking services and associated systems and methods
US10564804B2 (en) 2009-03-18 2020-02-18 Touchtunes Music Corporation Digital jukebox device with improved user interfaces, and associated methods
US9292166B2 (en) 2009-03-18 2016-03-22 Touchtunes Music Corporation Digital jukebox device with improved karaoke-related user interfaces, and associated methods
US10719149B2 (en) 2009-03-18 2020-07-21 Touchtunes Music Corporation Digital jukebox device with improved user interfaces, and associated methods
US8688798B1 (en) 2009-04-03 2014-04-01 Netapp, Inc. System and method for a shared write address protocol over a remote direct memory access connection
US8266136B1 (en) 2009-04-13 2012-09-11 Netapp, Inc. Mechanism for performing fast directory lookup in a server system
US8117388B2 (en) * 2009-04-30 2012-02-14 Netapp, Inc. Data distribution through capacity leveling in a striped file system
UA107791C2 (en) 2009-05-05 2015-02-25 Dow Agrosciences Llc Pesticidal compositions
US8949241B2 (en) * 2009-05-08 2015-02-03 Thomson Reuters Global Resources Systems and methods for interactive disambiguation of data
US9636094B2 (en) 2009-06-22 2017-05-02 W. L. Gore & Associates, Inc. Sealing device and delivery system
US20120029556A1 (en) 2009-06-22 2012-02-02 Masters Steven J Sealing device and delivery system
US8599850B2 (en) 2009-09-21 2013-12-03 Brocade Communications Systems, Inc. Provisioning single or multistage networks using ethernet service instances (ESIs)
EP2526494B1 (en) 2010-01-21 2020-01-15 SVIRAL, Inc. A method and apparatus for a general-purpose, multiple-core system for implementing stream-based computations
JP5571200B2 (en) 2010-01-26 2014-08-13 タッチチューンズ ミュージック コーポレイション Digital jukebox device with improved user interface and related techniques
US8544026B2 (en) * 2010-02-09 2013-09-24 International Business Machines Corporation Processing data communications messages with input/output control blocks
US8725931B1 (en) 2010-03-26 2014-05-13 Western Digital Technologies, Inc. System and method for managing the execution of memory commands in a solid-state memory
US8782327B1 (en) 2010-05-11 2014-07-15 Western Digital Technologies, Inc. System and method for managing execution of internal commands and host commands in a solid-state memory
US9026716B2 (en) 2010-05-12 2015-05-05 Western Digital Technologies, Inc. System and method for managing garbage collection in solid-state memory
US8996647B2 (en) 2010-06-09 2015-03-31 International Business Machines Corporation Optimizing storage between mobile devices and cloud storage providers
US8489809B2 (en) 2010-07-07 2013-07-16 International Business Machines Corporation Intelligent storage provisioning within a clustered computing environment
US8635412B1 (en) 2010-09-09 2014-01-21 Western Digital Technologies, Inc. Inter-processor communication
US9164886B1 (en) 2010-09-21 2015-10-20 Western Digital Technologies, Inc. System and method for multistage processing in a memory storage subsystem
US9021192B1 (en) 2010-09-21 2015-04-28 Western Digital Technologies, Inc. System and method for enhancing processing of memory access requests
KR20130083446A (en) * 2010-10-20 2013-07-22 후지쯔 가부시끼가이샤 Information processing system, recording device, information processing device, and method for controlling information processing system
US8489812B2 (en) 2010-10-29 2013-07-16 International Business Machines Corporation Automated storage provisioning within a clustered computing environment
US8949453B2 (en) 2010-11-30 2015-02-03 International Business Machines Corporation Data communications in a parallel active messaging interface of a parallel computer
EP2649580A4 (en) 2010-12-09 2014-05-07 Ip Reservoir Llc Method and apparatus for managing orders in financial markets
US8447134B1 (en) * 2010-12-20 2013-05-21 Ambarella, Inc. Image warp caching
US9158670B1 (en) 2011-06-30 2015-10-13 Western Digital Technologies, Inc. System and method for dynamically adjusting garbage collection policies in solid-state memory
US8949328B2 (en) 2011-07-13 2015-02-03 International Business Machines Corporation Performing collective operations in a distributed processing system
US9770232B2 (en) 2011-08-12 2017-09-26 W. L. Gore & Associates, Inc. Heart occlusion devices
GB2511003B (en) 2011-09-18 2015-03-04 Touchtunes Music Corp Digital jukebox device with karaoke and/or photo booth features, and associated methods
US9047243B2 (en) 2011-12-14 2015-06-02 Ip Reservoir, Llc Method and apparatus for low latency data distribution
US11151224B2 (en) 2012-01-09 2021-10-19 Touchtunes Music Corporation Systems and/or methods for monitoring audio inputs to jukebox devices
US8930962B2 (en) 2012-02-22 2015-01-06 International Business Machines Corporation Processing unexpected messages at a compute node of a parallel computer
US9990393B2 (en) 2012-03-27 2018-06-05 Ip Reservoir, Llc Intelligent feed switch
US10650452B2 (en) 2012-03-27 2020-05-12 Ip Reservoir, Llc Offload processing of data packets
US10121196B2 (en) 2012-03-27 2018-11-06 Ip Reservoir, Llc Offload processing of data packets containing financial market data
US11436672B2 (en) 2012-03-27 2022-09-06 Exegy Incorporated Intelligent switch for processing financial market data
WO2013181640A1 (en) * 2012-05-31 2013-12-05 MCDOUGALL, Christine, A. Virtual classroom management delivery system and method
US9214067B2 (en) 2012-09-06 2015-12-15 Igt Gaming system and method for providing a streaming symbols game
US9028318B2 (en) 2012-09-27 2015-05-12 Igt Gaming system and method for providing a game which populates symbols along a path
US9039512B2 (en) 2012-09-27 2015-05-26 Igt Gaming system and method for providing a game which populates symbols along a path
US8992301B2 (en) 2012-09-27 2015-03-31 Igt Gaming system and method for providing a game which populates symbols along a path
US9633093B2 (en) 2012-10-23 2017-04-25 Ip Reservoir, Llc Method and apparatus for accelerated format translation of data in a delimited data format
EP2912579B1 (en) 2012-10-23 2020-08-19 IP Reservoir, LLC Method and apparatus for accelerated format translation of data in a delimited data format
US10133802B2 (en) 2012-10-23 2018-11-20 Ip Reservoir, Llc Method and apparatus for accelerated record layout detection
US10828019B2 (en) 2013-01-18 2020-11-10 W.L. Gore & Associates, Inc. Sealing device and delivery system
US8851979B2 (en) 2013-03-07 2014-10-07 Igt Gaming system and method for providing a symbol elimination game
US8784191B1 (en) 2013-03-07 2014-07-22 Igt Gaming system and method for providing a symbol elimination game
US10070839B2 (en) 2013-03-15 2018-09-11 PME IP Pty Ltd Apparatus and system for rule based visualization of digital breast tomosynthesis and other volumetric images
US10540803B2 (en) 2013-03-15 2020-01-21 PME IP Pty Ltd Method and system for rule-based display of sets of images
US9509802B1 (en) 2013-03-15 2016-11-29 PME IP Pty Ltd Method and system FPOR transferring data to improve responsiveness when sending large data sets
US11244495B2 (en) 2013-03-15 2022-02-08 PME IP Pty Ltd Method and system for rule based display of sets of images using image content derived parameters
US8976190B1 (en) 2013-03-15 2015-03-10 Pme Ip Australia Pty Ltd Method and system for rule based display of sets of images
US11183292B2 (en) 2013-03-15 2021-11-23 PME IP Pty Ltd Method and system for rule-based anonymized display and data export
US9197584B2 (en) * 2013-08-05 2015-11-24 Globalfoundries Inc. Increasing efficiency of data payloads to data arrays accessed through registers in a distributed virtual bridge
JP6476672B2 (en) * 2013-09-17 2019-03-06 株式会社リコー Communication terminal, information processing method, and program
FR3011355B1 (en) 2013-10-01 2017-01-27 Bull DOUBLE DEPTH OF TREATMENT TO ADDITIONAL TREATMENT DEVICES AND CENTRAL
US9098413B2 (en) * 2013-10-18 2015-08-04 International Business Machines Corporation Read and write requests to partially cached files
US9921717B2 (en) 2013-11-07 2018-03-20 Touchtunes Music Corporation Techniques for generating electronic menu graphical user interface layouts for use in connection with electronic devices
US9304799B2 (en) * 2013-12-27 2016-04-05 International Business Machines Corporation Placement of input / output adapter cards in a server
WO2015148644A1 (en) 2014-03-25 2015-10-01 Touchtunes Music Corporation Digital jukebox device with improved user interfaces, and associated methods
WO2015164639A1 (en) 2014-04-23 2015-10-29 Ip Reservoir, Llc Method and apparatus for accelerated data translation
US9808230B2 (en) 2014-06-06 2017-11-07 W. L. Gore & Associates, Inc. Sealing device and delivery system
US9904481B2 (en) 2015-01-23 2018-02-27 Commvault Systems, Inc. Scalable auxiliary copy processing in a storage management system using media agent resources
US9898213B2 (en) 2015-01-23 2018-02-20 Commvault Systems, Inc. Scalable auxiliary copy processing using media agent resources
US11599672B2 (en) 2015-07-31 2023-03-07 PME IP Pty Ltd Method and apparatus for anonymized display and data export
US9984478B2 (en) 2015-07-28 2018-05-29 PME IP Pty Ltd Apparatus and method for visualizing digital breast tomosynthesis and other volumetric images
US10942943B2 (en) 2015-10-29 2021-03-09 Ip Reservoir, Llc Dynamic field data translation to support high performance stream data processing
US10186106B2 (en) 2016-09-21 2019-01-22 Igt Gaming system and method for determining awards based on interacting symbols
WO2018119035A1 (en) 2016-12-22 2018-06-28 Ip Reservoir, Llc Pipelines for hardware-accelerated machine learning
US11010261B2 (en) 2017-03-31 2021-05-18 Commvault Systems, Inc. Dynamically allocating streams during restoration of data
US10524022B2 (en) 2017-05-02 2019-12-31 Seagate Technology Llc Data storage system with adaptive data path routing
US11287985B2 (en) 2017-05-17 2022-03-29 Seagate Technology Llc Network data storage buffer system
US10909679B2 (en) 2017-09-24 2021-02-02 PME IP Pty Ltd Method and system for rule based display of sets of images using image content derived parameters
US11277442B2 (en) * 2019-04-05 2022-03-15 Cisco Technology, Inc. Verifying the trust-worthiness of ARP senders and receivers using attestation-based methods
CN110311954B (en) * 2019-05-31 2022-02-15 上海赫千电子科技有限公司 Data reading system and method for vehicle sensor
US11429564B2 (en) 2019-06-18 2022-08-30 Bank Of America Corporation File transferring using artificial intelligence
CN110321199B (en) * 2019-07-09 2022-04-12 成都卫士通信息产业股份有限公司 Method and device for notifying common data change, electronic equipment and medium
FR3103073B1 (en) * 2019-11-12 2021-12-03 Thales Sa MULTIMEDIA SERVER INTENDED TO BE ON BOARD AN AIRCRAFT, ELECTRONIC ENTERTAINMENT SYSTEM INCLUDING SUCH SERVER, SOFTWARE CONFIGURATION PROCESS FOR SUCH SERVER AND ASSOCIATED COMPUTER PROGRAM
US20210365416A1 (en) * 2020-05-25 2021-11-25 Hewlett Packard Enterprise Development Lp Mount parameter in file systems

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2542869A (en) * 1948-03-19 1951-02-20 Merck & Co Inc N-pyridoxyl-amino acids and process of preparing the same
US3074942A (en) * 1958-01-13 1963-01-22 Geigy Chem Corp alpha-substituted glycine derivatives
NL125657C (en) * 1963-11-26
GB1080470A (en) * 1963-12-31 1967-08-23 Merck & Co Inc Indole derivatives
US4075691A (en) * 1975-11-06 1978-02-21 Bunker Ramo Corporation Communication control unit
US4156907A (en) * 1977-03-02 1979-05-29 Burroughs Corporation Data communications subsystem
US4399503A (en) * 1978-06-30 1983-08-16 Bunker Ramo Corporation Dynamic disk buffer control unit
US4377843A (en) * 1979-04-19 1983-03-22 Wescom Switching, Inc. Data distribution interface
EP0031653A1 (en) * 1979-12-19 1981-07-08 Beecham Group Plc N-Substituted alpha-amino acids, processes for making them and pharmaceutical compositions containing them
US4333144A (en) * 1980-02-05 1982-06-01 The Bendix Corporation Task communicator for multiple computer system
US4488231A (en) * 1980-09-29 1984-12-11 Honeywell Information Systems Inc. Communication multiplexer having dual microprocessors
FR2500659B1 (en) * 1981-02-25 1986-02-28 Philips Ind Commerciale DEVICE FOR THE DYNAMIC ALLOCATION OF THE TASKS OF A MULTIPROCESSOR COMPUTER
US4456457A (en) * 1981-04-28 1984-06-26 Nippon Soken, Inc. Exhaust gas cleaning device for diesel engine
US4456957A (en) * 1981-09-28 1984-06-26 Ncr Corporation Apparatus using a decision table for routing data among terminals and a host system
US4685125A (en) * 1982-06-28 1987-08-04 American Telephone And Telegraph Company Computer system with tasking
US4550368A (en) * 1982-07-02 1985-10-29 Sun Microsystems, Inc. High-speed memory and memory management system
US4527232A (en) * 1982-07-02 1985-07-02 Sun Microsystems, Inc. High-speed memory and memory management system
LU85035A1 (en) * 1983-10-07 1985-06-19 Midit AMIDE ACID AMIDE DERIVATIVES, PREPARATION AND USE THEREOF AS WELL AS COMPOSITIONS CONTAINING THESE DERIVATIVES
US4710868A (en) * 1984-06-29 1987-12-01 International Business Machines Corporation Interconnect scheme for shared memory local networks
US4719569A (en) * 1985-10-11 1988-01-12 Sun Microsystems, Inc. Arbitrator for allocating access to data processing resources
US4825354A (en) * 1985-11-12 1989-04-25 American Telephone And Telegraph Company, At&T Bell Laboratories Method of file access in a distributed processing computer network
US4803621A (en) * 1986-07-24 1989-02-07 Sun Microsystems, Inc. Memory access system
US4780821A (en) * 1986-07-29 1988-10-25 International Business Machines Corp. Method for multiple programs management within a network having a server computer and a plurality of remote computers
US4819159A (en) * 1986-08-29 1989-04-04 Tolerant Systems, Inc. Distributed multiprocess transaction processing system and method
US4783730A (en) * 1986-09-19 1988-11-08 Datapoint Corporation Input/output control technique utilizing multilevel memory structure for processor and I/O communication
US4766534A (en) * 1986-10-16 1988-08-23 American Telephone And Telegraph Company, At&T Bell Laboratories Parallel processing network and method
US4887204A (en) * 1987-02-13 1989-12-12 International Business Machines Corporation System and method for accessing remote files in a distributed networking environment
US4897781A (en) * 1987-02-13 1990-01-30 International Business Machines Corporation System and method for using cached data at a local node after re-opening a file at a remote node in a distributed networking environment
US5109515A (en) * 1987-09-28 1992-04-28 At&T Bell Laboratories User and application program transparent resource sharing multiple computer interface architecture with kernel process level transfer of user requested services
IL88165A (en) * 1987-12-21 1993-01-31 Honeywell Bull Apparatus and method for a data processing system having a peer relationship among a plurality of central processing units
US4914583A (en) * 1988-04-13 1990-04-03 Motorola, Inc. Method of indicating processes resident within a cell of a data processing system
AU679806B2 (en) * 1993-12-24 1997-07-10 Portland Coast Region Water Authority Cooling tower

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7689754B2 (en) 1997-12-31 2010-03-30 Crossroads Systems, Inc. Storage router and method for providing virtual local storage
US7694058B2 (en) 1997-12-31 2010-04-06 Crossroads Systems, Inc. Storage router and method for providing virtual local storage
US7934040B2 (en) 1997-12-31 2011-04-26 Crossroads Systems, Inc. Storage router and method for providing virtual local storage
US7934041B2 (en) 1997-12-31 2011-04-26 Crossroads Systems, Inc. Storage router and method for providing virtual local storage
US7937517B2 (en) 1997-12-31 2011-05-03 Crossroads Systems, Inc. Storage router and method for providing virtual local storage
US7984221B2 (en) 1997-12-31 2011-07-19 Crossroads Systems, Inc. Storage router and method for providing virtual local storage
US7984224B2 (en) 1997-12-31 2011-07-19 Crossroads Systems, Inc. Storage router and method for providing virtual local storage
US7987311B2 (en) 1997-12-31 2011-07-26 Crossroads Systems, Inc. Storage router and method for providing virtual local storage
US8015339B2 (en) 1997-12-31 2011-09-06 Crossroads Systems, Inc. Storage router and method for providing virtual local storage
US8028117B2 (en) 1997-12-31 2011-09-27 Crossroads Systems, Inc. Storage router and method for providing virtual local storage
USRE42761E1 (en) 1997-12-31 2011-09-27 Crossroads Systems, Inc. Storage router and method for providing virtual local storage
US8046515B2 (en) 1997-12-31 2011-10-25 Crossroads Systems, Inc. Storage router and method for providing virtual local storage
US8402193B2 (en) 1997-12-31 2013-03-19 Crossroads Systems, Inc. Storage router and method for providing virtual local storage
US8402194B2 (en) 1997-12-31 2013-03-19 Crossroads Systems, Inc. Storage router and method for providing virtual local storage

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US5163131A (en) 1992-11-10
US20020083111A1 (en) 2002-06-27

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