CA2067032C - Terminating devices detection and verification circuit - Google Patents
Terminating devices detection and verification circuitInfo
- Publication number
- CA2067032C CA2067032C CA002067032A CA2067032A CA2067032C CA 2067032 C CA2067032 C CA 2067032C CA 002067032 A CA002067032 A CA 002067032A CA 2067032 A CA2067032 A CA 2067032A CA 2067032 C CA2067032 C CA 2067032C
- Authority
- CA
- Canada
- Prior art keywords
- signal
- present
- resistor
- terminating device
- cable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40045—Details regarding the feeding of energy to the node from the bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4086—Bus impedance matching, e.g. termination
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0298—Arrangement for terminating transmission lines
Abstract
A circuit for detecting and verifying a presence of a terminating device for a high speed data transmission line. The circuit contains a first cable detector which generates a first signal if a first cable is present. A
second cable detector generates a second signal if a second cable is present. The terminating device is contained in a plurality of resistor packs, each of the which contains an extra resistor. A terminating device detector senses the extra resistor presence, thereby detecting the presence of the resistor packs. The terminating device detector generates an ALL-EQUIPPED
signal and a NON-EQUIPPED signal, the ALL-EQUIPPED signal is generated when all of the plurality of resistor packs are present, the NON-EQUIPPED signal is generated when all of the plurality of resistor packs are absent.
Finally, a verifier circuit receives the first signal, the second signal, the ALL-EQUIPPED signal and the NON-EQUIPPED signal. The verifier circuit verifies that if the ALL-EQUIPPED signal is present then only one of the first signal or the second signal is present, or, if the NON-EQUIPPED signal is present both the first signal and the second signal are present.
second cable detector generates a second signal if a second cable is present. The terminating device is contained in a plurality of resistor packs, each of the which contains an extra resistor. A terminating device detector senses the extra resistor presence, thereby detecting the presence of the resistor packs. The terminating device detector generates an ALL-EQUIPPED
signal and a NON-EQUIPPED signal, the ALL-EQUIPPED signal is generated when all of the plurality of resistor packs are present, the NON-EQUIPPED signal is generated when all of the plurality of resistor packs are absent.
Finally, a verifier circuit receives the first signal, the second signal, the ALL-EQUIPPED signal and the NON-EQUIPPED signal. The verifier circuit verifies that if the ALL-EQUIPPED signal is present then only one of the first signal or the second signal is present, or, if the NON-EQUIPPED signal is present both the first signal and the second signal are present.
Description
A TERMINATING DEVICES DETECTION AND VERIFICATION CIRCUIT
FIELD OF THE INVENTION
The present invention relates in general to data communication systems, and more particularly, circuit for automatically detecting that the terminating devices on a data transmission line are properly configured.
BACKGROUND OF THE INVENTION
It is well known in the art of transmission that when a signal encounters a change in the characteristic impedance of a transmission line, a reflected signal is generated. This reflected signal sets up standing waves on the transmission line and depending on the relative location on the line the voltage can be substantially affected. As data transmission speeds increase, the presence of reflected waves can corrupt the integrity of a particular signal. In addition, the presence of stand-ing waves cause a counter electromagnetic force (EMF) to be generated around the transmission line, thus "launching" a wave into free space. In other words, the transmission line becomes an antenna. The launching of a wave is not desirable for data transmission because elec-tromagnetic interference (EMI) is increased and the amount of energy transferred to the receiver is de-creased. Because of this and other reasons, it is the general practice in the art of digital transmission to insure that transmission lines are properly terminated thereby providing an uninterrupted characteristic impedance on the transmission line.
In the art of digital transmission, a transmission line may have several transmitters and receivers on the line. If each device (transmitter or receiver) contained a terminating device, the transmission line's impedance would not be properly matched. For this reason a trans-mission line must only be terminated on the ends, and not in the middle of a chain. In addition, parallel stubs -1- ~
20~7032 ~ extruding from the chain must not be of any appreciable length.
Prior to the present invention, the installer had to properly determine if physical disposition of the termi-nating resistors agreed with the theocratical needs.
It is therefore a primary objective to provide an automatic means of detecting the presence of the termi-nating resistors, and further, to determine if the de-tected configuration agrees with the expected configuration.
SUMMARY OF THE INVENTION
In order to accomplish the object of the present invention there is provided a circuit for detecting and verifying a presence of a terminating device. The cir-cuit contains a first cable detector which generates afirst signal if a first cable is present. A second cable detector generates a second signal if a second cable is present.
The terminating device is contained in a plurality of resistor packs, each of the which contains an extra resistor. A terminating device detector senses the extra resistor presence, thereby detecting the presence of the resistor packs. The terminating device detector gener-ates an ALL-EQUIPPED signal and a NON-EQUIPPED signal, the ALL-EQUIPPED signal is generated when all of the plu-rality of resistor packs are present, the NON-EQUIPPED
signal is generated when all of the plurality of resistor packs are absent.
Finally, a verifier circuit receives the first sig-nal, the second signal, the ALL-EQUIPPED signal and the NON-EQUIPPED signal. The verifier circuit verifies that if the ALL-EQUIPPED signal is present then only one of the first signal or the second signal is present, or, if the NON-EQUIPPED signal is present both the first signal and the second signal are present.
- DESCRIPTION OF THE DRAWINGS
A better understanding of the invention may be had from the consideration of the following detailed descrip-tion taken in conjunction with the accompanying drawings, in which:
FIG. 1 shows a plurality of units connected in a daisy-chain configuration.
FIG. 2 is a schematic diagram of the present inven-tion showing the cable sense points.
FIG. 3 shows the recommended termination for single-ended devices.
FIG. 4 shows the recommended termination for differ-ential devices.
FIG. 5 is a schematic diagram of the present inven-tion using the termination scheme of FIG. 4.
FIG. 6 is a schematic diagram of the present inven-tion showing the termination sense points.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring first to FIG. 1, a typical daisy-chained configuration is shown. As FIG. 1 shows, Dl and Dn have terminating devices in place, D2 through Dn_l do not.
With this configuration, assuming the terminating devices match the transmission line properly, there are no changes in the characteristic impedance of the trans-mission line, thereby reducing standing waves on thetransmission line.
To properly determine if the actual configuration meets the predicted configuration, two facts must be determined. First, should the termination devices be present. Second, are the termination devices present.
The first fact depends on the position in the daisy-chain.
In the present invention, each device on the daisy-chain has two connection ports. If a device is on the end of the daisy-chain then only one port is occupied.
However, if the device is in the middle of the daisy-chain, both ports are occupied. The circuit in FIG. 2 is used to detect the presence of each cable. If only one - cable is present (i.e. the device is on the end of the daisy-chain) then either CON_l_EQUIP or CON_2_EQUIP will be a logic high, but not both. If both cables are present (i.e. the device is in the middle of the daisy-chain) then both CON_l_EQUIP or CON_2_EQUIP will be alogic high. To facilitate multiple connections and detections, the connecting wire may need to be twisted or jumpered such that each cable sense pin senses a ground in the far end port.
Referring to FIGs. 3 and 4, where the recommended termination circuits for a single-ended and differential devices are shown respectively. Both configuration properly create a 132 ohm load for the termination of signal as required for the Small Computer Interface (SCSI). The present invention, as shown in FIG. 5, implements the load scheme of FIG. 4. It will be appre-ciated to one skilled in the art that the present inven-tion is not limited to this type of interface.
The signal names (e.g. -ACK) are used as described in American National Standard for Information Systems -Small Computer System Interface (SCSI) X3.131-1986. An exact meaning and function of the individual signals is not needed to understand the present invention. Looking closely at FIG. 5, an extra resistor in each package can be seen. For example RESISTOR PACK 1 contains an extra resistor. The extra resistor is connected to RESISTOR
R64 such that only when RESISTOR PACK 1 is present is the signal TERM_EQP_l a logic one. The extra resistor of RESISTOR PACKS 2 through 7 are used to control signals thereby indicating the presence or absence of the respective resistor pack. The seven signals from the individual resistor packs are used by the circuit in FIG.
6 to generate two signals; ALL_TERM_EQP and NO_TERM_EQP.
If and only if all seven resistor packs are equipped is the ALL_TERM_EQP signal a logic high. If and only if all seven resistor packs are absent is the NO_TERM_EQP signal a logic high. If some, but not all, of the seven resistor packs are installed then both ALL_TERM_EQP and NO_TERM_EQP will be a logic low.
The circuits of FIG. 2 and 6 can then be logically tested to determine if the configuration is correct. If only one of CON_l_EQUIP or CON_2_EQUIP is a logic high, then ALL_TERM_EQP must also be a logic high. If both CON_l_EQUIP or CON_2_EQUIP are a logic high, then NO_TERM_EQP must also be a logic high. Any other signal combination would be an error state and an appropriate indication should be enabled.
Although the preferred embodiment of the invention has been illustrated, and that form described, it will be readily apparent to those skilled in the art that various modifications may be made therein without departing from the spirit of the invention or from the scope of the appended claims.
FIELD OF THE INVENTION
The present invention relates in general to data communication systems, and more particularly, circuit for automatically detecting that the terminating devices on a data transmission line are properly configured.
BACKGROUND OF THE INVENTION
It is well known in the art of transmission that when a signal encounters a change in the characteristic impedance of a transmission line, a reflected signal is generated. This reflected signal sets up standing waves on the transmission line and depending on the relative location on the line the voltage can be substantially affected. As data transmission speeds increase, the presence of reflected waves can corrupt the integrity of a particular signal. In addition, the presence of stand-ing waves cause a counter electromagnetic force (EMF) to be generated around the transmission line, thus "launching" a wave into free space. In other words, the transmission line becomes an antenna. The launching of a wave is not desirable for data transmission because elec-tromagnetic interference (EMI) is increased and the amount of energy transferred to the receiver is de-creased. Because of this and other reasons, it is the general practice in the art of digital transmission to insure that transmission lines are properly terminated thereby providing an uninterrupted characteristic impedance on the transmission line.
In the art of digital transmission, a transmission line may have several transmitters and receivers on the line. If each device (transmitter or receiver) contained a terminating device, the transmission line's impedance would not be properly matched. For this reason a trans-mission line must only be terminated on the ends, and not in the middle of a chain. In addition, parallel stubs -1- ~
20~7032 ~ extruding from the chain must not be of any appreciable length.
Prior to the present invention, the installer had to properly determine if physical disposition of the termi-nating resistors agreed with the theocratical needs.
It is therefore a primary objective to provide an automatic means of detecting the presence of the termi-nating resistors, and further, to determine if the de-tected configuration agrees with the expected configuration.
SUMMARY OF THE INVENTION
In order to accomplish the object of the present invention there is provided a circuit for detecting and verifying a presence of a terminating device. The cir-cuit contains a first cable detector which generates afirst signal if a first cable is present. A second cable detector generates a second signal if a second cable is present.
The terminating device is contained in a plurality of resistor packs, each of the which contains an extra resistor. A terminating device detector senses the extra resistor presence, thereby detecting the presence of the resistor packs. The terminating device detector gener-ates an ALL-EQUIPPED signal and a NON-EQUIPPED signal, the ALL-EQUIPPED signal is generated when all of the plu-rality of resistor packs are present, the NON-EQUIPPED
signal is generated when all of the plurality of resistor packs are absent.
Finally, a verifier circuit receives the first sig-nal, the second signal, the ALL-EQUIPPED signal and the NON-EQUIPPED signal. The verifier circuit verifies that if the ALL-EQUIPPED signal is present then only one of the first signal or the second signal is present, or, if the NON-EQUIPPED signal is present both the first signal and the second signal are present.
- DESCRIPTION OF THE DRAWINGS
A better understanding of the invention may be had from the consideration of the following detailed descrip-tion taken in conjunction with the accompanying drawings, in which:
FIG. 1 shows a plurality of units connected in a daisy-chain configuration.
FIG. 2 is a schematic diagram of the present inven-tion showing the cable sense points.
FIG. 3 shows the recommended termination for single-ended devices.
FIG. 4 shows the recommended termination for differ-ential devices.
FIG. 5 is a schematic diagram of the present inven-tion using the termination scheme of FIG. 4.
FIG. 6 is a schematic diagram of the present inven-tion showing the termination sense points.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring first to FIG. 1, a typical daisy-chained configuration is shown. As FIG. 1 shows, Dl and Dn have terminating devices in place, D2 through Dn_l do not.
With this configuration, assuming the terminating devices match the transmission line properly, there are no changes in the characteristic impedance of the trans-mission line, thereby reducing standing waves on thetransmission line.
To properly determine if the actual configuration meets the predicted configuration, two facts must be determined. First, should the termination devices be present. Second, are the termination devices present.
The first fact depends on the position in the daisy-chain.
In the present invention, each device on the daisy-chain has two connection ports. If a device is on the end of the daisy-chain then only one port is occupied.
However, if the device is in the middle of the daisy-chain, both ports are occupied. The circuit in FIG. 2 is used to detect the presence of each cable. If only one - cable is present (i.e. the device is on the end of the daisy-chain) then either CON_l_EQUIP or CON_2_EQUIP will be a logic high, but not both. If both cables are present (i.e. the device is in the middle of the daisy-chain) then both CON_l_EQUIP or CON_2_EQUIP will be alogic high. To facilitate multiple connections and detections, the connecting wire may need to be twisted or jumpered such that each cable sense pin senses a ground in the far end port.
Referring to FIGs. 3 and 4, where the recommended termination circuits for a single-ended and differential devices are shown respectively. Both configuration properly create a 132 ohm load for the termination of signal as required for the Small Computer Interface (SCSI). The present invention, as shown in FIG. 5, implements the load scheme of FIG. 4. It will be appre-ciated to one skilled in the art that the present inven-tion is not limited to this type of interface.
The signal names (e.g. -ACK) are used as described in American National Standard for Information Systems -Small Computer System Interface (SCSI) X3.131-1986. An exact meaning and function of the individual signals is not needed to understand the present invention. Looking closely at FIG. 5, an extra resistor in each package can be seen. For example RESISTOR PACK 1 contains an extra resistor. The extra resistor is connected to RESISTOR
R64 such that only when RESISTOR PACK 1 is present is the signal TERM_EQP_l a logic one. The extra resistor of RESISTOR PACKS 2 through 7 are used to control signals thereby indicating the presence or absence of the respective resistor pack. The seven signals from the individual resistor packs are used by the circuit in FIG.
6 to generate two signals; ALL_TERM_EQP and NO_TERM_EQP.
If and only if all seven resistor packs are equipped is the ALL_TERM_EQP signal a logic high. If and only if all seven resistor packs are absent is the NO_TERM_EQP signal a logic high. If some, but not all, of the seven resistor packs are installed then both ALL_TERM_EQP and NO_TERM_EQP will be a logic low.
The circuits of FIG. 2 and 6 can then be logically tested to determine if the configuration is correct. If only one of CON_l_EQUIP or CON_2_EQUIP is a logic high, then ALL_TERM_EQP must also be a logic high. If both CON_l_EQUIP or CON_2_EQUIP are a logic high, then NO_TERM_EQP must also be a logic high. Any other signal combination would be an error state and an appropriate indication should be enabled.
Although the preferred embodiment of the invention has been illustrated, and that form described, it will be readily apparent to those skilled in the art that various modifications may be made therein without departing from the spirit of the invention or from the scope of the appended claims.
Claims (6)
1. A circuit for detecting and verifying a presence of a terminating device, said circuit comprising:
a first cable detector means for generating a first signal if a first cable is present;
a second cable detector means for generating a second signal if a second cable is present;
a terminating device detector means for generating a third signal if said terminating device is present; and a verifier means arranged to receive said first signal, said second signal and said third signal, said verifier means verifies that if said third signal is present then only one of said first signal or said second signal is present, said verifier means verifies that if said third signal is absent both said first signal and said second signal are present.
a first cable detector means for generating a first signal if a first cable is present;
a second cable detector means for generating a second signal if a second cable is present;
a terminating device detector means for generating a third signal if said terminating device is present; and a verifier means arranged to receive said first signal, said second signal and said third signal, said verifier means verifies that if said third signal is present then only one of said first signal or said second signal is present, said verifier means verifies that if said third signal is absent both said first signal and said second signal are present.
2. A circuit for detecting and verifying a presence of a terminating device as claimed in 1, said terminating device comprises a resistor network.
3. A circuit for detecting and verifying a presence of a terminating device as claimed in 2, wherein:
said resistor network is contained in a plurality of resistor packs;
each of said plurality of resistor packs contains an extra resistor: and said terminating device detector means senses said extra resistor presence, thereby detecting said presence of said terminating device.
said resistor network is contained in a plurality of resistor packs;
each of said plurality of resistor packs contains an extra resistor: and said terminating device detector means senses said extra resistor presence, thereby detecting said presence of said terminating device.
4. A circuit for detecting and verifying a presence of a terminating device as claimed in 3, wherein said terminating device detector means generating an ALL-EQUIPPED signal and a NON-EQUIPPED signal, said ALL-EQUIPPED signal is generated when all of said plurality of resistor packs are present, said NON-EQUIPPED signal is generated when all of said plurality of resistor packs are absent.
5. A circuit for detecting and verifying a presence of a terminating device, said circuit comprising:
a first cable detector means for generating a first signal if a first cable is present;
a second cable detector means for generating a second signal if a second cable is present;
said terminating device is contained in a plurality of resistor packs;
each of said plurality of resistor packs contains an extra resistor;
a terminating device detector means for generating a third signal if said terminating device is present, said terminating device detector means senses said extra resistor presence, thereby detecting said presence of said terminating device; and a verifier means arranged to receive said first signal, said second signal and said third signal, said verifier means verifies that if said third signal is present then only one of said first signal or said second signal is present, said verifier means verifies that if said third signal is absent both said first signal and said second signal are present.
a first cable detector means for generating a first signal if a first cable is present;
a second cable detector means for generating a second signal if a second cable is present;
said terminating device is contained in a plurality of resistor packs;
each of said plurality of resistor packs contains an extra resistor;
a terminating device detector means for generating a third signal if said terminating device is present, said terminating device detector means senses said extra resistor presence, thereby detecting said presence of said terminating device; and a verifier means arranged to receive said first signal, said second signal and said third signal, said verifier means verifies that if said third signal is present then only one of said first signal or said second signal is present, said verifier means verifies that if said third signal is absent both said first signal and said second signal are present.
6. A circuit for detecting and verifying a presence of a terminating device, said circuit comprising:
a first cable detector means for generating a first signal if a first cable is present;
a second cable detector means for generating a second signal if a second cable is present;
said terminating device is contained in a plurality of resistor packs;
each of said plurality of resistor packs contains an extra resistor;
a terminating device detector means for generating an ALL-EQUIPPED signal and a NON-EQUIPPED signal, said ALL-EQUIPPED signal is generated when all of said plurality of resistor packs are present, said NON-EQUIPPED signal is generated when all of said plurality of resistor packs are absent; and a verifier means arranged to receive said first signal, said second signal, said ALL-EQUIPPED signal and said NON-EQUIPPED signal, said verifier means verifies that if said ALL-EQUIPPED signal is present then only one of said first signal or said second signal is present, said verifier means verifies that if said NON-EQUIPPED
signal is present both said first signal and said second signal are present.
a first cable detector means for generating a first signal if a first cable is present;
a second cable detector means for generating a second signal if a second cable is present;
said terminating device is contained in a plurality of resistor packs;
each of said plurality of resistor packs contains an extra resistor;
a terminating device detector means for generating an ALL-EQUIPPED signal and a NON-EQUIPPED signal, said ALL-EQUIPPED signal is generated when all of said plurality of resistor packs are present, said NON-EQUIPPED signal is generated when all of said plurality of resistor packs are absent; and a verifier means arranged to receive said first signal, said second signal, said ALL-EQUIPPED signal and said NON-EQUIPPED signal, said verifier means verifies that if said ALL-EQUIPPED signal is present then only one of said first signal or said second signal is present, said verifier means verifies that if said NON-EQUIPPED
signal is present both said first signal and said second signal are present.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US692,404 | 1991-04-26 | ||
| US07/692,404 US5120909A (en) | 1991-04-26 | 1991-04-26 | Terminating devices detection and verification circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2067032A1 CA2067032A1 (en) | 1992-10-27 |
| CA2067032C true CA2067032C (en) | 1997-02-11 |
Family
ID=24780445
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002067032A Expired - Fee Related CA2067032C (en) | 1991-04-26 | 1992-04-24 | Terminating devices detection and verification circuit |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US5120909A (en) |
| CA (1) | CA2067032C (en) |
Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1994008305A1 (en) * | 1992-10-02 | 1994-04-14 | Compaq Computer Corporation | Automatic disabling of termination of a digital computer bus |
| US5473264A (en) * | 1992-11-13 | 1995-12-05 | Apple Computer, Inc. | Methods and apparatus for electrically terminating a high speed communications pathway |
| US5313595A (en) * | 1992-12-10 | 1994-05-17 | Digital Equipment Corporation | Automatic signal termination system for a computer bus |
| JP3483594B2 (en) * | 1993-07-20 | 2004-01-06 | 富士通株式会社 | Semiconductor device |
| US6567877B1 (en) * | 1993-08-16 | 2003-05-20 | Sun Microsystems, Inc. | Automatically enabling terminator for internal SCSI buses with external SCSI bus expansion |
| EP0645716A1 (en) * | 1993-09-24 | 1995-03-29 | Advanced Micro Devices, Inc. | Termination circuits for SCSI host bus adapter |
| US5568046A (en) * | 1994-08-04 | 1996-10-22 | Methode Electronics, Inc. | Inactive state termination tester |
| US5613074A (en) * | 1994-12-30 | 1997-03-18 | Compaq Computer Corporation | Automatic disabling of SCSI bus terminators |
| US5596757A (en) * | 1995-02-16 | 1997-01-21 | Simple Technology, Inc. | System and method for selectively providing termination power to a SCSI bus terminator from a host device |
| US5592123A (en) * | 1995-03-07 | 1997-01-07 | Linfinity Microelectronics, Inc. | Frequency stability bootstrapped current mirror |
| US5686872A (en) * | 1995-03-13 | 1997-11-11 | National Semiconductor Corporation | Termination circuit for computer parallel data port |
| US5608312A (en) * | 1995-04-17 | 1997-03-04 | Linfinity Microelectronics, Inc. | Source and sink voltage regulator for terminators |
| US5635852A (en) * | 1995-04-17 | 1997-06-03 | Linfinity Microelectronics, Inc. | Controllable actice terminator for a computer bus |
| EP0742612A3 (en) * | 1995-05-02 | 1997-07-23 | Symbios Logic Inc | Multi-connector termination method and apparatus |
| US5680555A (en) * | 1995-07-26 | 1997-10-21 | Computer Performance Inc. | Host adapter providing automatic terminator configuration |
| JPH09204243A (en) * | 1996-01-29 | 1997-08-05 | Fujitsu Ltd | Data transfer method |
| US5864715A (en) * | 1996-06-21 | 1999-01-26 | Emc Corporation | System for automatically terminating a daisy-chain peripheral bus with either single-ended or differential termination network depending on peripheral bus signals and peripheral device interfaces |
| GB9615445D0 (en) * | 1996-07-23 | 1996-09-04 | 3Com Ireland | Cascade connection of communicating devices |
| US6070206A (en) * | 1997-03-31 | 2000-05-30 | Lsi Logic Corporation | Method and apparatus for terminating a bus |
| US6061806A (en) * | 1997-05-12 | 2000-05-09 | Lsi Logic Corporation | Method and apparatus for maintaining automatic termination of a bus in the event of a host failure |
| US6029216A (en) * | 1997-06-27 | 2000-02-22 | Lsi Logic Corporation | Auto-termination method and apparatus for use with either active high or active low terminators |
| US6092131A (en) * | 1997-07-28 | 2000-07-18 | Lsi Logic Corporation | Method and apparatus for terminating a bus at a device interface |
| US20040249991A1 (en) * | 2003-06-03 | 2004-12-09 | Dell Products L.P. | Cable detection using cable capacitance |
| US7464195B2 (en) * | 2006-05-22 | 2008-12-09 | International Business Machines Corporation | Method and apparatus for detecting a presence of a device |
| US7614767B2 (en) * | 2006-06-09 | 2009-11-10 | Abl Ip Holding Llc | Networked architectural lighting with customizable color accents |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2498846B1 (en) * | 1981-01-23 | 1986-10-10 | Thomson Csf | SELF-CORRECTED ELECTRIC FILTERS IN GROUP PROPAGATION TIME |
-
1991
- 1991-04-26 US US07/692,404 patent/US5120909A/en not_active Expired - Lifetime
-
1992
- 1992-04-24 CA CA002067032A patent/CA2067032C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US5120909A (en) | 1992-06-09 |
| CA2067032A1 (en) | 1992-10-27 |
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