CA2067384A1 - Metal pin grid array package - Google Patents
Metal pin grid array packageInfo
- Publication number
- CA2067384A1 CA2067384A1 CA002067384A CA2067384A CA2067384A1 CA 2067384 A1 CA2067384 A1 CA 2067384A1 CA 002067384 A CA002067384 A CA 002067384A CA 2067384 A CA2067384 A CA 2067384A CA 2067384 A1 CA2067384 A1 CA 2067384A1
- Authority
- CA
- Canada
- Prior art keywords
- holes
- package
- array
- base component
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
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- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
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- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
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- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
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Abstract
A metal pin grid array package (50) and a process for the assembly of the package (50) is provided. The package (50) includes a metal or metal alloy base component (12) having an ordered array of holes (35). Terminal pins (30) are electrically interconnected to a desired circuit (14) and extend through the ordered array of holes (35). A dielectric polymer sealant (52) bonds a cover component (36) to both the circuit (14) and to the base component (12). During package (50) assembly, the polymer sealant (52) flows into the holes comprising the ordered array of holes (35) electrically isolating the terminal pins (30) from the base component (12).
Description
w 0 91/~8587 2 0 ~ 7 3 8 ~ PCr~US90/06600 METAL PIN GRID ARRAY PACKAGE INCLUDING DIELECTRIC POLYMER SEALANT
While the invention is subject to a wide range of applications, it is particularly suited for,metal packages to house an electronic device. In particular, the invention relates to epoxy sealed pin grid array-type packages having S a metal or metal alloy base component.
Microelectronic devices are typically manufactured .
from a semiconductor material, such as silicon, germanium or gallium/arsenide. The semiconductor material is fashioned into a die, a generally rectangular.structure having lo circuitry formed on one surface. Along the periphery of that surface are input/output pads to facilitate electrical '' interconnection to e~ternal components. :~
- The semiconductor device is brittle and requires .-:~
protection from moisture and mechanical damage.~ This . ,.'~
15 protection is pro~ided by a package. The package-also ''c'ontiins an electrically conducti~e means. to transport electrical signals between.the semiconductor device and ~'~' esternal circuitry. ~ J,~
~ 'One package design which.minimizes space requirements ;^and provides a high density of.~:interconnections,between the ; electronic:device'and esternal circuitry.~is the::pin grid ~
array 'pickage. 'The conventional pin;~grid array:package ' comprises-a-multilayer;alumina.,(A12O3)msubstrate havinq '~ 25''c`o~nducti~ve'``circuitry'disposed between~-,the.layers;.,ilThe circuitry terminates at--a plurality..of conductive.pads to '~;'~ ;''which terminalCpins;are-brazéd - The pins.,are generally ^? ;configu`red into a:regularaarray7;i~iu;s~ P,atent~Number ~ ' i,'821',1Sirto'Pryor~et~.al~aiscloses a.ceramic:pin~grid array '~' `30~pac`kige.;~ r.; ~ n~ ;N .3L~ . j .-~t '~
' :: `
While the invention is subject to a wide range of applications, it is particularly suited for,metal packages to house an electronic device. In particular, the invention relates to epoxy sealed pin grid array-type packages having S a metal or metal alloy base component.
Microelectronic devices are typically manufactured .
from a semiconductor material, such as silicon, germanium or gallium/arsenide. The semiconductor material is fashioned into a die, a generally rectangular.structure having lo circuitry formed on one surface. Along the periphery of that surface are input/output pads to facilitate electrical '' interconnection to e~ternal components. :~
- The semiconductor device is brittle and requires .-:~
protection from moisture and mechanical damage.~ This . ,.'~
15 protection is pro~ided by a package. The package-also ''c'ontiins an electrically conducti~e means. to transport electrical signals between.the semiconductor device and ~'~' esternal circuitry. ~ J,~
~ 'One package design which.minimizes space requirements ;^and provides a high density of.~:interconnections,between the ; electronic:device'and esternal circuitry.~is the::pin grid ~
array 'pickage. 'The conventional pin;~grid array:package ' comprises-a-multilayer;alumina.,(A12O3)msubstrate havinq '~ 25''c`o~nducti~ve'``circuitry'disposed between~-,the.layers;.,ilThe circuitry terminates at--a plurality..of conductive.pads to '~;'~ ;''which terminalCpins;are-brazéd - The pins.,are generally ^? ;configu`red into a:regularaarray7;i~iu;s~ P,atent~Number ~ ' i,'821',1Sirto'Pryor~et~.al~aiscloses a.ceramic:pin~grid array '~' `30~pac`kige.;~ r.; ~ n~ ;N .3L~ . j .-~t '~
' :: `
2 0 ~ 7 ~ ~ ~1 PCT/US90/06 ~' Molded plastic pin grid array packages are also known in the art. In one configuration, disclosed in U.S.
Patent No. 4,688,152 to Chia, a printed circuit wiring board having plated through holes serves as the package 5 base. An integrated circuit device is bonded to one face of the printed circuit board. Lead wires electrically interconnect the integrated circuit device to circuit traces on the board. The circuit traces terminate at conductive rings containing terminal pins which pass lo through the printed wiring board and exit the opposite - surface of the board. The surface containing the integrated circuit, wire bond and circuit traces, is then encapsulated in a molding plastic.
Yet another molded plastic pin grid array package is 15 disclosed in V.S. Patent Number 4,816,426 to Bridges et al. The patent discloses a circuit tape having terminal pins prebonded to the tape. The pins are electrically interconnected to circuit traces formed on the tape. The assembly is then partially encapsulated within a polymer 20'resin.
; : Ceramic pin grid array packages have e~cellent ~ reliability, but are brittle, espensive and are poor conductors of heat. One of the chief advantages of,a pin grid array package is the high number of electrical : 25 interconnections possible. The more complex the integrated - ~^ circuit,-:the-more heat-generated-during,operation., If this heat is-not removed,.the.device operating--life--is-, ' -- decreased.':-:It,has been estimated that-fo,r "every.~10 C
? '~increase.in operating temperature the effect,i,v,e operating i: 30 life of the dev,ice is:decreased by~,50,percent.,-, _ Plastic pin grid.array,packages,,,ar,e not brittle and :considerably cheaper toïmanufacture than,ceramic,pin grid array packages.i The thermaliperformance of a;plastic pin grid array packige may be improved by moldingi,a metal~heat 35 spreader into the body of the package as disclosed in the ' : . :
''~'. WO91/08587 2d6~3~ PCT/US90/06600 above cited U.S. Patent Number 4,816,426. While such a package gives e~ceptional performance, the large surface area of e~posed plastic makes plastic pin grid array packages susceptible to moisture permeation.
One way to achieve the hermeticity and reliability of the ceramic package with the reduced cost and improve thermal performance of the plastic pin grid array package is with a metal pin grid array package. A hermetic metal pin grid array package is disclosed in a Toshiba new 10 product release entitled ~METAL PIN GRID ARRAY PACKAGE".
The publication discloses a printed wiring board circuit containing a plurality of terminal pins.. The pins exit the -wiring board and pass through a metal base. An isolation '.
seal electrically isolates the terminal pins from the metal 15 package base. .. '.
The composition of the isolation seal is not disclosed. It appears to be a cylindrically-shaped apertured preform of a metal sealing glass composition such - as-a borosilicate. ~hese preforms are widely used to ~20 isolate,feed through~pins from.metal-package,bases in .
'; hybrid packaging.-:.E~amples-of.:.isolation seals:are given in ~ U.S. Patent Number.4,706,3821to Suppinger.et,al as well as : -': - U.-S. Patent Number 4,716,082 to Ahearn,;et al.. -~.. , ;~ Disadvantages with,the use of isolation seals :.
--' : ^25-'-include:cost and.difficulty~.of assembly. .Preforms, either ' ._.'? . ' glass~or~plastic, are inserted~on,each terminal~pin. Each tèrminal-pin~`is-then-~aligned.iwithin the metal base prior to formation1of the?isola~ion.seal.-.~-,;If the seal:is,glass, it ' must be~carefully selected so that:~the.coefficient of 30 thermal~,e~pansion--of?the glass.iis~close.:(typically within about 10 percent) tosthe coefficient of thermal,expansion ''t~of~the~package baseiand;the:terminal pins.~ Since the glass is~inherently~brittle, glass-fracture-.and..loss.of electrical isolation is a potential problem.-,,,.~;
'. 35 Accordingly, it is an object of the invention to provide a metal pin grid array package ha~ing improved . ~ .
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WO91/08587 PCT/US90/06 ~ ' thermal performance over both ceramic and plastic packages, while retaining the cost benefits of a molded plastic package. It is a further object of the invention to minimize water permeation by limiting the amount of plastic 5 e~posed to the atmosphere. It is an advantage of the invention that feed throughs are not employed for electrical isolation. It is a further advantage of the invention that the metal package components may be easily formed by conventional stamping techniques. It is a lo feature of the invention that the metal base component may - be either copper or aluminum, or alloys of these metals to masimize ,conduction of heat from the integrated circuit device. It is yet another feature of the invention that ' metal package components may be coated with another metal 15 or with a refractory oside layer to ma~imize adhesion.
Accordingly, there is provided a metal pin grid array package. The package has a cover component and a metal or metal alloy base component. The base component ' contains--an ordered array of holes. A circuit is disposed 20 between~the cover component-and the base component. A
plurality of terminal--pins are electrically interconnected - to the circuit. The:pins e~tend outwardly through the ordered~array of holes:in the package base. -A dielectric - sealing means bonds the cover component to both the circuit ' : 2s and~to theibase component, as well~as the base component to 7the circuit. The dielectric sealing meanslfurther e~tends 'i -' into thesarray of,holes to,:electrically isolate the ;'' -' ~- terminal~pins from the metal-,or metal alloy.base component.
The above'stated objects, features-and advantages of ~,' 30 the invention will~become more~apparent from the~, ~ specification and;Figures which-follow:,7 :~ ? -~s~ *':S;Y~ Figure l shows~in~top planar view~the,relationship betweenithe package:base--component of;the invention and a circuit-.~ -.~i -'-; ~ ,;~~i .,~, ~ Y,'`';', .. , ~ . . ... ... . . . .
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Figure 2 shows in cross-sectional representation the metal pin grid array package of the invention prior to assembly. ..
Figure 3 shows in cross-sectional representation a -' 5 metal pin grid array package in accordance with the invention. ~ :.
Figure 4 shows in cross-sectional representation a ~ -means for electrically isolating the terminal pins in accordance with one embodiment of the invention.
lo Figure S shows in cross-sectional representatio~ a metal pin grid array package in accordance with a second embodiment of the invention.
Figure 1 shows in top planar view a portion of a pin grid array package 10 in accordance with the invention. - ' 15 The package 10 includes a base component 12 and a.circuit 14. A first polymer sealant 16 is disposed between the base component 12 and circuit 19. The peripheral dimension of base component 12, that:is the sum of the length and width, is larger than the peripheral dimension of the first 20 polymer sealant.16, which in~iturn-has larger.~peripheral dimensions-than the circuit.l4. Although the'packa~e ~ components-.are shown.as square and most conventional pin . ;. grid array-packages.have equal lengths and widths, the package.10 may be rectangular or any-desired shape in ...... 25 accordance with the.-invention.' - - ..i ~tt . A personality window~'l8 is formed through both the ;circuitl14 and.the first~polymer sealant 16 to permit the integrated circuit device (not shown) to be bonded directly .tO the base::component:12.~ a 30...~ ., 3~.The circuit i4~comprises at least one metal layer and preferably, at .least-one dielectric::support~layer 20.
;The-dielectric:.:support~.layer.;20:may;.be.any non-conductive .Dmedium<~uch as a-ceramic;?~glass'or~polymer.`'A-polymer support.layer.may be :rigid'such as-'a glass filled epo~y or 35 flesible.such as a polyimide. One suitable'polyimide'is Rapton manufactured by Dupont.
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WO91/085~7 PCT/US90/066 A conductive metal layer 22 is bonded to the dielectric support layer 20 such as by lamination. The conductive metal layer is generally quite thin, on the order of about .018mm (.0007 inches) to about .071mm (.0028 5 inches) thick. To insure adequate current carrying capability through the relatively small cross sectional area circuit traces, a metal having high electrical conductivity such as copper or a dilute copper alloy preferably form the conductive layer 22. The conductive lo layer is formed into a plurality of circuit traces 23 and terminal pin bonding sites 24.
The conductive layer is typically patterned by photolithographic technigues. Briefly, this process entails applying a-photosensitive resist over the 15 conductive metal layer 22. A mask defining the desired circuit pattern or its negative image is placed over the resist. A light source esposes those areas not shielded by the mask. The photoresist polymerizes in the esposed areas and becomes resistant to a first solvent. The photoresist 20 which.did.not polymerize::is.then removed-by dissolution in -this first solvent. The e~posed metal foil.is.then etched, .using a suitable acid or.combination of acids to:e2pose the underlying polyimide layer. After rinsing away..the acid . etchant,-a second solvent removes by.dissolution the 2s polymerized resist. Metal circuit .traces.23 in .the desired .... léad-pattern remain.. The photolithographic techniques may employ .either positive or negative photoresists.as known in the:art. ~ J;..i`~. _ .. ' - . `' ' ;' ' '~.' ' ~'~ ' -i Fig. 1 shows circuit traces.23.originating from only :30 a portion of.the bonding~sites 24 to.-facilitate drawing ~ clarity. -.Generally,~a circuit.trace .23 will originate from j~ .ul.each or!~most circuit!traces.and terminate~at:personality ~ .window.18. ..;~he total number.of bondin~ sites.is..limited - --. only by..the resolution of the photolitographic technique .35 employed and the size of-the-base component 12 and .
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personality window 1~. It is within the scope of the invention for the circuit 14 to include several hundred bonding sites 24.
The terminal pin bonding sites 24 include a 5 metallized region 26 formed in conjunction with the circuit trace 23. An aperture 28 e~tends through the center of each metallized region and the underlying support layer.
The aperture 28 diameter is sized to receive a terminal pin.
Figure 2 shows in cross-sectional representation a o metal pin grid array package 10~ prior to assembly. A
terminal pin 30 passes through the circuit 14 by way of aperture 28. The terminal pins 30 are formed from any machinable electrically conductive material. The terminal pins 30 preferably have sufficient tensile strength to 15 resist deformation during repeated insertions and removals. Preferably, the terminal pins are formed from copper or a copp~r base alloy, such as C510 .(also known as phosphor-bronze, having the nominal composition 3.5-4.9% by weight tin, 0.03-03.5% by weight phosphorus, and~the ~ 20 balance~copper)..- Alternati~ely, an iron nickel alloy,--such :i :. as XOVAR-i(a.trade name for an iron-nickel-cobalt alloy) may ` be employed. The~terminal pins 30 may be.coated with : another metal to enhance solderability and.adhesion as ; -~described-below.-... :. -2s ~ ; The~terminal pins.30 are electrically~interconnected . to the.bonding~sites~24. Electrical.iinterconnection may beby mechanical.contact::as disclosed:in U.S.~Paten~ Number ;-4,~816,426-cited.above, or by~a technique such ~s.f;soldering ^is'disclosed.in U.S.~ Patent~No. 4;965,27?..by Chang et al.
30 A.solder paste is applied to.the metallized region~26:of ?~bondingrsites 24 by~a process such:as~screen~printing.
~-?After insertionJof~the~pins,.a.solder bond is formed by .`lheating the assembly to;a temperaturelsufficient to melt and flow the.solder. ~For e~ample,-a solder paste : 35 comprising 60ipercent.by weight lead and 40 percent-by weight tin would melt and flow at a temperature of about 250C.
- .' , ~' , ' ., Wosl/085g7 2 0 G ~ '~ 8 '1 PCT/US90/06 ~'' Any solder having a melting point below about 275C and capable of bonding to the metallized regions 26 of bonding sites 24 and to tRrminal pins 30 is acceptable.
The temperature limitation'is related to the dielectric 5 support layer 20. At temperatures above about 275 polyimide begins to degrade. Of course, if a more thermally resistant support layer is employed, the ma~imum ' temperature and number of suitable solders are both increased.
lo An integrated circuit device 32 which may be a silicon based semiconductor circuit is electrically interconnected to circuit traces 23. Electrical interconnection may be by bond wires 34. The bond wires 34 are thin, on the order of .025mm (.001 inch) in diameter, 15 wires formed from copper, aluminum, gold or alloys thereof. The bond wires are bonded to the integrated circuit device 32 and to the circuit traces 22 by a wire - bonding process such-as thermosonic or thermocompression bonding.
'' 20 -' -As^ an alternative to bond'wires 34,- foil leads-(not shown) formed'from the conductive metal layer 22 may e~tend 'in cantilever fashion into the personality window 18. The foil'leads are then bonded to the input/output pads of the integrated circuit device 32 by thermocompression bonding 25'by:the technique known as tape'automated bonding (TAB).
~: ^~-The circuit-assembly comprising the circuit 19, :'~; bonded-termi'nal''pins~30-and bonded device 32 is disposed ;;between''thë base'component 12 and a~-cover component 36.
~ The"terminal pins'32~pass through'a first:arra~y~of holes 35 30~formed'in`the base component; The base:component~l2 is 'formed!from~a-metal or a metal alloy.:. To ma~imize the '~ dissipation''iof heat from the electronic-device 32 through '''''~'the bise'component'l2,;!the base component is preferably formed from~':copper, aluminum or alloys thereof. Most 35:preferably, the base component comprises an aluminum base `, ~
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20S73~
'~ WO9~/08~81 PCT/US90/06600 alloy, such as aluminum alloy 3003 (nominal composition 0.05-0.20 weight percent copper, up to 0.6 weight percent silicon, up to 0.7 weight percent iron, up to 0.1 weight percent zinc and the balance aluminum). Aluminum and 5 aluminum base alloys are preferred since they have been found as effective as copper for the dissipation of heat from the electronic device and have a density only 60% that of copper. The thermal performance of an aluminum base alloy package is about equivalent to that of a copper or lo copper alloy base package and yet weighs only 60~ as much.
Reduced package weight is desirable in applications such as aerospace and where e2cess weight is a penalty such as packages subject to rapid acceleration.
The first array of holes 35 has the same 15 configuration as the apertures 28 formed'in the circuit 14. The diameters of the holes comprising the first array of holes 35 is sufficiently large that.terminal pins 30 pass through the holes without contacting the base component 12.
~ -~i ;;Th'e array 'o`fAholes"-3~ may-be formed by.any suitable '' metal removal~'techniques'such'as drilling, piercing, stamping or:themicil-'milling.- From.both.-a process -repr'oduc`ibility and a'process--rate-standpoint, stamping or piercing a're preférred to`form the first array of holes 35.
` 2s'~ ` 'The'c'over~component-36:may-be--fashioned.from any material`which bonds'`to-a second polymer~sealant 3~. The cover compone`nt 36'2is s'elected from:.the.groupiconsisting of - thermose'tting 'polymers,~ thermoplastic.3polymers, ceramics, --~-meta'ls a'nd~metal alloys~5às-~well~as-composite materials, 30 ? such~asLcèrmets'~ind cerglassm ~The-choice~of:material^is ~''dependentlupon the"application and the.desired.,properties ;1~ of-the'~mëtal'pingrid array-package.c-~A~molded~plastic *cover component 3j 6`~ 2 ~uch''as~a~pre-molded~epo~y.cover, --i providés the'advantagès of low cost,agood adhesion to 35'-polymer seilantland:light weight.- However, moisture.
permeation i8 a problem.
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WO 91/08587 2 0 5 ~ PCr/US90/06~
A ceramic cover component has the advantages of being lightweight and imparting rigidity to the overall metal pin grid array package. However, most common ceramics such.as aluminum o~ide ~A12O3) have a S coefficient of thermal e~pansion of about 4.9~10 7/oC.
Copper and aluminum have coefficients of thermal e~pansion ' in e~cess of about 170~10 7/oC. The mismatch in coefficients of thermal e~pansion may result in package fle~ure during thermal cycling severe enough to fracture lo the electronic device 32.
Most.preferably, the cover component 36 is selected to be a metal.or metal alloy. The cover component 36 may have the same composition as the base component 12 or a different alloy may be selected. For e~ample, the base 15 component 12 may be selected to be copper or a copper base alloy having high thermal conductivity such as CllO
(electrolytic tough pitch copper having the nominal composition 99.90% by weight copper and a maximum o~ygen concentration of 0.05%). The cover component 36 may be 20uselected to-be high strength,copper alloy such as C724 (nominal composition.84.3% by~weight-copper, 13.0% nickel, 2.~0%-:aluminum, 0.5% manganese and 0.,2% magnesium). Thermal ~conduction is ma~imized through the dilute copper base -alloy. The high yield strength alloy ~forming t.he cover ~:
25 contributes:rigidity:of~the-metal pin,grid,,array package ';' lO'.': To minimi,ze.,package weight.~both ,the.base.and.,cover '~' S~ components~may.~be an aluminum base.alloy..,~
A dielectric.:sealing means-.is,,provided as,first 16 ;'S-and second 38 polymer~sealant~layers.j,-The,dielectric :~;30iproperty:;0f.the sealant-,mainta,i,ns,electrical,isolation : i ~between the:terminal pins,30",the~conduc,t,iv,e~,met,al,1ayer '~''22,~theibase~component.12~and the coverlcomponent.36. The -~first~16.~and~second 38 polym,er?,sealant}layers may~.be .~provided,as discrete sheets of an,adhesive or in paste or 35 1iquid:form and deposited by a process such as screen printing.
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' WO91/08587 PCT/US90/06600 The dielectric sealant is selected to be a polymer adhesive which cures at a temperature below about 275C
to prevent thermal degradation of the dielectric support layer 20. The polymer sealant is selected to be what is 5 known in the art as ~semiconductor grade~. Semiconductor grade adhesives release lower amounts of ionic contaminants during the cure reaction than standard adhesives. Ionic - contaminants are undesirable. They may deposit on the bond wires 34 or metallized surfaces of the electronic device 32 lo leading to corrosion and device failure.
The dielectri~ sealant is preferably selected to be a thermosetting polymer resin such as an epo~y. One suitable epo2y is Abléstik 550 is manufactured by Ablestik ' Labs, Gardenia, CA. The adhesive cures and provides 15 sufficient flow when heated to a temperature of from about 125C to about 175C and a pressure of from about 35 gm/cm2 (0.5 psi) to about 105gm/cm2 (1.5 psi).
- Pressure may be applied through the use of a clamp.
The'second adhesi've layer 38 has essentially the 20 samé peripheral'dimension~''asrthe~first7adhesive 1ayer 16.
The second polymer sealant layer 38 is larger-than the c'ircuit 14 and smaller than the base component 12 or cover ''component 36.
~'- The'first polymer adhesive layer-16 is disposed 2s between~bise component'l2 and circuit 14. ~The,'first -;
polymerisèala,nt'layer-16 is-~provided,with a second array of ~holes 40'correspo'nding"to the'first array-of holes-35. The --diàmetër~of the-holés;maki~ngi-up;this second~array of holes 40'i's s'1ightlyilarger than"the--diameter:of terminal pins '30 30. To minimize9the;required Yolume-of sealant,~,the'-:
- ^diimëter of-tXe-~sëcond arr'ay-of~holes-40iis~lessfthan about 25mm-~(.'010iinchës)''iarger thin'the~diameteriof~the term;nai pins'j0.'3AMor'e'~preferably,';the diameter of the -second array'-~of~'holes~'40;is from about .O25mm~to about 35 l.'1i7mm (.001 - .005'inches) làrger than the diameter of the terminal pins 30. ' ~
WO91/08587 2 0 6 7 ~ 3 ~ PCT/US90/066~' The diameter of the first array of holes 35 is on the order of about .127mm to .51mm (.005 to .020 inches) larger than the diameter of the terminal pins 30. More preferably, the diameter of the holes comprising the first 5 array of holes is from about .25mm to about .38mm (.010 to ~015 inches) larger than the diameter of the terminal pins 30. The terminal pins 30 e~tend through the first 35 and second 40 arrays of holes. Electrical isolation between the metal or metal alloy base component 12 and the terminal lo pins 30 is provided by the first polymer adhesive 16 which flows into the first array of holes 35. In one embodiment of the:invention a refractory oside layer is formed within the first array of holes 35. The refractory o~ide also contributes to terminal pin isolation.
~ The second polymer adhesive layer 38 is disposed between the cover component and the circuit 14. An '~
aperture 44 is preferably provided in the second polymer sealant layer 38 so adhesive does not flow over the bond wires 34 or the integrated circuit device 32. Other . ,20 techniques.'.~to control.polymer.flow.such as dams may also be -~
::employed.
-~ . . A:die-attach material 46 is disposed between the integrated circuit 32 and package base 12... While the ... electronic device 32 may be free,floating and supported ~5 solely.,by the bond wires,34 the..~use of a,die attach .: , .provides aniimproved thermal,-conduction pa,th.~.The die . '.attach material 46,may be any,thermally conductive material '.which-bonds to the.backside,of;,the integrated~circuit ..!'':'` device~32~~.and,package base-12.,.The-die.attach material 46 30ishould.have a melting or cure temper,ature approximately .. ., ',equal-,to,the cure.~temperature ,of-the~dielectric.sealant.
Suitable~die.attach materials~-~include~low~melting solders ; 'such as 60% lead/40%.tin,,~or.~.pr,eferably,..a polymer,jadhesive - :;filled.with a..thermally conductive.material. One such ; - -35 adhesive;.is a silver:filled epo~y known as Ablefilms , manufactured by Ablestik Labs.
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WOgl/08587 PCT/US90/06600 The package 10' of Figure 2 is bonded to complete assembly of the metal pin grid array package 50 of Figure 3. The application of heat and pressure causes first 16 and second 38 polymer adhesive layers to flow. The layers 5 fuse to form a continuous dielectric layer 52. Since the peripheral dimension of first 16 and second 38 polymer sealant layers is larger than the peripheral dimension of fle~ible circuit 14 following the cure cycle the dielectric sealing means 52 e~tends beyond the edges of the circuit 14 ~ to form a continuous surface 54.
A major source of moisture penetration into an electronic package is along plastic~metal interfaces.
Elimination of the circuit 14 with metal circuit traces 23 from the edges of the package 50 reduces the possibility of 15 moisture penetration. The dielectric sealing means 52 ,-bonds the cover component 36 to both the circuit 19 and to the base component 12.
' The base component 12 is bonded to -the circuit 14.
During the cure cycle, the dielectric sealing means 52 '20 flows'into the first:-array,of holes.35.in;^.the base, component 12. -The polymer sealant 52 effectively centers 'the interconnect pins 30'within each hole comprising the array..' - ' ~
The dielectric sealant S2 further electrically 25-isolates'the terminal pins 30 from the,metal.,or.metal ~alloy 'base component 12. To prevent electr.ical,leakage".,through ~' 'the dielectric sealant 52, the resistivity-..of-~the.:~
' '''dielectric-within the firs't:~array of,holes.35!mus.t,~be '''sufficientlylhigh. ~Resistïvity..is defined.-as-the..electric 30 resistance^offered:by a material to the flow of current.
~ ''It'is a':function 'of the cross sectional.;area,of the current ~r -' C` '-' f low ind''the~unit~'length''-of~current~path.~Resistance.to -' currentl~leakage`'within the:'first array.nfi~holes,,35~,is a function of the'dielectric sealant 52 as well as the 35 separation distance between the terminal pin 30 and the ~ --.
WO91/08587 2 0 ~ 7 3 ~ ~ PCT/US90/066~. ~
base component 12. For a typical eposy adhesive having a dielectric constant of about 4, a separation of about .25mm (.01 inches) will provide for electrical resistivity of greater than about 101 ohms which is sufficient to 5 prevent current leakage.
~ y regulating cure cycle time, pressure and temperature, the depth of dielectric sealant 52 penetration within the first array of holes 35 is controlled.
Preferably the cure cycle is selected so that the lo dielectric sealant does not flow beyond the bottom edge 55 of the base component 12. The e~cess flow of sealant and the resulting formation of a flash along the terminal pins 30 may interfere-with the proper electrical functioning of the pins.
To improve the bond between dielectric sealant 52 and the metal components of the pin grid array package 50, it is prefera~le to provide a surface coating on the metal components or at least those surfaces of the components in contact with the dielectric sealant. The surface coating 20 may-be-formed'in situ. An in situ coatinq is formed from the metal alloy itself. Certain copper or copper base alloys such as C638 ~2.5-3;1 weight percent aluminum, 1.5-2.1 weight percent silicon, 0.25-0.55 weight percent cobalt and the balance copper) are capable of forming an in '25 situ refractory oside layer,~substantially A1203,. The , refractory oside layerris typically:formed by placing the copper base'alloy;in a.container having an atmosphere of 4%
hydrogen',,-96% nitrogen and a,trace o,,f,water. ~,The gas is heated.to a-itemperature of,between about,330,C and about 30?-820C.~ Depending on the:temperature,:dwell~ti,me,~a "J refràctory o~ide-layer of.-a desired-thickness,is formed on '-''3 -~:the~surface~;of--the-alloy.~~Formation,of-suchsa refractory ~ ~ o~i'de~is disclosed in U.~S.-,~Patent,Number 4,461,924~to Butt e`t al.'`' - ,' , , 20S73~
, : WO91/08587 PCT/US90/06600 The coating layer may be formed by depositing a second material on the metal components. For copper and copper base alloys a coating layer of a second metal such as nickel is preferred. As disclosed in U.S. Patent 54,888,449 to Crane et al, electrolytically deposited dull nickel plate on copper or copper base alloy substrates pro~ides e~ceptional adhesion to an epo~y adhesive. Other suitable coating materials include chromium, iron and their alloys.
Most preferred for the package base 12 and cover 36 components are aluminum alloys coated with a hydrated aluminum oside. The coating is applied by anodization. As disclosed in U.S. Patent No. 4,939,316 by Mahulikar et al., an anodized aluminum surface provides esceptional adhesion 15 between the eposy sealant and the anodized surface.
Further, the anodized aluminum package substrate has been found to have thermal dissipation capabilities about equal to that of-copper or a copper based~alloy.
In an embodiment of the invention illustrated in - `20 Figure 4, the package substrate 12 comprises an aluminum or aluminum base alloy.' An anodization layer 56 is~applied to all surfaces of the package base 12.~ While this embodiment discloses all aluminum-alloy surfaces~coated,with the anodization layer 56 only-those surfaces-e~posed the ~- 25 e~ternal environment need be covered with the anodization -~ -layer.to prevent salt-spray-induced corrosion.~ Preferably, thosersurfaces in contact with the~polymer~adhesive 52 are - .-also anodized~to improve adhesion-to the substrate.: The thickness of the anodized coating layeri56 is typically on 30~the order of from-about~.-5 micron-..(20 microinches) to about 50 microns':(2-mils).- More preferably,-;thickness~-is.from ,-about:25~microns (l mil)~to:aboutc50~microns~(2:mils).
3-i'--The resistance'bf an.anodized~aluminumlsurface is greater'than--about-1010~ ohms.-:-An-anodization layer on 35 the walls.of.the holes contributes to the electrical ...: . . ... ~; - :
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isolation of terminal pins 30. However, the bulk of the electrical isolation is still provided by the dielectric sealant 52. Therefore, the diameter of the holes comprising the first array of holes 35 is essentially the ssame whether or not an anodization layer 56 is applied.
The terminal pins 30 may also contain a coating layer 58 to improve adhesion. The coating 58 is preferably a metal coating layer. While a refractory o~ide layer also enhances adhesion, this type of coating is less preferred lodue to increased resistivity. Preferably the terminal pins 30 are coated with a second metal such as nickel or gold.
A shoulder 60 may be provided on the terminal pins 30. The diameter of the shoulder 60 exceeds the diameter of the holes within the first array of holes 35. The l55houlder 60 prevents the pins from pulling loose from the adhesiYe 52 during insertion or withdrawal. The yield strength of the metal base component 12 is much higher than the yield strength of conventional moldinq resins so the terminal pins of the package of the invention are ~20significantly:less;1ikely to pull 1oose~from the package than the terminal:pins of a molded.plastic package.
^. - ~ ,Another metal pin gird:array package of the -invention:is-illustrated-:in.cross-sectional representation in Figure.5.-^The first~array. of holes:35 is formed in the -2Scover component 36' rather than:the base component. When the'terminal pins 30,are inserted into~.esternal circuitry, ' the cavity-72 housing the electronic devi:ce:32 faces ''~ downward.~: The package.:70.is of the.type known in the art - rL~as a-~cavityldown~packagep~ ~ ; ? ~
--. 30 ;,~r. ;The..metal:base:..12'~of:the metal. pin,:grid array.
.:'`pickage:70.may be:formed:with a.series:of ,fins 74 .to . ma~imizeithertransferi~.~of~heat from the~.base-12~ito,.the surrounding~;environment.~,Unlike;-ceramic or..plastic pin -~g~id~array~pickige-bases,,the'-~metal'-.base.12' of.,the-invention may be readily machined-to include a plurality of fins 74 or any other desired shape.
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' WO91/08~87 2 0 ~ 7 3 ~ ~ PCT/VS90/06600 While the invention has been particularly described in terms of pin grid array type packages, it is equally applicable to other types of metal packages which employ through pins, for esample, hybrid microelectronic packages.
While the pin grid array packages of the invention have been described in terms of a cover component bonded to a base component, it is within the scope of the invention to bond a seal ring to the base component and to bond the cover component to the seal ring at a later time. This Otype of assembly is known as a "window frame'~ package.
It is apparent that there has been provided in accordance with this invention a metal pin grid array package which fully satisfies the objects, means and advantages set forth herein ~efore. While the invention shas been described in combination with specific embodiments thereof, it is evident that many alternatives, modifications and variations would be apparent to those skilled in the art in light of the foregoing description.
Accordinqly, it is intended to embrace all such 20alternatives, modifications and variations as fall within -the spirit and broad scope of the appended claims.
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Patent No. 4,688,152 to Chia, a printed circuit wiring board having plated through holes serves as the package 5 base. An integrated circuit device is bonded to one face of the printed circuit board. Lead wires electrically interconnect the integrated circuit device to circuit traces on the board. The circuit traces terminate at conductive rings containing terminal pins which pass lo through the printed wiring board and exit the opposite - surface of the board. The surface containing the integrated circuit, wire bond and circuit traces, is then encapsulated in a molding plastic.
Yet another molded plastic pin grid array package is 15 disclosed in V.S. Patent Number 4,816,426 to Bridges et al. The patent discloses a circuit tape having terminal pins prebonded to the tape. The pins are electrically interconnected to circuit traces formed on the tape. The assembly is then partially encapsulated within a polymer 20'resin.
; : Ceramic pin grid array packages have e~cellent ~ reliability, but are brittle, espensive and are poor conductors of heat. One of the chief advantages of,a pin grid array package is the high number of electrical : 25 interconnections possible. The more complex the integrated - ~^ circuit,-:the-more heat-generated-during,operation., If this heat is-not removed,.the.device operating--life--is-, ' -- decreased.':-:It,has been estimated that-fo,r "every.~10 C
? '~increase.in operating temperature the effect,i,v,e operating i: 30 life of the dev,ice is:decreased by~,50,percent.,-, _ Plastic pin grid.array,packages,,,ar,e not brittle and :considerably cheaper toïmanufacture than,ceramic,pin grid array packages.i The thermaliperformance of a;plastic pin grid array packige may be improved by moldingi,a metal~heat 35 spreader into the body of the package as disclosed in the ' : . :
''~'. WO91/08587 2d6~3~ PCT/US90/06600 above cited U.S. Patent Number 4,816,426. While such a package gives e~ceptional performance, the large surface area of e~posed plastic makes plastic pin grid array packages susceptible to moisture permeation.
One way to achieve the hermeticity and reliability of the ceramic package with the reduced cost and improve thermal performance of the plastic pin grid array package is with a metal pin grid array package. A hermetic metal pin grid array package is disclosed in a Toshiba new 10 product release entitled ~METAL PIN GRID ARRAY PACKAGE".
The publication discloses a printed wiring board circuit containing a plurality of terminal pins.. The pins exit the -wiring board and pass through a metal base. An isolation '.
seal electrically isolates the terminal pins from the metal 15 package base. .. '.
The composition of the isolation seal is not disclosed. It appears to be a cylindrically-shaped apertured preform of a metal sealing glass composition such - as-a borosilicate. ~hese preforms are widely used to ~20 isolate,feed through~pins from.metal-package,bases in .
'; hybrid packaging.-:.E~amples-of.:.isolation seals:are given in ~ U.S. Patent Number.4,706,3821to Suppinger.et,al as well as : -': - U.-S. Patent Number 4,716,082 to Ahearn,;et al.. -~.. , ;~ Disadvantages with,the use of isolation seals :.
--' : ^25-'-include:cost and.difficulty~.of assembly. .Preforms, either ' ._.'? . ' glass~or~plastic, are inserted~on,each terminal~pin. Each tèrminal-pin~`is-then-~aligned.iwithin the metal base prior to formation1of the?isola~ion.seal.-.~-,;If the seal:is,glass, it ' must be~carefully selected so that:~the.coefficient of 30 thermal~,e~pansion--of?the glass.iis~close.:(typically within about 10 percent) tosthe coefficient of thermal,expansion ''t~of~the~package baseiand;the:terminal pins.~ Since the glass is~inherently~brittle, glass-fracture-.and..loss.of electrical isolation is a potential problem.-,,,.~;
'. 35 Accordingly, it is an object of the invention to provide a metal pin grid array package ha~ing improved . ~ .
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WO91/08587 PCT/US90/06 ~ ' thermal performance over both ceramic and plastic packages, while retaining the cost benefits of a molded plastic package. It is a further object of the invention to minimize water permeation by limiting the amount of plastic 5 e~posed to the atmosphere. It is an advantage of the invention that feed throughs are not employed for electrical isolation. It is a further advantage of the invention that the metal package components may be easily formed by conventional stamping techniques. It is a lo feature of the invention that the metal base component may - be either copper or aluminum, or alloys of these metals to masimize ,conduction of heat from the integrated circuit device. It is yet another feature of the invention that ' metal package components may be coated with another metal 15 or with a refractory oside layer to ma~imize adhesion.
Accordingly, there is provided a metal pin grid array package. The package has a cover component and a metal or metal alloy base component. The base component ' contains--an ordered array of holes. A circuit is disposed 20 between~the cover component-and the base component. A
plurality of terminal--pins are electrically interconnected - to the circuit. The:pins e~tend outwardly through the ordered~array of holes:in the package base. -A dielectric - sealing means bonds the cover component to both the circuit ' : 2s and~to theibase component, as well~as the base component to 7the circuit. The dielectric sealing meanslfurther e~tends 'i -' into thesarray of,holes to,:electrically isolate the ;'' -' ~- terminal~pins from the metal-,or metal alloy.base component.
The above'stated objects, features-and advantages of ~,' 30 the invention will~become more~apparent from the~, ~ specification and;Figures which-follow:,7 :~ ? -~s~ *':S;Y~ Figure l shows~in~top planar view~the,relationship betweenithe package:base--component of;the invention and a circuit-.~ -.~i -'-; ~ ,;~~i .,~, ~ Y,'`';', .. , ~ . . ... ... . . . .
., .. , - . . - .
Figure 2 shows in cross-sectional representation the metal pin grid array package of the invention prior to assembly. ..
Figure 3 shows in cross-sectional representation a -' 5 metal pin grid array package in accordance with the invention. ~ :.
Figure 4 shows in cross-sectional representation a ~ -means for electrically isolating the terminal pins in accordance with one embodiment of the invention.
lo Figure S shows in cross-sectional representatio~ a metal pin grid array package in accordance with a second embodiment of the invention.
Figure 1 shows in top planar view a portion of a pin grid array package 10 in accordance with the invention. - ' 15 The package 10 includes a base component 12 and a.circuit 14. A first polymer sealant 16 is disposed between the base component 12 and circuit 19. The peripheral dimension of base component 12, that:is the sum of the length and width, is larger than the peripheral dimension of the first 20 polymer sealant.16, which in~iturn-has larger.~peripheral dimensions-than the circuit.l4. Although the'packa~e ~ components-.are shown.as square and most conventional pin . ;. grid array-packages.have equal lengths and widths, the package.10 may be rectangular or any-desired shape in ...... 25 accordance with the.-invention.' - - ..i ~tt . A personality window~'l8 is formed through both the ;circuitl14 and.the first~polymer sealant 16 to permit the integrated circuit device (not shown) to be bonded directly .tO the base::component:12.~ a 30...~ ., 3~.The circuit i4~comprises at least one metal layer and preferably, at .least-one dielectric::support~layer 20.
;The-dielectric:.:support~.layer.;20:may;.be.any non-conductive .Dmedium<~uch as a-ceramic;?~glass'or~polymer.`'A-polymer support.layer.may be :rigid'such as-'a glass filled epo~y or 35 flesible.such as a polyimide. One suitable'polyimide'is Rapton manufactured by Dupont.
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WO91/085~7 PCT/US90/066 A conductive metal layer 22 is bonded to the dielectric support layer 20 such as by lamination. The conductive metal layer is generally quite thin, on the order of about .018mm (.0007 inches) to about .071mm (.0028 5 inches) thick. To insure adequate current carrying capability through the relatively small cross sectional area circuit traces, a metal having high electrical conductivity such as copper or a dilute copper alloy preferably form the conductive layer 22. The conductive lo layer is formed into a plurality of circuit traces 23 and terminal pin bonding sites 24.
The conductive layer is typically patterned by photolithographic technigues. Briefly, this process entails applying a-photosensitive resist over the 15 conductive metal layer 22. A mask defining the desired circuit pattern or its negative image is placed over the resist. A light source esposes those areas not shielded by the mask. The photoresist polymerizes in the esposed areas and becomes resistant to a first solvent. The photoresist 20 which.did.not polymerize::is.then removed-by dissolution in -this first solvent. The e~posed metal foil.is.then etched, .using a suitable acid or.combination of acids to:e2pose the underlying polyimide layer. After rinsing away..the acid . etchant,-a second solvent removes by.dissolution the 2s polymerized resist. Metal circuit .traces.23 in .the desired .... léad-pattern remain.. The photolithographic techniques may employ .either positive or negative photoresists.as known in the:art. ~ J;..i`~. _ .. ' - . `' ' ;' ' '~.' ' ~'~ ' -i Fig. 1 shows circuit traces.23.originating from only :30 a portion of.the bonding~sites 24 to.-facilitate drawing ~ clarity. -.Generally,~a circuit.trace .23 will originate from j~ .ul.each or!~most circuit!traces.and terminate~at:personality ~ .window.18. ..;~he total number.of bondin~ sites.is..limited - --. only by..the resolution of the photolitographic technique .35 employed and the size of-the-base component 12 and .
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personality window 1~. It is within the scope of the invention for the circuit 14 to include several hundred bonding sites 24.
The terminal pin bonding sites 24 include a 5 metallized region 26 formed in conjunction with the circuit trace 23. An aperture 28 e~tends through the center of each metallized region and the underlying support layer.
The aperture 28 diameter is sized to receive a terminal pin.
Figure 2 shows in cross-sectional representation a o metal pin grid array package 10~ prior to assembly. A
terminal pin 30 passes through the circuit 14 by way of aperture 28. The terminal pins 30 are formed from any machinable electrically conductive material. The terminal pins 30 preferably have sufficient tensile strength to 15 resist deformation during repeated insertions and removals. Preferably, the terminal pins are formed from copper or a copp~r base alloy, such as C510 .(also known as phosphor-bronze, having the nominal composition 3.5-4.9% by weight tin, 0.03-03.5% by weight phosphorus, and~the ~ 20 balance~copper)..- Alternati~ely, an iron nickel alloy,--such :i :. as XOVAR-i(a.trade name for an iron-nickel-cobalt alloy) may ` be employed. The~terminal pins 30 may be.coated with : another metal to enhance solderability and.adhesion as ; -~described-below.-... :. -2s ~ ; The~terminal pins.30 are electrically~interconnected . to the.bonding~sites~24. Electrical.iinterconnection may beby mechanical.contact::as disclosed:in U.S.~Paten~ Number ;-4,~816,426-cited.above, or by~a technique such ~s.f;soldering ^is'disclosed.in U.S.~ Patent~No. 4;965,27?..by Chang et al.
30 A.solder paste is applied to.the metallized region~26:of ?~bondingrsites 24 by~a process such:as~screen~printing.
~-?After insertionJof~the~pins,.a.solder bond is formed by .`lheating the assembly to;a temperaturelsufficient to melt and flow the.solder. ~For e~ample,-a solder paste : 35 comprising 60ipercent.by weight lead and 40 percent-by weight tin would melt and flow at a temperature of about 250C.
- .' , ~' , ' ., Wosl/085g7 2 0 G ~ '~ 8 '1 PCT/US90/06 ~'' Any solder having a melting point below about 275C and capable of bonding to the metallized regions 26 of bonding sites 24 and to tRrminal pins 30 is acceptable.
The temperature limitation'is related to the dielectric 5 support layer 20. At temperatures above about 275 polyimide begins to degrade. Of course, if a more thermally resistant support layer is employed, the ma~imum ' temperature and number of suitable solders are both increased.
lo An integrated circuit device 32 which may be a silicon based semiconductor circuit is electrically interconnected to circuit traces 23. Electrical interconnection may be by bond wires 34. The bond wires 34 are thin, on the order of .025mm (.001 inch) in diameter, 15 wires formed from copper, aluminum, gold or alloys thereof. The bond wires are bonded to the integrated circuit device 32 and to the circuit traces 22 by a wire - bonding process such-as thermosonic or thermocompression bonding.
'' 20 -' -As^ an alternative to bond'wires 34,- foil leads-(not shown) formed'from the conductive metal layer 22 may e~tend 'in cantilever fashion into the personality window 18. The foil'leads are then bonded to the input/output pads of the integrated circuit device 32 by thermocompression bonding 25'by:the technique known as tape'automated bonding (TAB).
~: ^~-The circuit-assembly comprising the circuit 19, :'~; bonded-termi'nal''pins~30-and bonded device 32 is disposed ;;between''thë base'component 12 and a~-cover component 36.
~ The"terminal pins'32~pass through'a first:arra~y~of holes 35 30~formed'in`the base component; The base:component~l2 is 'formed!from~a-metal or a metal alloy.:. To ma~imize the '~ dissipation''iof heat from the electronic-device 32 through '''''~'the bise'component'l2,;!the base component is preferably formed from~':copper, aluminum or alloys thereof. Most 35:preferably, the base component comprises an aluminum base `, ~
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20S73~
'~ WO9~/08~81 PCT/US90/06600 alloy, such as aluminum alloy 3003 (nominal composition 0.05-0.20 weight percent copper, up to 0.6 weight percent silicon, up to 0.7 weight percent iron, up to 0.1 weight percent zinc and the balance aluminum). Aluminum and 5 aluminum base alloys are preferred since they have been found as effective as copper for the dissipation of heat from the electronic device and have a density only 60% that of copper. The thermal performance of an aluminum base alloy package is about equivalent to that of a copper or lo copper alloy base package and yet weighs only 60~ as much.
Reduced package weight is desirable in applications such as aerospace and where e2cess weight is a penalty such as packages subject to rapid acceleration.
The first array of holes 35 has the same 15 configuration as the apertures 28 formed'in the circuit 14. The diameters of the holes comprising the first array of holes 35 is sufficiently large that.terminal pins 30 pass through the holes without contacting the base component 12.
~ -~i ;;Th'e array 'o`fAholes"-3~ may-be formed by.any suitable '' metal removal~'techniques'such'as drilling, piercing, stamping or:themicil-'milling.- From.both.-a process -repr'oduc`ibility and a'process--rate-standpoint, stamping or piercing a're preférred to`form the first array of holes 35.
` 2s'~ ` 'The'c'over~component-36:may-be--fashioned.from any material`which bonds'`to-a second polymer~sealant 3~. The cover compone`nt 36'2is s'elected from:.the.groupiconsisting of - thermose'tting 'polymers,~ thermoplastic.3polymers, ceramics, --~-meta'ls a'nd~metal alloys~5às-~well~as-composite materials, 30 ? such~asLcèrmets'~ind cerglassm ~The-choice~of:material^is ~''dependentlupon the"application and the.desired.,properties ;1~ of-the'~mëtal'pingrid array-package.c-~A~molded~plastic *cover component 3j 6`~ 2 ~uch''as~a~pre-molded~epo~y.cover, --i providés the'advantagès of low cost,agood adhesion to 35'-polymer seilantland:light weight.- However, moisture.
permeation i8 a problem.
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WO 91/08587 2 0 5 ~ PCr/US90/06~
A ceramic cover component has the advantages of being lightweight and imparting rigidity to the overall metal pin grid array package. However, most common ceramics such.as aluminum o~ide ~A12O3) have a S coefficient of thermal e~pansion of about 4.9~10 7/oC.
Copper and aluminum have coefficients of thermal e~pansion ' in e~cess of about 170~10 7/oC. The mismatch in coefficients of thermal e~pansion may result in package fle~ure during thermal cycling severe enough to fracture lo the electronic device 32.
Most.preferably, the cover component 36 is selected to be a metal.or metal alloy. The cover component 36 may have the same composition as the base component 12 or a different alloy may be selected. For e~ample, the base 15 component 12 may be selected to be copper or a copper base alloy having high thermal conductivity such as CllO
(electrolytic tough pitch copper having the nominal composition 99.90% by weight copper and a maximum o~ygen concentration of 0.05%). The cover component 36 may be 20uselected to-be high strength,copper alloy such as C724 (nominal composition.84.3% by~weight-copper, 13.0% nickel, 2.~0%-:aluminum, 0.5% manganese and 0.,2% magnesium). Thermal ~conduction is ma~imized through the dilute copper base -alloy. The high yield strength alloy ~forming t.he cover ~:
25 contributes:rigidity:of~the-metal pin,grid,,array package ';' lO'.': To minimi,ze.,package weight.~both ,the.base.and.,cover '~' S~ components~may.~be an aluminum base.alloy..,~
A dielectric.:sealing means-.is,,provided as,first 16 ;'S-and second 38 polymer~sealant~layers.j,-The,dielectric :~;30iproperty:;0f.the sealant-,mainta,i,ns,electrical,isolation : i ~between the:terminal pins,30",the~conduc,t,iv,e~,met,al,1ayer '~''22,~theibase~component.12~and the coverlcomponent.36. The -~first~16.~and~second 38 polym,er?,sealant}layers may~.be .~provided,as discrete sheets of an,adhesive or in paste or 35 1iquid:form and deposited by a process such as screen printing.
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' WO91/08587 PCT/US90/06600 The dielectric sealant is selected to be a polymer adhesive which cures at a temperature below about 275C
to prevent thermal degradation of the dielectric support layer 20. The polymer sealant is selected to be what is 5 known in the art as ~semiconductor grade~. Semiconductor grade adhesives release lower amounts of ionic contaminants during the cure reaction than standard adhesives. Ionic - contaminants are undesirable. They may deposit on the bond wires 34 or metallized surfaces of the electronic device 32 lo leading to corrosion and device failure.
The dielectri~ sealant is preferably selected to be a thermosetting polymer resin such as an epo~y. One suitable epo2y is Abléstik 550 is manufactured by Ablestik ' Labs, Gardenia, CA. The adhesive cures and provides 15 sufficient flow when heated to a temperature of from about 125C to about 175C and a pressure of from about 35 gm/cm2 (0.5 psi) to about 105gm/cm2 (1.5 psi).
- Pressure may be applied through the use of a clamp.
The'second adhesi've layer 38 has essentially the 20 samé peripheral'dimension~''asrthe~first7adhesive 1ayer 16.
The second polymer sealant layer 38 is larger-than the c'ircuit 14 and smaller than the base component 12 or cover ''component 36.
~'- The'first polymer adhesive layer-16 is disposed 2s between~bise component'l2 and circuit 14. ~The,'first -;
polymerisèala,nt'layer-16 is-~provided,with a second array of ~holes 40'correspo'nding"to the'first array-of holes-35. The --diàmetër~of the-holés;maki~ngi-up;this second~array of holes 40'i's s'1ightlyilarger than"the--diameter:of terminal pins '30 30. To minimize9the;required Yolume-of sealant,~,the'-:
- ^diimëter of-tXe-~sëcond arr'ay-of~holes-40iis~lessfthan about 25mm-~(.'010iinchës)''iarger thin'the~diameteriof~the term;nai pins'j0.'3AMor'e'~preferably,';the diameter of the -second array'-~of~'holes~'40;is from about .O25mm~to about 35 l.'1i7mm (.001 - .005'inches) làrger than the diameter of the terminal pins 30. ' ~
WO91/08587 2 0 6 7 ~ 3 ~ PCT/US90/066~' The diameter of the first array of holes 35 is on the order of about .127mm to .51mm (.005 to .020 inches) larger than the diameter of the terminal pins 30. More preferably, the diameter of the holes comprising the first 5 array of holes is from about .25mm to about .38mm (.010 to ~015 inches) larger than the diameter of the terminal pins 30. The terminal pins 30 e~tend through the first 35 and second 40 arrays of holes. Electrical isolation between the metal or metal alloy base component 12 and the terminal lo pins 30 is provided by the first polymer adhesive 16 which flows into the first array of holes 35. In one embodiment of the:invention a refractory oside layer is formed within the first array of holes 35. The refractory o~ide also contributes to terminal pin isolation.
~ The second polymer adhesive layer 38 is disposed between the cover component and the circuit 14. An '~
aperture 44 is preferably provided in the second polymer sealant layer 38 so adhesive does not flow over the bond wires 34 or the integrated circuit device 32. Other . ,20 techniques.'.~to control.polymer.flow.such as dams may also be -~
::employed.
-~ . . A:die-attach material 46 is disposed between the integrated circuit 32 and package base 12... While the ... electronic device 32 may be free,floating and supported ~5 solely.,by the bond wires,34 the..~use of a,die attach .: , .provides aniimproved thermal,-conduction pa,th.~.The die . '.attach material 46,may be any,thermally conductive material '.which-bonds to the.backside,of;,the integrated~circuit ..!'':'` device~32~~.and,package base-12.,.The-die.attach material 46 30ishould.have a melting or cure temper,ature approximately .. ., ',equal-,to,the cure.~temperature ,of-the~dielectric.sealant.
Suitable~die.attach materials~-~include~low~melting solders ; 'such as 60% lead/40%.tin,,~or.~.pr,eferably,..a polymer,jadhesive - :;filled.with a..thermally conductive.material. One such ; - -35 adhesive;.is a silver:filled epo~y known as Ablefilms , manufactured by Ablestik Labs.
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20~7~
WOgl/08587 PCT/US90/06600 The package 10' of Figure 2 is bonded to complete assembly of the metal pin grid array package 50 of Figure 3. The application of heat and pressure causes first 16 and second 38 polymer adhesive layers to flow. The layers 5 fuse to form a continuous dielectric layer 52. Since the peripheral dimension of first 16 and second 38 polymer sealant layers is larger than the peripheral dimension of fle~ible circuit 14 following the cure cycle the dielectric sealing means 52 e~tends beyond the edges of the circuit 14 ~ to form a continuous surface 54.
A major source of moisture penetration into an electronic package is along plastic~metal interfaces.
Elimination of the circuit 14 with metal circuit traces 23 from the edges of the package 50 reduces the possibility of 15 moisture penetration. The dielectric sealing means 52 ,-bonds the cover component 36 to both the circuit 19 and to the base component 12.
' The base component 12 is bonded to -the circuit 14.
During the cure cycle, the dielectric sealing means 52 '20 flows'into the first:-array,of holes.35.in;^.the base, component 12. -The polymer sealant 52 effectively centers 'the interconnect pins 30'within each hole comprising the array..' - ' ~
The dielectric sealant S2 further electrically 25-isolates'the terminal pins 30 from the,metal.,or.metal ~alloy 'base component 12. To prevent electr.ical,leakage".,through ~' 'the dielectric sealant 52, the resistivity-..of-~the.:~
' '''dielectric-within the firs't:~array of,holes.35!mus.t,~be '''sufficientlylhigh. ~Resistïvity..is defined.-as-the..electric 30 resistance^offered:by a material to the flow of current.
~ ''It'is a':function 'of the cross sectional.;area,of the current ~r -' C` '-' f low ind''the~unit~'length''-of~current~path.~Resistance.to -' currentl~leakage`'within the:'first array.nfi~holes,,35~,is a function of the'dielectric sealant 52 as well as the 35 separation distance between the terminal pin 30 and the ~ --.
WO91/08587 2 0 ~ 7 3 ~ ~ PCT/US90/066~. ~
base component 12. For a typical eposy adhesive having a dielectric constant of about 4, a separation of about .25mm (.01 inches) will provide for electrical resistivity of greater than about 101 ohms which is sufficient to 5 prevent current leakage.
~ y regulating cure cycle time, pressure and temperature, the depth of dielectric sealant 52 penetration within the first array of holes 35 is controlled.
Preferably the cure cycle is selected so that the lo dielectric sealant does not flow beyond the bottom edge 55 of the base component 12. The e~cess flow of sealant and the resulting formation of a flash along the terminal pins 30 may interfere-with the proper electrical functioning of the pins.
To improve the bond between dielectric sealant 52 and the metal components of the pin grid array package 50, it is prefera~le to provide a surface coating on the metal components or at least those surfaces of the components in contact with the dielectric sealant. The surface coating 20 may-be-formed'in situ. An in situ coatinq is formed from the metal alloy itself. Certain copper or copper base alloys such as C638 ~2.5-3;1 weight percent aluminum, 1.5-2.1 weight percent silicon, 0.25-0.55 weight percent cobalt and the balance copper) are capable of forming an in '25 situ refractory oside layer,~substantially A1203,. The , refractory oside layerris typically:formed by placing the copper base'alloy;in a.container having an atmosphere of 4%
hydrogen',,-96% nitrogen and a,trace o,,f,water. ~,The gas is heated.to a-itemperature of,between about,330,C and about 30?-820C.~ Depending on the:temperature,:dwell~ti,me,~a "J refràctory o~ide-layer of.-a desired-thickness,is formed on '-''3 -~:the~surface~;of--the-alloy.~~Formation,of-suchsa refractory ~ ~ o~i'de~is disclosed in U.~S.-,~Patent,Number 4,461,924~to Butt e`t al.'`' - ,' , , 20S73~
, : WO91/08587 PCT/US90/06600 The coating layer may be formed by depositing a second material on the metal components. For copper and copper base alloys a coating layer of a second metal such as nickel is preferred. As disclosed in U.S. Patent 54,888,449 to Crane et al, electrolytically deposited dull nickel plate on copper or copper base alloy substrates pro~ides e~ceptional adhesion to an epo~y adhesive. Other suitable coating materials include chromium, iron and their alloys.
Most preferred for the package base 12 and cover 36 components are aluminum alloys coated with a hydrated aluminum oside. The coating is applied by anodization. As disclosed in U.S. Patent No. 4,939,316 by Mahulikar et al., an anodized aluminum surface provides esceptional adhesion 15 between the eposy sealant and the anodized surface.
Further, the anodized aluminum package substrate has been found to have thermal dissipation capabilities about equal to that of-copper or a copper based~alloy.
In an embodiment of the invention illustrated in - `20 Figure 4, the package substrate 12 comprises an aluminum or aluminum base alloy.' An anodization layer 56 is~applied to all surfaces of the package base 12.~ While this embodiment discloses all aluminum-alloy surfaces~coated,with the anodization layer 56 only-those surfaces-e~posed the ~- 25 e~ternal environment need be covered with the anodization -~ -layer.to prevent salt-spray-induced corrosion.~ Preferably, thosersurfaces in contact with the~polymer~adhesive 52 are - .-also anodized~to improve adhesion-to the substrate.: The thickness of the anodized coating layeri56 is typically on 30~the order of from-about~.-5 micron-..(20 microinches) to about 50 microns':(2-mils).- More preferably,-;thickness~-is.from ,-about:25~microns (l mil)~to:aboutc50~microns~(2:mils).
3-i'--The resistance'bf an.anodized~aluminumlsurface is greater'than--about-1010~ ohms.-:-An-anodization layer on 35 the walls.of.the holes contributes to the electrical ...: . . ... ~; - :
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, . ~ -~ . . -wo 9l~08s87 2 0 5 7 3 ~ ~` PCT/US90/06~
isolation of terminal pins 30. However, the bulk of the electrical isolation is still provided by the dielectric sealant 52. Therefore, the diameter of the holes comprising the first array of holes 35 is essentially the ssame whether or not an anodization layer 56 is applied.
The terminal pins 30 may also contain a coating layer 58 to improve adhesion. The coating 58 is preferably a metal coating layer. While a refractory o~ide layer also enhances adhesion, this type of coating is less preferred lodue to increased resistivity. Preferably the terminal pins 30 are coated with a second metal such as nickel or gold.
A shoulder 60 may be provided on the terminal pins 30. The diameter of the shoulder 60 exceeds the diameter of the holes within the first array of holes 35. The l55houlder 60 prevents the pins from pulling loose from the adhesiYe 52 during insertion or withdrawal. The yield strength of the metal base component 12 is much higher than the yield strength of conventional moldinq resins so the terminal pins of the package of the invention are ~20significantly:less;1ikely to pull 1oose~from the package than the terminal:pins of a molded.plastic package.
^. - ~ ,Another metal pin gird:array package of the -invention:is-illustrated-:in.cross-sectional representation in Figure.5.-^The first~array. of holes:35 is formed in the -2Scover component 36' rather than:the base component. When the'terminal pins 30,are inserted into~.esternal circuitry, ' the cavity-72 housing the electronic devi:ce:32 faces ''~ downward.~: The package.:70.is of the.type known in the art - rL~as a-~cavityldown~packagep~ ~ ; ? ~
--. 30 ;,~r. ;The..metal:base:..12'~of:the metal. pin,:grid array.
.:'`pickage:70.may be:formed:with a.series:of ,fins 74 .to . ma~imizeithertransferi~.~of~heat from the~.base-12~ito,.the surrounding~;environment.~,Unlike;-ceramic or..plastic pin -~g~id~array~pickige-bases,,the'-~metal'-.base.12' of.,the-invention may be readily machined-to include a plurality of fins 74 or any other desired shape.
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' WO91/08~87 2 0 ~ 7 3 ~ ~ PCT/VS90/06600 While the invention has been particularly described in terms of pin grid array type packages, it is equally applicable to other types of metal packages which employ through pins, for esample, hybrid microelectronic packages.
While the pin grid array packages of the invention have been described in terms of a cover component bonded to a base component, it is within the scope of the invention to bond a seal ring to the base component and to bond the cover component to the seal ring at a later time. This Otype of assembly is known as a "window frame'~ package.
It is apparent that there has been provided in accordance with this invention a metal pin grid array package which fully satisfies the objects, means and advantages set forth herein ~efore. While the invention shas been described in combination with specific embodiments thereof, it is evident that many alternatives, modifications and variations would be apparent to those skilled in the art in light of the foregoing description.
Accordinqly, it is intended to embrace all such 20alternatives, modifications and variations as fall within -the spirit and broad scope of the appended claims.
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Claims (45)
IN THE CLAIMS
1. A metal pin grid array package 50, characterized by:
a cover component 36;
a metal or metal alloy base component 12 having a first array of holes 35; -a circuit 14 disposed between said cover component 36 and said base component 12;
a plurality of terminal pins 30 electrically interconnected to said circuit 19 and extending through said first array of holes 35;
a dielectric sealing means 52 for bonding said cover component 36 both to said circuit 14 and to said base component-12 and said base-component 12 to said circuit 14;
and said dielectric sealing means 52 extending into said first array of holes 35 electrically isolating said plurality of terminal pins 30 from said base component 12.
a cover component 36;
a metal or metal alloy base component 12 having a first array of holes 35; -a circuit 14 disposed between said cover component 36 and said base component 12;
a plurality of terminal pins 30 electrically interconnected to said circuit 19 and extending through said first array of holes 35;
a dielectric sealing means 52 for bonding said cover component 36 both to said circuit 14 and to said base component-12 and said base-component 12 to said circuit 14;
and said dielectric sealing means 52 extending into said first array of holes 35 electrically isolating said plurality of terminal pins 30 from said base component 12.
2. The-package 50 of claim 1 characterized in that said base component 12 is selected from the group consisting of copper, aluminum and alloys thereof.
3. The package 50 of claim 2 characterized in that the diameter of said holes comprising said first array of holes 35 is from about .13mm (.005 inches) to about .51mm (.020 inches) larger than the diameter of said terminal pins 30.
4. The package 50 of claim 3 characterized in that the diameter of said holes comprising said first array of holes 35 is from about .25mm (.010 inches) to about .38mm (.015 inches) larger than the diameter of said terminal pins 30.
5. The package 50 of claim 3 characterized in that the dielectric sealing means 52 is a polymer adhesive having a resistivity effective to electrically isolate said terminal pins 30 from said base component 12.
6. The package 50 of claim 5 characterized in that said polymer adhesive 52 provides a resistivity in excess of about 101° ohms.
7. The package 50 of claim 6 characterized in that said polymer adhesive 52 is selected to be a thermosetting epoxy.
8. The package 50 of claim 6 characterized in that said metal or metal alloy base component 12 is formed from an aluminum alloy, said base component 12 having an anodization layer 56 over at least those surfaces exposed to the external environment.
9. The package 50 of claim 8 characterized in that said anodization layer 56 extends to the walls of said holes comprising said first array of holes 35.
10. The package 50 of claim 9 characterized in that said cover component 36 is also formed from an aluminum alloy and has an anodization layer 56 over at least those surfaces exposed to the external environment.
11. The package 50 of claim 6 characterized in that said base component 12 is selected to be copper or a copper base alloy.
12. The package 50 of claim 11 characterized in that said base component 12 is a copper alloy capable of forming an in situ refractory oxide layer on at least those surfaces in contact with the polymer adhesive.
13. The package 50 of claim 11 characterized in that said copper or copper alloy base component 12 is coated with a second metal or metal alloy on at least those surfaces in contact with the dielectric sealing means, said coating layer selected from the group consisting of nickel, chromium. iron and their alloys.
14. The package 50 of claim 11 characterized in that said cover component 36 is also copper or a copper alloy.
15. The package 50 of claim 14 characterized in that said cover component 36 is selected to be a copper alloy having relatively high tensile strength and said base component 12 is selected to be a copper alloy having relatively high thermal conductivity.
16. The package 50 of claim, 14 characterized in that at least that portion of said cover component 36 in connect with said polymer adhesive 52 is coated with a second metal or metal alloy selected from the group consisting of nickel, chromium, iron and their alloys.
17. A process for the manufacture of a pin grid array-package 50, characterized by:
forming an ordered array of holes 35 in a metal or metal alloy base component 12;
electrically interconnecting a plurality of terminal pins 30 to a circuit 14, said terminal pins 30 forming a configuration corresponding to said ordered array of holes 35;
inserting said plurality of terminal pins 30 through said ordered array of holes 35;
disposing a first polymer sealant 16 between said circuit 14 and said base component 12 and a second polymer sealant 38 between said base component 12 and said circuit 14; and bonding a cover component 36 to said circuit 14 and to said base component 12 and said base component 12 to said circuit 14 by a means effective to cause said polymer sealant 52 to flow into the holes comprising said ordered array of holes 35 thereby electrically isolating said terminal pins 30 from said base component 12.
forming an ordered array of holes 35 in a metal or metal alloy base component 12;
electrically interconnecting a plurality of terminal pins 30 to a circuit 14, said terminal pins 30 forming a configuration corresponding to said ordered array of holes 35;
inserting said plurality of terminal pins 30 through said ordered array of holes 35;
disposing a first polymer sealant 16 between said circuit 14 and said base component 12 and a second polymer sealant 38 between said base component 12 and said circuit 14; and bonding a cover component 36 to said circuit 14 and to said base component 12 and said base component 12 to said circuit 14 by a means effective to cause said polymer sealant 52 to flow into the holes comprising said ordered array of holes 35 thereby electrically isolating said terminal pins 30 from said base component 12.
18. The process of claim 17 characterized in that said effective bonding means comprises subjecting said pin grid array package components 12, 36 to sufficient heat and pressure to cause the polymer sealant 52 to bond to said package components 12, 36 and to flow into the holes comprising said ordered array of holes 35.
19. The process of claim 18 characterized in that said polymer sealant 52 is selected to be an epoxy resin having a low ionic concentration.
20. The process of claim 19 characterized in that said polymer sealant 52 is provided in the form of first 16 and second 38 sheets of polymer adhesive;
disposing said first sheet of polymer adhesive 16 between said base component 12 and said circuit 14 and said second sheet of polymer adhesive 38 between said cover component 36 and said circuit 14; and forming a second array of holes 40 corresponding to said first array of holes 35 in said first sheet of polymer adhesive 16.
WO 91/08587 PCT/US90/066?
disposing said first sheet of polymer adhesive 16 between said base component 12 and said circuit 14 and said second sheet of polymer adhesive 38 between said cover component 36 and said circuit 14; and forming a second array of holes 40 corresponding to said first array of holes 35 in said first sheet of polymer adhesive 16.
WO 91/08587 PCT/US90/066?
21. The process of claim 20 characterized in that said package components 12, 36 are heated to a temperature of from about 125°C to about 175°C and subjected to a pressure of from about 35gm/cm2 (.5 psi) to about 105gm/cm2 (1.5 psi).
22. The process of claim 18 characterized in that said holes comprising said first array of holes 35 have a diameter of from about .13mm (.005 inches) to about .51mm (.020 inches) larger than the diameter of said terminal pins
23. The process of claim 22 characterized in that the said ordered array of holes 35 is formed by a process selected from the group consisting of drilling, piercing, stamping and chemical etching.
24. The process of claim 23 characterized in that said ordered array of holes 35 is formed by piercing or stamping.
25. The process of claim 23 characterized in that said plurality of terminal pins 30 are electrically interconnected to said circuit 14 by soldering.
26. The process of claim 23 characterized in that said base component 12 is selected to be aluminum or an aluminum alloy and anodizing at least those surfaces of said base component 12 exposed to the external environment.
27. The process of claim 26 characterized in that the walls of the holes comprising said first array of holes 35 are anodized.
28. The process of claim 23 characterized in that said metal or metal alloy base component 12 is selected to be copper or a copper alloy and coated on at least those portions of said base component 12 in contact with said polymer sealant 52.
29. The process of claim 28 characterized in that said coating comprises a second metal or metal alloy deposited on said base component 12.
30. The process of claim 29 characterized in that nickel is electrolytically deposited on said portions of said base component 12 in contact with said polymer sealant 52.
31. The process of claim 28 characterized in that said coating is a refractory oxide formed in situ.
32. The process of claim 31 characterized in that said refractory oxide coating is also formed on the walls of the holes comprising said first array of holes 35.
33. A metal pin grid array package 72, characterized by:
a cover component 36' having a first array of holes 35;
a metal or metal alloy base component 12';
a circuit 14 disposed between said cover component 36' and said base component 12;
a plurality of terminal pins 30 electrically interconnected to said circuit 14 and extending through said first array of holes 35;
a dielectric sealing means 52 for bonding said cover component 36' to both said circuit 14 and to said base component 12 and said base component 12 to said circuit 14;
and WO 91/08587 PCT/US90/066?
said dielectric sealing means 52 further extending into said first array of holes 35 electrically isolating said plurality of terminal pins 30 from said cover component 36'.
a cover component 36' having a first array of holes 35;
a metal or metal alloy base component 12';
a circuit 14 disposed between said cover component 36' and said base component 12;
a plurality of terminal pins 30 electrically interconnected to said circuit 14 and extending through said first array of holes 35;
a dielectric sealing means 52 for bonding said cover component 36' to both said circuit 14 and to said base component 12 and said base component 12 to said circuit 14;
and WO 91/08587 PCT/US90/066?
said dielectric sealing means 52 further extending into said first array of holes 35 electrically isolating said plurality of terminal pins 30 from said cover component 36'.
34. The package 72 of claim 33 characterized in that the diameter of said first array of holes 35 is from about .13mm (.005 inches) to about .51mm (.020 inches) larger than the diameter of said terminal pins 30.
35. The package of 72 claim 34 characterized in that said dielectric sealing means 52 is a thermosetting epoxy having a resistivity in excess of about 1010 ohms.
36. The package of 72 claim 35 characterized in that said cover component 36' is an aluminum alloy having an anodization layer 56 over at least those surfaces exposed to the external environment and the walls of the holes forming said first array of holes 35.
37. The package 72 of claim 36 characterized in that said base component 12' is an aluminum alloy.
38. The package 72 of claim 37 characterized in that said base component 12' is coated with an anodization layer 56 on at least those surfaces exposed to the external environment.
39. A process for the manufacture of a pin grid array package 72, characterized by:
forming a first array of holes 35 in a cover component 36';
electrically interconnecting a plurality of terminal pins 30 to a circuit 14, said terminal pins 30 forming a configuration corresponding to said first array of holes;
inserting said interconnected terminal pins through said first array of holes 35;
disposing a first polymer sealant 16 between said circuit 14 and a metal or metal alloy base component 12' and a second polymer sealant 38 between said base component 12' and said circuit 14; and bonding said cover component 36' to said circuit 14 and to said metal or metal alloy base component 12' by a means effective to cause said polymer sealant 52 to flow into the holes comprising said first array of holes 35 thereby electrically isolating said terminal pins 30 from said base component.
forming a first array of holes 35 in a cover component 36';
electrically interconnecting a plurality of terminal pins 30 to a circuit 14, said terminal pins 30 forming a configuration corresponding to said first array of holes;
inserting said interconnected terminal pins through said first array of holes 35;
disposing a first polymer sealant 16 between said circuit 14 and a metal or metal alloy base component 12' and a second polymer sealant 38 between said base component 12' and said circuit 14; and bonding said cover component 36' to said circuit 14 and to said metal or metal alloy base component 12' by a means effective to cause said polymer sealant 52 to flow into the holes comprising said first array of holes 35 thereby electrically isolating said terminal pins 30 from said base component.
40. The process of claim 39 characterized in that said effective bonding means comprises subjecting said pin grid array package components 12', 36' to sufficient heat and pressure to cause the polymer sealant 52 to bond said package components 12', 36' and to flow into the holes comprising said first array of holes 35.
41. The process of claim 40 characterized in that said polymer sealant 52 is an epoxy resin having a low ionic concentration and said effective bonding means comprises heating said components 12', 36' to a temperature of from about 125°C to about 175°C and subjecting said components 12', 36' to a pressure of from about 35gm/cm2 (.5 psi) to about 105gm/cm2 (1.5 psi).
42. The process of claim 41 characterized in that said first array of holes .35 are formed by stamping or piercing.
43. The process of claim 42 characterized in that said base component 12' is formed from an aluminum alloy and is anodized on at least those surfaces exposed to the external environment.
WO 91/08587 PCT/US90/066?
WO 91/08587 PCT/US90/066?
44. The process of claim 43 characterized in that said cover component 36' is also formed from an aluminum alloy and is anodized over at least those surfaces exposed to the external environment.
45. The process of claim 44 characterized in that said cover component 36' is also anodized on the walls of the holes comprising said first array of holes 35.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US442,877 | 1989-11-29 | ||
| US07/442,877 US5103292A (en) | 1989-11-29 | 1989-11-29 | Metal pin grid array package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2067384A1 true CA2067384A1 (en) | 1991-05-30 |
Family
ID=23758502
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002067384A Abandoned CA2067384A1 (en) | 1989-11-29 | 1990-11-13 | Metal pin grid array package |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US5103292A (en) |
| EP (2) | EP0502887B1 (en) |
| JP (1) | JPH05501638A (en) |
| AU (1) | AU6750190A (en) |
| CA (1) | CA2067384A1 (en) |
| DE (1) | DE69027781T2 (en) |
| HK (1) | HK1008113A1 (en) |
| MX (1) | MX173437B (en) |
| WO (1) | WO1991008587A1 (en) |
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-
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- 1989-11-29 US US07/442,877 patent/US5103292A/en not_active Expired - Fee Related
-
1990
- 1990-11-13 AU AU67501/90A patent/AU6750190A/en not_active Abandoned
- 1990-11-13 EP EP90917154A patent/EP0502887B1/en not_active Expired - Lifetime
- 1990-11-13 DE DE69027781T patent/DE69027781T2/en not_active Expired - Fee Related
- 1990-11-13 EP EP96100021A patent/EP0721212A1/en not_active Withdrawn
- 1990-11-13 JP JP3500561A patent/JPH05501638A/en active Pending
- 1990-11-13 CA CA002067384A patent/CA2067384A1/en not_active Abandoned
- 1990-11-13 WO PCT/US1990/006600 patent/WO1991008587A1/en active IP Right Grant
- 1990-11-29 MX MX023531A patent/MX173437B/en unknown
-
1998
- 1998-06-27 HK HK98107154A patent/HK1008113A1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| HK1008113A1 (en) | 1999-04-30 |
| MX173437B (en) | 1994-03-03 |
| DE69027781T2 (en) | 1997-02-27 |
| DE69027781D1 (en) | 1996-08-14 |
| US5103292A (en) | 1992-04-07 |
| EP0502887B1 (en) | 1996-07-10 |
| EP0721212A1 (en) | 1996-07-10 |
| WO1991008587A1 (en) | 1991-06-13 |
| EP0502887A4 (en) | 1992-10-28 |
| JPH05501638A (en) | 1993-03-25 |
| AU6750190A (en) | 1991-06-26 |
| EP0502887A1 (en) | 1992-09-16 |
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| Date | Code | Title | Description |
|---|---|---|---|
| FZDE | Discontinued |