CA2067596C - System for monitorimg atm cross-connecting apparatus by inside-apparatus monitoring cell - Google Patents
System for monitorimg atm cross-connecting apparatus by inside-apparatus monitoring cellInfo
- Publication number
- CA2067596C CA2067596C CA 2067596 CA2067596A CA2067596C CA 2067596 C CA2067596 C CA 2067596C CA 2067596 CA2067596 CA 2067596 CA 2067596 A CA2067596 A CA 2067596A CA 2067596 C CA2067596 C CA 2067596C
- Authority
- CA
- Canada
- Prior art keywords
- cell
- sequence
- test cell
- connecting apparatus
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
- H04L49/3009—Header conversion, routing tables or routing tags
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/50—Testing arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
- H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/55—Prevention, detection or correction of errors
- H04L49/555—Error detection
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
- H04Q11/0478—Provisions for broadband connections
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5628—Testing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
Abstract
A system for monitoring an ATM cross-connecting apparatus by inputting a test cell through a path for a main signal into the ATM cross-connecting apparatus, and examining the cell after the cell passed through the ATM
cross-connecting apparatus. An initial value of a PN
sequence and the PN sequence generated based on the initial bit sequence is written in the test cell before inputting to the ATM cross-connecting apparatus. When examining the test cell, the initial bit sequence and the PN sequence are read from the cell, a PN sequence is generated based on the initial bit sequence, and is then compared with the PN sequence read from the test cell to detect an error in the test cell. In addition, a bit pattern indicating a primitive polynomial to generate the PN sequence may be written in the test cell. In this case, the bit pattern is used for generating the PN
sequence when examining the test cell. Further, the same VPI values may be written in both the header and the information field of the test cell before inputting the cell to the ATM cross-connecting apparatus, and the VPI
value in the information field is compared with a VPI
value in the header of the test cell when examining the test cell.
cross-connecting apparatus. An initial value of a PN
sequence and the PN sequence generated based on the initial bit sequence is written in the test cell before inputting to the ATM cross-connecting apparatus. When examining the test cell, the initial bit sequence and the PN sequence are read from the cell, a PN sequence is generated based on the initial bit sequence, and is then compared with the PN sequence read from the test cell to detect an error in the test cell. In addition, a bit pattern indicating a primitive polynomial to generate the PN sequence may be written in the test cell. In this case, the bit pattern is used for generating the PN
sequence when examining the test cell. Further, the same VPI values may be written in both the header and the information field of the test cell before inputting the cell to the ATM cross-connecting apparatus, and the VPI
value in the information field is compared with a VPI
value in the header of the test cell when examining the test cell.
Description
- 1 FJ, NDD-9061-CA
SYSTEM FOR MONITORING ATM CROSS-CONNECTING APPARATUS BY
INSIDE-APPARATU~, MONITORING CELL
BACKGROUND OF THE lNV~NllON
(1~ Field of the Invention The present invention relates to a system for monitoring an ATM cross-connecting apparatus by inputting a test cell through a normal signal path into the ATM cross-connecting apparatus, ~nd ext ;n;ng the cell after the cell passes through the A~M cross-connecting apparatus.
SYSTEM FOR MONITORING ATM CROSS-CONNECTING APPARATUS BY
INSIDE-APPARATU~, MONITORING CELL
BACKGROUND OF THE lNV~NllON
(1~ Field of the Invention The present invention relates to a system for monitoring an ATM cross-connecting apparatus by inputting a test cell through a normal signal path into the ATM cross-connecting apparatus, ~nd ext ;n;ng the cell after the cell passes through the A~M cross-connecting apparatus.
(2) Description of the Related Art In ATM ~Asynchronous Transfer Mode) networks, virtual paths are cross-connected (switched) by an ATM
cross-connecting (virtual path switching) apparatus, which is generally provided in nodes in the ATM network.
In each ATM cross-connecting apparatus, a virtual pa~h identifier (VPI) in each cell incoming thereto is re-written in accordance with a virtual path identifierconversion table, and the cell is cross-connected to another virtual path in accordance with a routing table.
Conventionally, to monitor the normality of the operation of the ATM cross-connecting apparatus, an OAM
(Operation, Al~ ;n;~tration~ and Maintenance) cell is transferred as a test cell through a path of the main signal (signal representing information to be transmitted between users of the ATM network), and the content of the transferred OAM cell is e~m;ned.
However, conventionally, the content of the above OAM cell as a test cell is wxitten by software in a controller of the ATM cross-connecting apparatus in a node, and is examined by software in the same controller of the ATM cross-connecting apparatus or a controller of an ATM cross-connecting apparatus in the next node to which the OAM cell is outgoing from the above ATM cross-connecting apparatus. The testing and monitoring by - 2 - FJ, NDD-9061-CA
transferring the OAM cell is carried out for every virtual path connected to the ATM cross-connecting apparatus, and the content of information fields of the OAM cells must be various data (bit) patterns.
Therefore, a heavy load is imposed on processors in the controller of the ATM cross-connecting apparatuses. In addition, the above various patterns must be stored from the time the patterns are written in the OAM cell until the content of the transferred OAM cell are respectively compared with the stored patterns (examined). Further, the stored patterns may be transferred to the next node when the e~. ;nation is carried out in the next node.
Since the size of the information field is 48 bytes, a memory areas of considerable size are required to store the above patterns, and a considerable amount of data (patterns) must be transferred to the next node.
Otherwise, the patterns to be written in the OAM cells may be delivered from a central monitoring apparatus to each pair of nodes when the OAM cells are input to an ATM cross-connecting apparatus in one of the pair of nodes and are ~ inefl in the other of the pair of the nodes. In this case, a large amount of data (patterns) must be delivered to the pairs of nodes.
SUMMARY OF THE lNv~NllON
An object of the present invention is to provide a system for monitoring an ATM cross-connecting apparatus wherein a load imposed on software in a controller of the ATM cross-connecting apparatus is reduced.
Another object of the presant invention is to provide a system for monitoring an ATM cross-connecting apparatus wherein a whole bit pattern written in a test cell is not required to be supplied for e~r;n;ng the test cell after being cross-connected in the ATM cross-connecting apparatus.
According to the first aspect of the present invention, there is provided a system for monitoring an - 3 - FJ, NDD-9061-CA
ATM cross-connecting apparatus by inputting a test cell through a path for a main signal into the ATM cross-connecting apparatus, and ~ ;ning the cell after the cell passes through the ATM cross-connecting apparatus.
The ATM cross-connecting apparatus contains: a plurality of input ports and a plurality of output ports, and a switching unit for cross-connecting the plurality of input ports with the plurality of output ports in accordance with a given routing information. The system contains for each input port of the ATM cross~connecting apparatus: a first sequence generating unit for inputting an initial bit sequence having a predetermined length, and generating a PN sequence initiated by the initial bit sequence; a test cell generating unit for generating a test cell containing the initial bit sequence and the PN sequence generated as above; and a test cell inputting unit for inputting the test cell in the ATM cross-connecting apparatus through the input port. The system contains for at least one of the output ports of the ATM cross-connecting apparatus, connected with the above each input port through the ~TM cross-connecting apparatus: a test cell receiving unit for receiving the test cell output from the above at least one output port; an initial bit sequence extracting uni~
for extracting the above initial bit sequence written in the test cell received through the output port; a PN
sequence extracting unit for extracting the above PN
sequence from the test cell output from the above at least one output port; a second PN sequence generating unit, having the same construction as said first Pi~
sequence generating unit, for inputting said generating a PN sequence initiated by the initial bit sequence extracted by the initial bit sequence extracted unit; a comparing unit for comparing the extracted PN sequence with the PN sequence generated in the second PN sequence generating unit initiated by the extracted initial bit sequence, to output an error detect signal when the - 4 - FJ, NDD-gO61-CA
above two PN sequences are not equal.
According to the second aspect of the present invention, there is provided a system for monitoring an ATM cross-connecting apparatus by inputting a test cell through a path for a main signal into the ATM cross-connecting apparatus, and ~ ; n; ng the cell after the cell passed through the ATM cross-connecting apparatus.
The ATM cross-connecting apparatus contains: a plurality of input ports and a plurality of output ports, and a switching unit for cross-connecting the plurality of input ports with the plurality of output ports in accordance with a given routing information. The system contains for each input port of the ATM cross-connecting apparatus: a first sequence generating unit for inputting information indicating a primitive polynomial to be used for generating a PN sequence, and an initial bit sequence having a predete ;ned length, and generating a PN sequence based on the primitive polynomial and initiated by the initial bit sequence; a test cell generating unit for g~nerating a test cell containing the above information on the primitive polynomial, the initial bit sequence, and the PN
sequence generated as above; and a test cell inputting unit for inputting the test cell in the ATM cross-connecting apparatus through the input port. The systemcontains for at least one of the output ports of the ATM
cross-connecting apparatus, connected with the above each input port through the ATM cross-connecting apparatus: a test cell receiving unit for receiving the test cell output from the above at least one output port; a primitive polynomial information extracting unit for extracting the above information on the primitive polynomial to be used for generating the PN sequence, from the received test cell; an initial bit sequence extracting unit for ex~racting the above initial bit sequence written in the test cell received through the output port; a PN sequence extracting unit for - 5 - FJ, NDD-9061-CA
extracting the above P~ sequence from the test cell output from the above at least one output port; a second PN sequence generating unit for inputting said generating a PN sequence based on the primitive polynomial indicated by the extracted information and initiated by the extracted initial bit sequence; a comparing unit for comparing the extracted PN sequence with the PN sequence generated in the second PN sequence generating unit initiated by the extracted initial bit sequence, to output an error detect signal when the above two PN sequences are not equal.
According to the third aspect of the present invention, there is provided a system for monitoring an ATM cross-connecting apparatus by inputting a test cell comprised of a header and an information field and containing a first virtual path identifier in the header, through a path for a main signal into the ATM
cross-connecting apparatus, and ~i in;ng the cell after the cell passes through the ATM cross-connecting apparatus. The ATM cross-connecting apparatus contains:
a plnrality of input ports and a plurality of output ports, a virtual path identifier converting unit for converting the first virtual path identifier contained in the test cell into a second virtual path identifier which is predetermined corresponding to the first virtual path identifier, and a switching unik for cross-connecting the plurality of input ports with the plurality of output ports in accordance with given routing information. The system contains, for each input port of the ATM cross-connecting apparatus: a test cell generating unit for generating a test cell containing, in addition to the first virtual path identifier in the header, the same first virtual path identifier in the information field thereof; and a test cell inputting unit for inputting the test cell in the ATM cross-connecting apparatus through the input port. The system contains for at least one of the outpu~ ports of the ATM
cross-connecting (virtual path switching) apparatus, which is generally provided in nodes in the ATM network.
In each ATM cross-connecting apparatus, a virtual pa~h identifier (VPI) in each cell incoming thereto is re-written in accordance with a virtual path identifierconversion table, and the cell is cross-connected to another virtual path in accordance with a routing table.
Conventionally, to monitor the normality of the operation of the ATM cross-connecting apparatus, an OAM
(Operation, Al~ ;n;~tration~ and Maintenance) cell is transferred as a test cell through a path of the main signal (signal representing information to be transmitted between users of the ATM network), and the content of the transferred OAM cell is e~m;ned.
However, conventionally, the content of the above OAM cell as a test cell is wxitten by software in a controller of the ATM cross-connecting apparatus in a node, and is examined by software in the same controller of the ATM cross-connecting apparatus or a controller of an ATM cross-connecting apparatus in the next node to which the OAM cell is outgoing from the above ATM cross-connecting apparatus. The testing and monitoring by - 2 - FJ, NDD-9061-CA
transferring the OAM cell is carried out for every virtual path connected to the ATM cross-connecting apparatus, and the content of information fields of the OAM cells must be various data (bit) patterns.
Therefore, a heavy load is imposed on processors in the controller of the ATM cross-connecting apparatuses. In addition, the above various patterns must be stored from the time the patterns are written in the OAM cell until the content of the transferred OAM cell are respectively compared with the stored patterns (examined). Further, the stored patterns may be transferred to the next node when the e~. ;nation is carried out in the next node.
Since the size of the information field is 48 bytes, a memory areas of considerable size are required to store the above patterns, and a considerable amount of data (patterns) must be transferred to the next node.
Otherwise, the patterns to be written in the OAM cells may be delivered from a central monitoring apparatus to each pair of nodes when the OAM cells are input to an ATM cross-connecting apparatus in one of the pair of nodes and are ~ inefl in the other of the pair of the nodes. In this case, a large amount of data (patterns) must be delivered to the pairs of nodes.
SUMMARY OF THE lNv~NllON
An object of the present invention is to provide a system for monitoring an ATM cross-connecting apparatus wherein a load imposed on software in a controller of the ATM cross-connecting apparatus is reduced.
Another object of the presant invention is to provide a system for monitoring an ATM cross-connecting apparatus wherein a whole bit pattern written in a test cell is not required to be supplied for e~r;n;ng the test cell after being cross-connected in the ATM cross-connecting apparatus.
According to the first aspect of the present invention, there is provided a system for monitoring an - 3 - FJ, NDD-9061-CA
ATM cross-connecting apparatus by inputting a test cell through a path for a main signal into the ATM cross-connecting apparatus, and ~ ;ning the cell after the cell passes through the ATM cross-connecting apparatus.
The ATM cross-connecting apparatus contains: a plurality of input ports and a plurality of output ports, and a switching unit for cross-connecting the plurality of input ports with the plurality of output ports in accordance with a given routing information. The system contains for each input port of the ATM cross~connecting apparatus: a first sequence generating unit for inputting an initial bit sequence having a predetermined length, and generating a PN sequence initiated by the initial bit sequence; a test cell generating unit for generating a test cell containing the initial bit sequence and the PN sequence generated as above; and a test cell inputting unit for inputting the test cell in the ATM cross-connecting apparatus through the input port. The system contains for at least one of the output ports of the ATM cross-connecting apparatus, connected with the above each input port through the ~TM cross-connecting apparatus: a test cell receiving unit for receiving the test cell output from the above at least one output port; an initial bit sequence extracting uni~
for extracting the above initial bit sequence written in the test cell received through the output port; a PN
sequence extracting unit for extracting the above PN
sequence from the test cell output from the above at least one output port; a second PN sequence generating unit, having the same construction as said first Pi~
sequence generating unit, for inputting said generating a PN sequence initiated by the initial bit sequence extracted by the initial bit sequence extracted unit; a comparing unit for comparing the extracted PN sequence with the PN sequence generated in the second PN sequence generating unit initiated by the extracted initial bit sequence, to output an error detect signal when the - 4 - FJ, NDD-gO61-CA
above two PN sequences are not equal.
According to the second aspect of the present invention, there is provided a system for monitoring an ATM cross-connecting apparatus by inputting a test cell through a path for a main signal into the ATM cross-connecting apparatus, and ~ ; n; ng the cell after the cell passed through the ATM cross-connecting apparatus.
The ATM cross-connecting apparatus contains: a plurality of input ports and a plurality of output ports, and a switching unit for cross-connecting the plurality of input ports with the plurality of output ports in accordance with a given routing information. The system contains for each input port of the ATM cross-connecting apparatus: a first sequence generating unit for inputting information indicating a primitive polynomial to be used for generating a PN sequence, and an initial bit sequence having a predete ;ned length, and generating a PN sequence based on the primitive polynomial and initiated by the initial bit sequence; a test cell generating unit for g~nerating a test cell containing the above information on the primitive polynomial, the initial bit sequence, and the PN
sequence generated as above; and a test cell inputting unit for inputting the test cell in the ATM cross-connecting apparatus through the input port. The systemcontains for at least one of the output ports of the ATM
cross-connecting apparatus, connected with the above each input port through the ATM cross-connecting apparatus: a test cell receiving unit for receiving the test cell output from the above at least one output port; a primitive polynomial information extracting unit for extracting the above information on the primitive polynomial to be used for generating the PN sequence, from the received test cell; an initial bit sequence extracting unit for ex~racting the above initial bit sequence written in the test cell received through the output port; a PN sequence extracting unit for - 5 - FJ, NDD-9061-CA
extracting the above P~ sequence from the test cell output from the above at least one output port; a second PN sequence generating unit for inputting said generating a PN sequence based on the primitive polynomial indicated by the extracted information and initiated by the extracted initial bit sequence; a comparing unit for comparing the extracted PN sequence with the PN sequence generated in the second PN sequence generating unit initiated by the extracted initial bit sequence, to output an error detect signal when the above two PN sequences are not equal.
According to the third aspect of the present invention, there is provided a system for monitoring an ATM cross-connecting apparatus by inputting a test cell comprised of a header and an information field and containing a first virtual path identifier in the header, through a path for a main signal into the ATM
cross-connecting apparatus, and ~i in;ng the cell after the cell passes through the ATM cross-connecting apparatus. The ATM cross-connecting apparatus contains:
a plnrality of input ports and a plurality of output ports, a virtual path identifier converting unit for converting the first virtual path identifier contained in the test cell into a second virtual path identifier which is predetermined corresponding to the first virtual path identifier, and a switching unik for cross-connecting the plurality of input ports with the plurality of output ports in accordance with given routing information. The system contains, for each input port of the ATM cross-connecting apparatus: a test cell generating unit for generating a test cell containing, in addition to the first virtual path identifier in the header, the same first virtual path identifier in the information field thereof; and a test cell inputting unit for inputting the test cell in the ATM cross-connecting apparatus through the input port. The system contains for at least one of the outpu~ ports of the ATM
- 6 FJ, NDD-9061-CA
cross-connecting apparatus, connected with the above each port through the ATM cross-connecting apparatus: a virtual path identifier conversion information storing unit for storing information on the above conversions carried out in the above virtual path identifier converting unit corresponding to the above at least one output port; a test cell receiving unit for receiving the test cell output from the above at least one output port; a first virtual path identifier extracting unit for extracting the above first virtual path identifier contained in the information field of the test cell received through the output port; a second virtual path identifier extracting unit for extracting the above second virtual path identifier con~erted by the virtual path identifier converting unit and contained in the header of the test cell received through the output port; and an error detecting unit for determining whether or not the first virtual path identifier extracted from the information field correctly corresponds to the second virtual path identifier extracted from the header, to output an error detect signal when the above first and second virtual path identifiers do not correspond to each other.
BRIEF DESCRIPTION OF THE DRAWINGS
In the drawings:
Figur! 1 is a diagram indicating a format of an ATM
cellr As indicated in Fig. 1, the above-mentioned virtual path identifier ~VPI) and a virtual channel identifier (VCI) for identifying a virtual path are written in the header area;
Figure 2 is a diagram indicating an outline of the construction of a conventional ATM cross-connecting ~pparatus, and an example path of an OAM cell for testing the operation of the ATM cross-connecting apparatus;
Figure 3 is a diagram indicating the construction - 7 - FJ, NDD-9061-CA
of the receiving unit lia ~i=1 to n~ in Fig. 2;
Figure 4 is a diagram indicating the construction of the transmitting unit ljb in Fig. 2;
Figure 5 is a diagram indicating an outline of the construction of the ATM cross-connecting apparatus according to the present invention;
Figure 6 is a diagram indicating the construction of the test cell generating unit 200 according to the first embodiment of the present invention;
Figure 7 is a diagram indicating the contents of the information field of the test cell in the first embodiment of the present invention;
Figure 8 is a diagram indicating the construction provided for an output port connected with each input port of the ATM cross-connecting apparatus through the switching unit 3, in the test cell error detecting unit 300 according to the first embodiment of the present invention;
Figure 9 is a diagram indicating the construction of the test cell generating unit 200 according to the second embodiment of the present invention;
Figure 10 is a diagram indicating the contents of the information field of the test cell in the second embodiment of the present invention;
Figure 11 is a diagram indicating the construction provided for an output port connected with each input port of the ATM cross-connecting apparatus through the switching unit 3, in the test cell error detecting unit 300 according to the second embodiment of the present invention;
Figure 12 is a diagram indicating the contents of the information field of the test cell in the third embodiment of the present invention; and Figure 13 is a diagram indicating the construction provided for an output port connected with each input port of the ATM cross-connecting apparatus through the switching unit 3, in the test cell error detecting unit - 8 - FJ, NDD-9061-CA
300, according to the third embodiment of ~he present invention.
DESCRIPTION OF T~E PREF~RRED EMBODIMENT~
Format of Cell (Fiq. 1) Figure 1 is a diagram indicating a format of an ATM
cell. As indicated in Fig. 1, the above-mentioned virtual path identifier (VPI) and a virtual channel identifier (VCI~ for identifying a virtual path are written in the header area. In addition, PT denotes a field of Pay Load Type, which is used to indicate whether the cell is used for a user, or is used as an OAM cell.
Conventional Monitoring System (Figs. 2, 3, and 4) Figure 2 is a diagram indicating an outline of the construction of a conventional ATM cross-connecting apparatus, and an example path of an OAM cell for testing the operation of the ATM cross-connecting apparatus. In Fig. 2, reference numerals li (i=l to n~
each denote an interface unit corresponding to each input/output port of the ATM cross-connecting apparatus, lia (i-l to n) each denote a receiving unit, ljb (j=l to n) each denote a transmitting unit, 2i (i=l to n) each denote a virtual path identifier (VPI) conversion unit, and 3 denotes a switching unit. An incoming cell transferred from another node or a terminal is received by the receiving unit lia (i=l to n) in each interface unit li, and is multiplexed therein. Then, a virtual path identifier (VPI) in each cell is replaced with another virtual path identifier (VPI) corresponding to a virtual path through which the cell is to be output to a next node. The replacement (conversion) of the virtual path identifier (VPI) is carried out in accordance with a virtual path identifier (VPI) conversion table (not shown) provided in each virtual path identifier (VPI) conversion unit 2i.
cross-connecting apparatus, connected with the above each port through the ATM cross-connecting apparatus: a virtual path identifier conversion information storing unit for storing information on the above conversions carried out in the above virtual path identifier converting unit corresponding to the above at least one output port; a test cell receiving unit for receiving the test cell output from the above at least one output port; a first virtual path identifier extracting unit for extracting the above first virtual path identifier contained in the information field of the test cell received through the output port; a second virtual path identifier extracting unit for extracting the above second virtual path identifier con~erted by the virtual path identifier converting unit and contained in the header of the test cell received through the output port; and an error detecting unit for determining whether or not the first virtual path identifier extracted from the information field correctly corresponds to the second virtual path identifier extracted from the header, to output an error detect signal when the above first and second virtual path identifiers do not correspond to each other.
BRIEF DESCRIPTION OF THE DRAWINGS
In the drawings:
Figur! 1 is a diagram indicating a format of an ATM
cellr As indicated in Fig. 1, the above-mentioned virtual path identifier ~VPI) and a virtual channel identifier (VCI) for identifying a virtual path are written in the header area;
Figure 2 is a diagram indicating an outline of the construction of a conventional ATM cross-connecting ~pparatus, and an example path of an OAM cell for testing the operation of the ATM cross-connecting apparatus;
Figure 3 is a diagram indicating the construction - 7 - FJ, NDD-9061-CA
of the receiving unit lia ~i=1 to n~ in Fig. 2;
Figure 4 is a diagram indicating the construction of the transmitting unit ljb in Fig. 2;
Figure 5 is a diagram indicating an outline of the construction of the ATM cross-connecting apparatus according to the present invention;
Figure 6 is a diagram indicating the construction of the test cell generating unit 200 according to the first embodiment of the present invention;
Figure 7 is a diagram indicating the contents of the information field of the test cell in the first embodiment of the present invention;
Figure 8 is a diagram indicating the construction provided for an output port connected with each input port of the ATM cross-connecting apparatus through the switching unit 3, in the test cell error detecting unit 300 according to the first embodiment of the present invention;
Figure 9 is a diagram indicating the construction of the test cell generating unit 200 according to the second embodiment of the present invention;
Figure 10 is a diagram indicating the contents of the information field of the test cell in the second embodiment of the present invention;
Figure 11 is a diagram indicating the construction provided for an output port connected with each input port of the ATM cross-connecting apparatus through the switching unit 3, in the test cell error detecting unit 300 according to the second embodiment of the present invention;
Figure 12 is a diagram indicating the contents of the information field of the test cell in the third embodiment of the present invention; and Figure 13 is a diagram indicating the construction provided for an output port connected with each input port of the ATM cross-connecting apparatus through the switching unit 3, in the test cell error detecting unit - 8 - FJ, NDD-9061-CA
300, according to the third embodiment of ~he present invention.
DESCRIPTION OF T~E PREF~RRED EMBODIMENT~
Format of Cell (Fiq. 1) Figure 1 is a diagram indicating a format of an ATM
cell. As indicated in Fig. 1, the above-mentioned virtual path identifier (VPI) and a virtual channel identifier (VCI~ for identifying a virtual path are written in the header area. In addition, PT denotes a field of Pay Load Type, which is used to indicate whether the cell is used for a user, or is used as an OAM cell.
Conventional Monitoring System (Figs. 2, 3, and 4) Figure 2 is a diagram indicating an outline of the construction of a conventional ATM cross-connecting apparatus, and an example path of an OAM cell for testing the operation of the ATM cross-connecting apparatus. In Fig. 2, reference numerals li (i=l to n~
each denote an interface unit corresponding to each input/output port of the ATM cross-connecting apparatus, lia (i-l to n) each denote a receiving unit, ljb (j=l to n) each denote a transmitting unit, 2i (i=l to n) each denote a virtual path identifier (VPI) conversion unit, and 3 denotes a switching unit. An incoming cell transferred from another node or a terminal is received by the receiving unit lia (i=l to n) in each interface unit li, and is multiplexed therein. Then, a virtual path identifier (VPI) in each cell is replaced with another virtual path identifier (VPI) corresponding to a virtual path through which the cell is to be output to a next node. The replacement (conversion) of the virtual path identifier (VPI) is carried out in accordance with a virtual path identifier (VPI) conversion table (not shown) provided in each virtual path identifier (VPI) conversion unit 2i.
- 9 FJ, NDD~9061-CA
The cell output from each virtual path identifier (VPI) conversion unit 2i is switched (cross-connected) to an output port of the switching unit 3, where the output port corresponds to another virtual path. The cell output from each output port of the switching unit 3 is applied to one of the transmitting units ljb in one of the interface units li corresponding to the virtual path, is demultiplexed therein, and is then transmitted therefrom to the next node.
Figure 3 is a diagram indicating the construction of the receiving unit lia (i=l to n) in Fig. 2. In Fig.
3, reference numeral 101 denotes a test cell inserting unit, 102 denotes an ATM reception processing unit, and 103 denotes a selector. A main signal containing an input cell (containing information to be transmitted between users of the ~TM network) is transferred from another node to the ATM reception processing unit 102.
The ATM reception processing unit 102 contains a buffer memory (not shown), and the above input cell is temporarily written in the buffer memory. The input cell in the buffer memory is then transferred to the selector 103. On the other hand, test cells are generated in and supplied from the above-mentioned controller of the ATM
cross-connecting apparatu~ (not shown) accompanied with the ATM cross-connecting apparatus. The test cell is temporarily held in the test cell inserting unit 101.
When at least one input cell is held in the buffer memory, the selector 103 selects the input cell from the ATM reception processing unit 102 as its output, or when no input cell is held in the buffer memory in the ATM
reception processing unit 102, the selector 103 selects the test cell supplied from the test cell inserting unit 101. Thus, the test cells are multiplexed with a flow of the input cells by the selector 103. The multiplexed cells are supplied to the virtual path identifier (VPI) conversion unit 2i.
Figure 4 is a diagram indicating the construction - 10 - FJ, NDD-9061-CA
of the transmitting unit ljb in Fig. 2. In Fig. 4, reference numeral 104 denotes a test cell separating unit, and 105 denotes an ATM transmission processing unit.
Each cell including either a cell of the main signal or a test cell, switched in the switching unit 3, is supplied to the test cell separating unit 104. In the test cell separating unit 104, test cells are separated from the other cells to be transmitted to the other node. The separation of each cell is carried out based Oll whether or not the field of the Pay Load Type indicates that the cell is an OAM cell. The separated test cells are supplied to the controller of the A~M
cross-connecting apparatus, and the above cells to be transmitted to the other node are supplied to the ATM
transmission processing unit 105. The ATM transmission processing unit also contains a buffer memory (not shown), and the above cells to be transmitted to the other node are temporarily held in the buffer memory, and are then transmitted therefrom to the other node.
Outline of ATM Cross-Connecting A~paratus (Fiq. 5) Figure 5 is a diagram indicating an outline of the construction of the ATM cross-connecting apparatus according to the present invention. In Fig. 5, reference numeral 100 denotes a main portion of the ATM cross-connecting apparatus which has almost the same construction as indicated in Figs. 2 to 4, 200 denotes a test cell generating unit, 300 denotes a test cell error detecting unit, and 400 denotes a controller of the ATM
cross-connecting apparatus. The controller 400 writes the contents of the above-mentioned virtual path identifier (VPI) conversion table (not shown) and the routing table in accordance with instructions given from a central control station (not shown) controlling the whole ATM network. In addition, the controller of the ATM cross-connecting apparatus monitors the operation of ~ FJ, NDD-9061-CA
the ATM cross-connecting apparatus in accordance with the present invention as explained below, and, when a malfunction of the ATM cross-connecting apparatus is detected, the malfunction is reported to the central control station. The test cell generating unit 200 and the test cell error detecting unit 300 are provided according to the present invention. The constructions and operations of these units 200 and 300 are explained below for first to third embodiments of the present invention, respectively.
First Embodiment (Figs. 6, 7 and 8) Figure 6 is a diagram indicating the construction provided for each input port of the ATM cross-connecting apparatus in the test cell generating unit 200 according to the first embodiment of the present invention. In Fig. 6, reference numeral 21 denotes a PN sequence generator, and lia' (i=1 to n) each denote a receiving unit. Namely, the test cell generating unit 200 according to the first embodiment of the present invention contains a PN sequence generator 21 for each receiving unit lia. The PN sequence generator 21 is constructed by, for example, a m-stage shift register with linear feedback in accordance with a predetermined primitive polynomial of order m (where m is an integer), inputs an initial bit sequence supplied from the controller 400 and having a predet~rm; ned length at least equal to m, and generates a PN sequence initiated by the initial bit sequence and based on a predetermined primitive polynomial. The initial bit sequence and the PN sequence generated by the PN sequence generator 21' are supplied to the test cell inserting unit 101' in the receivlng unit lial. The test cell inserting unit 101' generates a test cell by writing the initial bit sequence and the above-generated PN sequence in the information field as indicated in Fig. 7, and writing the indication that the cell is an OAM cell in the Pay - 12 - FJ, NDD-9061-CA
Load Type field in the header. The test cell inserting unit 101' inserts the generated test cell between the flows of the input cells through the selector 103 in the same manner as the construction of Fig. 3. The other construction of the receiving unit lia' is the same as the construction of Fig. 3.
Figure 8 is a diagram indicating the construction provided for an output port which is connected with each input port of the ATM cross-connecting apparatus through the switching unit 3, in the test cell error detecting unit 300 according to the first embodiment of the present invention. In Fig. 8, reference numeral 31 denotes an initial bit sequence extracting unit, 32 denotes a PN sequence ex~racting unit, 33 denotes a PN
sequence generator, 34 denotes a comparing unit, and ljb denotes the same construction of the transmitting unit of Fig. 4. The test cells are separated from the other cells to be transmitted to the other node, in the test cell separating unit 104 in the same manner as the construction of Fig. 4. The separated test cells are supplied to the initial bit sequence extracting unit 31 and the PN sequence extracting unit 32. The initial bit sequence extracting unit 31 extracts the ini~ial bit sequence of the PN sequence from the area of the initial bit sequence in the information field of the test cell, and the PN sequence extracting unit 32 extracts the PN
sequence from the area thereof in the information field of the test cell. The PN sequence generator 33 has the same construction as the PN sequence generator 21 provided for the input port connected with the output port through the switching unit 3. The PN sequence generator 33 generates a PN sequence initiated by the initial bit sequence extracted by the initial bit sequence extracting unit 31, and based on the same primitive polynomial as the above PN sequence generator 21. The comparing unit 34 compares the PN sequence generated in the PN sequence genera~or 33 with the PN
- 13 - FJ, NDD-9061-CA
sequence extracted b~ the PN sequence extracting unit 32, and outputs an error detect signal to the controller 400 when any difference between both the PN sequences is detected.
Thus, according to the above construction of the first embodiment of the present invention, when an error occurs in the area of the initial bit sequence of the PN
sequence in the information field of the test cell, the PN sequence generator generates a PN sequence different from the PN sequence generated in the PN sequence generator 21, and therefore, the error is detected as the difference between both the PN sequences. In addition, when an error occurs in the area of the PN
sequence in the information field of the test cell, the error is detected as the difference between both the PN
sequences.
Further, since all of the constructions of Figs. 6 and 8 are realized by a hardware logic circuit of a small size, no heavy load is imposed on the controller 400. Namely, the controller 400 of the ATM cross-connecting apparatus is required only to supply the initial bit sequence of a PN sequence to be generated, and monitor the error detect signal output from the comparing unit 34 of Fig. 8.
Second Embodiment ~Figs. 9 10 and 11) Figure 9 is a diagram indicating the construction provided for each input port of the ATM cross-connecting apparatus in the test cell generating unit 200 according to the second embodiment of the present invention. In Fig. 6, reference numeral 21' denotes a PN sequence generator, and lia" (i=l to n) each denote a receiving unitO Namely, the test cell generating unit 200 according to the second embodiment of the present inventlon contains a PN sequence generator 21' for each receiving unit lia. The PN sequence generator 21' is comprised of a plurality of PN sequence generating - 14 - FJ, NDD-9061-CA
circuits corresponding to a plurality of primitive polynomials, respectively. Each PN sequence generating circuit is constituted by a m-stage shift register with linear feedback in accordance with a corresponding primitive polynomial of order m (where m is an integer).
The PN sequence generator 21' comprises a selector (not shown) for activating one of the abov~ plurality of PN
sequence generating circuits when a bit pattern indicating a type of a primitive polynomial is supplied from the controller 400. Thus, PN sequence generator 21' functions as one of the plurality of PN sequence generating circuits designated by the bit pattern. The PN sequence generator 21' then inputs an initial bit sequence supplied from the controller 400 and having a predetermined length at least equal to m, and generates a PN sequence initiated by the received initial bit sequence and based on the primitive polynomial determined by the supplied bit pattern. Table 1 indicates examples of the bit patterns for some typical primitive polynomials.
Table 1 Bit Patterns and Primitive Polynomials ORDERBIT PATTERN PRIMITIVE POLYNOMIAL
2 00000111 X2+X+1 3 00001101 X3+X'+1 00101001 X*X3~1 7 11000001 X'+X6+1 The above bit pattern indicating the primitive polynomial, the initial bit sequence, and the PN
sequence generated by the PN sequence generator 21' are supplied to the test cell inserting unit 101" in the receiving unit lia". The test cell inserting unit 101"
generates a test cell by writing the bit pattern, the initial bit sequence, and the following PN sequence in - 15 - FJ, NDD-9061-CA
the information field as indicated in Fig. 10, and writing the indication that ~he cell is an OAM cell in the Pay Load Type field in the header. The test cell inserting unit 101" inserts the generated test cell between the flows of the input cells through the selector 103 in the same manner as the construction of Fig. 3. The other construction of the receiving unit lia" is the same as the construction of Fig. 3.
~igure 11 is a diagram indicating the construction provided for an output port connected with each input port of the ATM cross~connecting apparatus through the switching unit 3, in the test cell error detecting unit 300 according to the second embodiment of the present invention. In Fig. 11, reference numeral 41 denotes a bit pattern extracting unit, 42 denotes an initial bit sequence extracting unit, 43 denotes a PN sequence extracting unit, 44 denotes a PN sequence generator, 45 denotes a comparing unit, and ljb denotes the same construction of the transmitting unit of Fig. 4. The test cells are separated from the other cells to be transmitted to the other node, in the test cell separating unit 104 in the same manner as the construction of Fig. 4. ~he separated test cells are supplied to the bit pattern extracting unit 41, the initial bit sequence extracting unit 42, and the PN
sequence extracting unit 43. The bit pattern extracting unit 41 extracts the above bit pattern from the area of the bit pattern in the information field of the test cell. The initial bit sequence extracting unit 42 extracts ~he initial bit sequence of the PN sequence from the area of the initial bit sequence in the information field of the test cell, and the PN sequence extracting unit 43 extracts the PN sequence from the area thereof in the information field of the test cell.
The PN sequence generator 44 has the same construction as the PN sequence generator 21' provided for the input port connected with the output port through the - 16 - FJ, NDD-9061-CA
switching unit 3, and activates one of the plurality of PN sequence generating circuits therein in response to the bit pattern extracted by the bit pattern extrac~ing unit 41. The PN sequence generator 44 generates a PN
sequence initiated by the initial bit sequence extracted by the initial bit sequence extracting unit 42, and based on the primitive polynomial determined by the extracted bit pattern. The comparing unit 45 compares the PN sequence generated in the PN sequence generator 44 with the PN sequence extractQd by the PN sequence extracting unit 43, and outputs an error detect signal to the controller 400 of the ATM cross-connecting apparatus when any difference between both the PN
sequences is detected.
Thus, according to the above construction of the second embodiment of the present invention, when an error occurs in the area of the bit pattern indicating the primitive polynomial in the information field of the test cell, the PN sequence generator generates a PN
sequence different from the PN sequence generated in the PN sequence generator 21', and therefore, the error i9 detected as the difference between both the PN
sequences. In addition, the errors in the areas of the initial bit sequence and the PN sequence can be detected in then same manner as the first embodiment of the present invention.
Further, similar to the first embodiment, since all of the constructions of Figs. 9 and 11 are realized by a small size hardware logic circuit, no heavy load is imposed on the controller 400 of the ATM cross-connecting apparatus. Namely, the controller 400 is required only to supply the bit pattern indicating a primitive polynomial and the initial bit sequence of a PN sequence to be generated, and monitor the error detect signal output from the comparing unit 45 of Fig.
The cell output from each virtual path identifier (VPI) conversion unit 2i is switched (cross-connected) to an output port of the switching unit 3, where the output port corresponds to another virtual path. The cell output from each output port of the switching unit 3 is applied to one of the transmitting units ljb in one of the interface units li corresponding to the virtual path, is demultiplexed therein, and is then transmitted therefrom to the next node.
Figure 3 is a diagram indicating the construction of the receiving unit lia (i=l to n) in Fig. 2. In Fig.
3, reference numeral 101 denotes a test cell inserting unit, 102 denotes an ATM reception processing unit, and 103 denotes a selector. A main signal containing an input cell (containing information to be transmitted between users of the ~TM network) is transferred from another node to the ATM reception processing unit 102.
The ATM reception processing unit 102 contains a buffer memory (not shown), and the above input cell is temporarily written in the buffer memory. The input cell in the buffer memory is then transferred to the selector 103. On the other hand, test cells are generated in and supplied from the above-mentioned controller of the ATM
cross-connecting apparatu~ (not shown) accompanied with the ATM cross-connecting apparatus. The test cell is temporarily held in the test cell inserting unit 101.
When at least one input cell is held in the buffer memory, the selector 103 selects the input cell from the ATM reception processing unit 102 as its output, or when no input cell is held in the buffer memory in the ATM
reception processing unit 102, the selector 103 selects the test cell supplied from the test cell inserting unit 101. Thus, the test cells are multiplexed with a flow of the input cells by the selector 103. The multiplexed cells are supplied to the virtual path identifier (VPI) conversion unit 2i.
Figure 4 is a diagram indicating the construction - 10 - FJ, NDD-9061-CA
of the transmitting unit ljb in Fig. 2. In Fig. 4, reference numeral 104 denotes a test cell separating unit, and 105 denotes an ATM transmission processing unit.
Each cell including either a cell of the main signal or a test cell, switched in the switching unit 3, is supplied to the test cell separating unit 104. In the test cell separating unit 104, test cells are separated from the other cells to be transmitted to the other node. The separation of each cell is carried out based Oll whether or not the field of the Pay Load Type indicates that the cell is an OAM cell. The separated test cells are supplied to the controller of the A~M
cross-connecting apparatus, and the above cells to be transmitted to the other node are supplied to the ATM
transmission processing unit 105. The ATM transmission processing unit also contains a buffer memory (not shown), and the above cells to be transmitted to the other node are temporarily held in the buffer memory, and are then transmitted therefrom to the other node.
Outline of ATM Cross-Connecting A~paratus (Fiq. 5) Figure 5 is a diagram indicating an outline of the construction of the ATM cross-connecting apparatus according to the present invention. In Fig. 5, reference numeral 100 denotes a main portion of the ATM cross-connecting apparatus which has almost the same construction as indicated in Figs. 2 to 4, 200 denotes a test cell generating unit, 300 denotes a test cell error detecting unit, and 400 denotes a controller of the ATM
cross-connecting apparatus. The controller 400 writes the contents of the above-mentioned virtual path identifier (VPI) conversion table (not shown) and the routing table in accordance with instructions given from a central control station (not shown) controlling the whole ATM network. In addition, the controller of the ATM cross-connecting apparatus monitors the operation of ~ FJ, NDD-9061-CA
the ATM cross-connecting apparatus in accordance with the present invention as explained below, and, when a malfunction of the ATM cross-connecting apparatus is detected, the malfunction is reported to the central control station. The test cell generating unit 200 and the test cell error detecting unit 300 are provided according to the present invention. The constructions and operations of these units 200 and 300 are explained below for first to third embodiments of the present invention, respectively.
First Embodiment (Figs. 6, 7 and 8) Figure 6 is a diagram indicating the construction provided for each input port of the ATM cross-connecting apparatus in the test cell generating unit 200 according to the first embodiment of the present invention. In Fig. 6, reference numeral 21 denotes a PN sequence generator, and lia' (i=1 to n) each denote a receiving unit. Namely, the test cell generating unit 200 according to the first embodiment of the present invention contains a PN sequence generator 21 for each receiving unit lia. The PN sequence generator 21 is constructed by, for example, a m-stage shift register with linear feedback in accordance with a predetermined primitive polynomial of order m (where m is an integer), inputs an initial bit sequence supplied from the controller 400 and having a predet~rm; ned length at least equal to m, and generates a PN sequence initiated by the initial bit sequence and based on a predetermined primitive polynomial. The initial bit sequence and the PN sequence generated by the PN sequence generator 21' are supplied to the test cell inserting unit 101' in the receivlng unit lial. The test cell inserting unit 101' generates a test cell by writing the initial bit sequence and the above-generated PN sequence in the information field as indicated in Fig. 7, and writing the indication that the cell is an OAM cell in the Pay - 12 - FJ, NDD-9061-CA
Load Type field in the header. The test cell inserting unit 101' inserts the generated test cell between the flows of the input cells through the selector 103 in the same manner as the construction of Fig. 3. The other construction of the receiving unit lia' is the same as the construction of Fig. 3.
Figure 8 is a diagram indicating the construction provided for an output port which is connected with each input port of the ATM cross-connecting apparatus through the switching unit 3, in the test cell error detecting unit 300 according to the first embodiment of the present invention. In Fig. 8, reference numeral 31 denotes an initial bit sequence extracting unit, 32 denotes a PN sequence ex~racting unit, 33 denotes a PN
sequence generator, 34 denotes a comparing unit, and ljb denotes the same construction of the transmitting unit of Fig. 4. The test cells are separated from the other cells to be transmitted to the other node, in the test cell separating unit 104 in the same manner as the construction of Fig. 4. The separated test cells are supplied to the initial bit sequence extracting unit 31 and the PN sequence extracting unit 32. The initial bit sequence extracting unit 31 extracts the ini~ial bit sequence of the PN sequence from the area of the initial bit sequence in the information field of the test cell, and the PN sequence extracting unit 32 extracts the PN
sequence from the area thereof in the information field of the test cell. The PN sequence generator 33 has the same construction as the PN sequence generator 21 provided for the input port connected with the output port through the switching unit 3. The PN sequence generator 33 generates a PN sequence initiated by the initial bit sequence extracted by the initial bit sequence extracting unit 31, and based on the same primitive polynomial as the above PN sequence generator 21. The comparing unit 34 compares the PN sequence generated in the PN sequence genera~or 33 with the PN
- 13 - FJ, NDD-9061-CA
sequence extracted b~ the PN sequence extracting unit 32, and outputs an error detect signal to the controller 400 when any difference between both the PN sequences is detected.
Thus, according to the above construction of the first embodiment of the present invention, when an error occurs in the area of the initial bit sequence of the PN
sequence in the information field of the test cell, the PN sequence generator generates a PN sequence different from the PN sequence generated in the PN sequence generator 21, and therefore, the error is detected as the difference between both the PN sequences. In addition, when an error occurs in the area of the PN
sequence in the information field of the test cell, the error is detected as the difference between both the PN
sequences.
Further, since all of the constructions of Figs. 6 and 8 are realized by a hardware logic circuit of a small size, no heavy load is imposed on the controller 400. Namely, the controller 400 of the ATM cross-connecting apparatus is required only to supply the initial bit sequence of a PN sequence to be generated, and monitor the error detect signal output from the comparing unit 34 of Fig. 8.
Second Embodiment ~Figs. 9 10 and 11) Figure 9 is a diagram indicating the construction provided for each input port of the ATM cross-connecting apparatus in the test cell generating unit 200 according to the second embodiment of the present invention. In Fig. 6, reference numeral 21' denotes a PN sequence generator, and lia" (i=l to n) each denote a receiving unitO Namely, the test cell generating unit 200 according to the second embodiment of the present inventlon contains a PN sequence generator 21' for each receiving unit lia. The PN sequence generator 21' is comprised of a plurality of PN sequence generating - 14 - FJ, NDD-9061-CA
circuits corresponding to a plurality of primitive polynomials, respectively. Each PN sequence generating circuit is constituted by a m-stage shift register with linear feedback in accordance with a corresponding primitive polynomial of order m (where m is an integer).
The PN sequence generator 21' comprises a selector (not shown) for activating one of the abov~ plurality of PN
sequence generating circuits when a bit pattern indicating a type of a primitive polynomial is supplied from the controller 400. Thus, PN sequence generator 21' functions as one of the plurality of PN sequence generating circuits designated by the bit pattern. The PN sequence generator 21' then inputs an initial bit sequence supplied from the controller 400 and having a predetermined length at least equal to m, and generates a PN sequence initiated by the received initial bit sequence and based on the primitive polynomial determined by the supplied bit pattern. Table 1 indicates examples of the bit patterns for some typical primitive polynomials.
Table 1 Bit Patterns and Primitive Polynomials ORDERBIT PATTERN PRIMITIVE POLYNOMIAL
2 00000111 X2+X+1 3 00001101 X3+X'+1 00101001 X*X3~1 7 11000001 X'+X6+1 The above bit pattern indicating the primitive polynomial, the initial bit sequence, and the PN
sequence generated by the PN sequence generator 21' are supplied to the test cell inserting unit 101" in the receiving unit lia". The test cell inserting unit 101"
generates a test cell by writing the bit pattern, the initial bit sequence, and the following PN sequence in - 15 - FJ, NDD-9061-CA
the information field as indicated in Fig. 10, and writing the indication that ~he cell is an OAM cell in the Pay Load Type field in the header. The test cell inserting unit 101" inserts the generated test cell between the flows of the input cells through the selector 103 in the same manner as the construction of Fig. 3. The other construction of the receiving unit lia" is the same as the construction of Fig. 3.
~igure 11 is a diagram indicating the construction provided for an output port connected with each input port of the ATM cross~connecting apparatus through the switching unit 3, in the test cell error detecting unit 300 according to the second embodiment of the present invention. In Fig. 11, reference numeral 41 denotes a bit pattern extracting unit, 42 denotes an initial bit sequence extracting unit, 43 denotes a PN sequence extracting unit, 44 denotes a PN sequence generator, 45 denotes a comparing unit, and ljb denotes the same construction of the transmitting unit of Fig. 4. The test cells are separated from the other cells to be transmitted to the other node, in the test cell separating unit 104 in the same manner as the construction of Fig. 4. ~he separated test cells are supplied to the bit pattern extracting unit 41, the initial bit sequence extracting unit 42, and the PN
sequence extracting unit 43. The bit pattern extracting unit 41 extracts the above bit pattern from the area of the bit pattern in the information field of the test cell. The initial bit sequence extracting unit 42 extracts ~he initial bit sequence of the PN sequence from the area of the initial bit sequence in the information field of the test cell, and the PN sequence extracting unit 43 extracts the PN sequence from the area thereof in the information field of the test cell.
The PN sequence generator 44 has the same construction as the PN sequence generator 21' provided for the input port connected with the output port through the - 16 - FJ, NDD-9061-CA
switching unit 3, and activates one of the plurality of PN sequence generating circuits therein in response to the bit pattern extracted by the bit pattern extrac~ing unit 41. The PN sequence generator 44 generates a PN
sequence initiated by the initial bit sequence extracted by the initial bit sequence extracting unit 42, and based on the primitive polynomial determined by the extracted bit pattern. The comparing unit 45 compares the PN sequence generated in the PN sequence generator 44 with the PN sequence extractQd by the PN sequence extracting unit 43, and outputs an error detect signal to the controller 400 of the ATM cross-connecting apparatus when any difference between both the PN
sequences is detected.
Thus, according to the above construction of the second embodiment of the present invention, when an error occurs in the area of the bit pattern indicating the primitive polynomial in the information field of the test cell, the PN sequence generator generates a PN
sequence different from the PN sequence generated in the PN sequence generator 21', and therefore, the error i9 detected as the difference between both the PN
sequences. In addition, the errors in the areas of the initial bit sequence and the PN sequence can be detected in then same manner as the first embodiment of the present invention.
Further, similar to the first embodiment, since all of the constructions of Figs. 9 and 11 are realized by a small size hardware logic circuit, no heavy load is imposed on the controller 400 of the ATM cross-connecting apparatus. Namely, the controller 400 is required only to supply the bit pattern indicating a primitive polynomial and the initial bit sequence of a PN sequence to be generated, and monitor the error detect signal output from the comparing unit 45 of Fig.
11 .
- 17 - FJ, NDD-9061-CA
Third Embodiment (Figs. 12 and 13) In the third embodiment of the present invention, no construction is provided as the test cell generating unit 200, and a test cell containing the same value as the virtual path identifier (VPI) written in the header of the test cell, in a predetermined area of the information field of the test cell, is supplied from the controller 400 of the ATM cross-connecting apparatus to the test cell inserting unit 101 of the receiving unit lia (i=l to n). The construction of the receiving unit lia is the same as the construction of Fig. 4. Figure 12 is a diagram indicating ~he test cell used in the third embodiment of the present invention. In Fig. 12, "VPI1"
denotes the virtual path identifier (VPI) in the header, and :VPI2" denotes the above area in which the same value as the virtual path identifier (VPI) in the header is initially written. The above test cell is input into the ATM cross-connecting apparatus in the same manner as the construction of Fig. 4. Then, the virtual path identifier (VPI~ in the header is re-written in the corresponding virtual path identifier (VPI) conversion unit 2i (i=1 to n) in accordance with the above-mentioned virtual path identifier (VPI) conversion table (not shown), and the test cell is switched in the switching unit 3 to one of the transmitting units ljb (j=1 to n) corresponding to a virtual path determined in accordance with the above-mentioned routing table (not shown). The routing table contains information on connections between input ports and output ports of the switching unit 3.
Figure 13 is a diagram indicating the construction provided for an output port connected with each input port of the ATM cross-connecting apparatus through the switching unit 3, in the test cell error detecting unit 300 according to the third embodiment of the present invention. In Fig. 13, reference numeral 51 denotes a virtual path identifier (VPI) extracting unit, 52 - 18 - FJ, NDD-9061-CA
denotes a path monitoring unit, and ljb denotes the same construction of the transmitting unit of Fig. 4~ The test cells are separated fro]m the other cells to be transmitted to the other node, in the test cell separating unit 104 in the same manner as the construction of Fig. 4. The separated test cells are supplied to the virtual path identifier (VPI) extracting unit 51. The virtual path identifier (VPI) e~tracting unit ~1 extracts the above value of the virtual path identifier (VPI) from the area VPI2 in the information field of the test cell. The extracted value of the virtual path identifier (VPI) indicates the virtual path identifier (VPI) before being converted in the virtual path identifier (VPI) conversion table 2i (i-1 to n) when no error occurs in the area VPI2. The extracted value of the virtual path identifier (VPI) before the conversion is supplied to the path monitoring unit 52 together with the virtual path identifier (VPI) in the header of the test cell. In the path monitoring unit 52, the information relating to the output port of the switching unit 3 to which the transmitting unit ljb is connected, is supplied from the controller, and is stored therein in advance. When receiving the above extracted value of the virtual path identifier (VPI) before the conversion, the path monitoring unit 52 determines whether or not the extracted value of the virtual path identifier (VPI) before the conversion corresponds to the virtual path identifier (VPI) in the header of the test cell, based on the above informa~ion relating to the output port of the s~itching unit 3 to which the transmitting unit ljb is connected. When these virtual path identifier (VPI) values do not correspond to each other, the path monitoring unit 52 outputs an error detect signal to the controller 400 of the AT~
cross-connecting apparatus.
The above virtual path identifier (VPI) values will not correspond to each other when the conversion of the - 19 - FJ, NDD-90~1-CA
virtual path identifier (VPI) in the virtual path identifier (VPI) conversion table 2i or the switching operation in the switching unit 3 is not carried out correctly. Thus, according to the above construction of the third embodiment of the present invention, the normality of the operation of converting the virtual path identifier (VPI) in the ATM cross-connecting apparatus, and the operation of the switching unit 3 can be monitored.
Similar to the first and second embodiments, since all of the constructions of Figs. 9 and 11 are realized by a small size hardware logic circuit, no heavy load is imposed on the controller 400 of the ATM cross-connecting apparatus. Namely, the controller 400 i5 required only to supply the initial virtual path identifier (VPI) of the test cell, and monitor the error detect signal output from the path monitoring unit 52 of Fig. 12.
Other Variations Although the above explanation is for the case wherein the test cell is generated and input into an ATM
cross-connecting apparatus in a node, and the test cell output from the ATM cross-connecting apparatus is e~- ined in the same node, it is possible to ~ ine the test cell in the next nodes to which the test cells are transmitted from the node in which the ATM cross-connecting apparatus to be monitored is located. In this case, the provisions according to the first and second embodiments of the present invention are, in particular, advantageous because no information is required to be transmitted to the next nodes for carrying out the operations of the constructions of Figs. 8 and 11 in the first and second embodiments, respectively. As explained before, in the conventional monitoring system, all data of the PN sequence must be transmitted to the next nodes for determining whether or not the test cell contains an - 20 - FJ, NDD-9061-CA
error .
- 17 - FJ, NDD-9061-CA
Third Embodiment (Figs. 12 and 13) In the third embodiment of the present invention, no construction is provided as the test cell generating unit 200, and a test cell containing the same value as the virtual path identifier (VPI) written in the header of the test cell, in a predetermined area of the information field of the test cell, is supplied from the controller 400 of the ATM cross-connecting apparatus to the test cell inserting unit 101 of the receiving unit lia (i=l to n). The construction of the receiving unit lia is the same as the construction of Fig. 4. Figure 12 is a diagram indicating ~he test cell used in the third embodiment of the present invention. In Fig. 12, "VPI1"
denotes the virtual path identifier (VPI) in the header, and :VPI2" denotes the above area in which the same value as the virtual path identifier (VPI) in the header is initially written. The above test cell is input into the ATM cross-connecting apparatus in the same manner as the construction of Fig. 4. Then, the virtual path identifier (VPI~ in the header is re-written in the corresponding virtual path identifier (VPI) conversion unit 2i (i=1 to n) in accordance with the above-mentioned virtual path identifier (VPI) conversion table (not shown), and the test cell is switched in the switching unit 3 to one of the transmitting units ljb (j=1 to n) corresponding to a virtual path determined in accordance with the above-mentioned routing table (not shown). The routing table contains information on connections between input ports and output ports of the switching unit 3.
Figure 13 is a diagram indicating the construction provided for an output port connected with each input port of the ATM cross-connecting apparatus through the switching unit 3, in the test cell error detecting unit 300 according to the third embodiment of the present invention. In Fig. 13, reference numeral 51 denotes a virtual path identifier (VPI) extracting unit, 52 - 18 - FJ, NDD-9061-CA
denotes a path monitoring unit, and ljb denotes the same construction of the transmitting unit of Fig. 4~ The test cells are separated fro]m the other cells to be transmitted to the other node, in the test cell separating unit 104 in the same manner as the construction of Fig. 4. The separated test cells are supplied to the virtual path identifier (VPI) extracting unit 51. The virtual path identifier (VPI) e~tracting unit ~1 extracts the above value of the virtual path identifier (VPI) from the area VPI2 in the information field of the test cell. The extracted value of the virtual path identifier (VPI) indicates the virtual path identifier (VPI) before being converted in the virtual path identifier (VPI) conversion table 2i (i-1 to n) when no error occurs in the area VPI2. The extracted value of the virtual path identifier (VPI) before the conversion is supplied to the path monitoring unit 52 together with the virtual path identifier (VPI) in the header of the test cell. In the path monitoring unit 52, the information relating to the output port of the switching unit 3 to which the transmitting unit ljb is connected, is supplied from the controller, and is stored therein in advance. When receiving the above extracted value of the virtual path identifier (VPI) before the conversion, the path monitoring unit 52 determines whether or not the extracted value of the virtual path identifier (VPI) before the conversion corresponds to the virtual path identifier (VPI) in the header of the test cell, based on the above informa~ion relating to the output port of the s~itching unit 3 to which the transmitting unit ljb is connected. When these virtual path identifier (VPI) values do not correspond to each other, the path monitoring unit 52 outputs an error detect signal to the controller 400 of the AT~
cross-connecting apparatus.
The above virtual path identifier (VPI) values will not correspond to each other when the conversion of the - 19 - FJ, NDD-90~1-CA
virtual path identifier (VPI) in the virtual path identifier (VPI) conversion table 2i or the switching operation in the switching unit 3 is not carried out correctly. Thus, according to the above construction of the third embodiment of the present invention, the normality of the operation of converting the virtual path identifier (VPI) in the ATM cross-connecting apparatus, and the operation of the switching unit 3 can be monitored.
Similar to the first and second embodiments, since all of the constructions of Figs. 9 and 11 are realized by a small size hardware logic circuit, no heavy load is imposed on the controller 400 of the ATM cross-connecting apparatus. Namely, the controller 400 i5 required only to supply the initial virtual path identifier (VPI) of the test cell, and monitor the error detect signal output from the path monitoring unit 52 of Fig. 12.
Other Variations Although the above explanation is for the case wherein the test cell is generated and input into an ATM
cross-connecting apparatus in a node, and the test cell output from the ATM cross-connecting apparatus is e~- ined in the same node, it is possible to ~ ine the test cell in the next nodes to which the test cells are transmitted from the node in which the ATM cross-connecting apparatus to be monitored is located. In this case, the provisions according to the first and second embodiments of the present invention are, in particular, advantageous because no information is required to be transmitted to the next nodes for carrying out the operations of the constructions of Figs. 8 and 11 in the first and second embodiments, respectively. As explained before, in the conventional monitoring system, all data of the PN sequence must be transmitted to the next nodes for determining whether or not the test cell contains an - 20 - FJ, NDD-9061-CA
error .
Claims (3)
PROPERTY OR PRIVILEGE ITS CLAIMED ARE DEFINED AS FOLLOWS:
1. A monitoring system for an ATM cross-connecting apparatus, for re-writing a VPI of an input cell and outputting the input cell from an output port corresponding to the re-written VPI, comprising:
a setting portion for setting an initial value of a PN pattern and the PN pattern based on the initial value, in an information field in an inside-apparatus monitoring cell which is input into said ATM
cross-connecting apparatus; and a detecting portion for detecting an error in the cell by extracting the cell output from said ATM
cross-connecting apparatus and comparing the PN pattern in the cell with a PN pattern based on the initial value.
a setting portion for setting an initial value of a PN pattern and the PN pattern based on the initial value, in an information field in an inside-apparatus monitoring cell which is input into said ATM
cross-connecting apparatus; and a detecting portion for detecting an error in the cell by extracting the cell output from said ATM
cross-connecting apparatus and comparing the PN pattern in the cell with a PN pattern based on the initial value.
2. A monitoring system for an ATM cross-connecting apparatus, for re-writing a VPI of an input cell and outputting the input cell from an output port corresponding to the re-written VPI, comprising:
a setting portion for setting a bit pattern as a basis of a primitive polynomial, an initial value of a PN pattern, and the PN pattern based on the initial value, in an information field in an inside-apparatus monitoring cell which is input into said ATM
cross-connecting apparatus; and a detecting portion for detecting an error in the cell by extracting the cell output from said ATM
cross-connecting apparatus and comparing the PN pattern in the cell with a PN pattern based on the initial value and the bit pattern.
a setting portion for setting a bit pattern as a basis of a primitive polynomial, an initial value of a PN pattern, and the PN pattern based on the initial value, in an information field in an inside-apparatus monitoring cell which is input into said ATM
cross-connecting apparatus; and a detecting portion for detecting an error in the cell by extracting the cell output from said ATM
cross-connecting apparatus and comparing the PN pattern in the cell with a PN pattern based on the initial value and the bit pattern.
3. A monitoring system for an ATM cross-connecting apparatus, for re-writing a VPI of an input cell and outputting the input cell from an output port corresponding to the re-written VPI, comprising:
a setting portion for setting the same value as the VPI in a header portion of the cell, in an information field in an inside-apparatus monitoring cell which is input into said ATM cross-connecting apparatus;
and a detecting portion for detecting an error in the cell by extracting the cell output from said ATM
cross-connecting apparatus and comparing a VPI in the header portion with the VPI in the information field.
a setting portion for setting the same value as the VPI in a header portion of the cell, in an information field in an inside-apparatus monitoring cell which is input into said ATM cross-connecting apparatus;
and a detecting portion for detecting an error in the cell by extracting the cell output from said ATM
cross-connecting apparatus and comparing a VPI in the header portion with the VPI in the information field.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12863391A JP2892180B2 (en) | 1991-04-30 | 1991-04-30 | Monitoring system for ATM cross-connect equipment |
| JP03-128633 | 1991-04-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2067596A1 CA2067596A1 (en) | 1992-10-31 |
| CA2067596C true CA2067596C (en) | 1997-12-30 |
Family
ID=14989643
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2067596 Expired - Fee Related CA2067596C (en) | 1991-04-30 | 1992-04-29 | System for monitorimg atm cross-connecting apparatus by inside-apparatus monitoring cell |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5257311A (en) |
| EP (2) | EP0730359A3 (en) |
| JP (1) | JP2892180B2 (en) |
| CA (1) | CA2067596C (en) |
Families Citing this family (44)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3025068B2 (en) * | 1991-09-12 | 2000-03-27 | 富士通株式会社 | ATM switch path test method |
| JPH0583291A (en) * | 1991-09-19 | 1993-04-02 | Fujitsu Ltd | Atm test system |
| JP3262142B2 (en) * | 1992-01-16 | 2002-03-04 | 富士通株式会社 | ATM cell forming apparatus, ATM cell forming method, node, and multiplexing method in node |
| JPH05252184A (en) * | 1992-03-06 | 1993-09-28 | Hitachi Ltd | Virtual pass connection device and virtual pass tracing method |
| JP2766119B2 (en) * | 1992-04-20 | 1998-06-18 | 日本電気株式会社 | Space switch circuit |
| CA2097350C (en) * | 1992-08-17 | 1998-12-22 | Shahrukh S. Merchant | Asynchronous transfer mode (atm) transmission test cell generator |
| SE470544B (en) * | 1992-11-24 | 1994-07-25 | Ellemtel Utvecklings Ab | For a bit error monitoring in a device intended for selection |
| US5602826A (en) * | 1993-01-19 | 1997-02-11 | Fujitsu Limited | Test system in an ATM system |
| GB9301575D0 (en) * | 1993-01-27 | 1993-03-17 | Plessey Telecomm | Switch protection arrangement |
| KR950013847B1 (en) * | 1993-03-18 | 1995-11-16 | 한국전기통신공사 | Descrambler of the cell based parallel atm physical layer |
| JP2999342B2 (en) * | 1993-03-19 | 2000-01-17 | 富士通株式会社 | Path route test method in ATM transmission system |
| EP0619661A1 (en) * | 1993-04-08 | 1994-10-12 | Alcatel STR AG | Testing under load of an ATM switch |
| DE4317951C1 (en) * | 1993-05-28 | 1994-05-26 | Siemens Ag | Transmitting data packets in async. transfer mode - equalising propagation delays between transmission and reception of test packets over separate paths |
| FR2707819B1 (en) * | 1993-07-12 | 1995-09-15 | Tremel Jean Yves | Method and device for monitoring and / or testing an ATM type telecommunications network. |
| JPH07162435A (en) * | 1993-12-06 | 1995-06-23 | Fujitsu Ltd | Method and device for confirming semi-fixed path |
| JPH0823331A (en) * | 1994-07-07 | 1996-01-23 | Murata Mach Ltd | Method and device for ciphering communication |
| JPH0837527A (en) * | 1994-07-25 | 1996-02-06 | Fujitsu Ltd | Centralized testing device for atm exchange |
| US5717858A (en) * | 1994-10-17 | 1998-02-10 | Motorola, Inc. | Method and structure for prioritizing performance monitoring cells in an asynchronous transfer mode (ATM) system |
| JPH11510004A (en) * | 1995-07-19 | 1999-08-31 | フジツウ ネットワーク コミュニケーションズ，インコーポレイテッド | Point-to-multipoint transmission using subqueues |
| JP3171773B2 (en) * | 1995-08-31 | 2001-06-04 | 富士通株式会社 | Connection control method and apparatus in exchange |
| WO1997010656A1 (en) * | 1995-09-14 | 1997-03-20 | Fujitsu Network Communications, Inc. | Transmitter controlled flow control for buffer allocation in wide area atm networks |
| US5764626A (en) * | 1995-11-17 | 1998-06-09 | Telecommunications Techniques Corporation | Rate-matched cell identification and modification, replacement, or insertion for test and measurement of ATM network virtual connections |
| CA2237986C (en) * | 1995-11-17 | 2004-04-20 | Telecommunications Techniques Corporation | Instrument for test and measurement of atm network virtual connections |
| FR2742616B1 (en) * | 1995-12-18 | 1998-01-09 | Cit Alcatel | ENCRYPTION DEVICE AND ENCRYPTION DEVICE OF INFORMATION TRANSPORTED BY CELLS WITH ASYNCHRONOUS TRANSFER MODE |
| AU1697697A (en) * | 1996-01-16 | 1997-08-11 | Fujitsu Limited | A reliable and flexible multicast mechanism for atm networks |
| JPH09214511A (en) * | 1996-02-05 | 1997-08-15 | Nec Corp | System for self-monitoring fault in cell processor |
| US5822304A (en) * | 1996-03-22 | 1998-10-13 | Hewlett-Packard Company | Scanning for active ATM virtual channel/virtual path identifiers |
| US5748905A (en) * | 1996-08-30 | 1998-05-05 | Fujitsu Network Communications, Inc. | Frame classification using classification keys |
| US5825751A (en) * | 1996-09-10 | 1998-10-20 | Ncr Corporation | Method and apparatus for tracing frames transmitted through a network path |
| US5960088A (en) * | 1996-10-15 | 1999-09-28 | Fore Systems, Inc. | Method and apparatus for secure transmission of ATM cells |
| CA2307766C (en) * | 1997-11-07 | 2002-05-21 | Visual Networks Technologies, Inc. | Method and apparatus for performing service level analysis of communications network performance metrics |
| IT1297362B1 (en) * | 1997-12-31 | 1999-09-01 | Cit Alcatel | SYSTEM FOR DETECTION AND / OR MEASUREMENT OF THE DURATION OF MIXING IN TELECOMMUNICATIONS NETWORKS |
| EP0961437A1 (en) | 1998-05-29 | 1999-12-01 | Alcatel | Method for bit error rate measurements in a cell-based telecommunication system |
| US6411614B1 (en) * | 1998-10-30 | 2002-06-25 | National Semiconductor Corporation | Dynamic recovery of a TDMA signal during an undetected marker sequence |
| US7054273B1 (en) * | 1999-08-06 | 2006-05-30 | Tellabs Operations, Inc. | Circuit integrity in a packet-switched network |
| FR2808150B1 (en) * | 2000-04-19 | 2002-11-29 | France Telecom | METHOD FOR TESTING A SWITCHING SYSTEM, AND INSERTION DEVICE FOR USE IN THIS METHOD |
| GB2368504B (en) | 2000-07-13 | 2002-10-09 | Advantest Corp | Bit error measurement apparatus and method, and recording medium |
| US6914878B1 (en) * | 2000-10-16 | 2005-07-05 | Telefonaktiebolaget Lm Ericsson (Publ) | Fault detection in multi-plane switch |
| JP2002247001A (en) * | 2001-02-21 | 2002-08-30 | Ando Electric Co Ltd | Pseudo random pattern transmitter |
| US7184408B2 (en) * | 2001-07-31 | 2007-02-27 | Denton I Claude | Method and apparatus for programmable generation of traffic streams |
| JP4229810B2 (en) * | 2003-11-10 | 2009-02-25 | 富士通株式会社 | Communication test equipment |
| US7751421B2 (en) * | 2004-12-29 | 2010-07-06 | Alcatel Lucent | Traffic generator and monitor |
| CN1996898B (en) * | 2005-12-28 | 2010-04-14 | 中兴通讯股份有限公司 | A system and method for real time detection of the data channel states |
| DE102006031230B4 (en) * | 2006-07-06 | 2021-07-15 | Bayerische Motoren Werke Aktiengesellschaft | Method of transferring data |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5941939A (en) * | 1982-07-28 | 1984-03-08 | コミユニケ−シヨンズ・サテライト・コ−ポレ−シヨン | Communication system |
| US5012466A (en) * | 1987-10-13 | 1991-04-30 | At&T Bell Laboratories | Call service initialization arrangement |
| JP2551143B2 (en) * | 1989-04-14 | 1996-11-06 | 日本電気株式会社 | ATM switch communication path failure detection system |
| DE3912660C1 (en) * | 1989-04-18 | 1990-08-30 | Wandel & Goltermann Gmbh & Co, 7412 Eningen, De | |
| JP2964151B2 (en) * | 1989-07-03 | 1999-10-18 | 富士通株式会社 | Communication control method |
| JP2892689B2 (en) * | 1989-07-05 | 1999-05-17 | 株式会社日立製作所 | Packet communication network and packet switch |
| GB8921082D0 (en) * | 1989-09-18 | 1989-11-01 | Plessey Telecomm | Message routing check system |
| JPH03104451A (en) * | 1989-09-19 | 1991-05-01 | Fujitsu Ltd | Route changeover system for multi-stage link exchange system |
| JPH03135133A (en) * | 1989-10-20 | 1991-06-10 | Toshiba Corp | Multi-medium integration network system |
| EP0462349B1 (en) * | 1990-06-21 | 1995-02-22 | International Business Machines Corporation | Broadband ring communication system and access control method |
-
1991
- 1991-04-30 JP JP12863391A patent/JP2892180B2/en not_active Expired - Fee Related
-
1992
- 1992-04-29 CA CA 2067596 patent/CA2067596C/en not_active Expired - Fee Related
- 1992-04-30 EP EP19960104056 patent/EP0730359A3/en not_active Withdrawn
- 1992-04-30 US US07/876,417 patent/US5257311A/en not_active Expired - Lifetime
- 1992-04-30 EP EP19920107403 patent/EP0511671A3/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| EP0730359A3 (en) | 1998-04-01 |
| JPH05347632A (en) | 1993-12-27 |
| EP0511671A3 (en) | 1993-02-03 |
| EP0730359A2 (en) | 1996-09-04 |
| CA2067596A1 (en) | 1992-10-31 |
| US5257311A (en) | 1993-10-26 |
| JP2892180B2 (en) | 1999-05-17 |
| EP0511671A2 (en) | 1992-11-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA2067596C (en) | System for monitorimg atm cross-connecting apparatus by inside-apparatus monitoring cell | |
| CA2131080C (en) | Path changing system and method for use in atm communication apparatus | |
| US5265088A (en) | Cross-connection apparatus for B-ISDN | |
| JP3332474B2 (en) | ATM communication device and failure detection notification device | |
| US5303233A (en) | Arrangement favorably carrying out a connection by the use of an intermediate conversion parameter between input and output virtual channel identifiers (VCI's) | |
| JPH08242240A (en) | Atm exchange and method for switching path | |
| JPH04127743A (en) | Transmission line testing system for wide band isdn | |
| EP0523386B1 (en) | System for monitoring normality of operation of ATM cross-connecting apparatus | |
| JPH04248729A (en) | Atm exchange | |
| US5537428A (en) | Arrangement for bit error monitoring in switching equipment | |
| US6466576B2 (en) | ATM switching unit | |
| SE515274C2 (en) | Package selector for telecommunication system | |
| US6477141B1 (en) | Communication path quality monitoring method and quality monitoring apparatus | |
| EP0494772B1 (en) | Cell switch and network with simplified testing | |
| US6529473B1 (en) | Device for ATM cell switching, with failure tolerance | |
| KR20010041157A (en) | Protection switching of virtual connections | |
| JPH1127282A (en) | On-line circuit monitoring system | |
| JP2824483B2 (en) | Switch diagnostic method in ATM exchange | |
| JP3168945B2 (en) | ATM transmission line switching system | |
| JP3074570B2 (en) | ATM switch path test method | |
| US6526053B1 (en) | Method and apparatus for transmitting packets and network using the same | |
| JP2738344B2 (en) | ATM cell loopback method | |
| JPH07202897A (en) | In-equipment information notice method and alternate method for fault vp or vc | |
| KR0132939B1 (en) | Method and apparatus for checking oam cell of virtual | |
| KR100255800B1 (en) | Cell path testing method of atm exchange |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed | ||
| MKLA | Lapsed |
Effective date: 20100429 |