CA2068010A1 - Alternate master bursting data rate management techniques for use in computer systems having dual bus architecture - Google Patents

Alternate master bursting data rate management techniques for use in computer systems having dual bus architecture

Info

Publication number
CA2068010A1
CA2068010A1 CA2068010A CA2068010A CA2068010A1 CA 2068010 A1 CA2068010 A1 CA 2068010A1 CA 2068010 A CA2068010 A CA 2068010A CA 2068010 A CA2068010 A CA 2068010A CA 2068010 A1 CA2068010 A1 CA 2068010A1
Authority
CA
Canada
Prior art keywords
bus
processor
card
alternate
local
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2068010A
Other languages
French (fr)
Other versions
CA2068010C (en
Inventor
Robert Chih-Tsin Eng
John Walter Galella
Rex Eldon Mccrary
Mark Gehres Mcdonald
Eric Henry Stelzer
Frederick Charles Yentz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CA2068010A1 publication Critical patent/CA2068010A1/en
Application granted granted Critical
Publication of CA2068010C publication Critical patent/CA2068010C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/285—Halt processor DMA
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Computer And Data Communications (AREA)
  • Hardware Redundancy (AREA)

Abstract

Methods and apparatus are set forth which optimize and balance the use of processor card (or complex) resources (e. g., memory, the local bus, etc .), with the use of other system resources, such as the card to card communications bus and devices attached thereto, in dual bus computing systems. A new data rate management technique reduces data transfer overhead particularly for burst mode transfers.
The invention promptly services pending memory refresh requests; limits multiple accesses to on card (or processor complex) memory by an Alternate Bus Master to a predetermined number of cycles where the processor requests the use of its local bus; and allows an Alternate Bus Master unlimited accesses to the processor local bus when the Alternate Bus Master owns the card to card communications bus and the processor subsequently requests that bus. The aforementioned balance of resources is achieved using a Bus Hold On Grant ("BSHOG") scheduling procedure which, assuming a bursting Alternate Bus Master has gained control of the local processor bus and is conducting data transfer cycles when the processor requests the local bus, allows the Alternate Bus Master to conditionally retain local bus ownership over a plurality of Alternate Bus Master data transfer cycles.
CA002068010A 1991-08-30 1992-05-05 Alternate master bursting data rate management techniques for use in computer systems having dual bus architecture Expired - Fee Related CA2068010C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US75272591A 1991-08-30 1991-08-30
US752,725 1991-08-30

Publications (2)

Publication Number Publication Date
CA2068010A1 true CA2068010A1 (en) 1993-03-01
CA2068010C CA2068010C (en) 1996-10-22

Family

ID=25027548

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002068010A Expired - Fee Related CA2068010C (en) 1991-08-30 1992-05-05 Alternate master bursting data rate management techniques for use in computer systems having dual bus architecture

Country Status (5)

Country Link
US (1) US5469577A (en)
EP (1) EP0535793B1 (en)
JP (1) JP2532191B2 (en)
CA (1) CA2068010C (en)
DE (1) DE69219848T2 (en)

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DE59408326D1 (en) * 1993-04-20 1999-07-08 Siemens Ag Processor circuit with memory refresh
JP3490131B2 (en) * 1994-01-21 2004-01-26 株式会社ルネサステクノロジ Data transfer control method, data processor and data processing system
US5721882A (en) * 1994-08-05 1998-02-24 Intel Corporation Method and apparatus for interfacing memory devices operating at different speeds to a computer system bus
US5644788A (en) * 1994-10-28 1997-07-01 Cyrix Corporation Burst transfers using an ascending or descending only burst ordering
US5761483A (en) * 1995-08-18 1998-06-02 Xilinx, Inc. Optimizing and operating a time multiplexed programmable logic device
US5838954A (en) * 1995-08-18 1998-11-17 Xilinx, Inc. Computer-implemented method of optimizing a time multiplexed programmable logic device
US5784313A (en) * 1995-08-18 1998-07-21 Xilinx, Inc. Programmable logic device including configuration data or user data memory slices
US5701441A (en) * 1995-08-18 1997-12-23 Xilinx, Inc. Computer-implemented method of optimizing a design in a time multiplexed programmable logic device
US6243768B1 (en) * 1996-02-09 2001-06-05 Intel Corporation Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus
US5867675A (en) * 1996-08-06 1999-02-02 Compaq Computer Corp Apparatus and method for combining data streams with programmable wait states
US5907689A (en) * 1996-12-31 1999-05-25 Compaq Computer Corporation Master-target based arbitration priority
US6421817B1 (en) 1997-05-29 2002-07-16 Xilinx, Inc. System and method of computation in a programmable logic device using virtual instructions
US6047115A (en) * 1997-05-29 2000-04-04 Xilinx, Inc. Method for configuring FPGA memory planes for virtual hardware computation
US5996037A (en) * 1997-06-03 1999-11-30 Lsi Logic Corporation System and method for arbitrating multi-function access to a system bus
US6055609A (en) * 1997-06-19 2000-04-25 Chips & Technologies, Inc. Apparatus and method for improving bus usage in a system having a shared memory
US6430641B1 (en) * 1999-05-04 2002-08-06 International Business Machines Corporation Methods, arbiters, and computer program products that can improve the performance of a pipelined dual bus data processing system
US6636929B1 (en) 2000-04-06 2003-10-21 Hewlett-Packard Development Company, L.P. USB virtual devices
US6725312B1 (en) 2000-11-02 2004-04-20 Cml Versatel Inc. Bus architecture for high reliability communications in computer system
US8478921B2 (en) 2004-03-31 2013-07-02 Silicon Laboratories, Inc. Communication apparatus implementing time domain isolation with restricted bus access
CN102207919A (en) * 2010-03-30 2011-10-05 国际商业机器公司 Processing unit, chip, calculation equipment and method for expedited data transmission

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4257095A (en) * 1978-06-30 1981-03-17 Intel Corporation System bus arbitration, circuitry and methodology
GB2120429B (en) * 1982-04-29 1985-10-09 Honeywell Inf Systems Computer system with bus cycle sharing
US4570220A (en) * 1983-11-25 1986-02-11 Intel Corporation High speed parallel bus and data transfer method
US4837682A (en) * 1987-04-07 1989-06-06 Glen Culler & Associates Bus arbitration system and method
US5129090A (en) * 1988-05-26 1992-07-07 Ibm Corporation System bus preempt for 80386 when running in an 80386/82385 microcomputer system with arbitration
US4961140A (en) * 1988-06-29 1990-10-02 International Business Machines Corporation Apparatus and method for extending a parallel synchronous data and message bus
US5099420A (en) * 1989-01-10 1992-03-24 Bull Hn Information Systems Inc. Method and apparatus for limiting the utilization of an asynchronous bus with distributed controlled access
US5168568A (en) * 1989-02-06 1992-12-01 Compaq Computer Corporation Delaying arbitration of bus access in digital computers
US5127089A (en) * 1989-07-03 1992-06-30 Motorola, Inc. Synchronous bus lock mechanism permitting bus arbiter to change bus master during a plurality of successive locked operand transfer sequences after completion of current sequence
CA2021826A1 (en) * 1989-10-23 1991-04-24 Darryl Edmond Judice Delay logic for preventing cpu lockout from bus ownership
KR940002905B1 (en) * 1989-12-15 1994-04-07 Ibm Apparatus for conditioning priority arbitration in buffered direct memory addressing
US5253348A (en) * 1990-12-28 1993-10-12 Apple Computer, Inc. Method of arbitration for buses operating at different speeds

Also Published As

Publication number Publication date
DE69219848T2 (en) 1997-10-23
JP2532191B2 (en) 1996-09-11
EP0535793A3 (en) 1993-07-14
EP0535793B1 (en) 1997-05-21
CA2068010C (en) 1996-10-22
DE69219848D1 (en) 1997-06-26
US5469577A (en) 1995-11-21
EP0535793A2 (en) 1993-04-07
JPH06161950A (en) 1994-06-10

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