CA2076893C - Low noise fine frequency step synthesizer - Google Patents
Low noise fine frequency step synthesizerInfo
- Publication number
- CA2076893C CA2076893C CA002076893A CA2076893A CA2076893C CA 2076893 C CA2076893 C CA 2076893C CA 002076893 A CA002076893 A CA 002076893A CA 2076893 A CA2076893 A CA 2076893A CA 2076893 C CA2076893 C CA 2076893C
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- Canada
- Prior art keywords
- signal
- frequency
- frequency signal
- synthesized
- divided
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/185—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using a mixer in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
- H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
Abstract
A frequency synthesizer (10) and method the achieves low phase noise and provides synthesized frequency signals in fine frequency step intervals. The synthesizer (10) comprises an L-band low phase noise frequency synthesizer with fine frequency step increments. The synthesizer (10) employs half-interger digital frequency dividing (25), VCO frequency offsetting, local oscillator harmonic mixing (34) and two phase locked loop circuits (12, 13). The synthesizer (10) comprises a reference oscillator (11) for providing a reference frequency signal, and two phase locked loops (12, 13).
The first loop (12) is the fine loop and generates the frequency step size. The second loop (13) reduces the phase noise, reduces the frequency step size and translates to the desired frequency. The output from a first VCO (21) is divided by a predetermined fixed number (31) to reduce the frequency step size and to reduce the phase noise. The second loop (13) has a second VCO (32) whose output, at L-band, for example, is divided by two (33), and then mixed (34) with the third harmonic of the reference frequency signal to generate an offset frequency signal that is locked to the low phase noise fine frequency step signal of the first loop (12). The output frequency is adjusted by changing the digital programmable half-integer frequency divider (25). The low phase noise and fine frequency step frequency synthesizer (10) provides a major improvement for Doppler radar and communication receivers.
The first loop (12) is the fine loop and generates the frequency step size. The second loop (13) reduces the phase noise, reduces the frequency step size and translates to the desired frequency. The output from a first VCO (21) is divided by a predetermined fixed number (31) to reduce the frequency step size and to reduce the phase noise. The second loop (13) has a second VCO (32) whose output, at L-band, for example, is divided by two (33), and then mixed (34) with the third harmonic of the reference frequency signal to generate an offset frequency signal that is locked to the low phase noise fine frequency step signal of the first loop (12). The output frequency is adjusted by changing the digital programmable half-integer frequency divider (25). The low phase noise and fine frequency step frequency synthesizer (10) provides a major improvement for Doppler radar and communication receivers.
Description
2076~3 LOW NOISE FINE FREQUENCY STEP SYNTHESIZER
BACKGROUND
The present invention relatës generally to frequency synthesi7Prs, and more particularly, to a low noise, fine frequency step synthesi7er.
In prior art systems, the phase locked synthesi7e~ frequency provided by a frequency synthesizer either has many fine steps with high phase noise or has low S phase noise with very limited tuning step size. No conventional technology provides both low phase noise and syntheci7Yl frequencies having many fine steps at the same time. More specifically, the patents listed below disclose conventional synthesi7~rs that cannot provide both low phase noise and syntheci7~A frequencies having many finesteps at the same time.
The prior art patents referred to above are identifi~A as follows: U.S. Patent No.
4,940,950 entitled "Frequency Synthesis Method and Apparatus Using Approxi~lnation to Provide Closely Spaced Discrete r~ uencies Over a Wide Range with Rapid Acqui-sition," issued to Helfrick, U.S. Patent No. 4,965,533 entitled "Direct Digital Synthe-sizer Driven Phase Lock Loop Frequency Syntheci7er," issued to Gilmore, U.S. Patent No. 4,912,433 entided "VCO Cont.~lled by Separate Phase Locked Loop," issued to Motegi et al., U.S. Patent No. 4,234,929 entided "Control Device for a Phase Lock Loop Vernier Frequency Synthesi7er~ issued to Riley, Jr.,U.S. Patent No. 4,388,597 entided "Frequency Syntheci7er Having Plural Phase Locked Loops," issued to Bickley et al., and U.S. Patent No. 4,912,432 entitled "Plural Fee~bac'r Loop Digital Frequen-20 cy Syntheci7.or," issued to Galani et al. Of these references, the Bickley et al. and 237~3 Galani et al. patents disclose plural phase locked loop syn~hPsi7~rs, and are conciA~red pertinent to the present invention.
The Bickley et al. patent employs three phase locked loops to achieve synthesis The synthe--ci7~r includes a first phase locked loop compricing a mixer and a phase S Aetectt~r. A second phase locked loop having a programmable divider supplies a refer-ence frequency in pre~letf . ., li n~A steps to the mixer, while a third phase locked loop provides a reference frequency in preAetçrmin~o.A steps to the phase detector, which steps are different from the steps provided by the second phase locked loop. Also, in a preferred emboAim.-nt a fourth phase locked loop provides a reference signal to a 10 mixer in the third phase locked loop to reduce the o~ld~ing frequency therein and the output of the fourth phase locked loop is mixed with an output from the first phase locked loop to extend the range of the synthesi_er.
The Galani et al. patent discloses an indirect digital frequency syn~heci7~or adapted to produce a signal having a selPcteA one of a plurality of relatively closely 15 spaced frequenri~s and having a relatively fast frequency s~viLclfillg time. Multiple fee lh~ loops are fed by reference frequency signals whose frequency is greater than the desired frequency separation provided by the syntheci7~r. The bandwidth of each of the feeAharlf loops is less than the frequency of the reference frequency fed to each loop, and achievement of frequency separation less than the frequency of either of the 20 reference frequencies enables each of the feedback loops to have increased bandwidth and therefore reduced frequency switching times and increased noise ~u~lcssion.
SUMMARY OF THE INVENTION
In order to provide for a frequency syntheci7~r and a method of providing 25 synthesi7çd output frequency signals that achieves low phase noise and provides for synthesi_ed frequencies having many fine steps, the present invention comprises a low phase noise frequency synth~ci7~.r with fine frequency step tuning. The structure of the synshçci7~r is unique, and provides for half-integer digital frequency dividing, VCO
frequency offsetting, and local osçill~t~r harmonic mixing using two phase locked loop 30 circuits. The first loop genelates the required frequency steps, while in the second loop the signal is then divided by a pre~let~ d fixed number to reduce both the frequency step si_e and to reduce the phase noise. The second loop output, at L-band, for exam-ple, is divided by two, and then mixed with the third h~rrnonic of the lc;çelellce frequen-cy to ~ te an offset frequency that is locked to the low phase noise frequency of the 35 first loop. The low phase noise and fine step tuning provided by the present frequency synthesi_erprovidesamajorimprovementforDopplerradarandco.. ~ica*on receivers.
More specifically, the present invention is a frequency synthesi7~r that compris-es a l~fel~nce frequency oscillator for providing a reference frequency signal. A first phase locked loop is coupled to the reference frequency oscillator for generating a first synthesized signal at a selectable one of a plurality of desired fTequencies, each of the S frequencies differing from an adjacent frequency by a substantially uniforrn frequency step size. A second phase locked loop is coupled to the reference frequency oscillator and to the first phase locked loop for generating an output signal from the synthesi~r.
The second phase locked loop comprises a second oscillator for geneld~i lg a second synthçsi7~ signal at a selectable one of a second plurality of desired frequencies. A
first divider is coupled to the second oscillator for dividing the second synthesized signal by a first predetPmlined fLlced number to produce a divided second synthesized signal. A mixer is coupled to the reference frequency oscillator and to the first divider for mixing the divided second syntheci7~d signal with a preclçtç~min~d harmonic of the reference frequency signal to produce an offset frequency signal. A second divider is coupled to the first phase locked loop for dividing the first synth~si7~A signal by a second predetermined fixed~number to produce a divided second syntheci7~ signal having a reduced frequency step si~ and reduced phase noise. A phase detector iscoupled to the second divider and the mixer for locking the offset frequency signal to the divided second syntheci7ecl signal.
One method in accordance with the present invention that provides synthesized output frequency signals comprices the following steps. (1) Providing a reference fre-quency signal. (2) Generating a first synthçsi7~d signal at a selectable one of a plurality of desired frequencies, each of the frequencies differing from an adjacent frequency by a substantially uniform frequency step size. (3) Generating a second synthesi7e~1 signal at a selectable one of a second plurality of desired frequensies, which second synthe-sized signal comprises a synthesized output frequency signal. (4) Dividing the second synthesi7ed signal by a first predeterrnined fixed number to produce a divided second synthesized signal. (5) Mixing the divided second synthesi7ed signal with a predeter-mined ha~ ollic of the l~;fe,ence frequency signal to produce an offset ~equency sig-nal. (6) Dividing the first synthçsi7el1 signal by a second predetermined fixed nurnber to produce a divided second syntheci7e~ signal having a reduced frequency step size and reduced phase noise. (7) Phase locking the offset frequency signal to the divided second synthesized signal to provide the syn~hçci7ç~ output frequency signal.
. .
~, ~ 7 3a Other aspects of this invention are as follows:
A frequency synthesizer comprising:
a reference frequency oscillator for providing a reference frequency signal;
a first phase locked loop adapted to generate a synthesized signal at a selectable one of a plurality of desired frequencies, each of the frequencies differing from an adjacent frequency by a substantially uniform *equency step size, said first phase locked loop comprising a first voltage controlled oscillator for providing a relative!y low phase noise signal, a first mixer adapted to mix said reference frequency signal and said low phase noise signal, a first fixed frequency divider for dividing said reference frequency signal by a first predetermined number to provide a divided reference frequency signal, a digital programmable half-integer frequency divider coupled to said first mixer for providing a first offset frequency signal, a first phase detector for comparing the phase of said first offset frequency signal and the phase of said divided reference frequency signal to provide a first control signal that is adapted to lock said first voltage controlled oscillator; and 2 o a second phase locked loop comprising a second voltage controlled oscillator, a second divider for dividing the output of said second voltage controlled oscillator by a second predetermined number to provide a divided signal, a second mixer adapted t¢ mix a predetermined harmonic of said reference frequency signal with said divided signal to produce a second 2 5 offset frequency signal, a third divider coupled to said first voltage controlled oscillator for dividing said low noise signal by a third predetermined number to provide a divided second reference frequency signal, a second phase detector for comparing the phases of said second offset frequency signal and said divided second reference frequency signal to 3 o provide a second control signal that is adapted to lock said second voltage controlled oscillator.
A
~ ~ 7 ~
3b A metnod of providing a plurality of synthesized frequency signals comprising the steps of:
providing a reference frequency signal, generating a first synthesized signal at a selectable one of a plurality of desired frequencies, each of the frequencies differing from an adjacent frequency by a substantially uniform frequency step size;
generating a second synthesized signal at a selectable one of a second plurality of desired frequencies, which said second synthesized signal 0 comprises a synthesized output frequency signal;
dividing said second synthesized signal by a first predetermined fixed number to produced a divided second synthesized signal;
mixing said divided second synthesized signal with a predetermined harmonic of said reference frequency signal to produce an offset frequency signal;
dividing said first synthesized signal by a second predetermined fixed number to produce a divided second reference frequency signal having a reduced frequency step size and reduced phase noise; and phase locking said offset frequency signal to said divided second 2 o reference frequency signal by comparing the phases of said offset frequency signal and said divided second reference frequency signal and providing a control signal that locks the output frequency of said second synthesized signal to provide said synthesized output frequency signal.
BRIEF DESCRIPTION OF THE DRAWINGS
2 5 The various features and advantages of the present invention may be more readily understood with reference to the following detailed description taken in conjunction , ~
with the accompanying drawings, wherein like reference numerals designate like struc-tural elements, and in which the sole figure illustrates a low noise fine frequency step synthesi7Pr in accordance with the principles of the present invention.
DETAILED DESCRIPTION
The sole figure of the drawing is a schematic diagram in block forrn that illus-trates a preferred embodiment of a low noise fine frequency step synthesizer 10 in accordance with the principles of the present invention. The methods of the present invention will also be readily understood with reference to the drawing figure. The syn~hesi7er 10 is comprised of a low phase noise VHF reference oscillator 11 that provides a primary reference frequency signal 51, and first and second phase locked loops 12, 13 coupled to the reference oscillator 11 that are adapted to provide low phase noise and achieve fine step synthesized L-band frequencies.
The characteristics of the VHF reference oscillator 11 are important because thephase noise of the output signal from the synthesi_er 10 is dependent on and derived from it. The output frequency provided by the VHF reference oscillator 11 requires good short term frequency stability with very low AM and phase noises. The VHF
reference oscill~tor 11 is typically a co.~ ,ially available circuit using either a very high ~factor overtone crystal or using a surface acoustic wave (SAW) resonator. The ~/HF reference oscillator 11 employs the least amount of frequency mulhplication pos-sible to avoid introducing multiplication noise into the primary reference frequency signal 51.
The first phase locked loop 12 is the fine or VHF step tuning loop 12, and is shown at the left side of the drawing figure. The first phase locked loop 12 is adapted to generate a synthesi7ed signal 52 having fine frequency steps. It is comprised of a VHF voltage controlled oscillator (VCO) 21 having its output connected to one input of a mixer 22, an RF low pass filter 23 connected to the output of the mixer 22, and an RF arnplifier 24 connected from the low pass filter 23 to a half-integer digital prograrn-mable frequency divider 25. The details of the half-integer divider 25 are more fully discussed in U.S. Patent No. 4,975,931 issued December 4, 1990 to Albert E.
Cosand, and assigned to the assignee of the present invention. The first phase locked loop 12 is coupled to the output of the VHF reference oscillator 11 by first and second couplers 14, 15. The first coupler 14 couples the primary reference frequency signal 51 to a fixed &equency divider 27. The second coupler 15 couples the primary reference frequency signal 51 to the mixer 22. The output of the fixed frequency divider 27 is connected to one input of a phase detector 26. The output of the half-integer digital 2~7~93 s prog.~ ble frequency divider 25 is coupled to the other input of the phase ~lptecl~r 26. The output of the phase ~letector 26 is coupled by way of a video loop filter 28 to the control input of the VHF VCO 21. The video loop filter 28 co...l.. ;ses an opera-tional ~mplifi~ 29 having a resistor 29A in series with a car~ci~r 29B connect~l from 5 input to output. The output of the first phase locked loop 12 is coupled into the second phase locked loop 13 by a third coupler 16.
To get the lowest phase noise in the first phase locked loop 12, the frequency of the VHF VCO 21 is not directly divided down and locked to the step l~;rt;l~nce frequen-cy, but is offset by the primary reference frequency from the VHF reference oscillator 10 11. The digital pro~ll.lJable frequency divider 25 divides the offset frequency by half-integer steps to avoid increased dividing phase noise. By implemPn~ing these two processing steps, the rate of phase noise increase is reduced to a ..~i.~;..,ll... The offset frequency signal S1 is produced at the output of the mixer 22. The mixer 22 not only creates the offset frequency signal S 1, but also generates unwanted spurious high fre-15 quency signals as well. Therefore, the RF low pass filter 23 is n~ces~ry to suppressthese spurious high frequency signals.
After the RF low pass filter 23 cleans up the offset frequency signal 53, it is ~mplifie~l by the amplifier 24 to a high enough level to drive the half-integer digital pro-g-~.,u~able fiequency divider 25, also called a divide-by-N frequency divider 25. The 20 divide-by-N frequency divider 25 divides the offset frequency signal 53 by a predeter-mined count. Then the phase of the output signal 59 of the divide-by-N frequencydivider 25 is co~ ,d with the phase of a fine step reference frequency signal 58provided by the reference osçill~tnr 11 after being divided by the fixed frequency divider 27, also called a divide-by-M fixed frequency divider 27. Then the output volt-25 age of phase detector 26 is passed through the video loop filter 28 and the operationalamplifier 29 to adjust and control the frequency, phase, and phase noise of the VHF
VCO 21 after the loop is closed.
The operation of the first phase locked loop 12 will be illustrated with a specific example. The VHF reference oSc~ tor 11 may provide a primary reference frequency30 of 250 MHz, for example. The ~lilll~ y reference frequency signal S 1 is coupled through the first coupler 14 to the fixed frequency divider 27 which may divide by 250, for example. This provides a frequency of 1 ~Iz to one input of the phase ~ tector 26. The VHF VCO 21 may provide an output frequency of 280 MHz, for example.
The 280 MHz signal is coupled into one input of the mixer 22, and the 250 MHz 35 plill~ y reference ~quency signal S1 is coupled into the other input of the mixer 22 by the second coupler lS. The mixer 22 produces sum and dirr~.~,nce frequencies, but the RF low pass filter 23 passes only 280 - 250 = 30 MHz. The RF amplifier 24 amplifies 2Q7~~93 the 30 MHz signal to a sllffi~iP-ntly high level and applies it to the pro~~ able L~ut;n~;y divider 25. The pro~able frequency divider 25 may be set to divide by 30, for eY~mrl~ The output of the prog~able frequency divider 25 is 1 MHz which is applied to the phase detect. r 26. Since the phase delecLol 26 has 1 MHz 5 applied to its other input, the VHF VCO 21 is locked to exactly 280 M~ which is the frequency that is coupled into the second phase locked loop 13 by the third coupler 16.
It will be understood that by varying the half-integer digital progl... ,~ ble L~uency divider 25, the frequency of the VHF VCO 21 may be varied in inc~ l~n~ or steps.The second or L-band phase locked loop 13 is shown at the right side of the drawing figure. The L-band loop 13 converts the frequency provided by the first frequency locked loop 12 to L-band frequency, for example. The output signal 52 of the VHF VCO 21 is passed through a divide-by-L frequency divider 31 that reducesboth its fine step frequency and its phase noise and provides a divided second reference frequency signal 56. The fixed frequency divider 27 and the divide-by-L frequency divider 31 cooperate to reduce the frequency step size. The second phase locked loop 13 is comprised of an L-band VCO 32, a divide-by-two divider 33, a harmonic ~ruxer 34, three RF filters 35, 36, 37, two RF amplifiers 38, 39, the divide-by-L frequency divider 31, the phase detector 41, and a video amplifier 43 with a loop filter 42.
The frequency of the syl,ll,e~i7~A output signal 53 provided by the L-band VCO
32 is divided by two by the divide-by-two divider 33 to provide a divided secondsynthc~ci7eA signal 54 (or half VCO frequency signal 54) and then filtered by the first b~n-lpass filter 35 to suppress h~rmonics generated by the divide-by-two divider 33.
Then the half VCO frequency signal 54 produced by the divide-by-two divider 33 is mixed with the third h~rrnonic of the reference frequency signal 51 at the h~rmonic mixer 34. The frequency of the signal Sl produced by the lcre~ ce oscillator 11 is filtered by second b~ndp~cs filter 37 to prevent out-of-band noise, and is then amplified by the first RF amplifier 38 to provide a signal having a high enough level to drive the h~rmonic mixer 34. In this way, the second phase locked loop 13 avoids multiplying the reference osc~ t ~r frequency by six and reduces the circuit complexity. An offset frequency signal 55 produced by the mixer 34 is passed through the low pass filter 36 to ~U~ GSs ullw~ d frequencies gener~te.l by the rnixer 34. Subsequendy the offset frequency signal 55 is ~mplifiP~l in RF ~mplifi~r 39 to a level sufficient to drive the phase detector 41.
The signals provided by the VHF VCO 21 are divided by L in the divide-by-L
divider 31 to reduce fine step frequency size and phase noise. The divided output sig-nal from the VHF VCO 21 becom~s a second reference frequency signal 56 for the L-band offset frequency. The phases of the two signals 55, 56 are co~ ,d in dle phase - 2~76~9~
-~lPt~or 41, and the voltage of its phase dirr~lcnce signal 61 is arnplified by the video amplifier 43 and its loop filter 42 to adjust and control the frequency, phase and phase noise of the output of the L-band VCO 32 afterclosing the second loop 13. As a consequence, the synthesizer 10 produces fine step ~yl~tl~s;7ç~ frequency outputS signals 57 having low phase noise.
To continue the specific eY~mple given with respect to the first phase locked loop 12, the second phase locked loop 13 O~)GldtGS as follows. The VHF leÇe.~,nce oscillator 11 provides a reference signal S1 at 250 MHz, for exarnple, to the second phase locked loop 13. The VHF VCO 21 provides an output signal 52 of 280 MHz, for example, to the second phase locked loop 13. The L-band VCO 32 may provide an output signal 53 at 1388 MHz, for example. This output signal 53 is coupled out of the second phase locked loop 13 by a fourth coupler 30 as the synthesi7~or output signal 57.
In operation, the divide by L divider 31 may divide by S, for eY~mple, and have an output frequency of 280/S = 56 MHz. The b~ndp~cs filter 37 passes the 250 MHz signal S1 from the VHF reference oscill~tor 11 but ~U~J~)ltiSSe~S the noise above and below the 250 MHz signal. The RF amplifier 38 ~mplifies the 250 MHz signal to a level sufficient to drive the third harmonic rnixer 34. The third h~rmonic of the 250 MHz signal, or 750 MHz, is present in the mixer 34. The 1388 MHz signal 53 from the L-band VCO 32 is divided by two to provide a signal 54 of 694 MHz at the output of the divide by two divider 33. The b~n~lp~cc filter 35 passes only the 694 MHzsignal to the third harmonic mixer 34. The mixer 34 produces sum and difference frequencies, but the low pass filter 36 selects only 750 - 694 = 56 MHz. The 56 MHz signal is ~mplified by RF amplifier 39 to provide a level sllfficien~ to drive the phase detector 41. It is understood that the L-band VCO 32 is locked by the loop through the arnplifier 43.
The output frequency of the pl~Ç~.lcd embodirnent of the frequency synth,-.ci7~rof the present invention may be calculated by using the following equation:
F32 = 2[3 +(1 + N/M) /L]F~
where: F32 is the output frequency of the L-band VCO 32; Fll is the output frequency of the low phase noise VHF reference osçill~tor 11; and (1 _ N/M) represents theoperation of the first phase locked loop 12 in wh*h N is the dividing number of the half-integer digital pro~llable frequency divider 25. This is a half integlal incre-ment divider to double the frequency steps. M repl~i,e.lb the dividing number of the fixed frequency divider 27 and is used to gencl~lc the frequency step size of the first phase locked loop 12. L is the dividing nuln~l of the divide-by-L frequency divider 31 which reduces step size and phase noise of the first loop 12. The number 3 appears in equation (1) because of the third hA, ..lo-~;c mixing that occurs in the ha~monic mixer - 2a76~
34. The numbcl 2 appears in equation (1) because of the frequency being reduced by two in the divide-by-2 divider 33 of the second phase locked loop 13.
- The phase noise of the preferrcd embodiment of the frequency synth~ si7~r of the present invention may be ~1, t . ~ Yl by starting with the reference signal 51 from S the reference oscillator 11 and applying the a~ployliate mllltirlic~tion factors and divid-ing factors. The closed-in phase noise of the output signal of the ~ercllcd embodiment of the invention is ~et~ efl by the noise slope ge ~ ~ by the reference oscillator 11 and is increased by the various multiplication factors. The noise floor of the output signal of the ~lcrcllcd embodiment of the invention is derived from the dividing10 number of the half-integer digital plvgl,... ,..-~ble frequency divider 25 and the dividing number of the divide-by-L frequency divider 31 which is the output noise floor of the fixed frequency divider 27 increased by the dividing factor of N and reduced by the dividing factor of L. Hence, the noise power of the l~lcrcll~ embodiment of the system can be lc~lcsen~ed by following ~imrlified equation as:
L(fm)s7 = 22[32 L(fm)ll + (N/L)2 (KT13FDGD) /(2Po)] (2) where: L(fm)s7 is the output signal phase noise spectrum of the preferred embo~liment of the invention; 22 is the system noise power increased due to the L-band phase locked loop 13 divided by 2; and the term 32 L(fm)ll is the close-in phase noise ~.,L~ ulll increased due to the third order harmonic mixing of the reference oscillator 11, where 20 L(fm)ll is the phase noise s~e.,~ l of the reference oscill~tor 11. The second term (N/L)2 (KTBFDGD) /(2Po) is the fixed frequency divider 27 output signal to noise ratio (KTBFDGD) /(2Po)] incleased by the square of the divided number N, reduced by the square of the divided number L. In this term, the closed-in phase noise spectrum was omitted because it is too small COl~ d to the lcfelcnce oscillator 11 taking the25 multiplication factors into account, particularly after it is divided by L.
From the foregoing ~es~nrtion~ it should be clearly understood that the fre-quency synthesi7~r 10 of the present invention provides low phase noise along with fine frequency step tuning. This pcrf )rm~nce is due to the unique synthesi~r configu-ration employing half-integer digital frequency dividing, VCO frequency orrsel~ing, 30 local oscillator harmonic mixing, and two phase locked loop circuits. The first loop generates the required frequency steps. The output of the voltage controlled oscillator in the first loop is divided by a predetennined fixed number to reduce both the frequen-cy step size and the phase noise. The output of the L-band voltage controlled oscill~tor in the second loop is divided by two and then mixed with the third harmonic of the 35 reference frequency from the reference oscill~tor to generate an offset frequency. This offset frequency is then locked to the divided low phase noise fine fi~quency step out-put from the first loop. In jllllll~AI~ the first loop 12 is the fine loop and generates the - 20~6~93 , .
frequency step si_e. The second loop 13 reduces the phase noise, reduces the frequen-cy step si_e and trAn~l~tPs to the desired frequency. This results in a low cost circuit that provides excellent perfo. I~Ance This low phase noise and fine step size frequency synthPsi7~.rprovides amajorimprovementforDopplerradarandco.. l.. -i~Ation 5 receivers.
To s~ ;7P- one method in accordance with the principles of the present invention, it comprises the following steps. Providing a reference frequency signal 51.
Generating a first synthP~i7~1 signal 52 at a selectAble one of a plurality of desired fre-quencies, each of the frequencies differing from an A(ljAcent frequency by a subst_ntial-10 ly unirolm frequency step size. Generating a second synthesized signal 53 at a select-able one of a second plurality of desired frequencies, which second synthç~i7PA signal 53 comprises a sy..lhesi,e~l output frequency signal 57. Dividing the second synthe-sized signal 53 by a first pre letPrminP~ fixed number to produce a divided second synthesi7P~ signal 54. Mixing the divided second synthe~i7~d signal 54 with a prede-15 tPrmine~l h~rmoni~ of the reference frequency signal 51 to produce an offset frequencysignal 55. Dividing the first synthPci7~d signal 52 by a second pre~iP,tPrminPd fixed - number to produce a divided second reference frequency signal 56 having a reduced frequency step size and reduced phase noise. Phase locking the offset frequency signal 55 to the divided second reference frequency signal 56 to provide the synthesi_ed out-20 put frequency signal 57. The step of phase locking the offset frequency signal 55 to thedivided second reference frequency signal 56 typically comprises the steps of compar-ing the phases of the second offset frequency signal 55 and the divided second refer-ence frequency signal 56 to provide a second control signal 61 that locks the output frequency of the second synthPsi7~ signal 53 to provide the sy-nthesized output 25 frequency signal 57.
Thus there has been described a new and improved low noise, fine frequency step ~y~lhPs;7Pr. It is to be understood that t-h-e above-described embodiment is merely illustrative of some of the many specific emboflim~nts which l~lGsent applications of the principles of the present invention. Clearly, llullle~uus and other arrangell,ell~ can 30 be readily devised by those skilled in the art without departing from the scope of the in-vention.
BACKGROUND
The present invention relatës generally to frequency synthesi7Prs, and more particularly, to a low noise, fine frequency step synthesi7er.
In prior art systems, the phase locked synthesi7e~ frequency provided by a frequency synthesizer either has many fine steps with high phase noise or has low S phase noise with very limited tuning step size. No conventional technology provides both low phase noise and syntheci7Yl frequencies having many fine steps at the same time. More specifically, the patents listed below disclose conventional synthesi7~rs that cannot provide both low phase noise and syntheci7~A frequencies having many finesteps at the same time.
The prior art patents referred to above are identifi~A as follows: U.S. Patent No.
4,940,950 entitled "Frequency Synthesis Method and Apparatus Using Approxi~lnation to Provide Closely Spaced Discrete r~ uencies Over a Wide Range with Rapid Acqui-sition," issued to Helfrick, U.S. Patent No. 4,965,533 entitled "Direct Digital Synthe-sizer Driven Phase Lock Loop Frequency Syntheci7er," issued to Gilmore, U.S. Patent No. 4,912,433 entided "VCO Cont.~lled by Separate Phase Locked Loop," issued to Motegi et al., U.S. Patent No. 4,234,929 entided "Control Device for a Phase Lock Loop Vernier Frequency Synthesi7er~ issued to Riley, Jr.,U.S. Patent No. 4,388,597 entided "Frequency Syntheci7er Having Plural Phase Locked Loops," issued to Bickley et al., and U.S. Patent No. 4,912,432 entitled "Plural Fee~bac'r Loop Digital Frequen-20 cy Syntheci7.or," issued to Galani et al. Of these references, the Bickley et al. and 237~3 Galani et al. patents disclose plural phase locked loop syn~hPsi7~rs, and are conciA~red pertinent to the present invention.
The Bickley et al. patent employs three phase locked loops to achieve synthesis The synthe--ci7~r includes a first phase locked loop compricing a mixer and a phase S Aetectt~r. A second phase locked loop having a programmable divider supplies a refer-ence frequency in pre~letf . ., li n~A steps to the mixer, while a third phase locked loop provides a reference frequency in preAetçrmin~o.A steps to the phase detector, which steps are different from the steps provided by the second phase locked loop. Also, in a preferred emboAim.-nt a fourth phase locked loop provides a reference signal to a 10 mixer in the third phase locked loop to reduce the o~ld~ing frequency therein and the output of the fourth phase locked loop is mixed with an output from the first phase locked loop to extend the range of the synthesi_er.
The Galani et al. patent discloses an indirect digital frequency syn~heci7~or adapted to produce a signal having a selPcteA one of a plurality of relatively closely 15 spaced frequenri~s and having a relatively fast frequency s~viLclfillg time. Multiple fee lh~ loops are fed by reference frequency signals whose frequency is greater than the desired frequency separation provided by the syntheci7~r. The bandwidth of each of the feeAharlf loops is less than the frequency of the reference frequency fed to each loop, and achievement of frequency separation less than the frequency of either of the 20 reference frequencies enables each of the feedback loops to have increased bandwidth and therefore reduced frequency switching times and increased noise ~u~lcssion.
SUMMARY OF THE INVENTION
In order to provide for a frequency syntheci7~r and a method of providing 25 synthesi7çd output frequency signals that achieves low phase noise and provides for synthesi_ed frequencies having many fine steps, the present invention comprises a low phase noise frequency synth~ci7~.r with fine frequency step tuning. The structure of the synshçci7~r is unique, and provides for half-integer digital frequency dividing, VCO
frequency offsetting, and local osçill~t~r harmonic mixing using two phase locked loop 30 circuits. The first loop genelates the required frequency steps, while in the second loop the signal is then divided by a pre~let~ d fixed number to reduce both the frequency step si_e and to reduce the phase noise. The second loop output, at L-band, for exam-ple, is divided by two, and then mixed with the third h~rrnonic of the lc;çelellce frequen-cy to ~ te an offset frequency that is locked to the low phase noise frequency of the 35 first loop. The low phase noise and fine step tuning provided by the present frequency synthesi_erprovidesamajorimprovementforDopplerradarandco.. ~ica*on receivers.
More specifically, the present invention is a frequency synthesi7~r that compris-es a l~fel~nce frequency oscillator for providing a reference frequency signal. A first phase locked loop is coupled to the reference frequency oscillator for generating a first synthesized signal at a selectable one of a plurality of desired fTequencies, each of the S frequencies differing from an adjacent frequency by a substantially uniforrn frequency step size. A second phase locked loop is coupled to the reference frequency oscillator and to the first phase locked loop for generating an output signal from the synthesi~r.
The second phase locked loop comprises a second oscillator for geneld~i lg a second synthçsi7~ signal at a selectable one of a second plurality of desired frequencies. A
first divider is coupled to the second oscillator for dividing the second synthesized signal by a first predetPmlined fLlced number to produce a divided second synthesized signal. A mixer is coupled to the reference frequency oscillator and to the first divider for mixing the divided second syntheci7~d signal with a preclçtç~min~d harmonic of the reference frequency signal to produce an offset frequency signal. A second divider is coupled to the first phase locked loop for dividing the first synth~si7~A signal by a second predetermined fixed~number to produce a divided second syntheci7~ signal having a reduced frequency step si~ and reduced phase noise. A phase detector iscoupled to the second divider and the mixer for locking the offset frequency signal to the divided second syntheci7ecl signal.
One method in accordance with the present invention that provides synthesized output frequency signals comprices the following steps. (1) Providing a reference fre-quency signal. (2) Generating a first synthçsi7~d signal at a selectable one of a plurality of desired frequencies, each of the frequencies differing from an adjacent frequency by a substantially uniform frequency step size. (3) Generating a second synthesi7e~1 signal at a selectable one of a second plurality of desired frequensies, which second synthe-sized signal comprises a synthesized output frequency signal. (4) Dividing the second synthesi7ed signal by a first predeterrnined fixed number to produce a divided second synthesized signal. (5) Mixing the divided second synthesi7ed signal with a predeter-mined ha~ ollic of the l~;fe,ence frequency signal to produce an offset ~equency sig-nal. (6) Dividing the first synthçsi7el1 signal by a second predetermined fixed nurnber to produce a divided second syntheci7e~ signal having a reduced frequency step size and reduced phase noise. (7) Phase locking the offset frequency signal to the divided second synthesized signal to provide the syn~hçci7ç~ output frequency signal.
. .
~, ~ 7 3a Other aspects of this invention are as follows:
A frequency synthesizer comprising:
a reference frequency oscillator for providing a reference frequency signal;
a first phase locked loop adapted to generate a synthesized signal at a selectable one of a plurality of desired frequencies, each of the frequencies differing from an adjacent frequency by a substantially uniform *equency step size, said first phase locked loop comprising a first voltage controlled oscillator for providing a relative!y low phase noise signal, a first mixer adapted to mix said reference frequency signal and said low phase noise signal, a first fixed frequency divider for dividing said reference frequency signal by a first predetermined number to provide a divided reference frequency signal, a digital programmable half-integer frequency divider coupled to said first mixer for providing a first offset frequency signal, a first phase detector for comparing the phase of said first offset frequency signal and the phase of said divided reference frequency signal to provide a first control signal that is adapted to lock said first voltage controlled oscillator; and 2 o a second phase locked loop comprising a second voltage controlled oscillator, a second divider for dividing the output of said second voltage controlled oscillator by a second predetermined number to provide a divided signal, a second mixer adapted t¢ mix a predetermined harmonic of said reference frequency signal with said divided signal to produce a second 2 5 offset frequency signal, a third divider coupled to said first voltage controlled oscillator for dividing said low noise signal by a third predetermined number to provide a divided second reference frequency signal, a second phase detector for comparing the phases of said second offset frequency signal and said divided second reference frequency signal to 3 o provide a second control signal that is adapted to lock said second voltage controlled oscillator.
A
~ ~ 7 ~
3b A metnod of providing a plurality of synthesized frequency signals comprising the steps of:
providing a reference frequency signal, generating a first synthesized signal at a selectable one of a plurality of desired frequencies, each of the frequencies differing from an adjacent frequency by a substantially uniform frequency step size;
generating a second synthesized signal at a selectable one of a second plurality of desired frequencies, which said second synthesized signal 0 comprises a synthesized output frequency signal;
dividing said second synthesized signal by a first predetermined fixed number to produced a divided second synthesized signal;
mixing said divided second synthesized signal with a predetermined harmonic of said reference frequency signal to produce an offset frequency signal;
dividing said first synthesized signal by a second predetermined fixed number to produce a divided second reference frequency signal having a reduced frequency step size and reduced phase noise; and phase locking said offset frequency signal to said divided second 2 o reference frequency signal by comparing the phases of said offset frequency signal and said divided second reference frequency signal and providing a control signal that locks the output frequency of said second synthesized signal to provide said synthesized output frequency signal.
BRIEF DESCRIPTION OF THE DRAWINGS
2 5 The various features and advantages of the present invention may be more readily understood with reference to the following detailed description taken in conjunction , ~
with the accompanying drawings, wherein like reference numerals designate like struc-tural elements, and in which the sole figure illustrates a low noise fine frequency step synthesi7Pr in accordance with the principles of the present invention.
DETAILED DESCRIPTION
The sole figure of the drawing is a schematic diagram in block forrn that illus-trates a preferred embodiment of a low noise fine frequency step synthesizer 10 in accordance with the principles of the present invention. The methods of the present invention will also be readily understood with reference to the drawing figure. The syn~hesi7er 10 is comprised of a low phase noise VHF reference oscillator 11 that provides a primary reference frequency signal 51, and first and second phase locked loops 12, 13 coupled to the reference oscillator 11 that are adapted to provide low phase noise and achieve fine step synthesized L-band frequencies.
The characteristics of the VHF reference oscillator 11 are important because thephase noise of the output signal from the synthesi_er 10 is dependent on and derived from it. The output frequency provided by the VHF reference oscillator 11 requires good short term frequency stability with very low AM and phase noises. The VHF
reference oscill~tor 11 is typically a co.~ ,ially available circuit using either a very high ~factor overtone crystal or using a surface acoustic wave (SAW) resonator. The ~/HF reference oscillator 11 employs the least amount of frequency mulhplication pos-sible to avoid introducing multiplication noise into the primary reference frequency signal 51.
The first phase locked loop 12 is the fine or VHF step tuning loop 12, and is shown at the left side of the drawing figure. The first phase locked loop 12 is adapted to generate a synthesi7ed signal 52 having fine frequency steps. It is comprised of a VHF voltage controlled oscillator (VCO) 21 having its output connected to one input of a mixer 22, an RF low pass filter 23 connected to the output of the mixer 22, and an RF arnplifier 24 connected from the low pass filter 23 to a half-integer digital prograrn-mable frequency divider 25. The details of the half-integer divider 25 are more fully discussed in U.S. Patent No. 4,975,931 issued December 4, 1990 to Albert E.
Cosand, and assigned to the assignee of the present invention. The first phase locked loop 12 is coupled to the output of the VHF reference oscillator 11 by first and second couplers 14, 15. The first coupler 14 couples the primary reference frequency signal 51 to a fixed &equency divider 27. The second coupler 15 couples the primary reference frequency signal 51 to the mixer 22. The output of the fixed frequency divider 27 is connected to one input of a phase detector 26. The output of the half-integer digital 2~7~93 s prog.~ ble frequency divider 25 is coupled to the other input of the phase ~lptecl~r 26. The output of the phase ~letector 26 is coupled by way of a video loop filter 28 to the control input of the VHF VCO 21. The video loop filter 28 co...l.. ;ses an opera-tional ~mplifi~ 29 having a resistor 29A in series with a car~ci~r 29B connect~l from 5 input to output. The output of the first phase locked loop 12 is coupled into the second phase locked loop 13 by a third coupler 16.
To get the lowest phase noise in the first phase locked loop 12, the frequency of the VHF VCO 21 is not directly divided down and locked to the step l~;rt;l~nce frequen-cy, but is offset by the primary reference frequency from the VHF reference oscillator 10 11. The digital pro~ll.lJable frequency divider 25 divides the offset frequency by half-integer steps to avoid increased dividing phase noise. By implemPn~ing these two processing steps, the rate of phase noise increase is reduced to a ..~i.~;..,ll... The offset frequency signal S1 is produced at the output of the mixer 22. The mixer 22 not only creates the offset frequency signal S 1, but also generates unwanted spurious high fre-15 quency signals as well. Therefore, the RF low pass filter 23 is n~ces~ry to suppressthese spurious high frequency signals.
After the RF low pass filter 23 cleans up the offset frequency signal 53, it is ~mplifie~l by the amplifier 24 to a high enough level to drive the half-integer digital pro-g-~.,u~able fiequency divider 25, also called a divide-by-N frequency divider 25. The 20 divide-by-N frequency divider 25 divides the offset frequency signal 53 by a predeter-mined count. Then the phase of the output signal 59 of the divide-by-N frequencydivider 25 is co~ ,d with the phase of a fine step reference frequency signal 58provided by the reference osçill~tnr 11 after being divided by the fixed frequency divider 27, also called a divide-by-M fixed frequency divider 27. Then the output volt-25 age of phase detector 26 is passed through the video loop filter 28 and the operationalamplifier 29 to adjust and control the frequency, phase, and phase noise of the VHF
VCO 21 after the loop is closed.
The operation of the first phase locked loop 12 will be illustrated with a specific example. The VHF reference oSc~ tor 11 may provide a primary reference frequency30 of 250 MHz, for example. The ~lilll~ y reference frequency signal S 1 is coupled through the first coupler 14 to the fixed frequency divider 27 which may divide by 250, for example. This provides a frequency of 1 ~Iz to one input of the phase ~ tector 26. The VHF VCO 21 may provide an output frequency of 280 MHz, for example.
The 280 MHz signal is coupled into one input of the mixer 22, and the 250 MHz 35 plill~ y reference ~quency signal S1 is coupled into the other input of the mixer 22 by the second coupler lS. The mixer 22 produces sum and dirr~.~,nce frequencies, but the RF low pass filter 23 passes only 280 - 250 = 30 MHz. The RF amplifier 24 amplifies 2Q7~~93 the 30 MHz signal to a sllffi~iP-ntly high level and applies it to the pro~~ able L~ut;n~;y divider 25. The pro~able frequency divider 25 may be set to divide by 30, for eY~mrl~ The output of the prog~able frequency divider 25 is 1 MHz which is applied to the phase detect. r 26. Since the phase delecLol 26 has 1 MHz 5 applied to its other input, the VHF VCO 21 is locked to exactly 280 M~ which is the frequency that is coupled into the second phase locked loop 13 by the third coupler 16.
It will be understood that by varying the half-integer digital progl... ,~ ble L~uency divider 25, the frequency of the VHF VCO 21 may be varied in inc~ l~n~ or steps.The second or L-band phase locked loop 13 is shown at the right side of the drawing figure. The L-band loop 13 converts the frequency provided by the first frequency locked loop 12 to L-band frequency, for example. The output signal 52 of the VHF VCO 21 is passed through a divide-by-L frequency divider 31 that reducesboth its fine step frequency and its phase noise and provides a divided second reference frequency signal 56. The fixed frequency divider 27 and the divide-by-L frequency divider 31 cooperate to reduce the frequency step size. The second phase locked loop 13 is comprised of an L-band VCO 32, a divide-by-two divider 33, a harmonic ~ruxer 34, three RF filters 35, 36, 37, two RF amplifiers 38, 39, the divide-by-L frequency divider 31, the phase detector 41, and a video amplifier 43 with a loop filter 42.
The frequency of the syl,ll,e~i7~A output signal 53 provided by the L-band VCO
32 is divided by two by the divide-by-two divider 33 to provide a divided secondsynthc~ci7eA signal 54 (or half VCO frequency signal 54) and then filtered by the first b~n-lpass filter 35 to suppress h~rmonics generated by the divide-by-two divider 33.
Then the half VCO frequency signal 54 produced by the divide-by-two divider 33 is mixed with the third h~rrnonic of the reference frequency signal 51 at the h~rmonic mixer 34. The frequency of the signal Sl produced by the lcre~ ce oscillator 11 is filtered by second b~ndp~cs filter 37 to prevent out-of-band noise, and is then amplified by the first RF amplifier 38 to provide a signal having a high enough level to drive the h~rmonic mixer 34. In this way, the second phase locked loop 13 avoids multiplying the reference osc~ t ~r frequency by six and reduces the circuit complexity. An offset frequency signal 55 produced by the mixer 34 is passed through the low pass filter 36 to ~U~ GSs ullw~ d frequencies gener~te.l by the rnixer 34. Subsequendy the offset frequency signal 55 is ~mplifiP~l in RF ~mplifi~r 39 to a level sufficient to drive the phase detector 41.
The signals provided by the VHF VCO 21 are divided by L in the divide-by-L
divider 31 to reduce fine step frequency size and phase noise. The divided output sig-nal from the VHF VCO 21 becom~s a second reference frequency signal 56 for the L-band offset frequency. The phases of the two signals 55, 56 are co~ ,d in dle phase - 2~76~9~
-~lPt~or 41, and the voltage of its phase dirr~lcnce signal 61 is arnplified by the video amplifier 43 and its loop filter 42 to adjust and control the frequency, phase and phase noise of the output of the L-band VCO 32 afterclosing the second loop 13. As a consequence, the synthesizer 10 produces fine step ~yl~tl~s;7ç~ frequency outputS signals 57 having low phase noise.
To continue the specific eY~mple given with respect to the first phase locked loop 12, the second phase locked loop 13 O~)GldtGS as follows. The VHF leÇe.~,nce oscillator 11 provides a reference signal S1 at 250 MHz, for exarnple, to the second phase locked loop 13. The VHF VCO 21 provides an output signal 52 of 280 MHz, for example, to the second phase locked loop 13. The L-band VCO 32 may provide an output signal 53 at 1388 MHz, for example. This output signal 53 is coupled out of the second phase locked loop 13 by a fourth coupler 30 as the synthesi7~or output signal 57.
In operation, the divide by L divider 31 may divide by S, for eY~mple, and have an output frequency of 280/S = 56 MHz. The b~ndp~cs filter 37 passes the 250 MHz signal S1 from the VHF reference oscill~tor 11 but ~U~J~)ltiSSe~S the noise above and below the 250 MHz signal. The RF amplifier 38 ~mplifies the 250 MHz signal to a level sufficient to drive the third harmonic rnixer 34. The third h~rmonic of the 250 MHz signal, or 750 MHz, is present in the mixer 34. The 1388 MHz signal 53 from the L-band VCO 32 is divided by two to provide a signal 54 of 694 MHz at the output of the divide by two divider 33. The b~n~lp~cc filter 35 passes only the 694 MHzsignal to the third harmonic mixer 34. The mixer 34 produces sum and difference frequencies, but the low pass filter 36 selects only 750 - 694 = 56 MHz. The 56 MHz signal is ~mplified by RF amplifier 39 to provide a level sllfficien~ to drive the phase detector 41. It is understood that the L-band VCO 32 is locked by the loop through the arnplifier 43.
The output frequency of the pl~Ç~.lcd embodirnent of the frequency synth,-.ci7~rof the present invention may be calculated by using the following equation:
F32 = 2[3 +(1 + N/M) /L]F~
where: F32 is the output frequency of the L-band VCO 32; Fll is the output frequency of the low phase noise VHF reference osçill~tor 11; and (1 _ N/M) represents theoperation of the first phase locked loop 12 in wh*h N is the dividing number of the half-integer digital pro~llable frequency divider 25. This is a half integlal incre-ment divider to double the frequency steps. M repl~i,e.lb the dividing number of the fixed frequency divider 27 and is used to gencl~lc the frequency step size of the first phase locked loop 12. L is the dividing nuln~l of the divide-by-L frequency divider 31 which reduces step size and phase noise of the first loop 12. The number 3 appears in equation (1) because of the third hA, ..lo-~;c mixing that occurs in the ha~monic mixer - 2a76~
34. The numbcl 2 appears in equation (1) because of the frequency being reduced by two in the divide-by-2 divider 33 of the second phase locked loop 13.
- The phase noise of the preferrcd embodiment of the frequency synth~ si7~r of the present invention may be ~1, t . ~ Yl by starting with the reference signal 51 from S the reference oscillator 11 and applying the a~ployliate mllltirlic~tion factors and divid-ing factors. The closed-in phase noise of the output signal of the ~ercllcd embodiment of the invention is ~et~ efl by the noise slope ge ~ ~ by the reference oscillator 11 and is increased by the various multiplication factors. The noise floor of the output signal of the ~lcrcllcd embodiment of the invention is derived from the dividing10 number of the half-integer digital plvgl,... ,..-~ble frequency divider 25 and the dividing number of the divide-by-L frequency divider 31 which is the output noise floor of the fixed frequency divider 27 increased by the dividing factor of N and reduced by the dividing factor of L. Hence, the noise power of the l~lcrcll~ embodiment of the system can be lc~lcsen~ed by following ~imrlified equation as:
L(fm)s7 = 22[32 L(fm)ll + (N/L)2 (KT13FDGD) /(2Po)] (2) where: L(fm)s7 is the output signal phase noise spectrum of the preferred embo~liment of the invention; 22 is the system noise power increased due to the L-band phase locked loop 13 divided by 2; and the term 32 L(fm)ll is the close-in phase noise ~.,L~ ulll increased due to the third order harmonic mixing of the reference oscillator 11, where 20 L(fm)ll is the phase noise s~e.,~ l of the reference oscill~tor 11. The second term (N/L)2 (KTBFDGD) /(2Po) is the fixed frequency divider 27 output signal to noise ratio (KTBFDGD) /(2Po)] incleased by the square of the divided number N, reduced by the square of the divided number L. In this term, the closed-in phase noise spectrum was omitted because it is too small COl~ d to the lcfelcnce oscillator 11 taking the25 multiplication factors into account, particularly after it is divided by L.
From the foregoing ~es~nrtion~ it should be clearly understood that the fre-quency synthesi7~r 10 of the present invention provides low phase noise along with fine frequency step tuning. This pcrf )rm~nce is due to the unique synthesi~r configu-ration employing half-integer digital frequency dividing, VCO frequency orrsel~ing, 30 local oscillator harmonic mixing, and two phase locked loop circuits. The first loop generates the required frequency steps. The output of the voltage controlled oscillator in the first loop is divided by a predetennined fixed number to reduce both the frequen-cy step size and the phase noise. The output of the L-band voltage controlled oscill~tor in the second loop is divided by two and then mixed with the third harmonic of the 35 reference frequency from the reference oscill~tor to generate an offset frequency. This offset frequency is then locked to the divided low phase noise fine fi~quency step out-put from the first loop. In jllllll~AI~ the first loop 12 is the fine loop and generates the - 20~6~93 , .
frequency step si_e. The second loop 13 reduces the phase noise, reduces the frequen-cy step si_e and trAn~l~tPs to the desired frequency. This results in a low cost circuit that provides excellent perfo. I~Ance This low phase noise and fine step size frequency synthPsi7~.rprovides amajorimprovementforDopplerradarandco.. l.. -i~Ation 5 receivers.
To s~ ;7P- one method in accordance with the principles of the present invention, it comprises the following steps. Providing a reference frequency signal 51.
Generating a first synthP~i7~1 signal 52 at a selectAble one of a plurality of desired fre-quencies, each of the frequencies differing from an A(ljAcent frequency by a subst_ntial-10 ly unirolm frequency step size. Generating a second synthesized signal 53 at a select-able one of a second plurality of desired frequencies, which second synthç~i7PA signal 53 comprises a sy..lhesi,e~l output frequency signal 57. Dividing the second synthe-sized signal 53 by a first pre letPrminP~ fixed number to produce a divided second synthesi7P~ signal 54. Mixing the divided second synthe~i7~d signal 54 with a prede-15 tPrmine~l h~rmoni~ of the reference frequency signal 51 to produce an offset frequencysignal 55. Dividing the first synthPci7~d signal 52 by a second pre~iP,tPrminPd fixed - number to produce a divided second reference frequency signal 56 having a reduced frequency step size and reduced phase noise. Phase locking the offset frequency signal 55 to the divided second reference frequency signal 56 to provide the synthesi_ed out-20 put frequency signal 57. The step of phase locking the offset frequency signal 55 to thedivided second reference frequency signal 56 typically comprises the steps of compar-ing the phases of the second offset frequency signal 55 and the divided second refer-ence frequency signal 56 to provide a second control signal 61 that locks the output frequency of the second synthPsi7~ signal 53 to provide the sy-nthesized output 25 frequency signal 57.
Thus there has been described a new and improved low noise, fine frequency step ~y~lhPs;7Pr. It is to be understood that t-h-e above-described embodiment is merely illustrative of some of the many specific emboflim~nts which l~lGsent applications of the principles of the present invention. Clearly, llullle~uus and other arrangell,ell~ can 30 be readily devised by those skilled in the art without departing from the scope of the in-vention.
Claims (15)
1. A frequency synthesizer comprising:
reference frequency oscillator means for providing a reference frequency signal;a first phase locked loop coupled to said reference frequency oscillator means for generating a first synthesized signal at a selectable one of a plurality of desired frequencies, each of the frequencies differing from an adjacent frequency by a substantially uniform frequency step size; and a second phase locked loop coupled to said reference frequency oscillator means and to said first phase locked loop for generating an output signal having a predetermined frequency, said second phase locked loop comprising second oscillator means for generating a second synthesized signal at a selectable one of a second plurality of desired frequencies, first divider means coupled to said second oscillator means for dividing said second synthesized signal by a first predetermined fixed number to produce a divided second synthesized signal, mixing means coupled to said reference frequency oscillator and to said first divider means for mixing said divided second synthesized signal with a predetermined harmonic of said reference frequency signal to produce an offset frequency signal, second divider means coupled to said first phase locked loop for dividing said first synthesized signal by a second predetermined fixed number to produce a divided second reference frequency signal having a reduced frequency step size and reduced phase noise, and phase detector means coupled to said mixing means and to said second divider means for locking said offset frequency signal to said divided second reference frequency signal.
reference frequency oscillator means for providing a reference frequency signal;a first phase locked loop coupled to said reference frequency oscillator means for generating a first synthesized signal at a selectable one of a plurality of desired frequencies, each of the frequencies differing from an adjacent frequency by a substantially uniform frequency step size; and a second phase locked loop coupled to said reference frequency oscillator means and to said first phase locked loop for generating an output signal having a predetermined frequency, said second phase locked loop comprising second oscillator means for generating a second synthesized signal at a selectable one of a second plurality of desired frequencies, first divider means coupled to said second oscillator means for dividing said second synthesized signal by a first predetermined fixed number to produce a divided second synthesized signal, mixing means coupled to said reference frequency oscillator and to said first divider means for mixing said divided second synthesized signal with a predetermined harmonic of said reference frequency signal to produce an offset frequency signal, second divider means coupled to said first phase locked loop for dividing said first synthesized signal by a second predetermined fixed number to produce a divided second reference frequency signal having a reduced frequency step size and reduced phase noise, and phase detector means coupled to said mixing means and to said second divider means for locking said offset frequency signal to said divided second reference frequency signal.
2. The frequency synthesizer of Claim 1 wherein said first phase locked loop is adapted to provide said first synthesized signal at a selectable one of a first plurality of VHF frequencies and said second phase locked loop is adapted to provide said second synthesized signal at a selectable one of a second plurality of L-band frequencies.
3. The frequency synthesizer of Claim 1 wherein said second phase locked loop further comprises a first bandpass filter coupled between said first divider means and said mixing means.
4. The frequency synthesizer of Claim 1 wherein said second phase locked loop further comprises a serially coupled second bandpass filter and first amplifier coupled between said reference oscillator and said mixing means.
5. The frequency synthesizer of Claim 1 wherein said second phase locked loop further comprises a serially coupled first low pass filter and second amplifier coupled between said mixing means and said phase detector means.
6. The frequency synthesizer of Claim 1 wherein said second phase locked loop further comprises a loop filter coupled between said phase detector means and said second oscillator means.
7. A frequency synthesizer comprising:
a reference frequency oscillator for providing a reference frequency signal;
a first phase locked loop adapted to generate a synthesized signal at a selectable one of a plurality of desired frequencies, each of the frequencies differing from an adjacent frequency by a substantially uniform frequency step size, said first phase locked loop comprising a first voltage controlled oscillator for providing a relatively low phase noise signal, a first mixer adapted to mix said reference frequency signal and said low phase noise signal, a first fixed frequency divider for dividing said reference frequency signal by a first predetermined number to provide a divided reference frequency signal, a digital programmable half-integer frequency divider coupled to said first mixer for providing a first offset frequency signal, a first phase detector for comparing the phase of said first offset frequency signal and the phase of said divided reference frequency signal to provide a first control signal that is adapted to lock said first voltage controlled oscillator; and a second phase locked loop comprising a second voltage controlled oscillator, a second divider for dividing the output of said second voltage controlled oscillator by a second predetermined number to provide a divided signal, a second mixer adapted to mix a predetermined harmonic of said reference frequency signal with said divided signal to produce a second offset frequency signal, a third divider coupled to said first voltage controlled oscillator for dividing said low noise signal by a third predetermined number to provide a divided second reference frequency signal, a second phase detector forcomparing the phases of said second offset frequency signal and said divided second reference frequency signal to provide a second control signal that is adapted to lock said second voltage controlled oscillator.
a reference frequency oscillator for providing a reference frequency signal;
a first phase locked loop adapted to generate a synthesized signal at a selectable one of a plurality of desired frequencies, each of the frequencies differing from an adjacent frequency by a substantially uniform frequency step size, said first phase locked loop comprising a first voltage controlled oscillator for providing a relatively low phase noise signal, a first mixer adapted to mix said reference frequency signal and said low phase noise signal, a first fixed frequency divider for dividing said reference frequency signal by a first predetermined number to provide a divided reference frequency signal, a digital programmable half-integer frequency divider coupled to said first mixer for providing a first offset frequency signal, a first phase detector for comparing the phase of said first offset frequency signal and the phase of said divided reference frequency signal to provide a first control signal that is adapted to lock said first voltage controlled oscillator; and a second phase locked loop comprising a second voltage controlled oscillator, a second divider for dividing the output of said second voltage controlled oscillator by a second predetermined number to provide a divided signal, a second mixer adapted to mix a predetermined harmonic of said reference frequency signal with said divided signal to produce a second offset frequency signal, a third divider coupled to said first voltage controlled oscillator for dividing said low noise signal by a third predetermined number to provide a divided second reference frequency signal, a second phase detector forcomparing the phases of said second offset frequency signal and said divided second reference frequency signal to provide a second control signal that is adapted to lock said second voltage controlled oscillator.
8. A method of providing a synthesized output frequency signal comprising the steps of:
providing a reference frequency signal;
generating a first synthesized signal at a selectable one of a plurality of desired frequencies, each of the frequencies differing from an adjacent frequency by a substantially uniform frequency step size;
generating a second synthesized signal at a selectable one of a second plurality of desired frequencies, which said second synthesized signal comprises a synthesized output frequency signal;
dividing said second synthesized signal by a first predetermined fixed number toproduce a divided second synthesized signal;
mixing said divided second synthesized signal with a predetermined harmonic of said reference frequency signal to produce an offset frequency signal;
dividing said first synthesized signal by a second predetermined fixed number toproduce a divided second reference frequency signal having a reduced frequency step size and reduced phase noise; and phase locking said offset frequency signal to said divided second reference frequency signal to provide said synthesized output frequency signal.
providing a reference frequency signal;
generating a first synthesized signal at a selectable one of a plurality of desired frequencies, each of the frequencies differing from an adjacent frequency by a substantially uniform frequency step size;
generating a second synthesized signal at a selectable one of a second plurality of desired frequencies, which said second synthesized signal comprises a synthesized output frequency signal;
dividing said second synthesized signal by a first predetermined fixed number toproduce a divided second synthesized signal;
mixing said divided second synthesized signal with a predetermined harmonic of said reference frequency signal to produce an offset frequency signal;
dividing said first synthesized signal by a second predetermined fixed number toproduce a divided second reference frequency signal having a reduced frequency step size and reduced phase noise; and phase locking said offset frequency signal to said divided second reference frequency signal to provide said synthesized output frequency signal.
9. The method of providing a synthesized output frequency signal of Claim 8 wherein the step of generating said first synthesized signal comprises generating a VHF-band frequency signal and the step of generating said second synthesized signal comprises generating an L-band frequency signal.
10. The method of providing a synthesized output frequency signal of Claim 8 further comprising the step of bandpass filtering said divided second synthesized signal prior to mixing it with said predetermined harmonic of said reference frequency signal.
11. The method of providing a synthesized output frequency signal of Claim 8 further comprising the step of bandpass filtering and amplifying said reference frequency signal prior to mixing it with said divided second synthesized signal.
12. The method of providing a synthesized output frequency signal of Claim 8 further comprising the step of low pass filtering and amplifying said offset frequency signal prior to locking it to said divided second reference frequency signal.
13. The method of providing a synthesized output frequency signal of Claim 8 wherein the step of phase locking said offset frequency signal to said divided second reference frequency signal comprises the step of comparing the phases of said offset frequency signal and said divided second reference frequency signal to provide a control signal that locks the output frequency of said second synthesized signal to provide said synthesized output frequency signal.
14. The method of providing a synthesized output frequency signal of Claim 13 further comprises the step of filtering said control signal.
15. A method of providing a plurality of synthesized frequency signals comprising the steps of:
providing a reference frequency signal;
generating a first synthesized signal at a selectable one of a plurality of desired frequencies, each of the frequencies differing from an adjacent frequency by a substantially uniform frequency step size;
generating a second synthesized signal at a selectable one of a second plurality of desired frequencies, which said second synthesized signal comprises a synthesized output frequency signal;
dividing said second synthesized signal by a first predetermined fixed number toproduced a divided second synthesized signal;
mixing said divided second synthesized signal with a predetermined harmonic of said reference frequency signal to produce an offset frequency signal;
dividing said first synthesized signal by a second predetermined fixed number toproduce a divided second reference frequency signal having a reduced frequency step size and reduced phase noise; and phase locking said offset frequency signal to said divided second reference frequency signal by comparing the phases of said offset frequency signal and said divided second reference frequency signal and providing a control signal that locks the output frequency of said second synthesized signal to provide said synthesized output frequency signal.
providing a reference frequency signal;
generating a first synthesized signal at a selectable one of a plurality of desired frequencies, each of the frequencies differing from an adjacent frequency by a substantially uniform frequency step size;
generating a second synthesized signal at a selectable one of a second plurality of desired frequencies, which said second synthesized signal comprises a synthesized output frequency signal;
dividing said second synthesized signal by a first predetermined fixed number toproduced a divided second synthesized signal;
mixing said divided second synthesized signal with a predetermined harmonic of said reference frequency signal to produce an offset frequency signal;
dividing said first synthesized signal by a second predetermined fixed number toproduce a divided second reference frequency signal having a reduced frequency step size and reduced phase noise; and phase locking said offset frequency signal to said divided second reference frequency signal by comparing the phases of said offset frequency signal and said divided second reference frequency signal and providing a control signal that locks the output frequency of said second synthesized signal to provide said synthesized output frequency signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/799,817 US5150078A (en) | 1991-11-29 | 1991-11-29 | Low noise fine frequency step synthesizer |
| US799,817 | 1991-11-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2076893A1 CA2076893A1 (en) | 1993-05-30 |
| CA2076893C true CA2076893C (en) | 1999-01-26 |
Family
ID=25176833
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002076893A Expired - Fee Related CA2076893C (en) | 1991-11-29 | 1992-08-26 | Low noise fine frequency step synthesizer |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US5150078A (en) |
| EP (1) | EP0545232B1 (en) |
| JP (1) | JP2710528B2 (en) |
| CA (1) | CA2076893C (en) |
| DE (1) | DE69220460T2 (en) |
| ES (1) | ES2103024T3 (en) |
| NO (1) | NO302599B1 (en) |
| TR (1) | TR26254A (en) |
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| US5317284A (en) * | 1993-02-08 | 1994-05-31 | Hughes Aircraft Company | Wide band, low noise, fine step tuning, phase locked loop frequency synthesizer |
| KR100219709B1 (en) * | 1994-03-15 | 1999-09-01 | 윤종용 | Signal processing circuits for digital radio communication system |
| GB2294599B (en) * | 1994-10-28 | 1999-04-14 | Marconi Instruments Ltd | A frequency synthesiser |
| FR2734972B1 (en) * | 1995-05-31 | 1997-08-01 | Matra Communication | FREQUENCY MODULATED RADIO TRANSMISSION DEVICE |
| JPH0993090A (en) * | 1995-09-21 | 1997-04-04 | Pioneer Electron Corp | Receiver |
| US5870592A (en) * | 1996-10-31 | 1999-02-09 | International Business Machines Corp. | Clock generation apparatus and method for CMOS microprocessors using a differential saw oscillator |
| US5838205A (en) * | 1997-02-18 | 1998-11-17 | International Business Machines Corporation | Variable-speed phase-locked loop system with on-the-fly switching and method therefor |
| CN1153352C (en) | 1997-03-18 | 2004-06-09 | 皇家菲利浦电子有限公司 | Receiver tuning system |
| WO1998042076A2 (en) * | 1997-03-18 | 1998-09-24 | Koninklijke Philips Electronics N.V. | Receiver tuning system |
| US6014047A (en) * | 1998-01-07 | 2000-01-11 | International Business Machines Corporation | Method and apparatus for phase rotation in a phase locked loop |
| US5949262A (en) * | 1998-01-07 | 1999-09-07 | International Business Machines Corporation | Method and apparatus for coupled phase locked loops |
| US6072427A (en) * | 1999-04-01 | 2000-06-06 | Mcewan; Thomas E. | Precision radar timebase using harmonically related offset oscillators |
| US6564039B1 (en) * | 2000-02-29 | 2003-05-13 | Motorola, Inc. | Frequency generation circuit and method of operating a tranceiver |
| EP1255356B1 (en) * | 2001-05-02 | 2009-07-22 | Sony Deutschland GmbH | Dual mode/triple band frequency synthesiser |
| US6850745B2 (en) * | 2002-01-23 | 2005-02-01 | Broadcom Corp | Method and apparatus for generating a self-correcting local oscillation |
| US6759910B2 (en) * | 2002-05-29 | 2004-07-06 | Xytrans, Inc. | Phase locked loop (PLL) frequency synthesizer and method |
| US6940938B2 (en) * | 2002-07-31 | 2005-09-06 | Intel Corporation | Phase locked loop having a single sideband modulator |
| US6965224B1 (en) * | 2003-05-16 | 2005-11-15 | Cisco Technology, Inc. | Method and apparatus for testing synchronization circuitry |
| JP4391291B2 (en) * | 2004-03-31 | 2009-12-24 | 住友電工デバイス・イノベーション株式会社 | Wireless device |
| US7580691B1 (en) * | 2005-08-02 | 2009-08-25 | Rf Micro Devices, Inc. | System and method for reducing self interference |
| US7773026B2 (en) * | 2008-08-01 | 2010-08-10 | Infineon Technologies Ag | Heterodyne transceiver systems and methods |
| CN101464514B (en) * | 2009-01-22 | 2011-12-28 | 中国人民解放军国防科学技术大学 | Calibration method and calibration processor for step frequency radar system |
| CN105187058A (en) * | 2015-10-29 | 2015-12-23 | 南京健瑞电子科技有限公司 | Frequency synthesis system and active millimeter-wave imaging equipment |
| CN105227183B (en) * | 2015-11-16 | 2018-08-21 | 中国电子科技集团公司第四十三研究所 | A kind of agile frequency source of low spurious |
| US10598764B2 (en) * | 2017-10-30 | 2020-03-24 | Yekutiel Josefsberg | Radar target detection and imaging system for autonomous vehicles with ultra-low phase noise frequency synthesizer |
| US10205457B1 (en) * | 2018-06-01 | 2019-02-12 | Yekutiel Josefsberg | RADAR target detection system for autonomous vehicles with ultra lowphase noise frequency synthesizer |
| CN112886960B (en) * | 2021-01-12 | 2023-01-13 | 天津大学 | Phase-locked loop with ultra-low phase noise adjustability |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4234929A (en) * | 1979-09-24 | 1980-11-18 | Harris Corporation | Control device for a phase lock loop vernier frequency synthesizer |
| US4388597A (en) * | 1980-06-03 | 1983-06-14 | Motorola Inc. | Frequency synthesizer having plural phase locked loops |
| JPS63151220A (en) * | 1986-12-16 | 1988-06-23 | Matsushita Electric Ind Co Ltd | Microwave band frequency synthesizer |
| JP2531742B2 (en) * | 1988-05-17 | 1996-09-04 | 株式会社東芝 | Voltage controlled oscillator |
| US4940950A (en) * | 1988-08-12 | 1990-07-10 | Tel-Instrument Electronics Corporation | Frequency synthesis method and apparatus using approximation to provide closely spaced discrete frequencies over a wide range with rapid acquisition |
| US4912432A (en) * | 1989-04-17 | 1990-03-27 | Raytheon Company | Plural feedback loop digital frequency synthesizer |
| US4965533A (en) * | 1989-08-31 | 1990-10-23 | Qualcomm, Inc. | Direct digital synthesizer driven phase lock loop frequency synthesizer |
-
1991
- 1991-11-29 US US07/799,817 patent/US5150078A/en not_active Expired - Lifetime
-
1992
- 1992-08-26 CA CA002076893A patent/CA2076893C/en not_active Expired - Fee Related
- 1992-11-25 EP EP92120020A patent/EP0545232B1/en not_active Expired - Lifetime
- 1992-11-25 NO NO924545A patent/NO302599B1/en unknown
- 1992-11-25 DE DE69220460T patent/DE69220460T2/en not_active Expired - Fee Related
- 1992-11-25 ES ES92120020T patent/ES2103024T3/en not_active Expired - Lifetime
- 1992-11-26 TR TR92/1128A patent/TR26254A/en unknown
- 1992-11-30 JP JP4320494A patent/JP2710528B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2710528B2 (en) | 1998-02-10 |
| EP0545232B1 (en) | 1997-06-18 |
| EP0545232A1 (en) | 1993-06-09 |
| US5150078A (en) | 1992-09-22 |
| TR26254A (en) | 1995-02-15 |
| NO924545D0 (en) | 1992-11-25 |
| NO302599B1 (en) | 1998-03-23 |
| JPH05284022A (en) | 1993-10-29 |
| NO924545L (en) | 1993-06-01 |
| DE69220460D1 (en) | 1997-07-24 |
| ES2103024T3 (en) | 1997-08-16 |
| CA2076893A1 (en) | 1993-05-30 |
| DE69220460T2 (en) | 1998-02-05 |
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