CA2079623C - Method and apparatus for providing two parties transparent access to a single-port memory storage device - Google Patents

Abstract

A data communication controller having a memory access control unit characterized by a symmetrical access port architecture. The memory access control unit allows both a host processor and the medium access control (MAC) unit of the data communication controller to transparently access a single-port data packet buffer memory while operating a full specified operating speed and without interference between simultaneous memory access requests. The memory access control unit arbitrates asynchronous memory access requests from both the host processor and the medium access control unit, while permitting each of these processors unlimited access to the single-port buffer memory as if it alone had the full memory available to itself at all times. The above capabilities are achieved using automatic address incrementation and data-byte prefetching operations, without requiring the use of a port processor or additional internal data buses.

Description

DATA COMMUNICATION CONTROLLER FOR USE WITH A
SINCiLE-PORT DATA POCKET BUFFER
BACKGROUND OF THE INVENTION
1. Field of Invention The present: invention relates generally to a method and apparatus for_ providing two processors transparent access to a single-port memory storage device, such as a random access memory (RAM) storage do=vice. Yet, more particularly, the present invention relates to such method and apparatus adapted 1.0 for utilization in a communication controller interfaced between a host px-ocessor and the communication network.

2. Brief Description of the Prior Art Local-area networks (LAN) are communication systems which enable data-processing devices, such as computer workstations, to communicate with each other through a communication (e. g. transmission) media. Data-processing devices in such networks are typically referred to as nodes or stations. While many :such stations are likely to be relatively autonomous, requiring communication with other stations only occasionally, other stations may require more frequent communication. Typica7_ly, the amount of communication required by a particular ~~tation can vary from time to time.
In many loca7_ area networks, stations can be easily added to, removes. from, and moved from place to place within the network. While the re are numerous local area networks presently known, they c:an be classified into two general types.
The first type of network is referred to as a "centralized network" which is characterized by the requirement of a centralized netwcrk controller which implements the network protocol. The seconcLtype of local area network is referred to as a "distributed network" which does note require a centralized network c:o:ntroller, and instead provides each station within the network with a communication controller having a medium ~~cce:~s control (MAC) unit that locally implements the network protocol within each communication controller.
In a d:LStributed local area network, packet switching is a technique commonly employed to dynamically allocate the _~0 communication re;~ourc:es of the network among multiple communicating stations. According to this technique, messages to be communicatf~d between stations are partitioned (by the transmitting stal~ion''s processor) into packets, having a fixed maximum size. The packets are then ascribed a station (i.e.
:L5 source) identifier. The packets are then placed on the communication medium by the station's communication controller.
Such packets are then sensed and selectively processed by the communication controller of the destination station in the network.
:?0 Any pa~~ket from one station to another station contains various fields of information specified in accordance with a predetermined network protocol. The information typically includes the identity of the source station, the identity of the destination station, and various other :~5 information concerning the characteristics of the packet. In some network protoco:Ls, a number of different types of packets may appear on the communication medium in accordance with the network protocol. T~~pically, these packets relate to either communication contro:L or data-transfer functions.
30 To more fully appreciate the problems associated with conventional communication controllers used in the stations of distributed loca=L-area-networks, reference is made to FIGS. 1 and 2.
In FIG. 1, a distributed local area network 100 is shown, comprising a plurality of stations (i.e. nodes 102A
through 102M) wh:LCh are operably connected to a communication medium 103, such as a cable. In FIG. 2, each station is shown to generally comprise a host processor (e. g., central processing unit or CF?U) 104, a program memory 105, a system memory 106, a communication controller 107, a system (i.e. CPU) ._0 bus 108, and a communication medium interface unit 109. The processor, program memory and system memory are each connected to a system bus :L08, and the system bus, in turn, is connected to communication controller 107, as shown. The communication controller is connected to the communication medium 103 by way .L5 of the communicai~ion medium interface unit. Typically, the communication medium interface unit is suitably adapted for the particular characteristics of the communication medium being employed in the network.
In gene=ral, communications controllers, and LAN
:?0 controllers in particular, are usually integrated into a system architecture and software environment by providing the means for supporting t~NO independent data queues in software: a transmit queue and a receive queue. Each queue is associated with a process, namely, the transmit process and the receive :?5 process, of the :Low-.Level software communications driver.
The tr~~nsmit queue holds the elements that the software intends to t=ransmit. In a packet-switched environment of a local area :network, these elements are usually data packets that include a clock of data to be transmitted and some :30 associated information like the destination for the block of data. The receive queue holds the elements that the station has received, ag<~in usually packets containing a block of data and associated information identifying the sender of the data block.
Elemeni~s are added to the transmit queue by the software driver ~ahenEwer the host processor needs to transmit information. Elf~ment;s are removed from the transmit queue after successful transmission is assumed. Removal of these elements from the=_ transmit queue can be done either by the low-level software d=river or by the communication controller.
.LO Elements are added to the receive queue by the communication controller whene~;rer a relevant data packet is received.
Elements are removed from the receive queue by the low-level software driver upon processing the packet.
The transmit and receive queues that are managed by :L5 software in syst~=_m memory, eventually meet the communication controller. The interface between the queues and the communication co.ztroller determines the behavior of the queues during the addition of receive elements and removal of transmit elements.
:?0 Management of the transmit and receive queue elements at the level of the communication controller has been attempted in a variety of ways.
One type o.f prior art communication controller employs queues f~~r transmit and receive commands while storing :Z5 corresponding data packets in a data packet buffer memory associated with the communication controller. Representative of this type of :priorr art is the 90C66 Communication Controller from Standard Microsystems of Hauppauge, N.Y.
Using an a:Ltogether different technique than the 30 command queuing scheme described above, the prior art has sought to extend the transmit and receive data queues into the communication control_1~?r by simulating transmit and receive data queues in the data packet buffer memory of the communication contro7.l~~r. In general, there have been several different approaches to implementing this generalized memory management technique.
For example, according to one approach, many transmit and receive data elements can be managed as a "ring buffer", in which the data packet :buffer memory is configured as a number ._0 of memory element=s which can be sequentially allocated and accessed. Prior art representative of this approach includes the 8390 NIC Comrnunic:ation Controller from National Semiconductor Co_=poration, Santa Clara, Calif. and the Etherstar° Ethernet Communications Controller from Fujitsu ._5 Corporation.
An altc~rnat:ive approach for simulating transmit and receive data queues at the communication controller level, involves linking together a disjointed array of memory storage locations using <~ddress pointers compiled in accordance with a :?0 "linked list". Ln order for the link-list communication controller to find the memory storage location where a packet begins, as well <~s the storage locations where each one of the buffers (compris:ing a packet) begins, the software driver must perform a number of computations. Prior art representative of ;?5 the above type d~=_vice includes the 82586 and 82596 Communication Controllers from Intel Corporation, Santa Clara, Calif.
Notably, de=_spite the approach employed in simulating transmit and rec~=ive data queues at the communication :30 controller level, bot=h the host processor (i.e. CPU) and the medium access co:ztrol (MAC) unit must write and/or read a "packet" of data into 'the data packet buffer memory associated with the communication controller. Such memory access operations involjre movement of a byte of data at a time into or out of the data packet buffer memory, and typically a number of memory access operations are required for writing or reading a single data packet.
If. the host. ;processor wishes to transmit a data packet to a remoi~e node in the network, it must access the data packet buffer memory and write a packet of data into a selected .LO portion thereof. Then a transmit request or command is provided to the medium access controller instructing the medium access control unit where to transmit the buffered data packet when it is free 1~o do so. When the medium access control unit is ready to tran;~mit the buffered data packet, it accesses the :L5 data packet buffer memory and reads the buffered data packet therefrom and tr;~nsmits the data packet over the communication medium to its destination.
Similarly, when a receive request is stored within the communicatio:r~ controller a remote node transmits a data :?0 packet to the host processor over the network communication medium, then the medium access control unit can receive the data packet, access l~he data packet buffer memory and write the received data packet into a selected portion thereof.
Thereafter, the :host processor is issued an interrupt to advise :05 that a data packet h<~s been buffered in the data packet buffer memory and is ready to be received by the host processor. When the host processor is free, it then accesses the data packet buffer memory, reads the received data packet out therefrom and places it into the data packet receive queue maintained in 30 software.

Notably, the storage locations in the data packet buffer memory for each particular transmitted and received data packet can be predetermined, or dynamically assigned by the communication contro7_ler as needed. However, both the host processor and the medium access control unit must operate asychronously wit=h respect to each other and the data packet buffer memory. c~onsE~quently, the host processor and the medium access control unit will naturally access the common data packet buffer memory in an asynchronous manner while either .LO transmitting or :receiving data packets. While a single-port data packet buffer memory is preferred in terms of cost and manufacture, simultaneous memory accessed by these asynchronous processors will ~~ause contentions in time for memory access through the sing:Le-port, typically resulting in loss of data .L 5 and t ime .
While <~ dual-port data packet buffer memory obviates memory contention problems, this approach is often undesirable over a single-port st=ructure for economic and manufacturing considerations.
:?0 Thus, there is a great need in the art for a way to provide the host processor and medium access control unit transparent access to a single-port data packet buffer memory operably associated i~herewith.
OBJECTS AND SUMMARY OF THE PRESENT INVENTION
;05 Accordingly, it is a primary object of the present invention to provide a method and apparatus which permits two memory accessing processors, such as the host processor and medium access contro:L unit of a communication controller, to transparently access a single-port memory storage device 30 associated with the communication controller.

It is a further obj ect to provide such a method and apparatus in the form of a synchronous memory access control circuit within a communication controller having a single-port RAM data packet buffer memory. In the illustrated embodiment, the communication controller with the single-port RAM buffer memory and t:he memory access control circuit are all implemented on a single semiconductor integrated circuit (IC) chip. In operation, the memory access control circuit allows both the host prcces~~or and the medium access control unit to ._0 access the singlf~-port memory buffer while operating at full specified operating :peed, and without interference between simultaneous memory access requests. The memory access control circuit arbitrates asynchronous memory access requests from both the host prc~ces:~or and the medium access control unit, .L5 while permitting each of these processors unlimited access to the single-port buffer memory as if it alone had the full memory available to itself at all times. As a result, the single-port bufff~r memory appears to be of a dual-port design while physically a s_Lngle-port structure.
:?0 Another object of the present invention is to provide such a synchrono»s memory access control circuit, in which memory storage locations for data bytes to be stored are indirectly acces;~ed by the host processor and the medium access control unit, or the address generating unit acting on behalf :?5 of the memory ac~~essing processor. In this way, when buffering each data packet byte into the data packet buffer memory, the host processor o:r thE~ medium access control unit need only provide to a designated port in the memory access control circuit, (i) the data byte to be stored, (ii) the selected :30 address of the c~~rre:~ponding memory storage location, and (iii) a memory write request. Then whenever, the host processor or the medium access control unit returns to the memory access control circuit t:o wx-ite another data byte into the single-port buffer memory, the previous memory write request will always be executed.
Similar=ly, when retrieving each data packet byte stored in the dat=a packet buffer memory, the host processor or the medium acces:~ control unit need only ensure that a memory read request and the address of the memory storage location of the data byte, bc= provided to a designated port in the memory access control unit. Then, whenever the host processor or the .LO medium access contro7_ unit returns to the memory access control circuit to read another data byte out of the data packet buffer memory, the next data byte within the retrieved data packet will have been p=refet:ched from the data packet buffer memory and buffered at i~he designated port for instantaneous reading.
:~5 When either writing or reading a number of consecutively stared data packet bytes into or out of the data packet buffer memory, the host processor or the medium access control unit need only write into the port of the memory access control unit the data packet memory address of the first data :?0 byte, and therea:Eter write or read the first data byte. For each consecutive data byte to be written into or read from the data packet buffer mE=_mory, the memory access control unit will automatically generat=e the next address, and if a memory read request has been made, automatically prefetches the :?5 corresponding data byte and buffers it at the respective port for reading.
These ,end other objects of the present invention will become apparent :hereinafter.
E~RIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, the dc~tai=Led description of the illustrated embodiment is to be taken in connection with the following drawings, in which:
FIG. 1 is a schematic representation of a local area network system p~=_rmit~ting a plurality of stations to access to a shared communi~~ation medium allocated in accordance with a network protocol;
FIG. 2 is a block functional diagram of a prior art :LO station within t:ze local area network of FIG. 1, showing the major components of t=he station; and FIG. 3 is a block functional diagram of a station provided with a ~~ommunication controller according to the present invention, showing functional subunits of the L5 communication co:ntro_Ller arranged with the synchronous memory access control unit of the present invention;
FIG. 4 is a high-level schematic representation of the synchronous wemo:ry access unit of the present invention, illustrating the major components thereof and the general data, :00 address and control :Flow between the memory access control unit, the host processor, the medium access control unit and the data packet buffer memory;
FIG. 5 is a low-level schematic diagram of the synchronous memory access control unit of the present 25 invention;
FIG. 5A is a. block functional diagram of the address pointer register/cou:nter unit employed in each of the port interface units shown in FIG. 5;

FIG. 6 is a high level flow chart illustrating arbitration of mf=mory access requests from the host processor and the medium ac~ces;~ control unit, and the general control flow carried out by t:he sequential controller in the memory access control unit of the illustrative embodiment;
FIG. 7A is a schematic representation illustrating four consecutive clock half pulses generated by the external clock provided t~~ the memory access control unit during each memory (i.e. RAM) access cycle carried out therein;
:LO FIG. 7l3 is a table which shows the binary values of the timing contr~~l and mode status signals provided to the CPU
and MAC decoders, for each of the four time intervals occurring during the RAM write and read cycles, and the binary valves of the various enable s:Lgnals provided to the port interface units L 5 and the RAM buf f ~?r mE=mory; and FIGS. 8A and 8B represent a schematic representation showing a plurality of consecutive clock pulse time intervals elapsing during ~cper<~tion of the memory access control unit of the present invention, and the location of time-slots created :~0 within the sequential controller for sensing the presence of memory access cycle :requests by both the host processor and medium access contro:L unit.
DETAILED DESC:RIPT:LON OF THE ILLUSTRATIVE EMBODIMENT OF THE
PRESENT INVENTION
25 Referring to FIG. 3, the communication controller of the present invention is illustrated. In general, communication controller 109 comprises CPU interface unit 2, synchronous memory access control unit 3, medium access control (MAC) unit 4, and MAC interface unit 5. Associated with the 30 controller is a data packet buffer memory 6, realized in the illustrative embodiment as a single-port static randomly accessible memory (RAM) storage device, well known in the art.
The access time of RAM buffer memory 6 will be referred to hereinafter as Tlnem access ~ As shown, CPU data bus 7 and control lines 8 interface CPU interface unit 2 with synchronous memory access control unit 3, whereas MAC data bus 10 and MAC control lines 11 interfa~~e MAC interface unit 5 with memory access control unit 3. RAM data bus 12, RAM address bus 13 and RAM
control bus 14 interface RAM buffer memory 6 with memory access :LO control unit 3. As illustrated in FIG. 4, memory access control unity 3 c~~mprises CPU port. interface unit 15, MAC port interface unit l~, and sequential controller 17. As shown, CPU
interface unit 2 is .interfaced with CPU port interface unit 15 by way of CPU data bus 7 and CPU control lines 8, whereas MAC
:L5 interface unit 5 is interfaced with MAC port interface unit 16 by way of MAC data bus 10 and MAC control lines 11. An external clock 1B having a clock pulse frequency F~lo~x=1/T~lo~x is provided to the sequential controller to provide a periodic time base for synchronous operations of the memory access 20 control unit. Although T~lo~k is 50 nanoseconds in the illustrative emb~~dimc~nt, it is understood that this time clock period will typically vary from embodiment to embodiment.
As shown in FIGS. 4 and 5, memory access requests RWCPu and RRCPU are issued by the host processor ( i . a . CPU) and are 25 provided from CPU port interface unit 15. In turn, these requests are provided to sequential controller 17 for servicing. Similarl~~, memory access requests RW~,c and Roc are issued by the medium access control unit and are provided from MAC port interface unit 16. In turn, these requests are 30 provided to sequenti<~1 controller 17 for servicing. The manner in which these four :requests are serviced will be described in great detail hereinafter. While memory access requests may be simultaneously presented to memory access control unit 3 by both host proces;~or 104 and medium access control unit 4, memory access contentions will never occur for reasons which will hereinafter become apparent.
CPU int=erface unit 2 generally comprises logic circuitry suitab:Le for interfacing the data and control lines of host system bits 108 with CPU port interface unit 15. Part of such logic ci:_cuit:ry will include decoding circuitry, in which digital sic~nal:~ on system address and control lines are :_0 processed to produce control lines 8, provided to CPU port interface unit 16. ~3imilarly, MAC interface unit 5 generally comprises logic circuitry suitable for interfacing the address, data and control lines of MAC system bus 9 with MAC port interface unit 1G. F?art of such circuitry will also include :L5 decoding circuit=ry, in which digital signals on MAC system address and control lines are processed to produce control lines 11, provided to MAC port interface unit 16. The function of control lines 8 and 11 will be described in greater detail hereinafter.
:?0 As illustrated in FIG. 4, CPU port interface unit 15 comprises RAM ad~3res;~ pointer register/counter unit 20A, host read data regist~=_r 2:LA, host write data register 22A and a data byte transfer me~~hanism mechanism 23A. In a symmetrical fashion, MAC porv~ interface unit 16 comprises RAM address :?5 pointer register/counter unit 20B, MAC read data register 21B, MAC write data r~~gist~er 22B, and a data byte transfer mechanism 23B. In the illv.zstrative embodiment where each data byte is an eight bit word, the :Length of each register 21A, 21B, 22A, and 22B is eight bits, a:Lthough it is understood that this length :30 can and will typical:Ly vary from embodiment to embodiment. The bit length of RAI~t address registers 20A and 20B will be set by the number of byte st~,orage locations afforded by RAM buffer memory 6.
In acc~~rdance with the present invention, neither the host processor n~~r the medium access control unit directly access the data racket storage buffer 6. Instead, the host processor and th~~ medium access control unit are constrained to indirect accessing of data packet storage buffer 6 by either writing data bytes into or reading data bytes from their respective port interface units. As will be described in LO greater detail hereinafter with reference to FIGS. 5 and 6, this involves writing the RAM address into the pointer register/counter unii~ 20A or 20B. Then, after waiting for at least two memory aCCE?SS CyCleS (l..e. 2~Tmem access cycle SeCOndS~ t0 occur in memory acce;~s control unit 3, the respective port interface unit is once again accessed and a corresponding data byte is either written into the write data register or the corresponding data b~~te is read out of the read data register in the respective port interface unit. Thereafter, the memory access request is executed in a synchronous manner within the z0 2~Tmem access cycle second time period. During the execution of memory access cycles, RAM data, address and control buses 23, 24 and 25 are used to effect addressing and data transfers between RAM buffer merr~ory 6 and port interface units 15 and 16.
When the host processor or medium access control unit returns with another memory access request, the previously placed request will have been. automatically executed without delay.
Thus, by SatlSfylng S~1'Stem COristralnt Tport access~2'Z'mem access cycle, memory access control unit 3 guarantees that both the host processor and the medium access control unit are provided collision-free access to RAM buffer memory 6.

In ordf~r to appreciate the function and capabilities of pointer regisi:er/c:ounter units 20A, 20B and mechanisms 23A, 23B, a brief desc~ript;ion of the operation of memory access control circuit :3 during both the read and write modes of RAM
access will be p=rovided below with reference to FIG. 4 in particular.
When the host processor desires to write a data byte into RAM buffer memory 6, the host processor writes the RAM
address of t=he data byte into RAM address pointer .LO register/counter unity 20A. Then, after waiting at least 2~Tmem access cycle second '~~ime period, the host processor places the corresponding da~~a b~rte into host write data register 22A of the CPU porn into=_rface unit. In a synchronous manner, sequential controller 17 detects the RAM write request RWCPu :L5 during the next memory access time window created by the sequential contr~~ller_, and completely executes the request within two clock pul;~e periods ( i . a . 2~T~lo~x) .
The memory 6 access request RWCPU is generally carried out by the following controlled sequence of operations. First, :?0 the address in p~~inter register/counter unit 20A is provided to RAM buffer memory 6 by way of RAM address bus 24. Then RAM
enable signals a:re generated by the sequential controller and provided to RAM :buffer memory 6, to transfer the data byte in host write data :regi:~ter 22A over data bus 23 and into the :?5 addressed storage location in buffer memory 6. If the host processor selected automatic address incrementing at the time of writing the previous address into pointer register/counter unit 20A, then t:he Ri~M address value in this register will be incremented to t:he nc=_xt consecutive address value, 30 corresponding to the next data byte within the data packet being transmitted. 'Then when the host processor returns to the CPU port interface unit to write the next data byte into host write data byte regi:~t~er 22A, the corresponding address value will have been automatically loaded into pointer register/counter unit: 20A. The sequential controller, sensing (i.e. detecting) once again memory access request RWCPU, automatically exf~cutes memory access request RWCPU during the next memory acce;~s cycle, as described above.
When the host processor desires to read a data byte from RAM buffer memory 6, the host processor writes the :~0 corresponding RAT~I address into pointer register/counter unit 20A. Then after 2~TmE.m access cycle seconds when the host processor reads host read data register 21A, the addressed data byte will have been automal~ically read from buffer memory 6 and preloaded into host read data register 21A (i.e. data byte prefetching).
.L5 This automatic p:refet:ching of the addressed data byte is achieved by data byte transfer mechanism 23A carried out by the sequential controller and occurs automatically during the awaited time period of 2~Tmem access cycle. The reading of the addressed data byte from buffer memory 6 is generally carried :?0 out as follows. Fir:~t, the address in pointer register/counter unit 20A is provided to RAM buffer memory 6 by way of address bus 24. Then RAI~i en<~ble signals are generated by the sequential contr~~ller and provided to RAM buffer memory 6 so as to transfer the ~3ata byte stored in the address storage :Z5 location over RA1~I dai:a bus 23, and into host read data register 21A of the CPU pert .interface unit.
If the host: processor selected automatic address incrementation at thE= time of writing the previous address into pointer register/counter unit 20A, then after carrying out the :30 data byte prefetching operation, the RAM address value in the pointer register/counter unit 20A will be automatically incremented to the next consecutive address value, which corresponds to the next data byte within the data packet being retrieved from R~~M buffer memory 6. Then when the host processor return; to t:he CPU port interface unit after 2~Tmem access cycle seconds or 1_ater, the next data byte in the packet will have been automatically preloaded into read data register 22A, for reading by t:h~~ host processor.
The RAP~t write and read operations described above in connection with the host processor occur in identically the ~_0 same manner for the medium access control unit, as the structure and function of MAC port interface unit 16 is similar to the structure and function of CPU port interface unit 15.
Having described the structure and operation of the memory access contro7_ unit at a high level of representation ._5 afforded by FIG. 4, a detailed description thereof will now be provided with re:Eerence to FIGS . 5 and 6 .
As illustrated in FIG. 5, CPU port interface unit 15 comprises an arrangernent of components, namely RAM address pointer register/counter unit 20A, host read data register 21A, :?0 host write data :regi:~ter 22A, address pointer latch 27A, write request storage c=lement 28A, read request storage element 29A, AND gate 30A, OR gate 31A and inverter 32A. The structure and function of each of t:hese components will be described below.
As sho~Nn in FIG. 5A, pointer register/counter unit :?5 20A comprises an address pointer register 34A, a first control bit register 35A and a second control bit register 36A
configured as sh«wn. N lines of CPU data bus 7 are connected to the input of ;~ddre~ss pointer register 34A for transfer of RAM address bits. Also, one line of data bus 7 is connected to :30 the input of first control bit register 35A for transfer of a first control bit., B1, which in the illustrated embodiment functions to indicate selection of automatic address incrementation. Also shown, another line of data bus 7 is connected to the input of second control bit register 36A for transfer of a second control bit, B2, which in the illustrated embodiment functions to indicate selection of the RAM read mode, or the RAM write mode. Arbitrarily, BZ=1 indicates selection of the RAM read mode.
As illustrated in FIG. 5A, write pointer enable line ._0 HwPE is provided i~o the data load input of address pointer register 34A to c~nab7_e the loading of RAM address for buffering as shown. Automatic address increment bit B1 is provided to the "auto increment enable" input of address pointer register/counter 34A.. As shown, an address increment enable :L5 line EpINC from the sequential controller is provided to the "counter increment" (i.e. clock) input of address pointer register 34A. The output of address pointer register 34A is connected to RAM address bus 24A. Read mode enable line ERMODE
from the output c~f control bit register 36A is provided to the :?0 second input of ~~ND gate 30A and also to the input of inverter 32A, as described above.
As ill~.~strated in FIG. 5, CPU control lines 8 comprise write p~~inte~r enable (i . e. strobe) line HgpE, read pointer enable line HRI?E, read data enable lines HRDE, and write :?5 data enable line HWDE. As described hereinafter, these lines emanate from an ,~ddre~ss decoder within CPU interface unit 2 and convey strobe si~~nal:~ provided by the host processor or by an address management unit operating under the direction or on behalf of the host processor. Specifically, write pointer :30 enable line HWpg 1S p:rovided to the "load enable" input of pointer register/counter unit 20A. As shown, line HWPE is also provided to the input. of AND gate 30A and to the input of OR
gate 31A. The output: of AND gate 30A is provided to a first "flag set" input of x-e.ad request storage element 29A, which can be realized as a flip flop circuit. The output of read request storage element 29A, i:n turn, reflects whether a RAM read cycle request RRCPU has been. made by the host processor ( i . a . CPU) .
Also as shown, the output of OR gate 31A is provided to the "open" control input of address pointer latch 27A to selectively open the same in response to the presence of the :~0 first occurrence of a high level signal at the open control input after the <~ddrExss pointer latch has been closed. The read mode enable line EgMODE from pointer register/counter unit 20A, is provided to the second input of AND gate 30A, and also to the input of :inverter 32A, with the Output thereof provided :L5 to a second inpu~~ of OR gate 31A.
As ill,.zstrated, read pointer enable line HRpE 1S
provided to the "output enable" input of address pointer latch 27A. When line l-IRpg .Ls strobed, the contents of address latch 27A may be read '.ey the host processor over CPU data bus 7.
:?0 Read data enable line HRDE is provided to the "output enable"
input of host re,~d data register 21A for enabling the reading of a data byte stored therein by the automatic byte prefetching mechanism, to be described hereinafter. As shown, read data enable line HgDE is provided to the third input of OR gate 31A, :?5 and also to a second set request input of read request storage element 29A. The write data enable line Hr~DE 1S provided to the "load enable" input of host write data register 22A, and also to the "request-set" input of write request storage element 28A
which can also be re<~lized by a flip flop circuit. Notably, 30 the output of write :request storage element 28A reflects whether a RAM write cycle request RWCPU has been made by the host processor.

The structure of MAC port interface unit 16 is identical to the CPU port interface unit as described above.
For example, MAC port: interface unit 16 comprises an arrangement of components, namely RAM address pointer register/counter unit :20B, host read data register 21B, host write data regist:er 228, address pointer latch 27B, write register storage element 28B, read request storage element 29B, AND gate 30B, OR gatE: 31B and inverter 32B.
As shown in fIG. 5A, pointer register/counter unit =_0 20B comprises an addx-ess pointer register 34B, a first control bit register 35B and a second control bit register 36B operably configured in a rnannE:r identical to pointer register/counter unit 20A described ak>ove. As with CPU port interface unit 15, an automatic add==ess increment bit B1 and a read mode select bit ._5 BZ are provided over separate lines of MAC data bus 10 to the data input port of control bit registers 35B and 36B, respectively, whale RAM address bits are transferred to the data input of adc3res~~ pointer register 34B. Write pointer enable line MWpE :is provided to the data load enable input of :?0 address register/counter 34B to enable the transfer of RAM
address and control bits thereinto for buffering as shown.
Automatic addres;~ increment bit B1 is provided to the "auto increment enable" input of address pointer register/counter 34B. As shown, an address increment enable line EAINC from the :?5 sequential contr«ller is connected to the "address increment"
input of address pointer register/counter 34B, for incrementing the RAM address ~~oint:er in register/counter 34B, in response to signals provided from the sequential controller. The output of RAM address poinver register 34B is connected to RAM address :30 bus 24A. Read m«de enable line ERMODE from the output of control bit register 35 .is provided to the second input of AND gate 30B
and also to the inputs of inverter 32B.

As illustrate=_d in FIG. 5, MAC control lines 11 comprise write pointer enable line MWPE read pointer enable line MRpE, read data enable :Line MRDE and write data enable line MWDE.
As described hereinabove, these lines emanate from a decoder within MAC interface unit 5 and convey strobe signals provided by the medium adc3resa control unit or an address management unit operating under the direction or on behalf of the medium access control unit. Specifically, write pointer enable line MwpE 1S provided too the "load enable" input of address pointer 7.0 register/counter unit: :20B. As shown, line MWPE is also provided to a first input of AI~TD gate 30B and to a first input of OR
gate 31B. The output: of AND gate 30B is provided to a first "request-set" input of read request storage element 29B, which can be realized as a flip flop circuit. The output of read 7.5 request storage element 29B, in turn, reflects whether a RAM
read cycle reque:~t RR~.,,~", has been made by the medium access control unit. A=Lso as shown, the output of OR gate 31B is provided to the "open" control input of address pointer latch 27B to selective=Ly open the same in response to the presence of a:0 the first occurrence of a high level signal at the open control input after the address pointer latch has been closed. The read mode enable line .EgMODE from pointer register/counter unit 20B, is provided to t:he second input of AND gate 30B, and also to the input of :inverter 32B, with the output thereof provided 25 to the second input of OR gate 31B.
As illizstrat~~d, read pointer enable line Mgpg 1S
provided to the output enable input of address pointer latch 27B. When line P~IRDE is strobed, the contents of address latch 27B may be read i=o the medium access control unit over MAC data .30 bus 10. Read dai~a enable line MRDE 1S provided to the "output enable" input of MAC read data register 21B for enabling the reading of a date byte stored therein by the automatic data byte prefetching mechanism, to be described hereinafter. As shown, read data enablf=_ line MgDE is also provided to the third input of OR gate 31B, <~nd also to a second "request-set" input of read request :~torag~° element 29B. The write data enable line MWDE 1S provided to the "load" input of host write data register 228, and al~~o to the "request-set" input of write request storage E'lemen't 28A, which can also be realized by a flip flop circuit. DTotably, the output of write request storage element :?8B reflects whether a RAM write cycle request =_0 RW~~ has been made by t:he medium access control unit.
As illustrated in FIG. 5, sequential controller 17 also comprises a number of subcomponents, namely request arbitration logic 38, time-slot synchronizers 39A and 39B, OR
gates 40A and 4013, request storage registers 41A and 41B, .L5 timing signal generators 42A and 42B, OR gate 43, decoders 44A
and 44B, OR gate; 45A and 45B, and RAM address multiplexer 46.
The structure and function of these components will be described below.
As shown FIGS. 5 and 7A, external clock 18 generates :?0 clock pulses having a half period of 1/2~T~lo~x seconds, and a full clock period of T~lo~x seconds. In the illustrative embodiment, the time period T~lo~x is about 50 nanosecond. This periodic clock signal is provided to time-slot synchronizers 39A and 39B, as well as timing control signal generators 42A
:Z5 and 42B, as shown. :3ynchronizers 39A and 39B, realizable as a combination of flip :Flop circuits, create time-slots or "windows" through which request arbitration logic unit 38 can sense, via OR gates 40A and 40B, whether at least one of the request storage elemc=_nts 28A, 28B and/or 29A, 29B contains a 30 request. In this wa~~, request arbitration logic 38 is capable of determining whether' a memory access request has been made by the host processor an.d,~or the medium access control unit. As will be described in greater detail hereinafter, each "time-slot" created by synchronizers 39A and 39B occurs periodically at the beginning of each new clock period nT~lo~k as illustrated in FIG. 8.
In order to obtain RAM write cycle request RWCPU or RAM
read cycle reque:>t RRCPZ1 for use by decoders 44A and 44B during the duration of each memory access cycle ( i . a . Tmem access cycle) , the output of read request storage element 29A is provided to the "request-set" input. of request storage element 41A, realized in the illu~,trative embodiment as a toggle circuit.
The output of the writE=_ request storage element 28A is provided to the "reset" input of request storage element 41A. The output of request: stor<~ge element 41A is either RAM read cycle 1.5 request RRCPU or RAM write cycle request RWCPU, and is provided to decoder 44A by w~iy of .read/write line, R/WA. If request storage unit 41A contain: RANI .read cycle request RRCPU, then the signal level on line R/WA will. be a logical "1", whereas the signal level will be a 7_ogica:l "0" if request storage element 41A
~ 0 contains RAM write re: quest RwcPU.
Similarly, to retain RAM write cycle request RW~c or RAM read cycle request RR~c for use by decoder 44B during the duration of each memory access cycle, output of read request storage element ~?9B i.s provided to the "request-set" input of a;5 request storage Eelement 41B, also realized in the illustrative embodiment as a t;oggl.e circuit. The output of the write request storage element 28B is provided to the "reset" input of request storage elemE:nt 41B. The output of request storage element 41B is euther hAM read cycle request RRruc or RAM write cycle request Rw~,~c, and is provided to decoder 44B by way of read/write line, R/WH. If request storage unit 41B contains RAM

read cycle reque~~t RR,~c, then the signal level on line R/WB will be a logical "1", wherE~as the signal level will be a logical "0" if request st:orag~e element 41B contains RAM write request cyc 1 a RW~c .
As illustrated in FIG. 5, request arbitration logic 38 determines whether any memory access requests have been made within each time-slot created by synchronizers 39A and 39B. If only a memory access request has been made by the host processor, then this condition is indicated by providing enable 1.0 signal EcPU=1. to timing control signal generator 42A. In response, operation of timing control signal generator 42A is enabled, and wil7_ rerria:in enabled for the next four half clock cycles, i.e. 2~T~lo~k seconds as illustrated in FIG. 7A. Timing control signals produced from timing control signal generator 1.5 42A during the four ha:if clock cycle time period, depend solely on time interval: T1, T2, T3, T4. As shown, timing control signal generator 42A gc=_nerates the following signals: (i) timing control signals C1A and C2B which are provided to decoder 44A; (ii) request: flag reset signal FRESETA which is provided to a;0 the reset input of read and write request storage elements 29A
and 28A; and (iii) address increment enable signal EArrrcA which is provided to the increment input of address pointer register/counter 20A and to the "close" input of address pointer latch 27A. F~l;so, timing control signal CzA is provided a;5 to a first input of C>R gate 43 which provides as an output, the RAM enable signa=_ to E,~ RAM buffer memory 6.
The function of request arbitration logic 38 and timing control sugnal. generator 42B for memory access requests made by the medium ac:c~~ss control unit is similar to the _~0 function of request arbitration logic 38 and timing control signal generator 42A for memory access requests made by the host processor. For example, if only a memory access request has been made by the medium access control unit, then this condition is indicated by providing enable signal E~~=1 to timing control s:igna7_ generator 42B. In response, operation of timing control s:~gna7_ generator 42B is enabled, and will remain enabled for the next four half clock cycles, i . a . 2~T~lo~x seconds as illustrated in FIG. 7A. Timing control signals produced from timing cont:rol ~~ignal generator 42B during the four half clock cycle time period, depend solely on the time intervals T1, .LO T2, T3, or T.~. A;~ shown, timing control signal generator 42B
generates the fo:Llow_Lng binary level signals: (i) timing control signals C1H a:nd C2B which are provided to decoder 44B;
(ii) request flag re;~et signal FRESETa which is provided to the reset input of rE=ad and write request storage elements 29B and :L5 28B; and (iii) ac~dre:~s increment enable signal EAZNCB which is provided to the :increment input of pointer register counter 20B
and to the "clos~=" input of address pointer latch 27B.
If, ho~Never_, a memory access request is made by both the host process~~r and the medium access control unit during ;?0 the same tune-sl~~t or window created by synchronizers 38A and 38B, then as ill-astrated i.n blocks C and D of the flow chart of FIG. 6, the host processor request is accorded priority while the request placed by the MAC unit must wait one memory access cycle time perlo~~ Tmem access cycle for execution. Notably, however, :?5 as long as the pert access time TCpU port access of the host processor and the po:rt access time T~~ port access of the medium access control unit are greater than or equal to 2~Tmem access cycle then both the host processor and the medium access control unit will be guaranteed transparent, collision-free access to R.AM
30 buffer memory 6. Also, the fact that host processor requests have been accorded priority over those of the medium access control unit, is purely arbitrary. Instead, memory access requests made by the medium access control unit can be accorded priority over those of the host processor with equivalent performance obta=_ned b~~ the memory access control unit of the present invention.
As illustrated in the schematic diagram of FIG. 5, decoders 44A and 44B each produce four binary level enable signals, namely read data register enable signal ERDR, write data register enable signal EwDR, RAM write enable signal ERwE, and RAM read enable :signal ERRS. As shown, read data register 7_0 enable signal ERDR from decoder 44A is provided to the "load enable" input of host :read data register 21A, whereas write data register enable signal EwDR from decoder 44A is provided to the "output enab=Le" input of host write data register 22A. RAM
write enable signal ERwE from decode 44A is provided to a first 7_5 input of OR gate 45A, whereas RAM read enable signal ERRS from decoder 44A is provided to a first input of OR gate 45B.
Similarly, read data register enable signal ERnR from decoder 44B is provided too the "load enable" input of read data register 21B, wherea:~ 'write data enable signal EwDR from decoder a?0 44B is provided 1.o the "output enable" input of MAC write data register 22B. R~~M wz-ite enable signal ERws from decoder 44B is provided to a second input of OR gate 45A, whereas RAM read enable signal ERRS from decoder 44B is provided to a second input of OR gate 45B. The outputs of OR gates 45A and 45B, in :?5 turn, are providf~d to write and read enable inputs, respectively, of RAM buffer memory 6.
As sho~Nn in FIG. 5, RAM address bus 24A is provided to a first set o:E inputs of address multiplexer 46, whereas RAM
address bus 24B :is provided to a second set of inputs of 30 address multiple:~er 46. Address bus 24A is normally passed through multiple:~er 46 and onto the address inputs of RAM

buffer memory 6. In order to connect address bus 24B to the address inputs of: RAMP buffer memory 6, enable signal EB~D=C1B
from timing control signal generator 42B is provided to the control input of multiplexer 46, as shown. Thus, when C1B=1 during MAC initiated memory access cycles, address bus 24B will be automatically connected to the address inputs of RAM buffer memory 6. Taken togeaher, enable signals ERRS, ERwE and E~, comprise control bus 25 illustrated in FIG. 4.
As illustrated in FIGS. 7A and 7B, the actual binary 1.0 levels that each of t.hE=_ four enable signals ERDR, EWDR/ ERwE and ERRE take on during each of the four time intervals T1, T2, T3, T4 of each RAM write and .read cycle, depend on the status (i.e.
binary value) of the taming control signals C1 and C2 and the read/write reque:~t signal R/W during time intervals T1, T2, T3, 1.5 and T4. For simplicity, the designations "A" and "B" are omitted.
The structure=_ and function of the synchronous memory access control unit of the illustrative embodiment has been described in detail above. It is now proper at this junction a;0 to describe its operation during each of the four possible RAM
access cycles synchronously executed by the memory access control unit when write and/or read cycle requests are made at port interface unit 1.5 by the host processor and at port interface unit lE> by the medium access control unit.
25 For purposes of exposition, it is best to describe how the memory acces:~~~ontrol unit operates when the host processor and the medium access control unit have both simultaneously p=Laced memory access requests to control unit 3 during the same time--slot created by time-slot synchronizers a0 39A and 39B. As illustrated in FIG. 8A, periodic clock pulse intervals of length T~l.o~x are created one after the other by clock 18. However, in the illustrated embodiment, time-slots for request sensing (e.g. sampling) are created only at the beginning of each new clock pulse interval, as shown. While these time-slots or windows have been selected to be relatively short in the illustrat=ive embodiment and involve arbitration request logic 38 making two samples of the output of OR gates 40A and 40B, the times windows may be of longer extent in other embodiments. Whet i~;.important to note for the particular illustrated embodiment, is that only the completion of both 1.0 address pointer writing and data byte writing will constitute an arbitration rEeque~;t for requested RAM write cycles, while merely completion of address pointer writing will constitute an arbitration request f:o=r requested RAM read cycles. For the purposes of illu:~trat.ion, the situation where a RAM write cycle 1.5 request is made by the host processor and a RAM read cycle request is made by the medium access control unit, will be considered below.. Iriil~ially, all request storage registers are reset (i.e. cleared).
For the host processor to place a RAM write cycle request during a particular time-slot, for example, as indicated at 50 ._n FI:G. 8A, the host processor must previous to this time-slot, placEel~AM address and control bits B1 and B2 onto data bus 7 j=or a ,sufficient set up time, and then strobe write pointer enable line Hy~pg. For purposes of illustration, a5 automatic addres;~ increment mode is selected by setting control bit B1=1, and the write cycle mode is selected by setting read mode control bit B2=0. The data bus 7 is kept stable for a sufficient hold-t=ime period so as to write the RAM address and selected control bite into pointer register/counter unit 20A, >0 as hereinbefore <iescx~i:bed. Notably, these operations do not set the RAM read cycle request flag in read request storage element 29A, as data byte prefetching (i.e. preloading) by sequential controller =L7 is not necessary during a RAM write cycle. Notably, however, strobing the write pointer enable line HWPE causes t:he address pointer latch 27A to open, permitting the host processor to read the address loaded into address pointer regi~;tf=_r 34A.
After waiting at least the minimal port access time Tport access ~l.e. ~2~Tmem access cycle ~ the host processor returns t0 the CPU port interface unit and writes the corresponding data byte into host write data register 22A. This is achieved by 7.0 placing the data byte bits onto data bus 7 for a sufficient set-up time, strobind the write data enable line HWDE, and maintaining the data b,as stable for a hold-time sufficient to effect the writing of the data byte bits into register 22A.
Notably, the strobind action on line HwDE causes, at this time, 7_5 a RAM write request c:y~~le flag to be set within write request storage element :?8A. In turn, request storage register 41A is reset to retain write ~~ycle request RWCPU, while the output of OR
gate 40A indicates that a memory access cycle request has been made by the host processor. If at this time only the host a?0 processor has written a RAM write request, then at time-slot 50 request arbitrat=ion 7_ogic 38 will sense this request and commence execution of. a RAM write cycle as described above.
Now it is assumed for purposes of illustration that the medium acces;~ control unit makes a complete request at :?5 time-slot 50 to .read a data byte out of RAM buffer memory 6.
This would be achieved as follows. First, the medium access control unit pla~~es RAM address and control bits B1 and B2 onto data bus 10 for ~~ sufficient set-up time, and then strobes write pointer en<~ble line MWpE. For purposes of illustration, :30 the automatic addres;~ increment mode is selected by setting control bit B1=1 and the read cycle mode is selected by setting read mode control. bit BZ=1. Data bus 10 is kept stable for a sufficient hold-tame period so as to write the RAM address and selected control bits into pointer register/counter unit 20B, as hereinbefore described. Notably, the operation of strobing write pointer en~~ble lane MWPE causes a read request flag RR~c to be set in read rEeque~;t storage element 29B, as read mode enable signal ERMODE to t:ze input of AND gate 30B is a logical "1" . At the same time, st:robi.ng line MWPE causes address pointer latch 27B to open, permitting the medium access control unit to read 1.0 the address loaded into RAM address pointer register 34B.
If after the occurrence of the above-described asychronous events, a RAM read cycle request flag RR~c and a RAM
write cycle requE:st flag RwcPU are both set in request storage elements 29B and 28A during time-slot 50 illustrated in FIG.
7.5 8A, the synchronous memory access control unit processes these simultaneous memory access requests as follows.
As ind_LcatE:d at block A of FIG. 6, all memory access requests are init:iall_y cleared from storage registers 28A, 28B, 29A and 29B. As indicated in FIG. 7B, resetting of request 20 flags by flag re:~et :signal EFRESETS occurs during the transition from time interval T1 t:o Tz in each executed memory access cycle. Then, as indicated at block B in FIG. 6, request arbitration logi<~ 38 senses the output of OR gates 40A and 40B
and determines whether any memory access requests have been a?5 made during time-slot: 50, schematically illustrated in FIG. 8A, Then as indicated at block C, request arbitration logic 38 determines whether the request is solely from the host processor, (i.e. CPU) or from both the host processor and the medium access contro:_ unit.
:30 If req»est:~ are made by both the host processor and the medium acces;~ control unit or simply the host processor, then as indicatecl_ at block D in FIG. 6, the contents of request storage register 41A are anaylzed by decoder 44A in order to determine whethex- a RAM read cycle request RRCPU or a RAM write cycle request RWC,~u ha:~ been made during time-slot 50.
Arbitration logic: 38 and clock 18, cooperatively cause timing signal control generator 42A to produce timing control signals (C1A and C2A, a.g.) over the next four clock half cycles (i.a.
2~T~xo~x) . The tinning control signals and read/write signal R/WA
in turn, cause decoder 44A to generate enable signals that 1.0 effect a RAM write c~~c:Le to occur during time intervals T1 through T4, illustrated in FIG. 8B. The particular binary values of the various>;signals produced during this memory write cycle are summaruzed in FIG. 7B. Notably, after the first time interval T1, automatic address increment signal EAZNCa is set to 7.5 logical "0" to cause the next consecutive address value to be written into address pointer register 34A while closing address pointer register 27A during time intervals Tz, T3 and T4.
If., however, RAM read cycle request RRCPU was made by the host processor instead of request RWCPU, a RAM read request 20 cycle would have been ~~arried out by the sequential controller, resulting in the pref=etching of the addressed data byte from RAM buffer memor~r 6. 'Thereafter, as indicated at block G in FIG. 6 request f=lags set in request storage elements 28A and 29A are cleared. At block H, arbitration request logic 38 <?5 determines whether a memory access cycle request was made by the medium acces:~ control unit during time-slot 50. If not, then the sequential c:o:ntroller returns to block B, as shown.
If, however, a rc~que:~t was made by the medium access control unit during time-slot, 50, then the sequential controller 30 proceeds to bloclt I. Notably, advancement to block I could have also occurrf~d ate block C upon an initial indication that only a request w~is made by the medium access control unit during time-slot 50.
As indicated at block C in FIG. 6, arbitration request logic 38 determines whether a RAM read cycle request RR~c or a RAM write cycle request RW~,c has been made during time-slot 50. Arbitration logic 38 and clock 18 cause timing signal control generator 42B to produce timing control signals (C1B and C2B, e.g. ) over the next four clock half cycles (i.e.
2~T~lo~x) . Control signals and read/write signal R/WB, in turn, cause decoder 44F3 to generate enable signals that effect a RAM
read cycle to occur during time intervals T1' through T4' , illustrated in F=:G. 8B. The particular binary values of the various signals during this memory read cycle are summarized in FIG. 7B. Notabl;r, af:t~=r the first time interval T1' , auto 7_5 address increment: sic3nal EArNCS is set to logical "0" to cause the next consecut:ive address value to be written into address pointer register 34B, while closing address pointer latch 27B
during time interval~~ 'Tz' , T3' and T4' . In this way, the previous address stoned in latch 27B can be read by the medium a?0 access control unit if desired. Address pointer latch 27B will not be opened unit a subsequent data byte preloaded into MAC
read data registE~r 21B, is read from. This latch opening operation allows loading of the address pointer of the (preloaded) read data :byte, into pointer latch 27B. The a?5 reading of the p~~efet:c.hed (i.e. preloaded) data byte initiates a subsequent dat<~ byte preloading operation, during which the pointer latch wi:Ll c7_ose and the address pointer will increment, as de:~cribed above. Consequently, a data byte read from read data rc~gist:er 21A or 21B by either the host processor _30 or the medium access control unit, respectively, will have been fetched from a R~~M st:orage location specified by the address previously read, and not the current address pointer value which is one address increment greater, to indicate the next byte to be prefet;ched.
If, however, a RAM write cycle request Rw~c was made by the medium access control unit instead of request RR~c, then as indicated at t~loc~: :K, a RAM write cycle would have been carried out by the sequential controller, resulting in the writing of data .into RAM buffer memory 6. Then, as indicated at block L, request f=lags set in request storage elements 28B
and 29B are clew=ed. 'Thereafter, the sequential controller ._0 returns to block B, as shown in FIG. 6.
After i~he RAM read cycle has been executed, the host processor and thE~ medium access control unit are free to make subsequent write and read cycle requests, respectively, having both previously ;yet automatic address increment bit B1 during .L5 the address poinl~er writing operations associated with simultaneous req~zest:~ placed during time-slot 50. Notably, both the host prc~ces:~or and medium access control unit are free to initiate RAM :read and write cycles respectively at any time thereafter, as long as neither party violates the access time :? 0 constraint : TACC>_2 Tmem cycle access . In any event , memory access requests detected during the time-slot at the beginning of each new clock pulse .interval, will be processed in general accordance with the control process illustrated in FIG. 6.
While the particular illustrative embodiment shown :?5 and described ab~we will be useful in many applications in communication co:ntro=Ller art, further modifications to the present invention he=rein disclosed will occur to persons skilled in the art. A11 such modifications are deemed to be within the scope and spirit of the present invention defined by 30 the appended claims.

CLAIMS:
1. A data communication controller fabricated on a semiconductor chip, comprising:
first c:onne~ction means for connecting said data communication control.lc=r to a system bus operably connected to a host processor second connection means for connecting said data communication controller to a communication medium;
a medium ac:c~=ss control unit, operably connected to 7_0 said second connection means, for controlling access of said data communication controller to said communication medium;
a memory access control unit providing said host processor and said medium access control unit synchronous access to a sing=Le-port common buffer memory having a plurality ._5 of data byte stop=age locations, said memory access control unit including a firsi~ access port including a first= address pointer register for storing an address specifying a storage location in said buffer memory, :?0 a firsl~ read data register for storing a data byte readable by said host: processor, a firs. write data register for storing a data byte written therein by said host processor, a first request storage means for storing memory read :Z5 or write cycle r~=que:~ts placed by said host processor, and first address incrementation means for automatically incrementing an address written into said first address pointer register by said host: processor, in automatic response to the execution of each memory read cycle request or each said memory write cycle requE~st, and a second access port including a second address pointer register for storing an address specifying a storage location in said buffer memory, a second read data register for storing a data byte __0 readable by said medium access control unit, a second write data register for storing a data byte written therein by said medium access control unit, a second request storage means for storing memory read or write cycle requests placed by said medium access .L5 control unit, anc3 second address incrementation means for automatically incrementing an address written into said second address pointer register by raid second medium access control unit, in response to the c=_xecution of each memory read cycle request or :?0 each memory writ.=_ cycle request; and a sync:zronous controller operably coupled to said first and second access ports and said single-port common buffer memory, a:zd having means for executing said memory read and write cycle :?5 requests, means for l~ransferring data bytes between said first read data register and said single-port common buffer memory and between said fir~;t write data register and said single-port common buffer memory, <~nd means f_or transferring data bytes between said second read data register and said single-port common buffer memory and between said second write data register and said single-port common buffer memory, said synchronous controller further including first rnean~~:for automatically detecting a memory read cycle request placed in said first request storage means by 7_0 said host proces;~or, and in response to the detection of a memory read cycle request, automatically reading the data byte storage location of ~~aid single-port common buffer memory specified by the address stored in said first address pointer register so as to retrieve a first data byte therefrom, and 7_5 loading said fir:~t data byte into said first read data register, second means for automatically detecting a memory read cycle reque:~t placed in said second request storage means by said medium a<~ces:~ control unit, and in response to the ~?0 detection of said memory read cycle request, automatically reading the data byte storage location of said buffer memory specified by the address stored in said second address pointer register, so as i~o retrieve a second data byte therefrom, and loading said second data byte into said second read data :?5 register, third mean: for automatically detecting a memory write cycle request placed in said first request storage means by said host processor, and in response to the detection of a memory write cyc:Le request, automatically accessing said first 30 write data regisv~er too access a third data byte stored therein, and writing said third data byte into the data byte storage location in said singlE=_-port common buffer memory specified by the address stored in raid first address pointer register, and forth mean; for automatically detecting a memory write cycle request pl<~ced in said second request storage means by said medium ac:cess~ control unit, and in response to the detection of a memory write cycle request, automatically accessing said second write data register to access a fourth data byte stored therein, and writing said fourth data byte into the data byte storage location in said single-port common buffer memory specified by the address stored in said second address pointer register.
2. The data communication controller of claim 1, wherein said first acces~~ port further comprises means for retaining, for at least one memory read or write cycle, each previous address which said fir;~t address incrementation means increments in said fir;~t address pointer register, and wherein said second access port further comprises means for retaining, for at least one memory read or write cycle, each previous address which said second address incrementation mE~ans increments in said second address pointer register.
3. The data communication controller of claim 1, wherein said synchronous controller comprises timing means for creating periodic time-slots, during which said synchronous controller automatically detects t:he memory read or write cycle requests stored in said first and second request storage means.

Claims (3)

1. A data communication controller fabricated on a semiconductor chip, comprising:
first connection means for connecting said data communication controller to a system bus operably connected to a host processor;
second connection means for connecting said data communication controller to a communication medium;
a medium access control unit, operably connected to said second connection means, for controlling access of said data communication controller to said communication medium;
a memory access control unit providing said host processor and said medium access control unit synchronous access to a single-port common buffer memory having a plurality of data byte storage locations, said memory access control unit including a first access port including a first address pointer register for storing an address specifying a storage location in said buffer memory, a first read data register for storing a data byte readable by said host processor, a first write data register for storing a data byte written therein by said host processor, a first request storage means for storing memory read or write cycle requests placed by said host processor, and first address incrementation means for automatically incrementing an address written into said first address pointer register by said host processor, in automatic response to the execution of each memory read cycle request or each said memory write cycle request, and a second access port including a second address pointer register for storing an address specifying a storage location in said buffer memory, a second read data register for storing a data byte readable by said medium access control unit, a second write data register for storing a data byte written therein by said medium access control unit, a second request storage means for storing memory read or write cycle requests placed by said medium access control unit, and second address incrementation means for automatically incrementing an address written into said second address pointer register by raid second medium access control unit, in response to the execution of each memory read cycle request or each memory write cycle request; and a synchronous controller operably coupled to said first and second access ports and said single-port common buffer memory, and having means for executing said memory read and write cycle requests, means for transferring data bytes between said first read data register and said single-port common buffer memory and between said first write data register and said single-port common buffer memory, and means for transferring data bytes between said second read data register and said single-port common buffer memory and between said second write data register and said single-port common buffer memory, said synchronous controller further including first means for automatically detecting a memory read cycle request placed in said first request storage means by said host processor, and in response to the detection of a memory read cycle request, automatically reading the data byte storage location of said single-port common buffer memory specified by the address stored in said first address pointer register so as to retrieve a first data byte therefrom, and loading said first data byte into said first read data register, second means for automatically detecting a memory read cycle request placed in said second request storage means by said medium access control unit, and in response to the detection of said memory read cycle request, automatically reading the data byte storage location of said buffer memory specified by the address stored in said second address pointer register, so as to retrieve a second data byte therefrom, and loading said second data byte into said second read data register, third means for automatically detecting a memory write cycle request placed in said first request storage means by said host processor, and in response to the detection of a memory write cycle request, automatically accessing said first write data request to access a third data byte stored therein, and writing said third data byte into the data byte storage location in said single-port common buffer memory specified by the address stored in raid first address pointer register, and forth means for automatically detecting a memory write cycle request placed in said second request storage means by said medium access control unit, and in response to the detection of a memory write cycle request, automatically accessing said second write data register to access a fourth data byte stored therein, and writing said fourth data byte into the data byte storage location in said single-port common buffer memory specified by the address stored in said second address pointer register.

2. The data communication controller of claim 1, wherein said first access port further comprises means for retaining, for at least one memory read or write cycle, each previous address which said first address incrementation means increments in said first address pointer register, and wherein said second access port further comprises means for retaining, for at least one memory read or write cycle, each previous address which said second address incrementation means increments in said second address pointer register.

3. The data communication controller of claim 1, wherein said synchronous controller comprises timing means for creating periodic time-slots, during which said synchronous controller automatically detects the memory read or write cycle requests stored in said first and second request storage means.