CA2079654A1 - Transmission circuit for transmitting fixed-length data - Google Patents

Transmission circuit for transmitting fixed-length data

Info

Publication number
CA2079654A1
CA2079654A1 CA2079654A CA2079654A CA2079654A1 CA 2079654 A1 CA2079654 A1 CA 2079654A1 CA 2079654 A CA2079654 A CA 2079654A CA 2079654 A CA2079654 A CA 2079654A CA 2079654 A1 CA2079654 A1 CA 2079654A1
Authority
CA
Canada
Prior art keywords
data
cell data
normal cell
output circuit
idle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2079654A
Other languages
French (fr)
Other versions
CA2079654C (en
Inventor
Yuji Takizawa
Masaaki Kawai
Hidetoshi Naito
Kazuyuki Tajima
Satomi Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Yuji Takizawa
Masaaki Kawai
Hidetoshi Naito
Kazuyuki Tajima
Satomi Ikeda
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yuji Takizawa, Masaaki Kawai, Hidetoshi Naito, Kazuyuki Tajima, Satomi Ikeda, Fujitsu Limited filed Critical Yuji Takizawa
Publication of CA2079654A1 publication Critical patent/CA2079654A1/en
Application granted granted Critical
Publication of CA2079654C publication Critical patent/CA2079654C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/40—Constructional details, e.g. power supply, mechanical construction or backplane
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5614—User Network Interface
    • H04L2012/5616—Terminal equipment, e.g. codecs, synch.
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/55—Prevention, detection or correction of errors
    • H04L49/557—Error correction, e.g. fault recovery or fault tolerance

Abstract

A transmission circuit transmits a normal cell data and an idle cell data via a communication line. The idle cell data is transmitted to fill time slots in the communication line at which there is no normal cell data to be transmitted, each of the normal cell data and idle cell data including first data, second data and third data. The first, second and third data of the normal cell data respectively indicating a destination, an error correcting code of the first data and desired information. The first and second data of the idle cell data have predetermined bit patterns and the third data of the idle cell data may have any arbitrary bit pattern. The transmission circuit includes a first output circuit for outputting the normal cell data, an error correcting code generator for generating the second data based on the first data of the normal cell data supplied from first output circuit, a second output circuit for outputting the first and second data of the idle cell data, a scrambler for scrambling the third data of the normal cell data supplied from the first output circuit and a selector for selecting one of the first output circuit, the error correcting code generator, the second output circuit and the scrambler in accordance with a predetermined order, so that the normal cell data and the idle cell data are output from the selector.
CA 2079654 1991-10-02 1992-10-01 Transmission circuit for transmitting fixed-length data Expired - Fee Related CA2079654C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP28207291A JP3051223B2 (en) 1991-10-02 1991-10-02 Cell transmission circuit
JP3-282072 1991-10-02

Publications (2)

Publication Number Publication Date
CA2079654A1 true CA2079654A1 (en) 1993-04-03
CA2079654C CA2079654C (en) 1998-04-07

Family

ID=17647768

Family Applications (1)

Application Number Title Priority Date Filing Date
CA 2079654 Expired - Fee Related CA2079654C (en) 1991-10-02 1992-10-01 Transmission circuit for transmitting fixed-length data

Country Status (4)

Country Link
US (1) US5515386A (en)
EP (1) EP0535982A3 (en)
JP (1) JP3051223B2 (en)
CA (1) CA2079654C (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6157967A (en) * 1992-12-17 2000-12-05 Tandem Computer Incorporated Method of data communication flow control in a data processing system using busy/ready commands
US5473696A (en) * 1993-11-05 1995-12-05 At&T Corp. Method and apparatus for combined encryption and scrambling of information on a shared medium network
JP3630460B2 (en) * 1995-01-23 2005-03-16 富士通株式会社 Data length correction system
DE69629758T2 (en) * 1995-06-07 2004-06-03 Compaq Computer Corp., Houston Method and device for monitoring the data flow in a fault-tolerant multiprocessor system
JP3301682B2 (en) * 1995-08-11 2002-07-15 松下電器産業株式会社 Packet output device
JPH09284299A (en) * 1996-04-16 1997-10-31 Toshiba Corp Communication control method and its device
TW343317B (en) 1996-05-01 1998-10-21 Casio Computer Co Ltd Document output apparatus
US5844885A (en) * 1996-06-11 1998-12-01 Qualcomm Incorporated Method and apparatus of providing bit count integrity and synchronous data transfer over a channel which does not preserve synchronization
JP2998150B2 (en) 1997-08-05 2000-01-11 日本電気株式会社 ATM cell descramble circuit
JP3429994B2 (en) * 1997-11-25 2003-07-28 沖電気工業株式会社 Cell buffer circuit
JP2001268089A (en) * 2000-03-17 2001-09-28 Fujitsu Ltd Atm cell service equipment and its method
US7054379B2 (en) 2000-10-16 2006-05-30 Broadcom Corporation Data scrambler generation of pseudo-random bit sequence for semi-stationary Q-mode signal
US20050160178A1 (en) * 2003-12-17 2005-07-21 Venables Bradley D. Adjusting shaped rates
JP4491587B2 (en) * 2004-11-26 2010-06-30 テクトロニクス・インターナショナル・セールス・ゲーエムベーハー Data generator
WO2012166100A1 (en) * 2011-05-27 2012-12-06 Halliburton Energy Services, Inc. Downhole communication applications
US9778389B2 (en) 2011-05-27 2017-10-03 Halliburton Energy Services, Inc. Communication applications

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4518960A (en) * 1982-11-23 1985-05-21 Burroughs Corporation Speed independent selector switch employing M-out-of-N codes
JP2865692B2 (en) * 1989-02-22 1999-03-08 株式会社日立製作所 Switching system and configuration method thereof
JPH01150940A (en) * 1987-12-08 1989-06-13 Hitachi Ltd Crc arithmetic system
US4958341A (en) * 1988-03-31 1990-09-18 At&T Bell Laboratories Integrated packetized voice and data switching system
US5237593A (en) * 1989-05-04 1993-08-17 Stc, Plc Sequence synchronisation
DE4004889A1 (en) * 1990-02-16 1991-08-22 Philips Patentverwaltung Asynchronous time division multiplex transmission system - with storage of incoming cells during comparison of path information for selecting outgoing line
DE4004956A1 (en) * 1990-02-19 1991-08-22 Philips Patentverwaltung Interface circuit for async. time division multiplex system - uses comparators in conjunction with multiplexes and buffers
CA2059396C (en) * 1991-01-16 1996-10-22 Hiroshi Yamashita Compact device for checking a header error in asynchronous transfer mode cells

Also Published As

Publication number Publication date
JPH0595366A (en) 1993-04-16
US5515386A (en) 1996-05-07
JP3051223B2 (en) 2000-06-12
EP0535982A2 (en) 1993-04-07
EP0535982A3 (en) 1997-03-26
CA2079654C (en) 1998-04-07

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Legal Events

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MKLA Lapsed