CA2081863C - Ripple-free phase detector using two sample-and-hold circuits - Google Patents
Ripple-free phase detector using two sample-and-hold circuitsInfo
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- CA2081863C CA2081863C CA002081863A CA2081863A CA2081863C CA 2081863 C CA2081863 C CA 2081863C CA 002081863 A CA002081863 A CA 002081863A CA 2081863 A CA2081863 A CA 2081863A CA 2081863 C CA2081863 C CA 2081863C
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- voltage
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- sampling
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
- H03D13/005—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which one of the oscillations is, or is converted into, a signal having a special waveform, e.g. triangular
- H03D13/006—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which one of the oscillations is, or is converted into, a signal having a special waveform, e.g. triangular and by sampling this signal by narrow pulses obtained from the second oscillation
Abstract
A phase detector comprises a ramp voltage generator for receiving a reference pulse of a constant frequency and an input pulse and producing a ramp voltage proportional to the phase difference between these pulses.
A first sample-and-hold circuit samples the ramp voltage in response to a sampling pulse and holds the sampled voltage. To eliminate ripple component, a second sample-and-hold circuit is provided, which is also responsive to the sampling pulse for sampling a voltage from a constant voltage source and holding the sampled voltage. The voltages sampled by the first and second sample-and-hold circuits are input to a subtractor where the voltage difference between the two input voltages is detected.
Ripple components generated by the two sample-and-hold circuits are cancelled out by the subtractor.
A first sample-and-hold circuit samples the ramp voltage in response to a sampling pulse and holds the sampled voltage. To eliminate ripple component, a second sample-and-hold circuit is provided, which is also responsive to the sampling pulse for sampling a voltage from a constant voltage source and holding the sampled voltage. The voltages sampled by the first and second sample-and-hold circuits are input to a subtractor where the voltage difference between the two input voltages is detected.
Ripple components generated by the two sample-and-hold circuits are cancelled out by the subtractor.
Description
NE-477 ~ 3 TITLE OF THE INVENTION
2 "Ripple-Free Phase Detector Using Two Sample-and-Hold Circuits"
4 The present invention relates generally to phase detectors for phase lock loops, and more specifically to a sample-hold phase detector which 6 generates a ramp voltage proportional to a phase di~Ference between ~wo 7 input signais and samples and holds the ramp voltage to produce a phase 8 detectpr output.
g According to the prior art sample-hold phase detector, a "ramp"
capacitor is charged for an interval corresponding to a phase difference 11 between an input signal and a reference signal to develop a ramp voltage 12 proportional to the phase difference. A sample and-hold circuit is 13 connected to the ramp capacitor to sample and hold the ramp voltage in 14 response to a sampling pulse. With the recent tendency toward LSI
implementation of electronic circuit~, it is desirable to fabricate all 16 components of the sample-and-hold circuit on a single LSI chip. However, 17 the value of the storage capacitor of the sample-and-hold circuit cannot be18 made sufficiently large to prevent the applied sampling pulse from 19 bypassing the "sample" switch of the sample-and-hold circuit by way of its parasitic capacitance to its "hold" capacitor. Therefore, the phase detector 21 output contains an undesirable ripple voltage which occurs at the same 22 frequency as the reference signal.
24 It is therefore an object of the present invention to provide a phase 2s detector which enables the implementation of sample-hold phase 2 6 detectors using LSi technology.
27 According to the present invention, a ramp voltage generator is 28 provided for receiving a reference pulse of a constant frequency and an 29 input pulse from an external source and producing a ramp voltage 3 o proportional to the phase difference between these pulses. A first sample-NE-477 2 ~
and-hold circuit samples the ramp voltage in response to a sampling pulse 2 and holds the sampled voltage. Further provided is a second sample-and-3 hold circuit which is also responsive to the sampling pulse for sampling a 4 constant voltage and holding the sampled voltage. The voltages sampled by the first and second sample-and-hold circuits are input to a subtractor 6 where the voltage difference between the input voltages is detected.
7 Undesirable ripple components, which are generated by the two sarnple-8 and-hold circuits, are effectively cancelled out by the subtractor.
g Preferably, a delay circuit is providecl to receive the reference pulse as a first reference pulse and delay it to produce a second reference pulse. A
11 second ramp voltage generator produces the constant voltage that is 12 proportional to the interval between the first and second reference pulses.1 3 BRIEF [)ESPRIPTION OF THE DRAWINGS
14 The present invention will be described in further detail with reference to the accompanying drawings, in which:
16 Fig. 1 is a block diagram of a phase detector according to the present 1 7 invention;
1 8 Fig. 2 shows details of each of the switches used in Fig. 1; and 19 Fig. 3 is a timing diagram showing waveforms of the various signals generated in Fig. 1.
22 Referring now to Fig. 1, the phase detector of the present invention 23 comprises a first sample-and-hold circuit 30 and a second sample-and-24 hold circuit 31. First sample-and-hold circuit 30 includes a storage 2s capacltor 5 connected be~veen ground and the input of a buffer amplifier 26 3, and a sampling switch 10 connected between a first ramp capacitor 7 2 7 and the input of amplifier 3. A first charge timing switch 11 is connected to 2 8 the ramp capacitor 7 for charging it with a current supplied from a p-29 channel MOS (metal oxide semiconductor~ transistor 15 in response to a charge command pulse CP1 from a control circuit 32. A first discharge NE-477 2 0 ~ 3 timing switch 13 is connected to the ramp capacitor 7 fnr discharging it in 2 response to a discharge command pulse DP. Therefore, a first ramp 3 voltage i5 developed across the first ramp capacitor 7. The sarnpling 4 switch 9 is responsive to a sampling pulse SP from the control circuit to s sample and transfer the energy stored in the first ramp capacitor 7 into the 6 storage capacitor 5 where the sampled voltage is held until the next 7 sampling instant.
8 Likewise, the second sample-and-hold circuit 31 includes a storage 9 capacitor 6 connected to the input of a buffer amplifier 4, and a sampling switch 12 connected between a second ramp capacitor 7 and the input of 1 amplifier 4. A second charge tirning switch 12 is connected to the second 12 ramp capacitor 8 for charging it with a current supplied from a p-channel 13 MOS transistor 16 in response to a pulse CP2 from the controi circuit. A
14 second discharge timing switch 14 is connected to the second ramp capacitor 8 for discharging it in response to the discharge command pulse 16 DP. Therefore, a second ramp voltage is developed across the capacitor 17 7. The sampling switch 9 is responsive to the sampling pulse SP to sample 18 and transfer the energy stored in the second ramp capacitor 7 into the 19 storage tapacitor 5 to hold the sampled voltage.
Transistors 15 and 16 are of identical structure and their gate 21 electrodes are connected together to the gate electrode of a p-channel 22 MOS transistor 17 which is connected to ground through a resistor 18.
23 Specifically, transistor 17 provides a drain current la which is given by:
4 la = (VDD - VGS)/R (1 ) S where VDD is the source voltage and VGS is the gate-source voltage of 2 ~ transistor 17, and R is the value of resistor 18. Transistor 1 S forrns a current 27 mirror circuit with transistor 1 7 and the drain current Ib Of transistor 15 is:
28 la = (Ib)(N~) (2) 29 where Nl = (Wl6/L~6)(L17/W~7)~ where W16 and W17 are channel widths 30 of transistors 15,17, and Lls and L17are channel lengths of transistors 15, 17. Likewise, transistor 16 forms a current mirror circuit with transistor 17, 2 and therefore, the drain current Ic of transistor 16 is given by:
3 la = (k)(N2) (3~
4 where N2 = (W1 6/L1 6)(L1 7/W1 7), where W16 and L16 are the channel width and length of transistor 15, respectively. Since transistors lS and 16 6 of identical structure, N1 = N2 - N, and hence, currents Ib and Ic are of the 7 same value and are uniquely cletermined by resistor 18. Therefore, the 8 voltages developed in the first and second ramp capacitors 7 and 8 are g respectively linearly proportional to the duration of the charge command pulses CP1 and CP2.
11 All capacitors of the phase detector are implemented using LSI
12 technology and incorporated into the same LSI chip with other circuit 13 elements of the phase detector.
14 As shown in Fig. 2, all switches of the phase detector are implemented with analog transmission gates ~hat aliows a voltage of any amplitude 16 value to be passed from its inpu~ to its output in response to a switching 17 pulse applied from the control circuit. Each switch comprises a pair of 18 complementary MOS transistors 37 and 38 with the source and drain 19 electrodes of each transistor being connected to the corresponding electrodes of the other and the gate of transistor 38 being coupled 21 through an inverter 39 to the gate of transistor 37.
22 The outputs of buffer amplifiers 3 and 4 are coupled respectively to 23 inputs of a differential amplifier, or subtractor 2, which is typically 24 implemented with an operational ampiifier 20, resistors 20, 21 through which the buffer amplifier outputs are respectively coupled to the inverting 2 6 and noninverting inputs of the operational amplifier, and a resistor 23 27 coupling the noninverting input ~o ground. The output of operational 2 B amplifier 20 is connected to the phase detector output terminal 1.
2 9 Control circui~ 32, driven by externally generated clock pulses, receives 3 0 a reference pulse which occurs at interval T and an input pulse suppiied 2 ~ 3 from an external source. The phase timing of the input pulse is compared 2 with the reference pulse to produce a first charge timing pulse CP1 of 3 duration corresponding to ~he phase difference ~ as shown in Fig. 3. The 4 reference pulse is also input to a delay circuit 33 where it is delayed by a prescribed interval ~ to produce a delayed reference pulse, which is input 6 to control circuit 32. Control circuit 32 produces a second charge timing 7 pulse CP2 of duration corresponding to the prescribed interval p. Control 8 circuit 32 further generates a sampling pulse SP and a discharge timing 9 pulse DP in succession during the interval between the trailing edge of a reference pulse and the leading edge of the next reference pulse.
11 The following is a description of the operation of the phase detector of12 the present invention with reference to Fig. 3.
13 When the phase detector receives a reference pulse 40 and an input 14 pulse 41 at intervals ~, a CP1 command pulse 43 of duration ~ is output from control circuit 32 to the first charge timing switch 11, thus drawing a 16 current tb from the transistor 15 into the first ramp capacitor 7 to develop a 17 ramp voltage Vl which is given by:
18 V1 = (Ib)(~)(T)/(27~)(C7) (4) 19 where C7 is the value of ramp capacitor 7 and the delay interval ~ is given2 O in units of radian. By substituting Equation (2) into Equation (4), the 21 following relation is obtained:
2 2 V1 = (~)( r)(N)(VDD - VGS)/(2~)(C7)(R) 2 3 = (K)(a)/(C7)(R) (5) 2~ where K is the phase-to-voltage conversion coefficient and is given by the 2 5 relation (T)(N)(VDD - VGS)/2~
26 Concurrently, a CP2 command pulse 44 of duration ~ is applied to the 27 second charge timing switch 12. A current ic is drawn from the transistor 28 16 into the second ramp capacitor 8 to develop a ramp voltage V2 which 29 ;S given by:
3 O V2 = (k)(~)(T)/(2~)(C8) (6) - 6 ~ 5~
= (~)(T)(N)(VDD - VGS3/~2~)(C8)(R) = (K)(o/(c8)(R) (7~
3 In response to a sampling pulse 45 the first and second sampling 4 switches 9 and 10 are operated to sample and transfer the voltages V1 and V2 from the ramp capacitors 7 and 8 to the storage capacitors 3 and 4, 6 respectively. A discharge comrnand pulse 46 is then input to switches 13 7 and 14 to discharge the ramp capacitors 7 and 8 cornpietely. If the value 8 of each storage capacitor is much smaller than the vaiue of the 9 corresponding ramp capacitor, the voltages stored in the capacitors 3 and 10 4 are substantially equal to voltages V1 and V2, respectively.
11 Through buffer amplifiers 3 and 4, the sampled voltages V1 and V2 12 appear respectively as voltages VA and VB at the inputs of subtractor 2 13 where the difference between the input voltages VA and VB jS detected and 14 output to the terminal 1.
Because of the small capacitance values of the storage capacitors 3 16 and 4, a feedthrough effect occurs through the sampling switches 9 and 17 10. Therefore, the sampling pulse applied to the first sample-and-hold 18 circuit 30 finds a leakage path through switch 9 to capacitor 5 to develop a 19 ripple voltage, as indicated by hatching 47, which is superposed on the 2Q sampled voltage V1. In like manner, the sampling pulse applied to the 21 second sample-and-hold circuit 31 finds a leakage path through switch 10 22 to capacitor 6 to develop a ripple of the same magnitude as ripple voltage 23 47, as indicated by hatching 48, which is superposed on the sarnpled 24 voltage V2. However, due to the differential action of subtractor 2, the leakage voltages 47 and 48 are cancelled out, thus producing a phase 2 6 detector output voltage VO indicative of the difference between voltages 27 VA and VB at the output terminal 1.
28 Since the second ramp voltage attains a constant level in so far as the 29 interval between the non-delayed and delayed reference pulses remains 3 0 constant, it could equally be as well provided by an external source of constant voltage, instead of by the ramp voltage generating circuit formed 2 by capacitor 8, switches 12, 14, deiay circuit 33 and control circuit 32.
g According to the prior art sample-hold phase detector, a "ramp"
capacitor is charged for an interval corresponding to a phase difference 11 between an input signal and a reference signal to develop a ramp voltage 12 proportional to the phase difference. A sample and-hold circuit is 13 connected to the ramp capacitor to sample and hold the ramp voltage in 14 response to a sampling pulse. With the recent tendency toward LSI
implementation of electronic circuit~, it is desirable to fabricate all 16 components of the sample-and-hold circuit on a single LSI chip. However, 17 the value of the storage capacitor of the sample-and-hold circuit cannot be18 made sufficiently large to prevent the applied sampling pulse from 19 bypassing the "sample" switch of the sample-and-hold circuit by way of its parasitic capacitance to its "hold" capacitor. Therefore, the phase detector 21 output contains an undesirable ripple voltage which occurs at the same 22 frequency as the reference signal.
24 It is therefore an object of the present invention to provide a phase 2s detector which enables the implementation of sample-hold phase 2 6 detectors using LSi technology.
27 According to the present invention, a ramp voltage generator is 28 provided for receiving a reference pulse of a constant frequency and an 29 input pulse from an external source and producing a ramp voltage 3 o proportional to the phase difference between these pulses. A first sample-NE-477 2 ~
and-hold circuit samples the ramp voltage in response to a sampling pulse 2 and holds the sampled voltage. Further provided is a second sample-and-3 hold circuit which is also responsive to the sampling pulse for sampling a 4 constant voltage and holding the sampled voltage. The voltages sampled by the first and second sample-and-hold circuits are input to a subtractor 6 where the voltage difference between the input voltages is detected.
7 Undesirable ripple components, which are generated by the two sarnple-8 and-hold circuits, are effectively cancelled out by the subtractor.
g Preferably, a delay circuit is providecl to receive the reference pulse as a first reference pulse and delay it to produce a second reference pulse. A
11 second ramp voltage generator produces the constant voltage that is 12 proportional to the interval between the first and second reference pulses.1 3 BRIEF [)ESPRIPTION OF THE DRAWINGS
14 The present invention will be described in further detail with reference to the accompanying drawings, in which:
16 Fig. 1 is a block diagram of a phase detector according to the present 1 7 invention;
1 8 Fig. 2 shows details of each of the switches used in Fig. 1; and 19 Fig. 3 is a timing diagram showing waveforms of the various signals generated in Fig. 1.
22 Referring now to Fig. 1, the phase detector of the present invention 23 comprises a first sample-and-hold circuit 30 and a second sample-and-24 hold circuit 31. First sample-and-hold circuit 30 includes a storage 2s capacltor 5 connected be~veen ground and the input of a buffer amplifier 26 3, and a sampling switch 10 connected between a first ramp capacitor 7 2 7 and the input of amplifier 3. A first charge timing switch 11 is connected to 2 8 the ramp capacitor 7 for charging it with a current supplied from a p-29 channel MOS (metal oxide semiconductor~ transistor 15 in response to a charge command pulse CP1 from a control circuit 32. A first discharge NE-477 2 0 ~ 3 timing switch 13 is connected to the ramp capacitor 7 fnr discharging it in 2 response to a discharge command pulse DP. Therefore, a first ramp 3 voltage i5 developed across the first ramp capacitor 7. The sarnpling 4 switch 9 is responsive to a sampling pulse SP from the control circuit to s sample and transfer the energy stored in the first ramp capacitor 7 into the 6 storage capacitor 5 where the sampled voltage is held until the next 7 sampling instant.
8 Likewise, the second sample-and-hold circuit 31 includes a storage 9 capacitor 6 connected to the input of a buffer amplifier 4, and a sampling switch 12 connected between a second ramp capacitor 7 and the input of 1 amplifier 4. A second charge tirning switch 12 is connected to the second 12 ramp capacitor 8 for charging it with a current supplied from a p-channel 13 MOS transistor 16 in response to a pulse CP2 from the controi circuit. A
14 second discharge timing switch 14 is connected to the second ramp capacitor 8 for discharging it in response to the discharge command pulse 16 DP. Therefore, a second ramp voltage is developed across the capacitor 17 7. The sampling switch 9 is responsive to the sampling pulse SP to sample 18 and transfer the energy stored in the second ramp capacitor 7 into the 19 storage tapacitor 5 to hold the sampled voltage.
Transistors 15 and 16 are of identical structure and their gate 21 electrodes are connected together to the gate electrode of a p-channel 22 MOS transistor 17 which is connected to ground through a resistor 18.
23 Specifically, transistor 17 provides a drain current la which is given by:
4 la = (VDD - VGS)/R (1 ) S where VDD is the source voltage and VGS is the gate-source voltage of 2 ~ transistor 17, and R is the value of resistor 18. Transistor 1 S forrns a current 27 mirror circuit with transistor 1 7 and the drain current Ib Of transistor 15 is:
28 la = (Ib)(N~) (2) 29 where Nl = (Wl6/L~6)(L17/W~7)~ where W16 and W17 are channel widths 30 of transistors 15,17, and Lls and L17are channel lengths of transistors 15, 17. Likewise, transistor 16 forms a current mirror circuit with transistor 17, 2 and therefore, the drain current Ic of transistor 16 is given by:
3 la = (k)(N2) (3~
4 where N2 = (W1 6/L1 6)(L1 7/W1 7), where W16 and L16 are the channel width and length of transistor 15, respectively. Since transistors lS and 16 6 of identical structure, N1 = N2 - N, and hence, currents Ib and Ic are of the 7 same value and are uniquely cletermined by resistor 18. Therefore, the 8 voltages developed in the first and second ramp capacitors 7 and 8 are g respectively linearly proportional to the duration of the charge command pulses CP1 and CP2.
11 All capacitors of the phase detector are implemented using LSI
12 technology and incorporated into the same LSI chip with other circuit 13 elements of the phase detector.
14 As shown in Fig. 2, all switches of the phase detector are implemented with analog transmission gates ~hat aliows a voltage of any amplitude 16 value to be passed from its inpu~ to its output in response to a switching 17 pulse applied from the control circuit. Each switch comprises a pair of 18 complementary MOS transistors 37 and 38 with the source and drain 19 electrodes of each transistor being connected to the corresponding electrodes of the other and the gate of transistor 38 being coupled 21 through an inverter 39 to the gate of transistor 37.
22 The outputs of buffer amplifiers 3 and 4 are coupled respectively to 23 inputs of a differential amplifier, or subtractor 2, which is typically 24 implemented with an operational ampiifier 20, resistors 20, 21 through which the buffer amplifier outputs are respectively coupled to the inverting 2 6 and noninverting inputs of the operational amplifier, and a resistor 23 27 coupling the noninverting input ~o ground. The output of operational 2 B amplifier 20 is connected to the phase detector output terminal 1.
2 9 Control circui~ 32, driven by externally generated clock pulses, receives 3 0 a reference pulse which occurs at interval T and an input pulse suppiied 2 ~ 3 from an external source. The phase timing of the input pulse is compared 2 with the reference pulse to produce a first charge timing pulse CP1 of 3 duration corresponding to ~he phase difference ~ as shown in Fig. 3. The 4 reference pulse is also input to a delay circuit 33 where it is delayed by a prescribed interval ~ to produce a delayed reference pulse, which is input 6 to control circuit 32. Control circuit 32 produces a second charge timing 7 pulse CP2 of duration corresponding to the prescribed interval p. Control 8 circuit 32 further generates a sampling pulse SP and a discharge timing 9 pulse DP in succession during the interval between the trailing edge of a reference pulse and the leading edge of the next reference pulse.
11 The following is a description of the operation of the phase detector of12 the present invention with reference to Fig. 3.
13 When the phase detector receives a reference pulse 40 and an input 14 pulse 41 at intervals ~, a CP1 command pulse 43 of duration ~ is output from control circuit 32 to the first charge timing switch 11, thus drawing a 16 current tb from the transistor 15 into the first ramp capacitor 7 to develop a 17 ramp voltage Vl which is given by:
18 V1 = (Ib)(~)(T)/(27~)(C7) (4) 19 where C7 is the value of ramp capacitor 7 and the delay interval ~ is given2 O in units of radian. By substituting Equation (2) into Equation (4), the 21 following relation is obtained:
2 2 V1 = (~)( r)(N)(VDD - VGS)/(2~)(C7)(R) 2 3 = (K)(a)/(C7)(R) (5) 2~ where K is the phase-to-voltage conversion coefficient and is given by the 2 5 relation (T)(N)(VDD - VGS)/2~
26 Concurrently, a CP2 command pulse 44 of duration ~ is applied to the 27 second charge timing switch 12. A current ic is drawn from the transistor 28 16 into the second ramp capacitor 8 to develop a ramp voltage V2 which 29 ;S given by:
3 O V2 = (k)(~)(T)/(2~)(C8) (6) - 6 ~ 5~
= (~)(T)(N)(VDD - VGS3/~2~)(C8)(R) = (K)(o/(c8)(R) (7~
3 In response to a sampling pulse 45 the first and second sampling 4 switches 9 and 10 are operated to sample and transfer the voltages V1 and V2 from the ramp capacitors 7 and 8 to the storage capacitors 3 and 4, 6 respectively. A discharge comrnand pulse 46 is then input to switches 13 7 and 14 to discharge the ramp capacitors 7 and 8 cornpietely. If the value 8 of each storage capacitor is much smaller than the vaiue of the 9 corresponding ramp capacitor, the voltages stored in the capacitors 3 and 10 4 are substantially equal to voltages V1 and V2, respectively.
11 Through buffer amplifiers 3 and 4, the sampled voltages V1 and V2 12 appear respectively as voltages VA and VB at the inputs of subtractor 2 13 where the difference between the input voltages VA and VB jS detected and 14 output to the terminal 1.
Because of the small capacitance values of the storage capacitors 3 16 and 4, a feedthrough effect occurs through the sampling switches 9 and 17 10. Therefore, the sampling pulse applied to the first sample-and-hold 18 circuit 30 finds a leakage path through switch 9 to capacitor 5 to develop a 19 ripple voltage, as indicated by hatching 47, which is superposed on the 2Q sampled voltage V1. In like manner, the sampling pulse applied to the 21 second sample-and-hold circuit 31 finds a leakage path through switch 10 22 to capacitor 6 to develop a ripple of the same magnitude as ripple voltage 23 47, as indicated by hatching 48, which is superposed on the sarnpled 24 voltage V2. However, due to the differential action of subtractor 2, the leakage voltages 47 and 48 are cancelled out, thus producing a phase 2 6 detector output voltage VO indicative of the difference between voltages 27 VA and VB at the output terminal 1.
28 Since the second ramp voltage attains a constant level in so far as the 29 interval between the non-delayed and delayed reference pulses remains 3 0 constant, it could equally be as well provided by an external source of constant voltage, instead of by the ramp voltage generating circuit formed 2 by capacitor 8, switches 12, 14, deiay circuit 33 and control circuit 32.
Claims (5)
1. A phase detector comprising:
ramp voltage generating means for receiving a reference pulse of a predetermined constant frequency and an input pulse and developing a ramp voltage proportional to a phase difference between the reference pulse and said input pulse;
means for generating a sampling pulse subsequent to the reference pulse;
first sample-and-hold means for sampling said ramp voltage in response to the sampling pulse;
second sample-and-hold means for sampling a constant voltage in response to said sampling pulse; and means for detecting a voltage difference between the voltages sampled by said first and second sample-and-hold means.
ramp voltage generating means for receiving a reference pulse of a predetermined constant frequency and an input pulse and developing a ramp voltage proportional to a phase difference between the reference pulse and said input pulse;
means for generating a sampling pulse subsequent to the reference pulse;
first sample-and-hold means for sampling said ramp voltage in response to the sampling pulse;
second sample-and-hold means for sampling a constant voltage in response to said sampling pulse; and means for detecting a voltage difference between the voltages sampled by said first and second sample-and-hold means.
2. A phase detector as claimed in claim 1, further comprising:
delay means for receiving said reference pulse as a first reference pulse and producing a second reference pulse delayed by a prescribed interval with respect to the first reference pulse; and second ramp voltage generating means for receiving said first and second reference pulses and developing said constant voltage proportional to said prescribed interval.
delay means for receiving said reference pulse as a first reference pulse and producing a second reference pulse delayed by a prescribed interval with respect to the first reference pulse; and second ramp voltage generating means for receiving said first and second reference pulses and developing said constant voltage proportional to said prescribed interval.
3. A phase detector comprising:
a first integrated-circuit capacitor;
charging means for receiving a reference pulse of a predetermined constant frequency and an input pulse and drawing a current at a constant rate into the first integrated-circuit capacitor during an interval corresponding to a phase difference between the reference pulse and said input pulse to develop a ramp voltage in said first integrated-circuit capacitor;
a first integrated-circuit sample-and-hold circuit connected to said first integrated-circuit capacitor;
second integrated-circuit sample-and-hold circuit connected to a source of constant voltage;
sampling means for causing said first and second integrated-circuit sample-and-hold circuits to sample said ramp voltage and said constant voltage, respectively, during an interval subsequent to said reference pulse;
and means for detecting a voltage difference between the voltages sampled by said first and second sample-and-hold circuits.
a first integrated-circuit capacitor;
charging means for receiving a reference pulse of a predetermined constant frequency and an input pulse and drawing a current at a constant rate into the first integrated-circuit capacitor during an interval corresponding to a phase difference between the reference pulse and said input pulse to develop a ramp voltage in said first integrated-circuit capacitor;
a first integrated-circuit sample-and-hold circuit connected to said first integrated-circuit capacitor;
second integrated-circuit sample-and-hold circuit connected to a source of constant voltage;
sampling means for causing said first and second integrated-circuit sample-and-hold circuits to sample said ramp voltage and said constant voltage, respectively, during an interval subsequent to said reference pulse;
and means for detecting a voltage difference between the voltages sampled by said first and second sample-and-hold circuits.
4. A phase detector as claimed in claim 3, wherein said source of constant voltage comprises:
delay means for receiving said reference pulse as a first reference pulse and producing a second reference pulse delayed by a prescribed interval with respect to the first reference pulse;
a second integrated-circuit capacitor; and second charging means for receiving said first and second reference pulses and drawing a current at said constant rate into said second integrated-circuit capacitor during an interval corresponding to said prescribed interval.
delay means for receiving said reference pulse as a first reference pulse and producing a second reference pulse delayed by a prescribed interval with respect to the first reference pulse;
a second integrated-circuit capacitor; and second charging means for receiving said first and second reference pulses and drawing a current at said constant rate into said second integrated-circuit capacitor during an interval corresponding to said prescribed interval.
5. A phase detector comprising:
a switching pulse source for receiving a first reference pulse of a predetermined constant frequency and an input pulse and producing said first charge timing pulse of duration corresponding to a phase difference between said first reference pulse and said input pulse, for receiving a second reference pulse of said predetermined constant frequency and producing a second charge timing pulse of constant duration corresponding to a phase difference between said first and second reference pulses, and for successively producing a sampling pulse and a discharge timing pulse during an interval following a trailing edge of said first reference pulse;
first and second identical constant current sources;
a first capacitor;
first switch means for drawing a current from the constant current source into the first capacitor in response to said first charge timing pulse and drawing a current from the first capacitor in response to said discharge timing pulse;
a first sample-and-hold circuit responsive to said sampling pulse for sampling a voltage developed in the first capacitor and holding the sampled voltage;
a second capacitor;
second switch means for drawing a current from the constant current source into the second capacitor in response to said second charge timing pulse and drawing a current from the second capacitor (8) in response to said discharge timing pulse;
a second sample-and-hold circuit responsive to said sampling pulse for sampling a voltage developed in the second capacitor and holding the sampled voltage; and means for detecting a voltage difference between the voltages sampled by said first and second sample-and-hold circuits.
a switching pulse source for receiving a first reference pulse of a predetermined constant frequency and an input pulse and producing said first charge timing pulse of duration corresponding to a phase difference between said first reference pulse and said input pulse, for receiving a second reference pulse of said predetermined constant frequency and producing a second charge timing pulse of constant duration corresponding to a phase difference between said first and second reference pulses, and for successively producing a sampling pulse and a discharge timing pulse during an interval following a trailing edge of said first reference pulse;
first and second identical constant current sources;
a first capacitor;
first switch means for drawing a current from the constant current source into the first capacitor in response to said first charge timing pulse and drawing a current from the first capacitor in response to said discharge timing pulse;
a first sample-and-hold circuit responsive to said sampling pulse for sampling a voltage developed in the first capacitor and holding the sampled voltage;
a second capacitor;
second switch means for drawing a current from the constant current source into the second capacitor in response to said second charge timing pulse and drawing a current from the second capacitor (8) in response to said discharge timing pulse;
a second sample-and-hold circuit responsive to said sampling pulse for sampling a voltage developed in the second capacitor and holding the sampled voltage; and means for detecting a voltage difference between the voltages sampled by said first and second sample-and-hold circuits.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3-313437 | 1991-10-31 | ||
| JP3313437A JP2897795B2 (en) | 1991-10-31 | 1991-10-31 | Sample and hold type phase comparator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2081863A1 CA2081863A1 (en) | 1993-05-01 |
| CA2081863C true CA2081863C (en) | 1997-10-14 |
Family
ID=18041289
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002081863A Expired - Fee Related CA2081863C (en) | 1991-10-31 | 1992-10-30 | Ripple-free phase detector using two sample-and-hold circuits |
Country Status (11)
| Country | Link |
|---|---|
| US (1) | US5410195A (en) |
| EP (1) | EP0540052B1 (en) |
| JP (1) | JP2897795B2 (en) |
| KR (1) | KR960012801B1 (en) |
| AU (1) | AU656630B2 (en) |
| CA (1) | CA2081863C (en) |
| DE (1) | DE69226417T2 (en) |
| ES (1) | ES2118777T3 (en) |
| HK (1) | HK1008374A1 (en) |
| SG (1) | SG52382A1 (en) |
| TW (1) | TW259904B (en) |
Families Citing this family (37)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0185756B1 (en) * | 1994-02-02 | 1999-05-15 | 정호선 | Non-linear circuit and chaos neural net using it |
| US5532629A (en) * | 1994-08-04 | 1996-07-02 | Texas Instruments Incorporated | Bipolar track and hold circuit |
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-
1991
- 1991-10-31 JP JP3313437A patent/JP2897795B2/en not_active Expired - Fee Related
-
1992
- 1992-10-29 US US07/968,575 patent/US5410195A/en not_active Expired - Fee Related
- 1992-10-30 CA CA002081863A patent/CA2081863C/en not_active Expired - Fee Related
- 1992-10-30 TW TW081108661A patent/TW259904B/zh active
- 1992-10-31 KR KR1019920020326A patent/KR960012801B1/en not_active IP Right Cessation
- 1992-11-02 ES ES92118718T patent/ES2118777T3/en not_active Expired - Lifetime
- 1992-11-02 SG SG1996003775A patent/SG52382A1/en unknown
- 1992-11-02 AU AU27482/92A patent/AU656630B2/en not_active Ceased
- 1992-11-02 EP EP92118718A patent/EP0540052B1/en not_active Expired - Lifetime
- 1992-11-02 DE DE69226417T patent/DE69226417T2/en not_active Expired - Fee Related
-
1998
- 1998-07-10 HK HK98109055A patent/HK1008374A1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| CA2081863A1 (en) | 1993-05-01 |
| EP0540052A1 (en) | 1993-05-05 |
| JPH05175737A (en) | 1993-07-13 |
| JP2897795B2 (en) | 1999-05-31 |
| SG52382A1 (en) | 1998-09-28 |
| KR960012801B1 (en) | 1996-09-24 |
| US5410195A (en) | 1995-04-25 |
| EP0540052B1 (en) | 1998-07-29 |
| TW259904B (en) | 1995-10-11 |
| KR930009257A (en) | 1993-05-22 |
| DE69226417D1 (en) | 1998-09-03 |
| DE69226417T2 (en) | 1998-12-03 |
| AU656630B2 (en) | 1995-02-09 |
| HK1008374A1 (en) | 1999-05-07 |
| AU2748292A (en) | 1993-05-06 |
| ES2118777T3 (en) | 1998-10-01 |
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| EEER | Examination request | ||
| MKLA | Lapsed |