CA2092050A1 - Method for fabricating diodes for electrostatic discharge protection and voltage references - Google Patents
Method for fabricating diodes for electrostatic discharge protection and voltage referencesInfo
- Publication number
- CA2092050A1 CA2092050A1 CA002092050A CA2092050A CA2092050A1 CA 2092050 A1 CA2092050 A1 CA 2092050A1 CA 002092050 A CA002092050 A CA 002092050A CA 2092050 A CA2092050 A CA 2092050A CA 2092050 A1 CA2092050 A1 CA 2092050A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
- H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
Abstract
ELECTROSTATIC DISCHARGE PROTECTION DIODES
ABSTRACT
A novel process is taught for forming diodes simulataneouly with the formation of typical prior art Ldd MOS
devices. The diodes thus formed have low breakdown voltages, making them suitable for use as voltage reference diodes, or diodes for ESD protection.
ABSTRACT
A novel process is taught for forming diodes simulataneouly with the formation of typical prior art Ldd MOS
devices. The diodes thus formed have low breakdown voltages, making them suitable for use as voltage reference diodes, or diodes for ESD protection.
Description
209~5~
METHt)D FOR FABRICAT:LNG DIODES FOR E:LECTROSTATIC DISC}lARGE
7 Technical Field This invention pertains to semiconductor devices, 11 particularly with respect to electrostatic discharge 12 protection.
Background 17 CMOS integrated circuits of current technologies require 18 very thorough protection against ~lectrostatic Discharge (ESD) 19 phenomena. The susceptihility of VLSI CMOS circuits to excessive voltages and currents caused by ESD requires 21 effective protection of all circuit pins. Figure 1 shows the 22 commonly used protection mechanism, where input protection 23 circuits (PCI) 101a and 101b are used to protect input circuit 24 111 from undesired ESD voltages received on input pin 101.
Similarly, output protection circuits (PCO) 102a and 102b 26 protect output circuit 112 from undesired ESD voltages 27 appearing on output pin 102. Voltage supply protection circuit 28 (PCV) 103 protects the entire circuit from ESD voltages 29 appearing on either one or both of the VSS and VDD supply pins.
It has been reported in the article "Internal Chip ESD
31 Phenomena Beyond the Protection Circuit" by Duvvury et. al., 32 IEEE/IRPS, 1988, pages 19-25, that all commonly used protection 33 circuits cause a circuit stress to the "protected" circuit. In 34 other words, circuit protection as it exists today is not very effective.
36 The common ESD protection practice, as depicted in Figure 37 2, is to use grounded gate thick or thin oxide transistors 38 291a, 201b, 202a, 202b. The drawback of using thin oxide 39 transistors is that the breakdown voltage of the grounded gate transistor approaches the thin oxide breakdown voltage. The 41 breakdown of these transistors in thP grounded gate mode is 1.
METHt)D FOR FABRICAT:LNG DIODES FOR E:LECTROSTATIC DISC}lARGE
7 Technical Field This invention pertains to semiconductor devices, 11 particularly with respect to electrostatic discharge 12 protection.
Background 17 CMOS integrated circuits of current technologies require 18 very thorough protection against ~lectrostatic Discharge (ESD) 19 phenomena. The susceptihility of VLSI CMOS circuits to excessive voltages and currents caused by ESD requires 21 effective protection of all circuit pins. Figure 1 shows the 22 commonly used protection mechanism, where input protection 23 circuits (PCI) 101a and 101b are used to protect input circuit 24 111 from undesired ESD voltages received on input pin 101.
Similarly, output protection circuits (PCO) 102a and 102b 26 protect output circuit 112 from undesired ESD voltages 27 appearing on output pin 102. Voltage supply protection circuit 28 (PCV) 103 protects the entire circuit from ESD voltages 29 appearing on either one or both of the VSS and VDD supply pins.
It has been reported in the article "Internal Chip ESD
31 Phenomena Beyond the Protection Circuit" by Duvvury et. al., 32 IEEE/IRPS, 1988, pages 19-25, that all commonly used protection 33 circuits cause a circuit stress to the "protected" circuit. In 34 other words, circuit protection as it exists today is not very effective.
36 The common ESD protection practice, as depicted in Figure 37 2, is to use grounded gate thick or thin oxide transistors 38 291a, 201b, 202a, 202b. The drawback of using thin oxide 39 transistors is that the breakdown voltage of the grounded gate transistor approaches the thin oxide breakdown voltage. The 41 breakdown of these transistors in thP grounded gate mode is 1.
2~92~0 1 approximately 13-17 volts, depending on dopant concentrations 2 and distributions. The typical oxide breakdown is 15-17 volts 3 for approximately 175 angstrom gate oxide and the grounded gate 4 thin oxide breakdown is 12-14 volts. Thus, the breakdown margin between device breakdown may be inadequate at only S several volts.
7 Figure 3 is an illustration depicting the proximity of the 8 breakdown region of the grounded gate thin oxide transistor, 9 including sourae/drain regions 302, 303, lightly doped source/drain extensions 304, 305, thin gate oxide 301, 11 polycrystalline silicon gate electrode 306, and sidewall 12 spacers 307. The channel region is formed between the 13 source/drain extensions 304, 305 within P well 310 in substrate 14 311. It is influenced by the control voltage applied to polycrystalline silicon gate 306, in this instance VSS, which 16 is also applied to source/drain region 302. The input or 17 output structure to be protected is connected to source/drain 18 region 303. With the breakdown of the thin gate occurring in l9 region 399 so close to thin gate oxide 301, a potentially unreliable device is created. The thin oxide grounded gate 21 configuration is used because this device has a lower breakdown 22 than the thick oxide field transistor; in fact it gives the 23 lowest controlled breakdown voltage of all devices commonly 24 available on the chip today. In fact the thick field transistor, whether operated as grounded gate or high gate, 26 will probably surpass the breakdown voltage of the thin gate 27 oxide and hence is useless for protection. ~ince the grounded 28 gate thin oxide transistor has a breakdown between 12-14 volts, 29 this limits the thinness of the gate oxide which may be used.
The gate oxide breakdown must be greater than the protection 31 device breakdown. Generally for low voltage lap top or 32 portable operation, it is desirable to have maximum drive for 33 a given threshold voltage. One way to accomplish this is by 34 thinning the gate oxide to i~crease the Id~s of the transistor.
If the protection device is limited to 12 volts breakdown, at 36 best this will limit gate oxide to at least 140 angstroms. on 37 the other hand, if 8.0 volts is the breakdown of the protection 38 device it would be possible to decrease the oxide thickness to 2~92~
1 approximately 100 angstroms. This would increase the drive by 2 approximately 40% over the thin gate protected circuit.
3 The N+ and P+ diffusions available in CMOS processes may 4 be used to make a diode but since these two diffusions are usually of such high concentrations, they lead to poor I/V
6 characteristics, i.e., they are usually very leaky and have 7 very poor V/I knee characteristics. These characteristics make 8 such a diode a poor candidate for a protection device, having 9 a typical breakdown of 4.5 volts, and unacceptably less than the typical 5.0 volt power supply voltage.
12 Summary 13 In accordance with the teachings of those inventions, a 14 novel process is taught for forming diodes in a process which simultaneously forms MOS or CMOS devices. These diodes have 16 relatively low breakdown voltage, making them suitable for ESD
17 protection devices or as voltage reference diodes.
19 Brief Description of ~rawinqs Figure l is a schematic diagram depicting a typical prior 21 art ESD protection scheme;
22 Figure 2 is a schematic diagram depic.ting a typical prior 23 art circuit implementing the ESD protection of Figure l;
24 Figure 3 is a cross-sectional view of a typical MOS
transistor used for ESD protection, showing its breakdown 26 mechanism;
27 Figure 4 is a cross-sectional view depicting one 28 embodiment of a diode constructed within an N type region in 29 accordance with the teachings of this invention;
Figure 5 is a cross-sectional view depicting one 31 embodiment of a diode constructed within a P type region in 32 accordance with the teachings of this invention;
33 Figures 6 through 8 are schematic diagrams depicting 34 various embodiments of ESD protection circuits utilizing the diodes constructed in accordance with the teachings of this 36 invention;
2 ~ a 1 Figures 9A through 9E are cross-sectional views depicting 2 a fabrication sequence in accordance with one embodiment of 3 this invention;
4 Figures 10A through 10E are cross-sectional views depicting a fabrication sequence in accordance with another 6 embodiment of this invention;
7 Figures llA through llE are cross-sectional views 8 depicting a fabrication sequence in accordance with another 9 embodiment of this invention;
Figures 12A through 12E are cross-sectional views 11 depicting a fabrication sequence in accordance with another 12 embodiment of this invention;
13 Figure 13 is a plan view depicting one embodiment of the 14 placement of diodes constructed in accordance with the teachings of this invention in an integrated circuit;
16 Figures 14A and 14B are top and cross-sectional views, 17 respectively, depicting diodes constructed in accordance with 18 the teachings of this invention;
19 Figure 15 is a plan view including bonding pads;
Figure 16 is a cross sectional view of an alternative 21 embodiment; and 22 Figure 17 is a cross sectional view of yet another 23 embodiment.
Detailed Description 26 In accordance with the teachings of this invention, a low 27 voltage protection device is taught which is capable of being 28 fabricated simultaneously with the fabrication of typical prior 29 art MOS or CMOS devices which include lightly doped drain devices. In accordance with the teachings of this inv~ntion, 31 such protection diodes can be formed without the need for 32 additional masking or implantation steps. The protection 33 diodes of this invention are compatible with the current 34 process technology including one micron and smaller CMOS and MOS process flows. In accordance with the teachings of this 36 invention, the use of lower breakdown voltage protection 37 devices allows the use of thinner gate oxide, thereby enhancing 38 operating speed and increasing transistor drive, without 2~2~
1 sacrificing reliability. Utilizing diodes in accordance with 2 the teachings of this invention for ESD protection alleviates 3 the problem associated with prior art use of thin oxide 4 transistors for this purpose, in which the thin oxide is placed at risk. In accordance with the teachings of this invention, 6 series resistors are not needed in order to affectuate ESD
7 protection, thereby saving integrated ci~cuit area, as well as 8 affording greater ES~ protection by quickly dissipating ESD
9 potentials through a low impedance path.
Examples of the protection diodes of this invention are 11 shown in cross-section in Figures 4 and 5. Since the diodes 12 are formed in bulk CMOS, the N well diode has one side 13 connected to VDD and the P well has one junction connected to 14 VSS, as shown in Figures 4 and 5, respectively.
Referring to Figure 4, within N type bulk 410 is ~ormed N
16 well 411, in a well known manner. Field oxide regions 412 are 17 also formed in a well known manner in order to expose only 18 those portions of the substrate surface which are of interest 19 for electrical connections and further doping. Within N well 411 is ormed N type regions 414 surrounding Pt region 413, and 21 spaced apart N+ region 415. An N protection diode in 22 accordance with the teachings of this invention, shown in 23 representative format as diode 416, is formed having its anode 24 as P+ region 413 and its cathode as N+ region 415. In this example, cathode 415 of protection diode 416 is connected to 26 positive supply VDD, and anode 413 of protection diode 416 is 27 connected to the inpu~ or output device to be protected (not 28 shown). As shown in Figure 4, reverse breakdown occurs in 29 region 499 where N type region 414 and P+ anode 413 have their greatest dopant differential~ In accordance with the teachings 31 of this invention, N well protection diode 416 meets the 32 requirement:
34 (VDD-YSS~<(diode breakdown voltage)<<(thin oxide breakdown voltage) (1) 37 Referring to Figure 5, within N type bulk 510 is formed P
38 well 511, in a well known manner. Field oxide regions 512 are 2 ~ 0 1 also formed in a well known manner in order to expose only 2 those portions of the substrate surface which are of interest 3 for electrical connections and further doping. Within P well 4 511 is formed P type regions 514 surrounding N+ region 513, and spaced apart P~ region 515. A P protection d.iode in accordance 6 with the teachings of this invention, shown in representative 7 format as diode 516, is formed having its anode as P~ region 8 515 and its cathode as N~ region 51~. In this example, anode 9 515 o~ protection diode 516 is connected to negative supply VSS, and cathode 513 of protection diode 516 i5 connected to 11 the input or output device to be protected (not shown). As 12 shown in Figure 5, reverse ~reakdown occurs in region 599 where 13 P type region 514 and N+ cathode 513 have their greates~ dopant 14 differential.
Figure 6 illustrates the use of novel diodes 416 and 516 16 of Figures 4 and 5, respectively, as VDD input protection diode 17 lOla, VDD output protection diode 102a, and VSS input 18 protection diode lOlb, VSS output protection diode 102b, 19 respectively. Voltage supply protection diode 103 can be fabricated as either N well diode 416 of Figure 4 or P well 21 diode 516 of Figure 5. The breakdown voltage of the diodes 22 fabricated in accordance with the teashings of this invention 23 is on the order of approximately 8.0 volts. With the 24 protection diodes utilized as shown, the actual protection offered by a diode of this invention is dependent on the size 26 of the protection diode, with larger diodes capable of 27 absorbing larger amounts of charge. Note there is no thin 28 oxide in the region of the breakdown of this structure, thus 29 making the diodes of this invention more desirable for handling ~SD than prior art devices.
31 Figures 7 and 8 show alt~rnative embodiments in which 32 protection diodes of this inv~ntion provide single ended 33 protection only (protection to only a single power supply), but 34 good protection is provided for both positive and neyative ESD, respectively~
36 Referring to Figure 7, a positive ESD pulse to input 101 37 reverse biases input protection diode lOlb/516 and forces i 38 into conduction when 8.0 volts is surpassed. The charge then 2 ~ 5 ~
1 passes to VSS line 115 which is protected by large protection 2 diode 103, which shunts the charge to VDD line 116. On the 3 other hand, a negative ESD pulse to input 101 forward biases 4 input protection diod~ 101b/516 and the pulse passes to VSS
line 115 which is protected by large protection diode 103, 6 which conducts if 8.0 volts is exceeded. Large protection 7 diode 103 limits VDD-VSS to 8.0 volts.
8 Still re~erring to ~igure 7, a positive ESD pulse to 9 output 102 reverse biases output protection diode 102b/516 and forces it into conduction when 8.0 volts is surpassed. The 11 charge then passes to VSS line 115 which is protected by large 12 protection diode 103, which shunts the charge to VDD line 116.
13 On the other hand, a negative ESD pulse to output 102 forward 14 biases output protection diode 102b/516 and the pulse passess to VSS line 115 which is protected by large protection diode 16 103, which sonducts if 8.0 volts is exceeded.
17 A similar ESD protection mechanism is shown in Figure ~, 18 in which a negative ESD pulse to input 101 reverse biases input 19 protection diode 101a/416 and forces it into conduction when 8.0 volts is surpassed. The charge then passes to VDD line 116 21 which is protected by large protection diode 103, which shunts 2Z the charge to VSS line 115. On the other hand, a positive ESD
23 pulse to input 101 forward biases input protection diode 24 101a/416 and the pulse passes to VDD line 116 whih is protected by large protection diode 103, which conducts if 8.0 26 volts is exceeded. Thus, larye protection diode 103 limits 27 VDD-VSS to 8.0 volts. A negative ~SD pulse to output 102 28 reverse biases output protection diode 102a/416 and forces it 29 into conduction when 8.0 volts is surpassed. The charge then passes to VDD line 116 which is protected by large protection 31 diode 103, which shunts the charge to VSS line 115. On the 32 other hand, a positive ESD pulse to output 102 forwaxd biases 33 output protection diode 102a/416 and the pulse passes to VDD
34 line 116 which is protected by large protection diode 103, which conducts if 8.0 volts is exceeded.
36 This 8.0V diode can also be used as a reference diode in 37 +5.0V linear circuit systems. In general, reference diodes are 38 difficult to build in an advanced CMOS process because dopant 7.
2~2~
1 concentrations of the appropriate level to make reliable diodes 2 o~ low breakdowns are not available. The method of this 3 invention overcomes the limitations of the prior art and 4 provides very good reference diodes.
Figures 9A through 9E illustrate the fabrication steps of 6 one embodiment of a method for constructing the novel diodes of 7 the inve~tion. Referrin~ to Figure 9A, substrate 1101 may be 8 either an N type substrate or a P type substrate, as both N
9 well 1102 and P well 1103 are formed therein. If desired, an N type substrate of desired doplng may be used, thereby 11 avoiding the need to form N well 1102 or a P type sub~trate of 12 desired doping may be used, thereby avoiding the need to form 13 P well 1103. N well 1102 is formed in a conventional manner, 14 for example, having a dopant concentration providing a sheet resistivity of approximately 3000 ohms per square. Similarly, 16 P well 1103 is formed in a conventional manner and has a dopant 17 concentration providing, for example, a sheet resistivity of 18 approximately 3000 ohms per square. A layer of field oxide 19 1104 is formed in a well known manner in order to expose those portions of N well 1102 and P well 1103 for which additional 21 implants are to be performed. A layer of gate oxide (not 22 shown) is then formed, for example, to a thickness of ~3 approximately 150 A , and a layer of polycrystalline silicon is 24 formed to a desired conductivity on that gate oxide and patterned in a conventional manner in order to form gate 26 electrodes 1105 and 1106. A blanket N type implant is then 27 performed, for example, using phosphorous dopa~ts implanted to 28 a dose of approximately 2.5E13 at approximately ~0 KEV in order 29 to provide a dopant concentration of approximately 2 x 1018/cm3. This forms N channel lightly doped drains 1111 and 3~ lightly doped N r~gion 1110, as well as lntroducing dopants 32 into the other expoæed portions of the devices.
33 As shown in Figure 9B, resist layer 1107 is used in order 34 to expose only those portions in which a P type im~lant is desired. At this time, a P type implant is performed, for 36 example, using boron implanted to a dose o~ approximately 6E13 37 at approximately 50 KEV to a net (i.e., over-compensated) 38 dopant concentration of approximately 3E18/cm3. This forms 2~0~a 1 lightly doped source/drain regions 1120 aligned to gate 1105 2 within N well 1102, and P type region 1121 within P well 1103.
3 This P type region 1121 is sufficiently concentrated to 4 compensate the previous N type implant in that same region, which was not necessary but introduced by way of convenience in 6 order to allow the N type implant to be a blanket implant.
7 Masking layer 1107 is removed and the device is then oxidized, 8 forming sidewall spacers 1108 on gate electrodes 1105 and 1106.
9 The oxide forming sidewall spacers 1108 is Pormed to a greater thickness on the sidewalls of polycrystalline silicon gates 11 1105 and 1106 than is the oxide which is simultaneously formed 12 on single crystal portions of the device, as is well known in 13 the artO
14 Referring to Figure 9C, another masking layer 1109 is used to expose those portions of the device which are to receive an 16 N type implant. This N type implant is performed, for example, 17 using arsenic implanted to a dose of approximately 5.5E15 at 18 approximately 60 KEV, to a sheet resistivity of approximately 19 75 ohms per square. This forms source/drain regions 1115 to a desired dopant concentration, while sidewall spacers 1108 21 maintain the previously established dopant level to provide 22 lightly doped source/drain regions 1111, a~ is well known in 23 the art. N+ region 1114 is also formed within P well 1103, as 24 is N type region 1116 within N well 1102~
Referring to Figure 9D, another masking layer 1113 is 26 formed to expose those regions which are to receive a P+
27 implant, which is performed, for example, using boron (BF2) 28 implanted to a dose of approximately 5.5E15 at approximately 60 29 KEV to achieve a sheet resistivity of approximately 105 ohms per square. This forms P type source/drain regions 1118, while 31 sidewall spacers 1108 maintain the previous doping level of P
32 type lightly doped source/dra`in extensions 1120. P+ region 33 1117 is also formed within N well 1102, as is P~ region 1119 34 within P well 1103. This yields the device shown in the cross-section of Figure 9E, including N well 1102 having P channel 36 lightly doped drain device 112~ and novel diode ~16 constructed 37 in accordance with the teachings o~ this invention, and P well 38 1103 including N channel lightly doped drain device 1129 and 2 ~ 9 ~ D~ ~ ~
1 novel diode 516 constructed in accordance with the teachings of 2 this invention. Of interest, the structure shown in Figure 9E
3 includes novel diodes constructed in accordance with the 4 teachings of this invention and typical prior art lightly doped drain (~DD) CMOS device fabricated utilizing a simple process 6 without the need for additional masking steps in order to form 7 the additional diodes of this invention.
8 Figures lOA through lOE illustrate the fabrication steps 9 of an alternative embodiment o~ a method for constructing the novel diodes of the invention. ~eferring to Figure lOA, ll substrate 2101 may be either an N type substrate or a P type 12 substrate, as both N well 2102 and P well 2103 are formed 13 therein~ If desired, an N type substrate of desired doping may 14 be used, thereby avoiding the need to form N well 2102 or a P
type substrate of desired doping may be used, thereby avoiding 16 the nePd to form P well 2103. N well 2102 is formed in a 17 conventional manner, for example, having a dopant concentration 18 providing a sheet resistivity of approximately 3000 ohms per 19 square. Similarly, P well 2103 is formed in a conventional manner and having a dopant concentration, for example, 21 providing a she~t resistivity of approximately 3000 ohms per 22 square. A layer of field oxide 2104 is formed in a well known 23 manner in order to expose those portions of N well 2102 and 24 P well 2103 for which additional implants are to be performed.
A layer of gate oxide (not shown) is then formed, for example, 26 to a thickness of approximately 150 A , and a layer of 27 polycrystalline silicon is formed to a desired conductivity on 28 that gate oxide and patterned in a conventional mannex in order 29 to ~orm P channel gate electrode 2105 and N channel gate electrode 2106. Masking layer 2107 is formed and patterned, 31 and an N type implant is then performed, for example, using 32 phosphorous dopants implanted to a dose of approximately 2.5E13 33 at approximately 60 KEV in order to form a dopant concentration 34 of approximately 2 x 10l8/cm3. This forms lightly doped source/drain r~gions 2111 aligned to gate 2106 within N well 36 2103 and lightly doped N region 2110 within N well 2103.
37 As shown in Figure lOB, resist layer 2109 is used in order 38 to expose only those portions in which a first P type implant 10 .
~9~
1 is desired. At this time, a P type implant is perPormed, for 2 example, using boron implanted to a dose of approximately 2E13 3 at approximately 50 KEV to a dopant concentration of 4 approximately 3E18/cm3. This forms lightly doped source/drain regions 2120 aliyned to gate 2105 within N well 2102, and P
6 type region 2121 within P well 2103. Masking layar 2109 is 7 then removed and the device is oxidized, forming sidewall 8 spacers 2108 and 2109 on gate electrodes 2105 and 2106, ~ respectively (Fig. lOC). The oxide forming the sidewall spacers is formed to a greater thickness on the sidewalls of 11 the polycrystalline silicon gate electrodes than is the oxide 12 which is simultaneously formed on single crystalline portions 13 of the device.
14 Referring to Figure lOC, another masking layer 2113 is used to expose those portions of the device which are to 1~ receive an N type implant. This N type implant is performed, 17 for example, using arsenic implanted to a dose of approximately 18 5.5E15 at approximately 60 KEV, to a sheet resistivity of 19 approximately 75 ohms per square. This forms source/drain regions 2115 to a desired dopant concentration, while sidewall 21 spacers 2109 maintain the previously established dopant level 22 of lightly doped source/dxain extensions 2111, as is well known 23 in the art. N~ region 2114 is also formed within P well 2103, 24 as is N type region 2116 within N well 2102.
Referring to Figure lOD, another masking layer 2124 is 26 formed to expose those regions which are to receive a second 27 P type implant which is performed, for example, using boron 28 (BF2) implanted to a dose of approximately 5.5E15 at approxi-29 mately 60 KEV to achieve a sheet resistivity of approximately 105 ohms per square. This forms P type source/drain regions 31 2118, while sidewall spacers 2108 maintain the previous doping 32 level of P type lightly doped source/drain extensions 2120. P+
33 region 2117 is also formed within N well 2102, as is P+ region 34 2119 within P well 2103. This yields the device shown in the cross-section of Figure lOE, including N well 2102 having P
36 channel lightly doped drain device 2128 and novel diode 416 37 constructed in accordance with the teachings of this invention, 38 and P well 2103 including N channel lightly doped drain device 2 ~
1 212g and novel diode 516 constructed in accordance with the 2 teachings oP this invention. Of interest, the structure shown 3 in Figure 10E includes novel diodes constructed in accordance 4 with the tPachings of this invention and typical prior art lightly doped drain ~LDD) CMOS device fabricated utilizing a 6 simple process without the need for additional masking steps in 7 order to form the additional diodes of this invention. The 8 process of Figure 10 avoids the blanket N type implant of the 9 process of Figure 9, and thus the need to over-compensate with P type dopants to form P type regions.
11 Figures llA through llE illustrate the fabrication steps 12 of another alternative embodiment of a method for constructing 13 the novel diodes of the invention. Referring to Figure llA, 14 substrate 3101 may be either an N type substrate or a P type substrate, as both N well 3102 and P well 3103 are formed 16 therein. If desired, an N type substrate of desired doping may 17 be used, thereby avoiding the need to form N well 3102 or a P
18 type substrate of desired doping may be used, thereby avoiding 19 the need to form P well 3103. N well 3102 is formed in a conventional manner, for example, having a dopant concentration 21 providing a sheet resistivity of approximately 3000 ohms per 22 square. Similarly, P well 3103 is formed in a conventional 23 manner and having a dopant concentration, for example, 24 providing a sheet resistivity of approximately 3000 ohms per square. A layer of field oxide 3104 is formed in a well known 26 manner in order to expose those portions of N well 3102 and 27 P well 3103 for which additional implants are to be performed.
28 A layer of gate oxide (not shown) is then formed/ for example, 29 to a thickness of approximately 150 A , and a layer of polycrystalline silicon is formed to a desired conductivity on 31 that gate oxide and patterned in a conventional manner in order 32 to form gate electrodes 3105 and 3106. Masking layer 3201 is 33 then formed and patterned as shown, and an implant is then used 34 to form lightly doped N reqion 3110. This implant is performed, for example, using phosphorous dopants implantad to 36 a dose of approximately 2.5E13 at approximately 60 KEV in order 37 to form a dopant concentration of approxlmately 2 x 1018/cm3.
38 In this embodiment, lightly doped drain regions 3115 and 31~0 5 ~
1 (Figure 11~) are formed in a well known manner, for example 2 either prior to the masking step which utilizes masking layer 3 3201, or after one or both of the masking steps which utilize 4 masking layers 3201 and 3107. The device is then oxidized, forming sidewall spacers 3108 and 3109 (Fig. llC) on gate 6 electrodes 3105 and 3106, respectively. The oxide forming 7 these sidewall spacers is formed to a greater thicknass on the 8 sidewalls of the polycrystalline silicon gates than is the 9 oxide which is simultaneously ~ormed on the single crystalline portions of the device.
11 As shown in Figure llB, resist layer 3107 is used in order 12 to expose only those portions in which a lightly doped P type 13 region 3121 is to be formed. At this time, a P type implant is 14 performed, for example, using boron implanted to a dose of approximately 6E13 at approximately 50 KEV to a dopant 16 concentration of approximately 3E18/cm3.
17 Referring to Figure llC, another masking layer 3113 is 18 used to expose those portions of the device which are ~o 19 receive an N type implant. This N type implant is performed, for example, using arsenic implanted to a dose of approximately 21 5.5E15 at approximately 60 XEV, to a sheet resistivity of 22 approximately 75 ohms per square. This forms source/drain 23 regions 3111 to a desired dopant concentration, while sidewall 24 spacers 3109 maintain the previously established dopant level of lightly doped source/drain regions 3115, as is well known 26 in the art. N+ region 311~ is also formed within P well 3103, 27 as is N type region 3116 within N well 3102.
28 Referring to Figure llD, another masking layer 3124 is 29 formed to expose those regions which are to receive a P+
implant, which is performed, for example, using boron (BF2) 31 implanted to a dose of approximately 6E15 ~t approximately 60 32 KEV to achieve a sheet resistivity of approximately 105 ohms 33 per square. This forms P type source/drain regions 3118, while 34 sidewall spacers 3108 maintain the previous doping level of P
type source/drain extensions 3120. P+ region 3117 is also 36 formed within N well 3102, as is P+ region 3119 within P well 37 3103. This yields the device shown in the cross-section of 38 Figure llE, including N well 3102 having P channel lightly 2~2~
1 doped drain device 3128 and novel diode 416 constructed in 2 accordance with the teachings of this invention, and P well 3 3103 including N channel lightly doped drain device 3129 and 4 novel diode 516 constructed in accordance with the teachings of this invention. 0f interest, the structure shown in Figure llE
6 includes novel diodes constructed in accordance with the 7 teachings of this invention and typical prior art lightly doped 8 drain (LDD) CMOS device fabricated with additional masking 9 steps in order to form the additional diodes of this invention.
ll Figures 12A through 12E illustrate the fabrication steps 12 of an alternative embodiment of a method for constructing the 13 novel diodes of the invention. Referring to Figure 12A, 14 substrate 4101 may be either an N type substrate or a P type substrate, as both N well 4102 and P well 4103 are formed 16 therein. If desired, an N type substrate of desired doping may 17 be used, thereby avoiding the need to form N well 4102 or a P
18 type substrate of desired doping may be used, thereby avoiding 19 the need to form P well 4103. N well 4102 is formed in a conventional manner, for example, having a dopant concentration 21 providing a sheet resistivity of approximately 3000 ohms per 22 square. Similarly, P well 4103 is formed in a conventional 23 manner and having a dopant concentration, for example, 24 providing a sheet resistivity of approximately 3000 ohms per square. ~ layer of field oxide 4104 is formed in a well known 26 manner in order to expose those portions of N well ~102 and 27 P well 4103 for which additional implants are to be performed.
28 A layer of gate oxide (not shown) is then formed, for example, 29 to a thickness of approximately 150 A I and a layer of polycrystalline silicon is formed to a dasired conductivity on 31 that gate oxide and patterned in a conventional manner in order 32 to form P channel gate electrode 4105 and N channel gate 33 Plectrode 4106. A masking layer 4107 is formed and patterned, 34 and an N type implant is then performed, for example, using phosphorous dopants implanted to a dose of approximately 2.5E13 36 at approximately 60 KEV in order to form a dopant concentration 37 of approximately 2 x 1018/cm3. This forms lightly doped drain 38 regions 4111 and lightly doped N region 4110, as well as 14.
2~9~5~
1 implanting N type dopants into other exposed portions of the 2 device.
3 As shown in Figure 12B, resist layer 4109 is used in order 4 to expose only those portions in which a first P type implant is desired. At this time, a P type implant is performed, for 6 example, using boron implanted to a dose of approximately 2E13 7 at approximately 50 KEV to a dopant concentration of 8 approximately 3E1~/cm3. This forms lightly doped source/drain 9 regions 4120 aligned to gate 4105 within N well 4102, and P
type region 4121 within P well 4103. Masking layer 4109 is ll removed and sidewall spacers 4108 and 4109 (Fig. 12C) are now 12 formed on gate electroedes 4105 and 4106, respectively. The 13 oxide forming these sidewall spacers is formed to a greater 14 thickness on the sidewalls of the polycrystalline silicon gate electrodes than is the oxide which is simultaneously formed on 16 single crystalline portions of the device.
17 Referring to Figure 12C, another masking layer 4113 is 18 used to expose those portions of the device which are to 19 receive an N type implant. This N type implant is performed, for example, using arsenic implanted to a dose of approximately 21 5.5E15 at approximately 60 KEV, to a sheet resistivity of 22 approximately 75 ohms per square. This forms source/drain 23 regions 4115 to a desired dopant concentration, while sidewall 24 spacers 4109 maintain the previously established dopant level of lightly doped source/drain regions 4111, as is well known in 26 the art. N+ region 4114 is also formed within P well 4103, as 27 is N type region 4116 within N well 4102.
28 Referring to Figure 12D, another masking layer 4124 is 29 formed to expose those regions which are to receive a second P type implant which is performed, for example, using boron 31 (~F2~ implanted to a dose of approximately 5.5E15 at approxi-32 mately 60 KEV to achieve a sheet resistivity of appxoximately 33 105 ohms per square. This forms P type source~drain regions 34 4118, while sidewall spacers 4108 maintain the previous doping level of P type lightly doped source/drain extensions 4120. P~
36 region 4117 is also formed within N well 4102, as is P~ region 37 4119 within P well 4103. This yields the device shown in the 38 cross-section of Figure 12E, including N well 4102 having P
15.
20~20~0 1 channel lightly doped drain device 4128 and novel diode 416 2 constructed in accordance with the teachings of this invention, 3 and P well 4103 including N channel lightly doped drain device 4 4129 and novel diode 516 constructed in accordance with the teachings of this invention. Of interest, the structure shown 6 in Figure 12E includes novel diodes constructed in accordance 7 with the teachings of this invention and typical prior art 8 lightly doped drain ~Ldd) CMOS device abricated utilizing a 9 simple process without the need for additional masking steps in order to form the additional diodes of this invention. The 11 process of Figure 12 avoids the blanket N type implant of the 12 process of Figure 9, and thus the need to over-compensate with 13 P type dopants to form P type regions. Also of interest, 14 masking layer 4107 servies to block the N type implant into region 4121, thereby allowing this region 4121 to have a net 16 more highly P type concentration. This reduces the breakdown 17 voltage of the resultant diode 516 (Fig. 12E).
18 Alternative methods of N+ and P~ doping are suitable for 19 example, use of polycrystalline silicon barriers and oxide ~arriers of the source drain regions, in accordance with the 21 teachings of this invention in which increased N well and P
22 well concentrations are provided using the respective Ldd 23 diffusions. This protection method may be used in processes 24 which utilize other gate materials, such as silicides and metal.
26 BiCMoS devices also utilize Ldd diffusions as in CMOS, and 27 accordingly the method of this invention is suitable for use 28 with BiCMoS circuits.
29 One embodiment of ESD protection devices in use in accordance with this invention is illustrated in the plan view 31 of Figure 13. In this embodiment, the outer edge of an 32 integrated circuit (but within the location of bending pads 33 101/102) is encircled (although not necessarily completely) 34 with the protection diodes of this invention.
Figure 14a shows a more detailed plan view of the 36 highlighted portion of the chip shown in Figure 13. As shown, 37 the peripheral ring includes a plurality of diffused regions 38 formed within P well 511 and N well 411. Reference numerals 16.
~2~5~
1 are used in Figure 14a which correspond with those utili~ed in 2 Figures 4, 5, and 6. Figure 14b is a cross sectional view 3 depicting thP structure of Figure 14a, using similar reference 4 numerals. Also shown in Figure 14b are the diodes constructed in accordance with the teachings of this invention. If 6 desired, metal strapping can be used to provide low impedance 7 paths, for example, for VSS and VDD diffusion, as well as the 8 remaining diffusions shown in Figure 14a. Also, any number of 9 diffusion strips can be utilized in this fashion, thereby providing a desired number of ESD protection diodes. If 11 desired, only a single bulk region need be employed in this 12 ~ashion, to provide diodes for ESD protection as descibed 13 earlier with reference to Figures 7 and 8.
14 Figure 15 is a more detailed plan view of the structure of Figure 14a, including input bonding pad 101 and output bonding 16 pad 102. As shown in Figure 14B, P+ region 515 may be formed 17 outside of P well 511, thereby affording space savings as 18 compared to the embodiment shown in the cross-sectional view of 19 Figure 5 in which P+ region 515 is ~ormed within P well 511 and separated from region 514 by field oxide 512. Simarily, as 21 shown in the cross-sectional view of Figure 14B, space savings 22 is achieved by including N+ region 415 within N well 411 and 23 not separated from diffused region 414 by field oxide 412, as 24 is the case in the cross-sectional embodiment of Figure 4.
Diodes are depicted between various diffused regions, and are 26 numbered in accordance with the numbering scheme utiliæed in 27 Figure 6. As shown, a second layer of metal M2 is used to 28 connect bonding pads 101 and 102 to their respective diffused 29 regions which in turn form one terminal of the protection diodes constructed in accordance with the teachings of this 31 invention.
32 Figure 16 is a cross sectional view depicting an 33 alternative embodiment in which CMOS devices are formed 34 together with a novel diode of this invention in only one bulk region, as described above with reference to Figure 8. In 36 Figure 16, P well 5103 includes N channel MOS device 5129 and 37 P type P well contact 5119. N well 5102 includes P channel MOS
17.
1 device 5128 (which need not include liqhtly doped source/drain 2 regions), and novel diode 416.
3 Figure 17 depi~ts an alternative embodiment in which 4 two separate N wells 1102a and 1102b are used, with N well 1102a including one or more novel diodes of this invention and 6 N well 1102b containing one or more MOS devices. Similarly, 7 two separate P wells 1103a and 1103b are used, with P well 8 1103a including one or move novel diodes of this invention and 9 with P well 1103b incLuding one or more N channel devices. Of interest, the entire structure formed within wells 1102a, 11 1102b, 1103a, and 1103b are formed simultaneously utilizing a 12 single process sequence.
13 Likewise, it is to be understood that the embodiment 14 of Figure 16 can be modified to include two separate N wells, one containing a novel diode of this invention and one 16 containing a P channel device. Similarly, it is to be 17 understood that the embodiment of Figure 16 can be reversed 18 such that there is one or more P wells including an N channel 19 device and a novel diode of this invention, and a single N well including a P channel device.
23 Accordingly, as taught by way of the representative 24 examples described herein, a novel ~SD protection scheme is taught in which novel semiconductor diodes are fakricated ~6 simultaneously with the formation of typical prior art Ldd MOS
27 devices~
28 In accordance with the teachings of this invention, ESD
29 protection is provided with greater area efficiency than with prior art ESD protection techniques which utilize thin oxide 31 transistors~ When utilizing a thin oxide transistor for ESD
32 protection as in the prior art, only that portion of the drain 33 adjacent the gate electrode provides enhanced breakdown and 34 thus ESD protection. Conversely, in accordance with the teachings of this invention, wi$hin about the same area 36 required to form a single thin gate oxide protection device two 37 novel diodes of this invention may be formed, each providing 38 ESD protection. Furthermore, in prior art techniques which 18.
1 utilize thin gate oxide transistors, the drain contacts which 2 will carry the undesirably high ESD voltage must be spaced an 3 appropriate distance from the gate electrode in order to 4 prevent destruction of the thin gate oxide transistor, for example either due to thin gate oxide breakdown, or aluminum 6 migration from the aluminum drain contact to the gate 7 electrode. In accordance with the teachings of this invention, 8 since thin gate oxide is not used, the placement of contacts is ~ of little concern.
11 All publications and patent applications mentioned in 12 this specification are herein incorporated by reference to the 13 same extent as if each individual publication or patent 14 application was specifically and individually indicated to be incorporated by reference.
~6 17 The invention now being fully described, it 18 will be apparent to one of ordinary skill in the art that many 19 changes and modifications can be made thereto without departing from the spirit or scope of the appended claims.
19 .
7 Figure 3 is an illustration depicting the proximity of the 8 breakdown region of the grounded gate thin oxide transistor, 9 including sourae/drain regions 302, 303, lightly doped source/drain extensions 304, 305, thin gate oxide 301, 11 polycrystalline silicon gate electrode 306, and sidewall 12 spacers 307. The channel region is formed between the 13 source/drain extensions 304, 305 within P well 310 in substrate 14 311. It is influenced by the control voltage applied to polycrystalline silicon gate 306, in this instance VSS, which 16 is also applied to source/drain region 302. The input or 17 output structure to be protected is connected to source/drain 18 region 303. With the breakdown of the thin gate occurring in l9 region 399 so close to thin gate oxide 301, a potentially unreliable device is created. The thin oxide grounded gate 21 configuration is used because this device has a lower breakdown 22 than the thick oxide field transistor; in fact it gives the 23 lowest controlled breakdown voltage of all devices commonly 24 available on the chip today. In fact the thick field transistor, whether operated as grounded gate or high gate, 26 will probably surpass the breakdown voltage of the thin gate 27 oxide and hence is useless for protection. ~ince the grounded 28 gate thin oxide transistor has a breakdown between 12-14 volts, 29 this limits the thinness of the gate oxide which may be used.
The gate oxide breakdown must be greater than the protection 31 device breakdown. Generally for low voltage lap top or 32 portable operation, it is desirable to have maximum drive for 33 a given threshold voltage. One way to accomplish this is by 34 thinning the gate oxide to i~crease the Id~s of the transistor.
If the protection device is limited to 12 volts breakdown, at 36 best this will limit gate oxide to at least 140 angstroms. on 37 the other hand, if 8.0 volts is the breakdown of the protection 38 device it would be possible to decrease the oxide thickness to 2~92~
1 approximately 100 angstroms. This would increase the drive by 2 approximately 40% over the thin gate protected circuit.
3 The N+ and P+ diffusions available in CMOS processes may 4 be used to make a diode but since these two diffusions are usually of such high concentrations, they lead to poor I/V
6 characteristics, i.e., they are usually very leaky and have 7 very poor V/I knee characteristics. These characteristics make 8 such a diode a poor candidate for a protection device, having 9 a typical breakdown of 4.5 volts, and unacceptably less than the typical 5.0 volt power supply voltage.
12 Summary 13 In accordance with the teachings of those inventions, a 14 novel process is taught for forming diodes in a process which simultaneously forms MOS or CMOS devices. These diodes have 16 relatively low breakdown voltage, making them suitable for ESD
17 protection devices or as voltage reference diodes.
19 Brief Description of ~rawinqs Figure l is a schematic diagram depicting a typical prior 21 art ESD protection scheme;
22 Figure 2 is a schematic diagram depic.ting a typical prior 23 art circuit implementing the ESD protection of Figure l;
24 Figure 3 is a cross-sectional view of a typical MOS
transistor used for ESD protection, showing its breakdown 26 mechanism;
27 Figure 4 is a cross-sectional view depicting one 28 embodiment of a diode constructed within an N type region in 29 accordance with the teachings of this invention;
Figure 5 is a cross-sectional view depicting one 31 embodiment of a diode constructed within a P type region in 32 accordance with the teachings of this invention;
33 Figures 6 through 8 are schematic diagrams depicting 34 various embodiments of ESD protection circuits utilizing the diodes constructed in accordance with the teachings of this 36 invention;
2 ~ a 1 Figures 9A through 9E are cross-sectional views depicting 2 a fabrication sequence in accordance with one embodiment of 3 this invention;
4 Figures 10A through 10E are cross-sectional views depicting a fabrication sequence in accordance with another 6 embodiment of this invention;
7 Figures llA through llE are cross-sectional views 8 depicting a fabrication sequence in accordance with another 9 embodiment of this invention;
Figures 12A through 12E are cross-sectional views 11 depicting a fabrication sequence in accordance with another 12 embodiment of this invention;
13 Figure 13 is a plan view depicting one embodiment of the 14 placement of diodes constructed in accordance with the teachings of this invention in an integrated circuit;
16 Figures 14A and 14B are top and cross-sectional views, 17 respectively, depicting diodes constructed in accordance with 18 the teachings of this invention;
19 Figure 15 is a plan view including bonding pads;
Figure 16 is a cross sectional view of an alternative 21 embodiment; and 22 Figure 17 is a cross sectional view of yet another 23 embodiment.
Detailed Description 26 In accordance with the teachings of this invention, a low 27 voltage protection device is taught which is capable of being 28 fabricated simultaneously with the fabrication of typical prior 29 art MOS or CMOS devices which include lightly doped drain devices. In accordance with the teachings of this inv~ntion, 31 such protection diodes can be formed without the need for 32 additional masking or implantation steps. The protection 33 diodes of this invention are compatible with the current 34 process technology including one micron and smaller CMOS and MOS process flows. In accordance with the teachings of this 36 invention, the use of lower breakdown voltage protection 37 devices allows the use of thinner gate oxide, thereby enhancing 38 operating speed and increasing transistor drive, without 2~2~
1 sacrificing reliability. Utilizing diodes in accordance with 2 the teachings of this invention for ESD protection alleviates 3 the problem associated with prior art use of thin oxide 4 transistors for this purpose, in which the thin oxide is placed at risk. In accordance with the teachings of this invention, 6 series resistors are not needed in order to affectuate ESD
7 protection, thereby saving integrated ci~cuit area, as well as 8 affording greater ES~ protection by quickly dissipating ESD
9 potentials through a low impedance path.
Examples of the protection diodes of this invention are 11 shown in cross-section in Figures 4 and 5. Since the diodes 12 are formed in bulk CMOS, the N well diode has one side 13 connected to VDD and the P well has one junction connected to 14 VSS, as shown in Figures 4 and 5, respectively.
Referring to Figure 4, within N type bulk 410 is ~ormed N
16 well 411, in a well known manner. Field oxide regions 412 are 17 also formed in a well known manner in order to expose only 18 those portions of the substrate surface which are of interest 19 for electrical connections and further doping. Within N well 411 is ormed N type regions 414 surrounding Pt region 413, and 21 spaced apart N+ region 415. An N protection diode in 22 accordance with the teachings of this invention, shown in 23 representative format as diode 416, is formed having its anode 24 as P+ region 413 and its cathode as N+ region 415. In this example, cathode 415 of protection diode 416 is connected to 26 positive supply VDD, and anode 413 of protection diode 416 is 27 connected to the inpu~ or output device to be protected (not 28 shown). As shown in Figure 4, reverse breakdown occurs in 29 region 499 where N type region 414 and P+ anode 413 have their greatest dopant differential~ In accordance with the teachings 31 of this invention, N well protection diode 416 meets the 32 requirement:
34 (VDD-YSS~<(diode breakdown voltage)<<(thin oxide breakdown voltage) (1) 37 Referring to Figure 5, within N type bulk 510 is formed P
38 well 511, in a well known manner. Field oxide regions 512 are 2 ~ 0 1 also formed in a well known manner in order to expose only 2 those portions of the substrate surface which are of interest 3 for electrical connections and further doping. Within P well 4 511 is formed P type regions 514 surrounding N+ region 513, and spaced apart P~ region 515. A P protection d.iode in accordance 6 with the teachings of this invention, shown in representative 7 format as diode 516, is formed having its anode as P~ region 8 515 and its cathode as N~ region 51~. In this example, anode 9 515 o~ protection diode 516 is connected to negative supply VSS, and cathode 513 of protection diode 516 i5 connected to 11 the input or output device to be protected (not shown). As 12 shown in Figure 5, reverse ~reakdown occurs in region 599 where 13 P type region 514 and N+ cathode 513 have their greates~ dopant 14 differential.
Figure 6 illustrates the use of novel diodes 416 and 516 16 of Figures 4 and 5, respectively, as VDD input protection diode 17 lOla, VDD output protection diode 102a, and VSS input 18 protection diode lOlb, VSS output protection diode 102b, 19 respectively. Voltage supply protection diode 103 can be fabricated as either N well diode 416 of Figure 4 or P well 21 diode 516 of Figure 5. The breakdown voltage of the diodes 22 fabricated in accordance with the teashings of this invention 23 is on the order of approximately 8.0 volts. With the 24 protection diodes utilized as shown, the actual protection offered by a diode of this invention is dependent on the size 26 of the protection diode, with larger diodes capable of 27 absorbing larger amounts of charge. Note there is no thin 28 oxide in the region of the breakdown of this structure, thus 29 making the diodes of this invention more desirable for handling ~SD than prior art devices.
31 Figures 7 and 8 show alt~rnative embodiments in which 32 protection diodes of this inv~ntion provide single ended 33 protection only (protection to only a single power supply), but 34 good protection is provided for both positive and neyative ESD, respectively~
36 Referring to Figure 7, a positive ESD pulse to input 101 37 reverse biases input protection diode lOlb/516 and forces i 38 into conduction when 8.0 volts is surpassed. The charge then 2 ~ 5 ~
1 passes to VSS line 115 which is protected by large protection 2 diode 103, which shunts the charge to VDD line 116. On the 3 other hand, a negative ESD pulse to input 101 forward biases 4 input protection diod~ 101b/516 and the pulse passes to VSS
line 115 which is protected by large protection diode 103, 6 which conducts if 8.0 volts is exceeded. Large protection 7 diode 103 limits VDD-VSS to 8.0 volts.
8 Still re~erring to ~igure 7, a positive ESD pulse to 9 output 102 reverse biases output protection diode 102b/516 and forces it into conduction when 8.0 volts is surpassed. The 11 charge then passes to VSS line 115 which is protected by large 12 protection diode 103, which shunts the charge to VDD line 116.
13 On the other hand, a negative ESD pulse to output 102 forward 14 biases output protection diode 102b/516 and the pulse passess to VSS line 115 which is protected by large protection diode 16 103, which sonducts if 8.0 volts is exceeded.
17 A similar ESD protection mechanism is shown in Figure ~, 18 in which a negative ESD pulse to input 101 reverse biases input 19 protection diode 101a/416 and forces it into conduction when 8.0 volts is surpassed. The charge then passes to VDD line 116 21 which is protected by large protection diode 103, which shunts 2Z the charge to VSS line 115. On the other hand, a positive ESD
23 pulse to input 101 forward biases input protection diode 24 101a/416 and the pulse passes to VDD line 116 whih is protected by large protection diode 103, which conducts if 8.0 26 volts is exceeded. Thus, larye protection diode 103 limits 27 VDD-VSS to 8.0 volts. A negative ~SD pulse to output 102 28 reverse biases output protection diode 102a/416 and forces it 29 into conduction when 8.0 volts is surpassed. The charge then passes to VDD line 116 which is protected by large protection 31 diode 103, which shunts the charge to VSS line 115. On the 32 other hand, a positive ESD pulse to output 102 forwaxd biases 33 output protection diode 102a/416 and the pulse passes to VDD
34 line 116 which is protected by large protection diode 103, which conducts if 8.0 volts is exceeded.
36 This 8.0V diode can also be used as a reference diode in 37 +5.0V linear circuit systems. In general, reference diodes are 38 difficult to build in an advanced CMOS process because dopant 7.
2~2~
1 concentrations of the appropriate level to make reliable diodes 2 o~ low breakdowns are not available. The method of this 3 invention overcomes the limitations of the prior art and 4 provides very good reference diodes.
Figures 9A through 9E illustrate the fabrication steps of 6 one embodiment of a method for constructing the novel diodes of 7 the inve~tion. Referrin~ to Figure 9A, substrate 1101 may be 8 either an N type substrate or a P type substrate, as both N
9 well 1102 and P well 1103 are formed therein. If desired, an N type substrate of desired doplng may be used, thereby 11 avoiding the need to form N well 1102 or a P type sub~trate of 12 desired doping may be used, thereby avoiding the need to form 13 P well 1103. N well 1102 is formed in a conventional manner, 14 for example, having a dopant concentration providing a sheet resistivity of approximately 3000 ohms per square. Similarly, 16 P well 1103 is formed in a conventional manner and has a dopant 17 concentration providing, for example, a sheet resistivity of 18 approximately 3000 ohms per square. A layer of field oxide 19 1104 is formed in a well known manner in order to expose those portions of N well 1102 and P well 1103 for which additional 21 implants are to be performed. A layer of gate oxide (not 22 shown) is then formed, for example, to a thickness of ~3 approximately 150 A , and a layer of polycrystalline silicon is 24 formed to a desired conductivity on that gate oxide and patterned in a conventional manner in order to form gate 26 electrodes 1105 and 1106. A blanket N type implant is then 27 performed, for example, using phosphorous dopa~ts implanted to 28 a dose of approximately 2.5E13 at approximately ~0 KEV in order 29 to provide a dopant concentration of approximately 2 x 1018/cm3. This forms N channel lightly doped drains 1111 and 3~ lightly doped N r~gion 1110, as well as lntroducing dopants 32 into the other expoæed portions of the devices.
33 As shown in Figure 9B, resist layer 1107 is used in order 34 to expose only those portions in which a P type im~lant is desired. At this time, a P type implant is performed, for 36 example, using boron implanted to a dose o~ approximately 6E13 37 at approximately 50 KEV to a net (i.e., over-compensated) 38 dopant concentration of approximately 3E18/cm3. This forms 2~0~a 1 lightly doped source/drain regions 1120 aligned to gate 1105 2 within N well 1102, and P type region 1121 within P well 1103.
3 This P type region 1121 is sufficiently concentrated to 4 compensate the previous N type implant in that same region, which was not necessary but introduced by way of convenience in 6 order to allow the N type implant to be a blanket implant.
7 Masking layer 1107 is removed and the device is then oxidized, 8 forming sidewall spacers 1108 on gate electrodes 1105 and 1106.
9 The oxide forming sidewall spacers 1108 is Pormed to a greater thickness on the sidewalls of polycrystalline silicon gates 11 1105 and 1106 than is the oxide which is simultaneously formed 12 on single crystal portions of the device, as is well known in 13 the artO
14 Referring to Figure 9C, another masking layer 1109 is used to expose those portions of the device which are to receive an 16 N type implant. This N type implant is performed, for example, 17 using arsenic implanted to a dose of approximately 5.5E15 at 18 approximately 60 KEV, to a sheet resistivity of approximately 19 75 ohms per square. This forms source/drain regions 1115 to a desired dopant concentration, while sidewall spacers 1108 21 maintain the previously established dopant level to provide 22 lightly doped source/drain regions 1111, a~ is well known in 23 the art. N+ region 1114 is also formed within P well 1103, as 24 is N type region 1116 within N well 1102~
Referring to Figure 9D, another masking layer 1113 is 26 formed to expose those regions which are to receive a P+
27 implant, which is performed, for example, using boron (BF2) 28 implanted to a dose of approximately 5.5E15 at approximately 60 29 KEV to achieve a sheet resistivity of approximately 105 ohms per square. This forms P type source/drain regions 1118, while 31 sidewall spacers 1108 maintain the previous doping level of P
32 type lightly doped source/dra`in extensions 1120. P+ region 33 1117 is also formed within N well 1102, as is P~ region 1119 34 within P well 1103. This yields the device shown in the cross-section of Figure 9E, including N well 1102 having P channel 36 lightly doped drain device 112~ and novel diode ~16 constructed 37 in accordance with the teachings o~ this invention, and P well 38 1103 including N channel lightly doped drain device 1129 and 2 ~ 9 ~ D~ ~ ~
1 novel diode 516 constructed in accordance with the teachings of 2 this invention. Of interest, the structure shown in Figure 9E
3 includes novel diodes constructed in accordance with the 4 teachings of this invention and typical prior art lightly doped drain (~DD) CMOS device fabricated utilizing a simple process 6 without the need for additional masking steps in order to form 7 the additional diodes of this invention.
8 Figures lOA through lOE illustrate the fabrication steps 9 of an alternative embodiment o~ a method for constructing the novel diodes of the invention. ~eferring to Figure lOA, ll substrate 2101 may be either an N type substrate or a P type 12 substrate, as both N well 2102 and P well 2103 are formed 13 therein~ If desired, an N type substrate of desired doping may 14 be used, thereby avoiding the need to form N well 2102 or a P
type substrate of desired doping may be used, thereby avoiding 16 the nePd to form P well 2103. N well 2102 is formed in a 17 conventional manner, for example, having a dopant concentration 18 providing a sheet resistivity of approximately 3000 ohms per 19 square. Similarly, P well 2103 is formed in a conventional manner and having a dopant concentration, for example, 21 providing a she~t resistivity of approximately 3000 ohms per 22 square. A layer of field oxide 2104 is formed in a well known 23 manner in order to expose those portions of N well 2102 and 24 P well 2103 for which additional implants are to be performed.
A layer of gate oxide (not shown) is then formed, for example, 26 to a thickness of approximately 150 A , and a layer of 27 polycrystalline silicon is formed to a desired conductivity on 28 that gate oxide and patterned in a conventional mannex in order 29 to ~orm P channel gate electrode 2105 and N channel gate electrode 2106. Masking layer 2107 is formed and patterned, 31 and an N type implant is then performed, for example, using 32 phosphorous dopants implanted to a dose of approximately 2.5E13 33 at approximately 60 KEV in order to form a dopant concentration 34 of approximately 2 x 10l8/cm3. This forms lightly doped source/drain r~gions 2111 aligned to gate 2106 within N well 36 2103 and lightly doped N region 2110 within N well 2103.
37 As shown in Figure lOB, resist layer 2109 is used in order 38 to expose only those portions in which a first P type implant 10 .
~9~
1 is desired. At this time, a P type implant is perPormed, for 2 example, using boron implanted to a dose of approximately 2E13 3 at approximately 50 KEV to a dopant concentration of 4 approximately 3E18/cm3. This forms lightly doped source/drain regions 2120 aliyned to gate 2105 within N well 2102, and P
6 type region 2121 within P well 2103. Masking layar 2109 is 7 then removed and the device is oxidized, forming sidewall 8 spacers 2108 and 2109 on gate electrodes 2105 and 2106, ~ respectively (Fig. lOC). The oxide forming the sidewall spacers is formed to a greater thickness on the sidewalls of 11 the polycrystalline silicon gate electrodes than is the oxide 12 which is simultaneously formed on single crystalline portions 13 of the device.
14 Referring to Figure lOC, another masking layer 2113 is used to expose those portions of the device which are to 1~ receive an N type implant. This N type implant is performed, 17 for example, using arsenic implanted to a dose of approximately 18 5.5E15 at approximately 60 KEV, to a sheet resistivity of 19 approximately 75 ohms per square. This forms source/drain regions 2115 to a desired dopant concentration, while sidewall 21 spacers 2109 maintain the previously established dopant level 22 of lightly doped source/dxain extensions 2111, as is well known 23 in the art. N~ region 2114 is also formed within P well 2103, 24 as is N type region 2116 within N well 2102.
Referring to Figure lOD, another masking layer 2124 is 26 formed to expose those regions which are to receive a second 27 P type implant which is performed, for example, using boron 28 (BF2) implanted to a dose of approximately 5.5E15 at approxi-29 mately 60 KEV to achieve a sheet resistivity of approximately 105 ohms per square. This forms P type source/drain regions 31 2118, while sidewall spacers 2108 maintain the previous doping 32 level of P type lightly doped source/drain extensions 2120. P+
33 region 2117 is also formed within N well 2102, as is P+ region 34 2119 within P well 2103. This yields the device shown in the cross-section of Figure lOE, including N well 2102 having P
36 channel lightly doped drain device 2128 and novel diode 416 37 constructed in accordance with the teachings of this invention, 38 and P well 2103 including N channel lightly doped drain device 2 ~
1 212g and novel diode 516 constructed in accordance with the 2 teachings oP this invention. Of interest, the structure shown 3 in Figure 10E includes novel diodes constructed in accordance 4 with the tPachings of this invention and typical prior art lightly doped drain ~LDD) CMOS device fabricated utilizing a 6 simple process without the need for additional masking steps in 7 order to form the additional diodes of this invention. The 8 process of Figure 10 avoids the blanket N type implant of the 9 process of Figure 9, and thus the need to over-compensate with P type dopants to form P type regions.
11 Figures llA through llE illustrate the fabrication steps 12 of another alternative embodiment of a method for constructing 13 the novel diodes of the invention. Referring to Figure llA, 14 substrate 3101 may be either an N type substrate or a P type substrate, as both N well 3102 and P well 3103 are formed 16 therein. If desired, an N type substrate of desired doping may 17 be used, thereby avoiding the need to form N well 3102 or a P
18 type substrate of desired doping may be used, thereby avoiding 19 the need to form P well 3103. N well 3102 is formed in a conventional manner, for example, having a dopant concentration 21 providing a sheet resistivity of approximately 3000 ohms per 22 square. Similarly, P well 3103 is formed in a conventional 23 manner and having a dopant concentration, for example, 24 providing a sheet resistivity of approximately 3000 ohms per square. A layer of field oxide 3104 is formed in a well known 26 manner in order to expose those portions of N well 3102 and 27 P well 3103 for which additional implants are to be performed.
28 A layer of gate oxide (not shown) is then formed/ for example, 29 to a thickness of approximately 150 A , and a layer of polycrystalline silicon is formed to a desired conductivity on 31 that gate oxide and patterned in a conventional manner in order 32 to form gate electrodes 3105 and 3106. Masking layer 3201 is 33 then formed and patterned as shown, and an implant is then used 34 to form lightly doped N reqion 3110. This implant is performed, for example, using phosphorous dopants implantad to 36 a dose of approximately 2.5E13 at approximately 60 KEV in order 37 to form a dopant concentration of approxlmately 2 x 1018/cm3.
38 In this embodiment, lightly doped drain regions 3115 and 31~0 5 ~
1 (Figure 11~) are formed in a well known manner, for example 2 either prior to the masking step which utilizes masking layer 3 3201, or after one or both of the masking steps which utilize 4 masking layers 3201 and 3107. The device is then oxidized, forming sidewall spacers 3108 and 3109 (Fig. llC) on gate 6 electrodes 3105 and 3106, respectively. The oxide forming 7 these sidewall spacers is formed to a greater thicknass on the 8 sidewalls of the polycrystalline silicon gates than is the 9 oxide which is simultaneously ~ormed on the single crystalline portions of the device.
11 As shown in Figure llB, resist layer 3107 is used in order 12 to expose only those portions in which a lightly doped P type 13 region 3121 is to be formed. At this time, a P type implant is 14 performed, for example, using boron implanted to a dose of approximately 6E13 at approximately 50 KEV to a dopant 16 concentration of approximately 3E18/cm3.
17 Referring to Figure llC, another masking layer 3113 is 18 used to expose those portions of the device which are ~o 19 receive an N type implant. This N type implant is performed, for example, using arsenic implanted to a dose of approximately 21 5.5E15 at approximately 60 XEV, to a sheet resistivity of 22 approximately 75 ohms per square. This forms source/drain 23 regions 3111 to a desired dopant concentration, while sidewall 24 spacers 3109 maintain the previously established dopant level of lightly doped source/drain regions 3115, as is well known 26 in the art. N+ region 311~ is also formed within P well 3103, 27 as is N type region 3116 within N well 3102.
28 Referring to Figure llD, another masking layer 3124 is 29 formed to expose those regions which are to receive a P+
implant, which is performed, for example, using boron (BF2) 31 implanted to a dose of approximately 6E15 ~t approximately 60 32 KEV to achieve a sheet resistivity of approximately 105 ohms 33 per square. This forms P type source/drain regions 3118, while 34 sidewall spacers 3108 maintain the previous doping level of P
type source/drain extensions 3120. P+ region 3117 is also 36 formed within N well 3102, as is P+ region 3119 within P well 37 3103. This yields the device shown in the cross-section of 38 Figure llE, including N well 3102 having P channel lightly 2~2~
1 doped drain device 3128 and novel diode 416 constructed in 2 accordance with the teachings of this invention, and P well 3 3103 including N channel lightly doped drain device 3129 and 4 novel diode 516 constructed in accordance with the teachings of this invention. 0f interest, the structure shown in Figure llE
6 includes novel diodes constructed in accordance with the 7 teachings of this invention and typical prior art lightly doped 8 drain (LDD) CMOS device fabricated with additional masking 9 steps in order to form the additional diodes of this invention.
ll Figures 12A through 12E illustrate the fabrication steps 12 of an alternative embodiment of a method for constructing the 13 novel diodes of the invention. Referring to Figure 12A, 14 substrate 4101 may be either an N type substrate or a P type substrate, as both N well 4102 and P well 4103 are formed 16 therein. If desired, an N type substrate of desired doping may 17 be used, thereby avoiding the need to form N well 4102 or a P
18 type substrate of desired doping may be used, thereby avoiding 19 the need to form P well 4103. N well 4102 is formed in a conventional manner, for example, having a dopant concentration 21 providing a sheet resistivity of approximately 3000 ohms per 22 square. Similarly, P well 4103 is formed in a conventional 23 manner and having a dopant concentration, for example, 24 providing a sheet resistivity of approximately 3000 ohms per square. ~ layer of field oxide 4104 is formed in a well known 26 manner in order to expose those portions of N well ~102 and 27 P well 4103 for which additional implants are to be performed.
28 A layer of gate oxide (not shown) is then formed, for example, 29 to a thickness of approximately 150 A I and a layer of polycrystalline silicon is formed to a dasired conductivity on 31 that gate oxide and patterned in a conventional manner in order 32 to form P channel gate electrode 4105 and N channel gate 33 Plectrode 4106. A masking layer 4107 is formed and patterned, 34 and an N type implant is then performed, for example, using phosphorous dopants implanted to a dose of approximately 2.5E13 36 at approximately 60 KEV in order to form a dopant concentration 37 of approximately 2 x 1018/cm3. This forms lightly doped drain 38 regions 4111 and lightly doped N region 4110, as well as 14.
2~9~5~
1 implanting N type dopants into other exposed portions of the 2 device.
3 As shown in Figure 12B, resist layer 4109 is used in order 4 to expose only those portions in which a first P type implant is desired. At this time, a P type implant is performed, for 6 example, using boron implanted to a dose of approximately 2E13 7 at approximately 50 KEV to a dopant concentration of 8 approximately 3E1~/cm3. This forms lightly doped source/drain 9 regions 4120 aligned to gate 4105 within N well 4102, and P
type region 4121 within P well 4103. Masking layer 4109 is ll removed and sidewall spacers 4108 and 4109 (Fig. 12C) are now 12 formed on gate electroedes 4105 and 4106, respectively. The 13 oxide forming these sidewall spacers is formed to a greater 14 thickness on the sidewalls of the polycrystalline silicon gate electrodes than is the oxide which is simultaneously formed on 16 single crystalline portions of the device.
17 Referring to Figure 12C, another masking layer 4113 is 18 used to expose those portions of the device which are to 19 receive an N type implant. This N type implant is performed, for example, using arsenic implanted to a dose of approximately 21 5.5E15 at approximately 60 KEV, to a sheet resistivity of 22 approximately 75 ohms per square. This forms source/drain 23 regions 4115 to a desired dopant concentration, while sidewall 24 spacers 4109 maintain the previously established dopant level of lightly doped source/drain regions 4111, as is well known in 26 the art. N+ region 4114 is also formed within P well 4103, as 27 is N type region 4116 within N well 4102.
28 Referring to Figure 12D, another masking layer 4124 is 29 formed to expose those regions which are to receive a second P type implant which is performed, for example, using boron 31 (~F2~ implanted to a dose of approximately 5.5E15 at approxi-32 mately 60 KEV to achieve a sheet resistivity of appxoximately 33 105 ohms per square. This forms P type source~drain regions 34 4118, while sidewall spacers 4108 maintain the previous doping level of P type lightly doped source/drain extensions 4120. P~
36 region 4117 is also formed within N well 4102, as is P~ region 37 4119 within P well 4103. This yields the device shown in the 38 cross-section of Figure 12E, including N well 4102 having P
15.
20~20~0 1 channel lightly doped drain device 4128 and novel diode 416 2 constructed in accordance with the teachings of this invention, 3 and P well 4103 including N channel lightly doped drain device 4 4129 and novel diode 516 constructed in accordance with the teachings of this invention. Of interest, the structure shown 6 in Figure 12E includes novel diodes constructed in accordance 7 with the teachings of this invention and typical prior art 8 lightly doped drain ~Ldd) CMOS device abricated utilizing a 9 simple process without the need for additional masking steps in order to form the additional diodes of this invention. The 11 process of Figure 12 avoids the blanket N type implant of the 12 process of Figure 9, and thus the need to over-compensate with 13 P type dopants to form P type regions. Also of interest, 14 masking layer 4107 servies to block the N type implant into region 4121, thereby allowing this region 4121 to have a net 16 more highly P type concentration. This reduces the breakdown 17 voltage of the resultant diode 516 (Fig. 12E).
18 Alternative methods of N+ and P~ doping are suitable for 19 example, use of polycrystalline silicon barriers and oxide ~arriers of the source drain regions, in accordance with the 21 teachings of this invention in which increased N well and P
22 well concentrations are provided using the respective Ldd 23 diffusions. This protection method may be used in processes 24 which utilize other gate materials, such as silicides and metal.
26 BiCMoS devices also utilize Ldd diffusions as in CMOS, and 27 accordingly the method of this invention is suitable for use 28 with BiCMoS circuits.
29 One embodiment of ESD protection devices in use in accordance with this invention is illustrated in the plan view 31 of Figure 13. In this embodiment, the outer edge of an 32 integrated circuit (but within the location of bending pads 33 101/102) is encircled (although not necessarily completely) 34 with the protection diodes of this invention.
Figure 14a shows a more detailed plan view of the 36 highlighted portion of the chip shown in Figure 13. As shown, 37 the peripheral ring includes a plurality of diffused regions 38 formed within P well 511 and N well 411. Reference numerals 16.
~2~5~
1 are used in Figure 14a which correspond with those utili~ed in 2 Figures 4, 5, and 6. Figure 14b is a cross sectional view 3 depicting thP structure of Figure 14a, using similar reference 4 numerals. Also shown in Figure 14b are the diodes constructed in accordance with the teachings of this invention. If 6 desired, metal strapping can be used to provide low impedance 7 paths, for example, for VSS and VDD diffusion, as well as the 8 remaining diffusions shown in Figure 14a. Also, any number of 9 diffusion strips can be utilized in this fashion, thereby providing a desired number of ESD protection diodes. If 11 desired, only a single bulk region need be employed in this 12 ~ashion, to provide diodes for ESD protection as descibed 13 earlier with reference to Figures 7 and 8.
14 Figure 15 is a more detailed plan view of the structure of Figure 14a, including input bonding pad 101 and output bonding 16 pad 102. As shown in Figure 14B, P+ region 515 may be formed 17 outside of P well 511, thereby affording space savings as 18 compared to the embodiment shown in the cross-sectional view of 19 Figure 5 in which P+ region 515 is ~ormed within P well 511 and separated from region 514 by field oxide 512. Simarily, as 21 shown in the cross-sectional view of Figure 14B, space savings 22 is achieved by including N+ region 415 within N well 411 and 23 not separated from diffused region 414 by field oxide 412, as 24 is the case in the cross-sectional embodiment of Figure 4.
Diodes are depicted between various diffused regions, and are 26 numbered in accordance with the numbering scheme utiliæed in 27 Figure 6. As shown, a second layer of metal M2 is used to 28 connect bonding pads 101 and 102 to their respective diffused 29 regions which in turn form one terminal of the protection diodes constructed in accordance with the teachings of this 31 invention.
32 Figure 16 is a cross sectional view depicting an 33 alternative embodiment in which CMOS devices are formed 34 together with a novel diode of this invention in only one bulk region, as described above with reference to Figure 8. In 36 Figure 16, P well 5103 includes N channel MOS device 5129 and 37 P type P well contact 5119. N well 5102 includes P channel MOS
17.
1 device 5128 (which need not include liqhtly doped source/drain 2 regions), and novel diode 416.
3 Figure 17 depi~ts an alternative embodiment in which 4 two separate N wells 1102a and 1102b are used, with N well 1102a including one or more novel diodes of this invention and 6 N well 1102b containing one or more MOS devices. Similarly, 7 two separate P wells 1103a and 1103b are used, with P well 8 1103a including one or move novel diodes of this invention and 9 with P well 1103b incLuding one or more N channel devices. Of interest, the entire structure formed within wells 1102a, 11 1102b, 1103a, and 1103b are formed simultaneously utilizing a 12 single process sequence.
13 Likewise, it is to be understood that the embodiment 14 of Figure 16 can be modified to include two separate N wells, one containing a novel diode of this invention and one 16 containing a P channel device. Similarly, it is to be 17 understood that the embodiment of Figure 16 can be reversed 18 such that there is one or more P wells including an N channel 19 device and a novel diode of this invention, and a single N well including a P channel device.
23 Accordingly, as taught by way of the representative 24 examples described herein, a novel ~SD protection scheme is taught in which novel semiconductor diodes are fakricated ~6 simultaneously with the formation of typical prior art Ldd MOS
27 devices~
28 In accordance with the teachings of this invention, ESD
29 protection is provided with greater area efficiency than with prior art ESD protection techniques which utilize thin oxide 31 transistors~ When utilizing a thin oxide transistor for ESD
32 protection as in the prior art, only that portion of the drain 33 adjacent the gate electrode provides enhanced breakdown and 34 thus ESD protection. Conversely, in accordance with the teachings of this invention, wi$hin about the same area 36 required to form a single thin gate oxide protection device two 37 novel diodes of this invention may be formed, each providing 38 ESD protection. Furthermore, in prior art techniques which 18.
1 utilize thin gate oxide transistors, the drain contacts which 2 will carry the undesirably high ESD voltage must be spaced an 3 appropriate distance from the gate electrode in order to 4 prevent destruction of the thin gate oxide transistor, for example either due to thin gate oxide breakdown, or aluminum 6 migration from the aluminum drain contact to the gate 7 electrode. In accordance with the teachings of this invention, 8 since thin gate oxide is not used, the placement of contacts is ~ of little concern.
11 All publications and patent applications mentioned in 12 this specification are herein incorporated by reference to the 13 same extent as if each individual publication or patent 14 application was specifically and individually indicated to be incorporated by reference.
~6 17 The invention now being fully described, it 18 will be apparent to one of ordinary skill in the art that many 19 changes and modifications can be made thereto without departing from the spirit or scope of the appended claims.
19 .
Claims (21)
1. A method of fabricating a semiconductor structure comprising the steps of:
a) forming within a first bulk region (1103) of a first conductivity type (p) a lightly doped source/drain region (1111) of a second conductivity type (N) opposite said first conductivity type;
b) forming within a second bulk region (1102) of said second conductivity type, a second conductivity type lightly doped portion (1110) of a first diode region;
c) forming within said second bulk region (1102) a lightly doped source/drain region (1120) of said first conductivity type;
d) forming within said first bulk region (1103) a first conductivity type lightly doped portion (1121) of a first diode region;
e) forming within said first bulk region (1103) a second conductivity type portion (1114) of said first diode region;
f) forming within said first bulk region (1103) a source/drain region (1115) of said second conductivity type;
g) forming within said second bulk region (1102) a second diode region (1116) of said second conductivity type;
h) forming within said first bulk region (1103) a second diode region (1119) of said first conductivity type;
i) forming within said second bulk region (1102) a source/drain region (1118) of said first conductivity type; and j) forming within said second bulk region (1102) a first conductivity type portion (1117) of said first diode region, wherein said first bulk region comprises a lightly doped source/drain MOS device and a diode having said second conductivity type portion of said first diode region formed within said first bulk region serving as a first terminal of 20.
said diode and said second diode region within said first bulk region serves as a second terminal of said diode, and wherein said second bulk region comprises a lightly doped source/drain MOS device and a diode having said first conductivity type portion of said first diode region within said second bulk region serving as a first terminal of said diode and said second diode region within said second bulk region serves as a second terminal of said diode.
a) forming within a first bulk region (1103) of a first conductivity type (p) a lightly doped source/drain region (1111) of a second conductivity type (N) opposite said first conductivity type;
b) forming within a second bulk region (1102) of said second conductivity type, a second conductivity type lightly doped portion (1110) of a first diode region;
c) forming within said second bulk region (1102) a lightly doped source/drain region (1120) of said first conductivity type;
d) forming within said first bulk region (1103) a first conductivity type lightly doped portion (1121) of a first diode region;
e) forming within said first bulk region (1103) a second conductivity type portion (1114) of said first diode region;
f) forming within said first bulk region (1103) a source/drain region (1115) of said second conductivity type;
g) forming within said second bulk region (1102) a second diode region (1116) of said second conductivity type;
h) forming within said first bulk region (1103) a second diode region (1119) of said first conductivity type;
i) forming within said second bulk region (1102) a source/drain region (1118) of said first conductivity type; and j) forming within said second bulk region (1102) a first conductivity type portion (1117) of said first diode region, wherein said first bulk region comprises a lightly doped source/drain MOS device and a diode having said second conductivity type portion of said first diode region formed within said first bulk region serving as a first terminal of 20.
said diode and said second diode region within said first bulk region serves as a second terminal of said diode, and wherein said second bulk region comprises a lightly doped source/drain MOS device and a diode having said first conductivity type portion of said first diode region within said second bulk region serving as a first terminal of said diode and said second diode region within said second bulk region serves as a second terminal of said diode.
2. A method as in claim 1, wherein steps a and b are performed simultaneously.
3. A method as in claim 2, wherein steps a and b are performed simultaneously using a blanket implant.
4. A method as in claim 1, wherein steps c and d are performed simultaneously.
5. A method as in claim 1, wherein steps e, f, and g are performed simultaneously.
6. A method as in claim 1, wherein steps h, i, and j are performed simultaneously.
7. A method as in claim 1, wherein one or both of said steps of forming within said bulk region said lightly doped source/drain regions utilizes gate electrodes as a portion of a mask and wherein said steps of forming within said bulk regions said source/drain regions utilize gate electrode sidewall spacers as a portion of a mask, thereby providing said source/drain regions laterally spaced apart from said gate electrode by a lightly doped source/drain region.
8. A method as in claim 3, wherein regions implanted by said blanket implant are over compensated in subsequent doping steps of opposite conductivity type.
9. A semiconductor structure comprising:
21.
a first bulk region (1103) of a first conductivity type (P);
a lightly doped source/drain region (1111) of a second conductivity type (N) opposite said first conductivity type, formed within said first bulk region;
a second bulk region (1102) of said second conductivity type;
a second conductivity type lightly doped portion (1110) of a first diode region formed within said second bulk region;
a lightly doped source/drain region (1120) of said first conductivity type formed within said second bulk region (1102);
a first conductivity type lightly doped portion (1121) of a first diode region, formed within said first bulk region (1103);
a second conductivity type portion (1114) of said first diode region, formed within said first bulk region (1103);
a source/drain region (1115) of said second conductivity type, formed within said first bulk region (1103);
a second diode region (1116) of said second conductivity type, formed within said second bulk region (1102);
a second diode region (1119) of said first conductivity type, formed within said first bulk regions (1103);
a source/drain region (1118) of said first conductivity type, formed within said second bulk regions (1102); and a first conductivity type portion (1117) of said first diode region, formed within second bulk regions (1102), wherein said first bulk regions comprise a lightly doped source/drain MOS device and a diode having said second conductivity type portion of said first diode region formed within said first bulk regions serving as a first terminal of 22.
said diode and said second diode region within said first bulk regions serves as a second terminal of said diode, and wherein said second bulk regions comprise a lightly doped source/drain MOS device and a diode having said first conductivity type portion of said first diode region within said second bulk regions serving as a first terminal of said diode and said second diode region within said second bulk regions serve as a second terminal of said diode.
21.
a first bulk region (1103) of a first conductivity type (P);
a lightly doped source/drain region (1111) of a second conductivity type (N) opposite said first conductivity type, formed within said first bulk region;
a second bulk region (1102) of said second conductivity type;
a second conductivity type lightly doped portion (1110) of a first diode region formed within said second bulk region;
a lightly doped source/drain region (1120) of said first conductivity type formed within said second bulk region (1102);
a first conductivity type lightly doped portion (1121) of a first diode region, formed within said first bulk region (1103);
a second conductivity type portion (1114) of said first diode region, formed within said first bulk region (1103);
a source/drain region (1115) of said second conductivity type, formed within said first bulk region (1103);
a second diode region (1116) of said second conductivity type, formed within said second bulk region (1102);
a second diode region (1119) of said first conductivity type, formed within said first bulk regions (1103);
a source/drain region (1118) of said first conductivity type, formed within said second bulk regions (1102); and a first conductivity type portion (1117) of said first diode region, formed within second bulk regions (1102), wherein said first bulk regions comprise a lightly doped source/drain MOS device and a diode having said second conductivity type portion of said first diode region formed within said first bulk regions serving as a first terminal of 22.
said diode and said second diode region within said first bulk regions serves as a second terminal of said diode, and wherein said second bulk regions comprise a lightly doped source/drain MOS device and a diode having said first conductivity type portion of said first diode region within said second bulk regions serving as a first terminal of said diode and said second diode region within said second bulk regions serve as a second terminal of said diode.
10. A semiconductor device comprising:
a plurality of bonding pads located along the periphery of an integrated circuit; and an area located within that region containing said bonding pads, which includes a plurality of diffused strips located within at least one bulk type region, said diffused strips forming one or more diodes serving as input protection diodes.
a plurality of bonding pads located along the periphery of an integrated circuit; and an area located within that region containing said bonding pads, which includes a plurality of diffused strips located within at least one bulk type region, said diffused strips forming one or more diodes serving as input protection diodes.
11. A method of fabricating a semiconductor structure comprising the steps of:
a) forming within a first bulk region (5103) of a first conductivity type (P), a lightly doped source/drain region (5111) of a second conductivity type (N) opposite said first conductivity type;
b) forming within one or more second bulk regions (5102) of said second conductivity type, a second conductivity type lightly doped portion (5110) of a first diode region;
c) forming within said first bulk region (5103) a source/drain region (5115) of said second conductivity type;
d) forming within said second bulk region (5102) a second diode region (5116) of said second conductivity type;
e) forming within said second bulk regions (5102) a source/drain region (5118) of said first conductivity type; and f) forming within said second bulk regions (5102) a first conductivity type portion (5117) of said first diode region, 23.
wherein said first bulk regions comprise a lightly doped source/drain MOS device, and wherein said second bulk regions comprise a MOS
device and a diode having said first conductivity type portion of said first diode region within said second bulk regions serving as a first terminal of said diode and said second diode region within said second bulk regions serve as a second terminal of said diode.
a) forming within a first bulk region (5103) of a first conductivity type (P), a lightly doped source/drain region (5111) of a second conductivity type (N) opposite said first conductivity type;
b) forming within one or more second bulk regions (5102) of said second conductivity type, a second conductivity type lightly doped portion (5110) of a first diode region;
c) forming within said first bulk region (5103) a source/drain region (5115) of said second conductivity type;
d) forming within said second bulk region (5102) a second diode region (5116) of said second conductivity type;
e) forming within said second bulk regions (5102) a source/drain region (5118) of said first conductivity type; and f) forming within said second bulk regions (5102) a first conductivity type portion (5117) of said first diode region, 23.
wherein said first bulk regions comprise a lightly doped source/drain MOS device, and wherein said second bulk regions comprise a MOS
device and a diode having said first conductivity type portion of said first diode region within said second bulk regions serving as a first terminal of said diode and said second diode region within said second bulk regions serve as a second terminal of said diode.
12. A method as in claim 11, wherein steps a and b are performed simultaneously.
13. A method as in claim 12, wherein steps a and b are performed simultaneously using a blanket implant.
14. A method as in claim 11, wherein steps c and d are performed simultaneously.
15. A method as in claim 11, wherein steps e and f are performed simultaneously.
16. A method as in claim 11, which further comprises the step of forming within said second bulk regions (5102) a lightly doped source/drain region of said first conductivity type.
17. A method as in claim 16, wherein one or both of said steps of forming within said bulk regions said lightly doped source/drain regions utilizes gate electrodes as a portion of a mask and wherein said steps of forming within said bulk regions said source/drain regions utilize gate electrode sidewall spacers as a portion of a mask, thereby providing said source/drain regions laterally spaced apart from said gate electrode by a lightly doped source/drain region.
18. A method as in claim 13, wherein regions implanted by said blanket implant are over compensated in subsequent doping steps of opposite conductivity type.
24.
24.
19. A method as in claim 11 which further comprises the step of forming within said first bulk region (5103) a first conductivity type well contact.
20. A method as in claim 19 wherein said step of forming said first conductivity well contact is performed simultaneously with said step of forming said source/drain region within said second bulk regions.
21. A semiconductor structure comprising:
a first bulk region (5103) of a first conductivity type (P);
a lightly doped source/drain region (5111) of a second conductivity type (N) opposite said first conductivity type, formed within said first bulk region;
one or more second bulk regions (5102) of said second conductivity type;
a second conductivity type lightly doped portion (5110) of a first diode region formed within said second bulk regions;
a source/drain region (5115) of said second conductivity type, formed within said first bulk region (5103);
a second diode region (5116) of said second conductivity type, formed within said second bulk regions (5102);
a source/drain region (5118) of said first conductivity type, formed within said second bulk regions (5102); and a first conductivity type portion (5117) of said first diode region, formed within second bulk regions (5102), wherein said first bulk regions comprise a lightly doped source/drain MOS device, and 25.
wherein said second bulk region comprises a MOS device and a diode having said first conductivity type portion of said first diode region within said second bulk regions serving as a first terminal of said diode and said second diode region within said second bulk regions serve as a second terminal of said diode.
26.
a first bulk region (5103) of a first conductivity type (P);
a lightly doped source/drain region (5111) of a second conductivity type (N) opposite said first conductivity type, formed within said first bulk region;
one or more second bulk regions (5102) of said second conductivity type;
a second conductivity type lightly doped portion (5110) of a first diode region formed within said second bulk regions;
a source/drain region (5115) of said second conductivity type, formed within said first bulk region (5103);
a second diode region (5116) of said second conductivity type, formed within said second bulk regions (5102);
a source/drain region (5118) of said first conductivity type, formed within said second bulk regions (5102); and a first conductivity type portion (5117) of said first diode region, formed within second bulk regions (5102), wherein said first bulk regions comprise a lightly doped source/drain MOS device, and 25.
wherein said second bulk region comprises a MOS device and a diode having said first conductivity type portion of said first diode region within said second bulk regions serving as a first terminal of said diode and said second diode region within said second bulk regions serve as a second terminal of said diode.
26.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/864,933 US5272097A (en) | 1992-04-07 | 1992-04-07 | Method for fabricating diodes for electrostatic discharge protection and voltage references |
| US864,933 | 1992-04-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2092050A1 true CA2092050A1 (en) | 1993-10-08 |
Family
ID=25344358
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002092050A Abandoned CA2092050A1 (en) | 1992-04-07 | 1993-03-19 | Method for fabricating diodes for electrostatic discharge protection and voltage references |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US5272097A (en) |
| EP (1) | EP0564897B1 (en) |
| JP (1) | JPH06125048A (en) |
| KR (1) | KR930022547A (en) |
| AT (1) | ATE195036T1 (en) |
| CA (1) | CA2092050A1 (en) |
| DE (1) | DE69329081T2 (en) |
Families Citing this family (43)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5416351A (en) * | 1991-10-30 | 1995-05-16 | Harris Corporation | Electrostatic discharge protection |
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-
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- 1992-04-07 US US07/864,933 patent/US5272097A/en not_active Expired - Lifetime
-
1993
- 1993-03-19 CA CA002092050A patent/CA2092050A1/en not_active Abandoned
- 1993-03-24 DE DE69329081T patent/DE69329081T2/en not_active Expired - Lifetime
- 1993-03-24 AT AT93104818T patent/ATE195036T1/en not_active IP Right Cessation
- 1993-03-24 EP EP93104818A patent/EP0564897B1/en not_active Expired - Lifetime
- 1993-03-31 KR KR1019930005345A patent/KR930022547A/en not_active Application Discontinuation
- 1993-04-07 JP JP5106158A patent/JPH06125048A/en active Pending
- 1993-08-20 US US08/093,074 patent/US5426322A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06125048A (en) | 1994-05-06 |
| EP0564897A1 (en) | 1993-10-13 |
| DE69329081D1 (en) | 2000-08-31 |
| KR930022547A (en) | 1993-11-24 |
| EP0564897B1 (en) | 2000-07-26 |
| ATE195036T1 (en) | 2000-08-15 |
| DE69329081T2 (en) | 2001-03-22 |
| US5426322A (en) | 1995-06-20 |
| US5272097A (en) | 1993-12-21 |
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| Date | Code | Title | Description |
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| FZDE | Discontinued |