CA2093638C - High dynamic range closed loop automatic gain control circuit - Google Patents
High dynamic range closed loop automatic gain control circuit Download PDFInfo
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- CA2093638C CA2093638C CA002093638A CA2093638A CA2093638C CA 2093638 C CA2093638 C CA 2093638C CA 002093638 A CA002093638 A CA 002093638A CA 2093638 A CA2093638 A CA 2093638A CA 2093638 C CA2093638 C CA 2093638C
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
- H03G3/20—Automatic control
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
- H03G3/3042—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers in modulators, frequency-changers, transmitters or power amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3052—Automatic control in amplifiers having semiconductor devices in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver
- H03G3/3078—Circuits generating control signals for digitally modulated signals
Abstract
A closed loop automatic gain control (AGC) circuit with high dynamic range capabilities having an amplifier circuit (18) for receiving an input signal, which is susceptible to variations in signal power, and a control signal. The amplifier circuit (18) is responsive to the control signal for amplifying the input signal at a gain level corresponding to the control signal so as to provide a corresponding output signal. A measurement circuit (20) is coupled to the amplifier means (18) for measuring logarithmic sig-nal power of the amplified input signal and providing a corresponding linear measurement signal. An integration circuit (22) is included for receiving the measurement signal, and a reference signal which corresponds to a desired signal power of the output signal. The integration circuit (22) integrates with respect to time the difference between the measurement signal and the reference signal, and generates the control signal which corresponds to the result of the integration.
Description
~~~~~J~
HIGH DYNAMIC RANGE CLOSED LOOP AUTOMATIC
GAIN CONTROL CIRCUIT
BACKGROUND OF THE INVENTION
I. Field of the Invention The present invention relates to automatic gain control circuits.
More particularly, the present invention relates to a novel and improved 1 0 closed loop automatic gain control gain control circuit with linear gain control over a very high dynamic range.
II. Description of the Related Art 1 5 Automatic gain control (AGC) circuits are widely used in receivers for controlling the gain applied to a signal to be processed. In both analog and digital signal receivers AGC circuits are implemented using different techniques. In analog receivers analog techniques are commonly used while in digital receivers, digital techniques are applied.
HIGH DYNAMIC RANGE CLOSED LOOP AUTOMATIC
GAIN CONTROL CIRCUIT
BACKGROUND OF THE INVENTION
I. Field of the Invention The present invention relates to automatic gain control circuits.
More particularly, the present invention relates to a novel and improved 1 0 closed loop automatic gain control gain control circuit with linear gain control over a very high dynamic range.
II. Description of the Related Art 1 5 Automatic gain control (AGC) circuits are widely used in receivers for controlling the gain applied to a signal to be processed. In both analog and digital signal receivers AGC circuits are implemented using different techniques. In analog receivers analog techniques are commonly used while in digital receivers, digital techniques are applied.
2 0 In analog receivers, such as used in narrowband FM cellular telephones, the power of the received signal is merely limited typically by clipping the signal. However, such an analog signal processing technique is not applicable to digital receivers since a clipping of a signal modulated with digital data would result in rnrruption of the data.
2 5 Typically in digital receivers, the level of signal power is detected, digitized and then measured. The measured value is typically compared with a set value and an error value generated, all values being in digital form. The error value is then used to control the gain of an amplifier so as to adjust the signal strength to coincide with the desired signal power.
2 5 Typically in digital receivers, the level of signal power is detected, digitized and then measured. The measured value is typically compared with a set value and an error value generated, all values being in digital form. The error value is then used to control the gain of an amplifier so as to adjust the signal strength to coincide with the desired signal power.
3 0 Digital AGC techniques however are relatively slow in controlling signal power due to saturation of the error signals involved in actually controlling the power. Digital techniques thus have the disadvantage of failing to provide accurate power control in environments where signal strength is rapidly changing, and particularly over a high dynamic range.
A I
z~~~s~s It is therefore an object of the present invention to provide a novel and improved AGC circuit for rapid, high dynamic range signal power control.
It is yet another object of the present invention to provide an AGC
circuit capable of providing gain control over both wideband and narrowband signals so as to maintain received signal power at a constant level.
It is still a further object of the present invention to provide an AGC
circuit capable of providing a control signal which can be used in 1 0 controlling transmitter power.
SUMMARY OF THE INVENTION
The present invention is a novel and improved closed loop 1 5 automatic gain control circuit which utilizes low cost analog circuitry to measure and control signal power of a received RF signal. In applications where the signal of interest is either a wideband signal, such as a CDMA
signal containing digital information, or a narrowband signal, such as an FM signal containing analog information, the circuitry of the present 2 0 invention is capable of providing the necessary gain control.
In accordance with the present invention a closed loop automatic gain control (AGC) circuit having high dynamic range capabilities is disclosed. The AGC circuit is comprised of an amplifier means for receiving an input signal which is susceptible to variations in signal 2 5 power. The amplifier means also receives a control signal and is responsive to the control signal for amplifying the input signal at a gain level in dB as a linear function of a control signal and providing a corresponding output signal. Measurement means is coupled to the amplifier means for measuring logarithmic signal power of the input 3 0 signal and providing a corresponding linear measurement signal in response to input signal power variations in dB. Integration means is included for receiving the measurement signal, and a reference signal which corresponds to a desired signal power of the output signal. The integration means integrates over time the difference between the measurement signal and i~he reference signal, and generates the control signal corresponding to the result of the integration.
In accordance with the present invention, there is provided a closed loop <~utomatic gain control (AGC) circuit comprising: a first amplifier having a signal input, a gain control input and an oui=put, said first amplifier signal input capable of receiving an :input signal; a filter having an input and an output, said filt=er input coupled to said first amplifier output; a second amplifier having a signal input, a gain control input and an output, said first amplifier signal input coupled to said filter output; a received signal strength indicator having an input coupled to said second amplifier output, and an output; an integrator having a pair of inputs and an output, one of said integrator inputs capable of receiving a reference s~_gnal and another one of said integrator inputs coupled to said received signal strength indicator output; and a compensat~_on circuit having an input coupled to said integrator output, and an output ~~oupled to said first and second amplifier gain control inputs.
In accordance with the present invention, there is also provided a closed loop automatic gain control (AGC) circuit comprising: amplifier means for receiving an ir_put signal which is susceptible to variations in signal power, receiving a control signal, amplifying said input signal at a gain level determined by said control .signal and providing a corresponding amplifier means output signal, said amplifier means comprising: compensation means for receiving said control signal and generating a corresponding compensation signal according to predetermined compensation characteristics;
input amplification means for, receiving an input signal and said compensation signal, amplifying said input signal a.t an input gain level determined by said compensation signal and providing a corresponding input amplification means output signal; filter means fo:r receiving and filtering said input amplification means output signal; and output amplification means for, receiving said filtered input amplification means output signal and said compensation signal, amplifying said filtered input amplification means output signal at an output gain level determined by said compensation signal and providing a corresponding output amplification means output signal as said amplifier means oui~put signal; measurement means coupled to said amplifier means for measuring logarithmic signal power of said amplifier means output signal and providing a corresponding linear measurement signal; and integration means for receiving said measurement signal, receiving a reference signal which corresponds to a desired signal power of said output signal, integrating with respect to time a difference between said measurements signal and said reference signal and providing said control signal.
In accordance with the present invention, there is further provided a method for providing closed loop automatic gain control over a high dynamic range comprising the steps of:
compensating a control signal according to predetermined compensation characteristics so as to provide a compensated control signal; amplifying an input signal at a gain determined by said compensated control signal, said amplification of said input signal comprising the steps of: receiving said input signal; receiving said compensated control signal; amplifying said input signal at a first gain level determined by said compensated control signal; providing a first amplified signal corresponding to said first gain level amplified input signal;
filtering said first amplified signal; amplifying said filtered first amplified signal at a second gain level determined by said compensated control- signal; providing an output signal corresponding to said second gain leverL amplified filtered first amplified signal; measuring log signal power of said 4a output signal; providing a measurement signal corresponding to measured signal power of said output signal; integrating with respect to time a difference between said measurement signal and a reference signal; and providing said control signal corresponding to a result of integrating said measurement signal and reference signal difference.
In accordance with the present invention, there is further provided a linear closed loop automatic gain control (AGC) circuit comprising: amplifier means for receiving an input signal which is susceptible to variations in signal power, receiving a control signal, amplifying said input. signal at a gain level in dB as a linear function of said control signal and providing a corresponding amplifier means output signal wherein said amp7_ifier means comprises: input amplification means for, receiving said input signal and said control signal, amplifying said input signal at an input. gain level in dB as a linear function of said control signal and providing a corresponding input amplification means output signal; filter means foz: receiving and filtering said input amplification means output signal; and output amplification means for, receiving said filtered input amplification means output signal and said control signal, amplifying said filtered input amplification means output signal at an output gain level in dB as a linear function of said control signal and providing a corresponding output amplifier means output signal;
measurement means couplE:d to said amplifier means for measuring logarithmic signal power of said amplifier means output signal and providing a corresponding linear measurement signal; and integration means for rE:ceiving said measurement signal and a reference signal, integz:ating a difference between said measurement signal and ~~aid reference signal, and providing as a result of said integration said control signal.
4b In accordance with the present invention, there is further provided a method for providing linear closed loop automatic gain control over a high dynamic range comprising the steps of: amplifying an input signal at a gain in dB as a linear function of a control signal, said step of amplifying of said input signal comprising the steps of: receiving said input signal; receiving said control signal; amplifying said input signal at a first gain level in dB as a linear function of said control signal; providing a first amplified signal corresponding to said first gain level amplified input signal;
filtering said first amplified signal; amplifying said filtered first amplified signal at a second gain level in dB as a linear function of said control signal; providing an output signal corresponding to said second gain level amplified filtered first amplified signal; measuring log signal power of said output signal; providing a linear measurement signal corresponding to measured log signal power of said output signal; integrating with respect to time a difference between said measurement signal and a reference signal; and providing as a result of integrating said control signal.
In accordance with the present invention, there is further provided an automatic gain control circuit comprising:
variable gain amplifier means for receiving an input signal and a control signal, amplif=ying said input signal in dB as a linear function of said control signal,, wherein said variable gain amplifier means comprises: first amplifier means for receiving said input sic~rlal and said control signal, amplifying said input signal at a gain in dB as a linear function of said control signal and providing a resultant first output signal;
filter means for receiving and filtering said first output signal; second amplifier means for, receiving said filtered first output signal and said control signal, amplifying said input signal at a gain i_n dB as a linear function of said 4c control signal and providing a resultant second output signal as said variable gain amplified means output signal;
measurement means coupled to said variable gain amplifier means for measuring logarithmic signal power of said variable gain amplifier means output ;signal and providing a corresponding linear measurement signal; and integrator means for receiving said measurement signal and a reference signal, integrating with respect to time a difference between said measurement signal and said reference signal, and providing said control signal.
In accordance with the present invention, there is further provided a closed loop automatic gain control (AGC) circuit comprising: a ~Tariable gain amplifier having a gain control input, a signal input, and an output, said amplifier having a linear gain control region wherein when a gain control signal within a predetermined range is applied to said gain control input, gain in dB of said amplifier a linear function of said gain control signal and providing an amplifier output signal; a power detector having an input coupled to said amplifier output and an output, said power detector providing a power detector output signal which varies linearly with power in dB of said amplifier output signal; and an integrator having a pair of inputs and an output, one of said integrator inputs coupled to said power detector output, another one of said integrator inputs for receiving a reference signal, and said integrator output coupled to said gain control input of said amplifier, wherein said integrator generates said gain control signal and when said gain control signal is within said predetermined range said gain control signal directly controls said amplifier gain.
4d BRIEF DESCRIPTION OF THE DRAWINGS
The features, objects, and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout and wherein:
Figure 1 is a block diagram illustrating in an exemplary application the elements of the closed loop automatic gain control circuit of the present invention; and Fiqures 2A and 2B illustrate in schematical form an exemplary embodiment o.f the closed loop automatic gain control circuit of Figure 1.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
In a digital i°eceiver, such as used in a code division multiple access (CDMA) mobile cellular telephone, it is necessary to limit the power of the received signal for proper signal processing of the received signal. In the cellular environment, a digital receiver may receive a signal which experiences rapid and wide variations in signal power.
In order to properly process the digital data contained within the received signal the signal power must be limited.
Accordingly, a closed loop automatic gain control circuit for a digital receiver is disclosed which is capable of limiting received signal power in such an environment.
Figure 1 illu~~trates in block diagram form an exemplary application of: the closed loop automatic gain control circuit of the present .i_nvention. In Figure 1, the closed loop automatic gain control circuit is implemented in the transceiver of a CDMA mobile cellular telephone 10. It is envisioned that telephone 10 may be exclusively CDMA
4e compatible or of a dual mode, i.e. CDMA and conventional FM
compatible. The closed loop automatic gain control circuit of the present invention is capable of providing power limiting of both wideband CDMA signals and narrowband FM signals. The compatibility of such circuitry to operate on both wideband and narrowband signals prov_Ldes cost, component and power savings for the receiver.
Telephone 10 _uncludes antenna 12 for receiving transmitted RF signals, including CDMA or FM communication signals, transmitted from a base station that are intended for reception and processing by mobile telephone 10. Antenna 12 couples the received signals to duplexer 14 which provides the received signals to the receiver portion of telephone 1G.
Duplexer 14 also receives CDMA or FM communication signals from the transmitter portion of telephone 10 for coupling to antenna 12 for transmission to a base station.
The received signals are output from duplexer 14 to downconverter 16 where t:he RF signals are converted to a lower frequency range and are provided as corresponding IF signals.
The IF signals from downconverter 16 are provided to automatic gain controlled IF amplifier 18. The :IF signals are amplified at a gain level determined by an AGC signal also provided to amplifier 18. Amplifier- 18 is capable of providing, in response to the AGC signal, linear control of gain in dB over a high dynamic range, su~~h as in excess of 80 dB. Amplifier 18 is preferably of a design described in U.S. Patent 5099204 entitled ~~LINEAR GAIN CONTROL AMPLIFIER", issued March 24, 1992, and assigned to the Assignee of the present invention.
The gain controlled IF signals are output from amplifier 18 to a second frequency downconverter, downconverter 20, where the IF signal: are converted to a lower frequency range and provided as ~~orresponding user baseband signals. In 4f the embodiment shown in Figure l, the baseband signals in the CDMA mode of operation <~.re I and Q samples of encoded digital data which are output for further demodulation and correlation.
In a dual mode receiver, downconverter 20 also frequency downconverts and demodulates the FM signals so as to provide an audio signal output.
Downconverte:r 20 also includes the capability of measuring the strength of the signal received by telephone 10 and generating a corresponding received signal strength indication (RSSI) signal. The RSSI signal along with a RSSI
reference signal are provided to integrator 22.
~~~~~1~~
The RSSI reference signal is generated by a controller (not shown) and corresponds to a desired signal strength level for the IF signals output from amplifier 18. Integrator 22 generates the AGC signal that is input to amplifier 18 for gain control.
A I
z~~~s~s It is therefore an object of the present invention to provide a novel and improved AGC circuit for rapid, high dynamic range signal power control.
It is yet another object of the present invention to provide an AGC
circuit capable of providing gain control over both wideband and narrowband signals so as to maintain received signal power at a constant level.
It is still a further object of the present invention to provide an AGC
circuit capable of providing a control signal which can be used in 1 0 controlling transmitter power.
SUMMARY OF THE INVENTION
The present invention is a novel and improved closed loop 1 5 automatic gain control circuit which utilizes low cost analog circuitry to measure and control signal power of a received RF signal. In applications where the signal of interest is either a wideband signal, such as a CDMA
signal containing digital information, or a narrowband signal, such as an FM signal containing analog information, the circuitry of the present 2 0 invention is capable of providing the necessary gain control.
In accordance with the present invention a closed loop automatic gain control (AGC) circuit having high dynamic range capabilities is disclosed. The AGC circuit is comprised of an amplifier means for receiving an input signal which is susceptible to variations in signal 2 5 power. The amplifier means also receives a control signal and is responsive to the control signal for amplifying the input signal at a gain level in dB as a linear function of a control signal and providing a corresponding output signal. Measurement means is coupled to the amplifier means for measuring logarithmic signal power of the input 3 0 signal and providing a corresponding linear measurement signal in response to input signal power variations in dB. Integration means is included for receiving the measurement signal, and a reference signal which corresponds to a desired signal power of the output signal. The integration means integrates over time the difference between the measurement signal and i~he reference signal, and generates the control signal corresponding to the result of the integration.
In accordance with the present invention, there is provided a closed loop <~utomatic gain control (AGC) circuit comprising: a first amplifier having a signal input, a gain control input and an oui=put, said first amplifier signal input capable of receiving an :input signal; a filter having an input and an output, said filt=er input coupled to said first amplifier output; a second amplifier having a signal input, a gain control input and an output, said first amplifier signal input coupled to said filter output; a received signal strength indicator having an input coupled to said second amplifier output, and an output; an integrator having a pair of inputs and an output, one of said integrator inputs capable of receiving a reference s~_gnal and another one of said integrator inputs coupled to said received signal strength indicator output; and a compensat~_on circuit having an input coupled to said integrator output, and an output ~~oupled to said first and second amplifier gain control inputs.
In accordance with the present invention, there is also provided a closed loop automatic gain control (AGC) circuit comprising: amplifier means for receiving an ir_put signal which is susceptible to variations in signal power, receiving a control signal, amplifying said input signal at a gain level determined by said control .signal and providing a corresponding amplifier means output signal, said amplifier means comprising: compensation means for receiving said control signal and generating a corresponding compensation signal according to predetermined compensation characteristics;
input amplification means for, receiving an input signal and said compensation signal, amplifying said input signal a.t an input gain level determined by said compensation signal and providing a corresponding input amplification means output signal; filter means fo:r receiving and filtering said input amplification means output signal; and output amplification means for, receiving said filtered input amplification means output signal and said compensation signal, amplifying said filtered input amplification means output signal at an output gain level determined by said compensation signal and providing a corresponding output amplification means output signal as said amplifier means oui~put signal; measurement means coupled to said amplifier means for measuring logarithmic signal power of said amplifier means output signal and providing a corresponding linear measurement signal; and integration means for receiving said measurement signal, receiving a reference signal which corresponds to a desired signal power of said output signal, integrating with respect to time a difference between said measurements signal and said reference signal and providing said control signal.
In accordance with the present invention, there is further provided a method for providing closed loop automatic gain control over a high dynamic range comprising the steps of:
compensating a control signal according to predetermined compensation characteristics so as to provide a compensated control signal; amplifying an input signal at a gain determined by said compensated control signal, said amplification of said input signal comprising the steps of: receiving said input signal; receiving said compensated control signal; amplifying said input signal at a first gain level determined by said compensated control signal; providing a first amplified signal corresponding to said first gain level amplified input signal;
filtering said first amplified signal; amplifying said filtered first amplified signal at a second gain level determined by said compensated control- signal; providing an output signal corresponding to said second gain leverL amplified filtered first amplified signal; measuring log signal power of said 4a output signal; providing a measurement signal corresponding to measured signal power of said output signal; integrating with respect to time a difference between said measurement signal and a reference signal; and providing said control signal corresponding to a result of integrating said measurement signal and reference signal difference.
In accordance with the present invention, there is further provided a linear closed loop automatic gain control (AGC) circuit comprising: amplifier means for receiving an input signal which is susceptible to variations in signal power, receiving a control signal, amplifying said input. signal at a gain level in dB as a linear function of said control signal and providing a corresponding amplifier means output signal wherein said amp7_ifier means comprises: input amplification means for, receiving said input signal and said control signal, amplifying said input signal at an input. gain level in dB as a linear function of said control signal and providing a corresponding input amplification means output signal; filter means foz: receiving and filtering said input amplification means output signal; and output amplification means for, receiving said filtered input amplification means output signal and said control signal, amplifying said filtered input amplification means output signal at an output gain level in dB as a linear function of said control signal and providing a corresponding output amplifier means output signal;
measurement means couplE:d to said amplifier means for measuring logarithmic signal power of said amplifier means output signal and providing a corresponding linear measurement signal; and integration means for rE:ceiving said measurement signal and a reference signal, integz:ating a difference between said measurement signal and ~~aid reference signal, and providing as a result of said integration said control signal.
4b In accordance with the present invention, there is further provided a method for providing linear closed loop automatic gain control over a high dynamic range comprising the steps of: amplifying an input signal at a gain in dB as a linear function of a control signal, said step of amplifying of said input signal comprising the steps of: receiving said input signal; receiving said control signal; amplifying said input signal at a first gain level in dB as a linear function of said control signal; providing a first amplified signal corresponding to said first gain level amplified input signal;
filtering said first amplified signal; amplifying said filtered first amplified signal at a second gain level in dB as a linear function of said control signal; providing an output signal corresponding to said second gain level amplified filtered first amplified signal; measuring log signal power of said output signal; providing a linear measurement signal corresponding to measured log signal power of said output signal; integrating with respect to time a difference between said measurement signal and a reference signal; and providing as a result of integrating said control signal.
In accordance with the present invention, there is further provided an automatic gain control circuit comprising:
variable gain amplifier means for receiving an input signal and a control signal, amplif=ying said input signal in dB as a linear function of said control signal,, wherein said variable gain amplifier means comprises: first amplifier means for receiving said input sic~rlal and said control signal, amplifying said input signal at a gain in dB as a linear function of said control signal and providing a resultant first output signal;
filter means for receiving and filtering said first output signal; second amplifier means for, receiving said filtered first output signal and said control signal, amplifying said input signal at a gain i_n dB as a linear function of said 4c control signal and providing a resultant second output signal as said variable gain amplified means output signal;
measurement means coupled to said variable gain amplifier means for measuring logarithmic signal power of said variable gain amplifier means output ;signal and providing a corresponding linear measurement signal; and integrator means for receiving said measurement signal and a reference signal, integrating with respect to time a difference between said measurement signal and said reference signal, and providing said control signal.
In accordance with the present invention, there is further provided a closed loop automatic gain control (AGC) circuit comprising: a ~Tariable gain amplifier having a gain control input, a signal input, and an output, said amplifier having a linear gain control region wherein when a gain control signal within a predetermined range is applied to said gain control input, gain in dB of said amplifier a linear function of said gain control signal and providing an amplifier output signal; a power detector having an input coupled to said amplifier output and an output, said power detector providing a power detector output signal which varies linearly with power in dB of said amplifier output signal; and an integrator having a pair of inputs and an output, one of said integrator inputs coupled to said power detector output, another one of said integrator inputs for receiving a reference signal, and said integrator output coupled to said gain control input of said amplifier, wherein said integrator generates said gain control signal and when said gain control signal is within said predetermined range said gain control signal directly controls said amplifier gain.
4d BRIEF DESCRIPTION OF THE DRAWINGS
The features, objects, and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout and wherein:
Figure 1 is a block diagram illustrating in an exemplary application the elements of the closed loop automatic gain control circuit of the present invention; and Fiqures 2A and 2B illustrate in schematical form an exemplary embodiment o.f the closed loop automatic gain control circuit of Figure 1.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
In a digital i°eceiver, such as used in a code division multiple access (CDMA) mobile cellular telephone, it is necessary to limit the power of the received signal for proper signal processing of the received signal. In the cellular environment, a digital receiver may receive a signal which experiences rapid and wide variations in signal power.
In order to properly process the digital data contained within the received signal the signal power must be limited.
Accordingly, a closed loop automatic gain control circuit for a digital receiver is disclosed which is capable of limiting received signal power in such an environment.
Figure 1 illu~~trates in block diagram form an exemplary application of: the closed loop automatic gain control circuit of the present .i_nvention. In Figure 1, the closed loop automatic gain control circuit is implemented in the transceiver of a CDMA mobile cellular telephone 10. It is envisioned that telephone 10 may be exclusively CDMA
4e compatible or of a dual mode, i.e. CDMA and conventional FM
compatible. The closed loop automatic gain control circuit of the present invention is capable of providing power limiting of both wideband CDMA signals and narrowband FM signals. The compatibility of such circuitry to operate on both wideband and narrowband signals prov_Ldes cost, component and power savings for the receiver.
Telephone 10 _uncludes antenna 12 for receiving transmitted RF signals, including CDMA or FM communication signals, transmitted from a base station that are intended for reception and processing by mobile telephone 10. Antenna 12 couples the received signals to duplexer 14 which provides the received signals to the receiver portion of telephone 1G.
Duplexer 14 also receives CDMA or FM communication signals from the transmitter portion of telephone 10 for coupling to antenna 12 for transmission to a base station.
The received signals are output from duplexer 14 to downconverter 16 where t:he RF signals are converted to a lower frequency range and are provided as corresponding IF signals.
The IF signals from downconverter 16 are provided to automatic gain controlled IF amplifier 18. The :IF signals are amplified at a gain level determined by an AGC signal also provided to amplifier 18. Amplifier- 18 is capable of providing, in response to the AGC signal, linear control of gain in dB over a high dynamic range, su~~h as in excess of 80 dB. Amplifier 18 is preferably of a design described in U.S. Patent 5099204 entitled ~~LINEAR GAIN CONTROL AMPLIFIER", issued March 24, 1992, and assigned to the Assignee of the present invention.
The gain controlled IF signals are output from amplifier 18 to a second frequency downconverter, downconverter 20, where the IF signal: are converted to a lower frequency range and provided as ~~orresponding user baseband signals. In 4f the embodiment shown in Figure l, the baseband signals in the CDMA mode of operation <~.re I and Q samples of encoded digital data which are output for further demodulation and correlation.
In a dual mode receiver, downconverter 20 also frequency downconverts and demodulates the FM signals so as to provide an audio signal output.
Downconverte:r 20 also includes the capability of measuring the strength of the signal received by telephone 10 and generating a corresponding received signal strength indication (RSSI) signal. The RSSI signal along with a RSSI
reference signal are provided to integrator 22.
~~~~~1~~
The RSSI reference signal is generated by a controller (not shown) and corresponds to a desired signal strength level for the IF signals output from amplifier 18. Integrator 22 generates the AGC signal that is input to amplifier 18 for gain control.
5 Downconverter 20 enables the use of an analog gain control technique for a digital signal impressed upon a carrier signal, unlike the gain control techniques typically used in digital receivers. In particular, downconverter 20 performs an analog measurement of RF power in the received signal and provides a corresponding RSSI signal. The RSSI signal 1 0 is a signal which varies linearly with respect to measured log power. This analog power measurement is used to provide control over the power in the received wideband signal so as to maintain the signal, as output for digital signal processing, at a constant power level. similarly when the received signal is a narrowband signal the power is also maintained at a 1 5 constant level.
Integrator 22 receives the RSSI signal from downconverter 20 along with the RSSI reference signal. In order to provide accurate power control, is necessary for the error between the RSSI signal (indicative of the measured power level) and the RSSI reference signal (indicative of the 2 0 desired power level) to be eliminated. Integrator 22 is used to provide this function in the AGC loop by forcing the error to zero. For example, if the gain of the signal is too high, the RSSI signal will also be high as compared to the RSSI reference signal. Until the two input signals to integrator ZZ
are identical, the integrator output signal will continue to go up resulting 2 5 in a reduction of the gain of amplifier 18.
It should be understood that the RSSI measurement can be made at various points in the processing of the received signal. Although illustrates in Figure 1 that the measurement is made in downconverter 20, and at an IF frequency, the measurement can be made in 3 0 downconverter 16 or at any other point in the signal processing at either an RF or IF frequency.
The use of analog techniques in wideband signal power control provides for a reduction in hardware required for a dual mode telephones.
As mentioned previously, in a dual mode telephone wideband and 3 5 narrowband signal power must be provided for the CDMA signal and the 1 ~ I
Integrator 22 receives the RSSI signal from downconverter 20 along with the RSSI reference signal. In order to provide accurate power control, is necessary for the error between the RSSI signal (indicative of the measured power level) and the RSSI reference signal (indicative of the 2 0 desired power level) to be eliminated. Integrator 22 is used to provide this function in the AGC loop by forcing the error to zero. For example, if the gain of the signal is too high, the RSSI signal will also be high as compared to the RSSI reference signal. Until the two input signals to integrator ZZ
are identical, the integrator output signal will continue to go up resulting 2 5 in a reduction of the gain of amplifier 18.
It should be understood that the RSSI measurement can be made at various points in the processing of the received signal. Although illustrates in Figure 1 that the measurement is made in downconverter 20, and at an IF frequency, the measurement can be made in 3 0 downconverter 16 or at any other point in the signal processing at either an RF or IF frequency.
The use of analog techniques in wideband signal power control provides for a reduction in hardware required for a dual mode telephones.
As mentioned previously, in a dual mode telephone wideband and 3 5 narrowband signal power must be provided for the CDMA signal and the 1 ~ I
FM signal. In using analog power control techniques for both the wideband and narrowband signals, the same power control circuitry can be used for both modes of operation.
Analog power control techniques provide a faster response to variations in signal power than conventional digital power control techniques. In using analog power control techniques to control a signal power of a wideband signal containing digital data, signal power can be controlled at a faster rate than using conventional digital power control techniques. The exemplary implementation of the AGC loop of the 1 0 present invention does not limit dynamic errors so as to achieve fast control of gain over a range of 100 dB.
Furthermore, in this embodiment, where a linear control and measurement circuit (linear with respect to voltage vs. dBm) is used, loop bandwidth is independent of signal power. Loop bandwidth is held 1 5 constant since the gain of each element in the loop is constant over a wide range of signal variations.
With respect to the transmitter portion of telephone 10, transmit power is also controlled. The AGC signal is again used to provide instantaneous control of transmit power. The AGC signal is provided to 2 0 the transmitter portion, along with various other control signals from the controller. In utilizing the AGC signal to also control transmit power, the transmitter gain is adjusted with respect to the receiver gain so that the transmitter gain tracks the receiver receiver gain.
In the transmission of CDMA communication signal from 2 5 telephone 10 to a base station, the transmitter portion of telephone I O
is provided with user baseband signals, typically I and Q samples of encoded digital data in the single mode telephone. In the dual mode telephone, I and Q samples, or FM signals would be provided as the user baseband signals. The I and Q samples, or FM signals, are provided as an input to 3 0 upconverter 26 where these baseband signals are converted in frequency to a higher frequency range and provided as IF signals. The IF signals are then provided to IF amplifier 28 where amplified at a level determined by the AGC signal provided through logic 24.
The amplified IF signals are provided to uprnverter 30 where they 3 5 are converted in frequency to a higher frequency range and provided as RF
PCTIUS ~ 1/08962 IPEA/US 2 ~ U UN 1992 signals. Upconverter 30 also includes an amplifier and receives signals from logic 24 for controlling the gain of the RF signals output therefrom.
The RF signals are then provided to duplexer 14 which couples the signals to antenna 12 for transmission.
It is to be noted that the application of the same AGC signal which controls the receiver gain to IF amplifier 28 provides an advantage to the telephone operation. The use of the AGC signal by the transmitter permits the transmitter gain to track receiver gain. For example, as the received signal increases in signal strength, less transmission signal power 1 0 is needed to maintain communications from the telephone to the base station. Accordingly, with the receiver ACG circuit forcing a decrease in gain for the received signal, the transmission gain is correspondingly decreased.
Turning now to Figures 2A and 2B illustrated therein is further 1 5 details of the exemplary embodiment of the closed loop automatic gain control circuit of Figure 1 as implemented in the receiver portion of telephone 10. Figures 2A and 2B in particular illustrate amplifier 18, downconverter 20 and integrator 22 as main elements of the closed loop.
In Figure 2A, integrator 22 is comprised of an operational amplifier, 2 0 op amp 100, having a feedback network to configured to such that op amp 100 functions as an integrator. In particular, op amp 100 receives the RSSI reference signal through resistor 102 at its inverting input. The RSSI
out signal (described in further detail below) is input to the noninverting input of op amp 100, while the noninverting input is also coupled to 2 5 ground through resistor 104. The output of op amp 100 is coupled to the inverting input of op amp 100 through capacitor 104. Integrator 22 produces an output voltage which is proportional to the integral, i.e. the product of the amplitude and duration, of the difference between the RSSI
reference signal and the RSSI out signal. The RSSI reference signal being 3 0 indicative of a desired signal strength while the RSSI out signal is indicative of measured signal strength. The output signal from op [QCPA3IPA.j25]
' 2~93b~8 amp 100 is an uncompensated AGC signal that is coupled as an input to IF
amplifier 18.
IF amplifier 18 is comprised of compensation circuit 1I0, amplifier circuit 130, filter 160 and amplifier circuit 170. Compensation circuit I10 receives the AGC signal and in response thereto generates a compensation signal, AGC SCALED, which compensates for nonlinearities in gain control over the dynamic range of amplifier circuits 130 and I70. The compensation signal is output from compensation circuit lI0 to both amplifier circuits 130 and 170.
1 0 Amplifier circuit 130 receives and amplifies an input IF signal at a gain level determined by the AGC SCALED signal. The amplified IF signal is then output to filter 160 where it is bandpass filtered and output to amplifier circuit I70. Amplifier circuit 170 receives the amplified and filtered IF signal where amplified at a gain level determined by the 1 5 compensation signal. The amplified IF signal is then output from amplifier circuit 170 for further processing.
Compensation circuit 110 is comprised of an operational amplifier, op amp 112, which has an inverting input coupled to receive the AGC
signal through input resistor 114. The inverting input is also coupled to 2 0 the output of op amp 112 through a nonlinear feedback circuit comprised of series coupled resistor 116 and diode 118 which are rnupled in parallel with variable resistor 120. The noninverting input of op amp I12 is provided with a reference or bias voltage across diode 122 that is provided through resistor 124 from the supply voltage -VCC.
2 5 Resistors 114, 1 I6 and I24 are typically of the same resistance, e.g., I
value, while variable resistor I20 is capable or providing a much larger resistance value, e.g. 50 KS2.
In the operation of compensation circuit 110, when the AGC
SCALED signal voltage is below the bias voltage appearing at the 3 0 noninverting input of op amp I12, the parallel resistance combination of resistor 116 and variable resistor 120, along with input resistor 114 ((R116 I ( R120) / 8114) sets a first slope gain curve for operation of op amp 112. When the AGC SCALED signal voltage is above the bias voltage, the value of variable resistor 120 along with input resistor 114 3 5 (R120 / 8114) sets a second, and different, gain curve for operation of op ".., . , 2~~~~b~u amp 112. Furthermore diodes 118 and 124 are preferably of the same type such that changes in temperature affecting diode 118, and thus the feedback, similarly affect diode 124 and the bias voltage. In the alternative, diode 124 may be replaced by a temperature sensitive element, such as a thermistor. It should be understood that the bias voltage appearing at the noninverting input of op amp 112 may be established at many different levels and by many different ways that are well known in the art.
The compensation signal generated by compensation circuit 110 is output from op amp 112 to both of amplifier circuits 130 and 170.
1 0 Amplifier circuit 130 is typically comprised of dual gate FET amplifier which has one gate (G1) coupled through resistor 134 to the output of op amp 112 and through capacitor 136 to ground. The other gate (G2) of FET 132 receives the input IF signal through variable capacitor 138, and is coupled to ground through the parallel combination of resistor 140, 1 5 variable capacitor 142 and inductor 144. The source (S) of FET 132 is also coupled to ground through the parallel combination of resistor 146 and capacitor 148. The drain (D) of FET 132 is coupled to the supply voltage +VCC through the parallel combination of resistor 150 and inductor I52 while also being coupled to ground through variable capacitor 154. The 2 0 drain (D) of FET 132 is coupled to the input of filter 160, which in the preferred embodiment is a surface acoustic wave (SAW) bandpass filter.
SAW filter 160 typically has a center frequency at 70 MHz and a bandwidth of 1.25 MHz The voltage at gate (Gl) as determined by the output of op amp 112 2 5 controls the level of gain of FET 132. The input IF signal is amplified at the determined gain level by FET 132 with the output voltage appearing across the input transducer (not shown) of SAW filter 160. The parallel combination of resistor 150 and inductor 152 are of values selected such that, in combination with the output impedance of FET I32 appearing at 3 0 the drain (D), the impedance of this circuit supplies the source impedance seen by SAW filter 160.
It may be shown that by using simple, tuned matching networks, the total insertion loss (IL) of the complete SAW filter is approximately:
2GaGs 2 5 IL = (I) (Ga + Gs)2 where: Ga is the real part of the acoustic admittance; and Gs is the real part of the source and load admittances.
1 0 Also, it may be shown that the triple transit response (TTR) of the complete filter is defined by 2 Ga Gs 2 Ga2 2 TTR = ~ (2) 1 5 (Ga + Gs)2 (Ga + Gs)2 Using the relationships set forth by equations (1) and (2), one can compute that for a triple transit response of 30 dB, relative to the main signal, an insertion loss of 12 dB can be achieved.
2 0 Amplifier circuit 170 is constructed in a manner similar to that of amplifier circuit 130. Amplifier circuit 170 is is comprised of dual gate FET
amplifier 172, preferably the same as FET 132, which has one gate (G1) coupled through resistor 174 to the output of op amp lI2 and through capacitor 176 to ground. The other gate (G2) of FET 172 is coupled to the 2 5 output of SAW filter 160 for receiving the filtered and amplified IF
signal the output therefrom, and is coupled to ground through the parallel combination of resistor I80, variable capacitor 182 and inductor 184. The source (S) of FET 172 is also coupled to ground through the parallel combination of resistor 186 and capacitor 188. The drain (D) of FET 172 is 3 0 coupled to the supply voltage +VCC through the parallel combination of resistor 190 and inductor 192 while also being coupled to ground through variable capacitor I94. The output of FET 172 is provided through variable capacitor 196 also coupled to the drain (D) of FET I72.
The voltage at gate (G1), as determined by the output of op amp 112, 3 5 again controls the level of gain of FET 172. The IF signal output from 20~~~~
SAW filter I60 is amplified at the determined gain level by FET 172 with the output voltage appearing at the output of variable capacitor 196. The parallel combination of resistor 180 and inductor 182 are of values selected such that, in combination with the input impedance of FET 172 appearing at the gate (G2), the impedance of this circuit provides the proper load for the output impedance of SAW filter 160.
The IF signal output from amplifier 170 is provided as an input to downconverter 20. In Figure 2B, portions of downconverter 20 are illustrated in further detail. The IF signal is provided as an input to a 1 0 mixer FM IF system 200 through a balanced input network comprised of capacitors 202, 204 and 206 and variable inductor 208. System 20 in the preferred embodiment is a high performance monolithic low power FM IF
system incorporating a mixer/oscillator, two limiting intermediate frequency amplifiers, quadrature detector, muting, logarithmic received 1 5 signal strength indicator (RSSI), and voltage regulator. Such a device is sold by Signetics Corporation of Sunnyvale, California under Part No. NE/SA 605.
The input IF is provided through the balanced input network to two input ports of mixer 210. A third input port receives a lower 2 0 frequency IF reference signal provided by oscillator 212 through driver 214.
Mixer 210 mixes the IF signal with the IF reference signal to provide a lower frequency IF signal which is output therefrom to filter 216.
Filter 216 is a bandpass filter, typically a crystal filter, with removes out of band frequencies from the IF signal. The filtered IF signal is output from 2 5 filter 216 to an input of IF amplifier 218.
Amplifier 218 includes a decoupling network comprised of capacitors 220 and 222 coupled thereto for proper IF decoupling.
Amplifier 218 amplifies the IF signal and provides the amplified IF signal as an output through resistor 224 to filter 226. Filter 226 is again a 3 0 bandpass filter, also typically a crystal filter, which removes out of band frequencies from the IF signal. The filtered IF signal is output from filter 226 to an input of IF amplifier 228.
The filtered IF signal output from filter 226 is also provided as an output to digital signal processing hardware (not shown) for 3 5 demodulation and correlation of I and Q samples of the encoded digital PCTIUS ~-~~.4 8 ~b 2 IPEAIUS 2 2 ..~ UN 1992 data ~ of which the IF signal is comprised when the received signals are CDMA signals. It is further envisioned that the signal output from filter may be further mixed with a lower frequency signal and filtered (by components of downconverter 20 not shown) to provide the user baseband signal for digital processing.
Amplifier 218 also provides an output of the amplified IF signal to a logarithmic received signal strength indicator, RSSI 228, which accurately measures the power of the IF signal over a 90 dB range. RSSI 228 provides an output of a linear signal, RSSI OUT, indicative of measured 1 0 logarithmic signal power. The output of RSSI 228 is coupled to the noninverting input of op amp 100 of integrator 22, while also being coupled to ground through parallel resistor 230 and capacitor 232. The RSSI OUT signal is thus provided as an output to integrator 22 where the AGC signal is generated as discussed above.
1 5 When telephone 10 is in the FM mode of operation, for dual mode telephones, the signal output from filter 226 is further processed as an FM
signal and not a digital signal. The signal output from filter 226 is also coupled to an input of IF amplifier 234.
Filters 216 and 226 need to be wide passband filters for eliminating 2 0 out of band frequencies in the CDMA mode of operation. However, additional filtering is required for the when telephone 10 is in the FM
mode of operation. Thus, additional filters (not shown) need to be added to the filtering arrangement with these filters being of a narrow passband tuned to the designated RF channel to which telephone 10 is assigned for 2 5 FM communications. It is envisioned that the additional filters would be selected from a bank of narrow passband filters in response to a filter selection signal corresponding to the FM channel of use. These additional filters may be switched into the circuit to provide additional filtering to that of filters 216 and 226, or having filters 216 and 226 switched out of the 3 0 circuit with the appropriately selected additional filters from the bank of filters providing the necessary filtering.
Amplifier 234 also includes a decoupling network comprised of capacitors 236 and 238 coupled thereto for proper IF decoupling.
Amplifier 234 amplifies the IF signal and provides the amplified IF signal [QCPA31PA.J25J
PCTNS 9i/08g62 _ _ .,.
IPEA/US ~,u~ ;~~
is 2~J~~38 as an output to quadrature detector 240. The other output of amplifier 234 is coupled to quadrature detector 240 and also AC coupled to a tuned quadrature network comprised of capacitors 242, 244, 246 and inductor 248.
The output of quadrature detector 240 is coupled across parallel coupled resistor 250 and capacitor 252 as the audio signal, UNMUTED AUDIO.
Quadrature detector 240 also provides an output to mute switch 254.
Mute switch 254 also has an input for receiving a control signal, MUTE IN, which controls whether the audio output therefrom is muted or unmuted. The output of mute switch 254 is coupled across parallel 1 0 coupled resistor 256 and capacitor 258 as the audio signal, MUTED AUDIO.
It can be seen from the Figures 2A and 2B, analog circuitry may be used to provide closed loop automatic gain control in the processing of both analog (FM) and digital (CDMA) signals. Such a circuit implementation eliminates the necessity to have both analog and digital 1 5 circuitry in a dual mode signal processing environment. Furthermore, the use of analog techniques in gain control of digital signals provides for faster gain control than over conventional techniques.
The circuit of the present invention provides for a low cost, low power implementation of an automatic gain control circuit for various 2 0 radio designs. Having accurate measurement of signal strength and linear control over gain over a relatively large bandwidth, typically in excess of 80 dB, the circuit is particularly applicable to the CDMA cellular environment where gain control is a critical element in the CDMA
telephone. The advantages of the present invention overcome many of 2 5 the deficiencies of other techniques for gain control, particularly those experienced in the cellular telephone environment.
The previous description of the preferred embodiments is provided to enable any person skilled in the art to make or use the present invention. The various modifications to these embodiments will be 3 0 readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without the use of the inventive faculty. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
3 5 WE CLAIM:
[QCPA31PA.J25]
Analog power control techniques provide a faster response to variations in signal power than conventional digital power control techniques. In using analog power control techniques to control a signal power of a wideband signal containing digital data, signal power can be controlled at a faster rate than using conventional digital power control techniques. The exemplary implementation of the AGC loop of the 1 0 present invention does not limit dynamic errors so as to achieve fast control of gain over a range of 100 dB.
Furthermore, in this embodiment, where a linear control and measurement circuit (linear with respect to voltage vs. dBm) is used, loop bandwidth is independent of signal power. Loop bandwidth is held 1 5 constant since the gain of each element in the loop is constant over a wide range of signal variations.
With respect to the transmitter portion of telephone 10, transmit power is also controlled. The AGC signal is again used to provide instantaneous control of transmit power. The AGC signal is provided to 2 0 the transmitter portion, along with various other control signals from the controller. In utilizing the AGC signal to also control transmit power, the transmitter gain is adjusted with respect to the receiver gain so that the transmitter gain tracks the receiver receiver gain.
In the transmission of CDMA communication signal from 2 5 telephone 10 to a base station, the transmitter portion of telephone I O
is provided with user baseband signals, typically I and Q samples of encoded digital data in the single mode telephone. In the dual mode telephone, I and Q samples, or FM signals would be provided as the user baseband signals. The I and Q samples, or FM signals, are provided as an input to 3 0 upconverter 26 where these baseband signals are converted in frequency to a higher frequency range and provided as IF signals. The IF signals are then provided to IF amplifier 28 where amplified at a level determined by the AGC signal provided through logic 24.
The amplified IF signals are provided to uprnverter 30 where they 3 5 are converted in frequency to a higher frequency range and provided as RF
PCTIUS ~ 1/08962 IPEA/US 2 ~ U UN 1992 signals. Upconverter 30 also includes an amplifier and receives signals from logic 24 for controlling the gain of the RF signals output therefrom.
The RF signals are then provided to duplexer 14 which couples the signals to antenna 12 for transmission.
It is to be noted that the application of the same AGC signal which controls the receiver gain to IF amplifier 28 provides an advantage to the telephone operation. The use of the AGC signal by the transmitter permits the transmitter gain to track receiver gain. For example, as the received signal increases in signal strength, less transmission signal power 1 0 is needed to maintain communications from the telephone to the base station. Accordingly, with the receiver ACG circuit forcing a decrease in gain for the received signal, the transmission gain is correspondingly decreased.
Turning now to Figures 2A and 2B illustrated therein is further 1 5 details of the exemplary embodiment of the closed loop automatic gain control circuit of Figure 1 as implemented in the receiver portion of telephone 10. Figures 2A and 2B in particular illustrate amplifier 18, downconverter 20 and integrator 22 as main elements of the closed loop.
In Figure 2A, integrator 22 is comprised of an operational amplifier, 2 0 op amp 100, having a feedback network to configured to such that op amp 100 functions as an integrator. In particular, op amp 100 receives the RSSI reference signal through resistor 102 at its inverting input. The RSSI
out signal (described in further detail below) is input to the noninverting input of op amp 100, while the noninverting input is also coupled to 2 5 ground through resistor 104. The output of op amp 100 is coupled to the inverting input of op amp 100 through capacitor 104. Integrator 22 produces an output voltage which is proportional to the integral, i.e. the product of the amplitude and duration, of the difference between the RSSI
reference signal and the RSSI out signal. The RSSI reference signal being 3 0 indicative of a desired signal strength while the RSSI out signal is indicative of measured signal strength. The output signal from op [QCPA3IPA.j25]
' 2~93b~8 amp 100 is an uncompensated AGC signal that is coupled as an input to IF
amplifier 18.
IF amplifier 18 is comprised of compensation circuit 1I0, amplifier circuit 130, filter 160 and amplifier circuit 170. Compensation circuit I10 receives the AGC signal and in response thereto generates a compensation signal, AGC SCALED, which compensates for nonlinearities in gain control over the dynamic range of amplifier circuits 130 and I70. The compensation signal is output from compensation circuit lI0 to both amplifier circuits 130 and 170.
1 0 Amplifier circuit 130 receives and amplifies an input IF signal at a gain level determined by the AGC SCALED signal. The amplified IF signal is then output to filter 160 where it is bandpass filtered and output to amplifier circuit I70. Amplifier circuit 170 receives the amplified and filtered IF signal where amplified at a gain level determined by the 1 5 compensation signal. The amplified IF signal is then output from amplifier circuit 170 for further processing.
Compensation circuit 110 is comprised of an operational amplifier, op amp 112, which has an inverting input coupled to receive the AGC
signal through input resistor 114. The inverting input is also coupled to 2 0 the output of op amp 112 through a nonlinear feedback circuit comprised of series coupled resistor 116 and diode 118 which are rnupled in parallel with variable resistor 120. The noninverting input of op amp I12 is provided with a reference or bias voltage across diode 122 that is provided through resistor 124 from the supply voltage -VCC.
2 5 Resistors 114, 1 I6 and I24 are typically of the same resistance, e.g., I
value, while variable resistor I20 is capable or providing a much larger resistance value, e.g. 50 KS2.
In the operation of compensation circuit 110, when the AGC
SCALED signal voltage is below the bias voltage appearing at the 3 0 noninverting input of op amp I12, the parallel resistance combination of resistor 116 and variable resistor 120, along with input resistor 114 ((R116 I ( R120) / 8114) sets a first slope gain curve for operation of op amp 112. When the AGC SCALED signal voltage is above the bias voltage, the value of variable resistor 120 along with input resistor 114 3 5 (R120 / 8114) sets a second, and different, gain curve for operation of op ".., . , 2~~~~b~u amp 112. Furthermore diodes 118 and 124 are preferably of the same type such that changes in temperature affecting diode 118, and thus the feedback, similarly affect diode 124 and the bias voltage. In the alternative, diode 124 may be replaced by a temperature sensitive element, such as a thermistor. It should be understood that the bias voltage appearing at the noninverting input of op amp 112 may be established at many different levels and by many different ways that are well known in the art.
The compensation signal generated by compensation circuit 110 is output from op amp 112 to both of amplifier circuits 130 and 170.
1 0 Amplifier circuit 130 is typically comprised of dual gate FET amplifier which has one gate (G1) coupled through resistor 134 to the output of op amp 112 and through capacitor 136 to ground. The other gate (G2) of FET 132 receives the input IF signal through variable capacitor 138, and is coupled to ground through the parallel combination of resistor 140, 1 5 variable capacitor 142 and inductor 144. The source (S) of FET 132 is also coupled to ground through the parallel combination of resistor 146 and capacitor 148. The drain (D) of FET 132 is coupled to the supply voltage +VCC through the parallel combination of resistor 150 and inductor I52 while also being coupled to ground through variable capacitor 154. The 2 0 drain (D) of FET 132 is coupled to the input of filter 160, which in the preferred embodiment is a surface acoustic wave (SAW) bandpass filter.
SAW filter 160 typically has a center frequency at 70 MHz and a bandwidth of 1.25 MHz The voltage at gate (Gl) as determined by the output of op amp 112 2 5 controls the level of gain of FET 132. The input IF signal is amplified at the determined gain level by FET 132 with the output voltage appearing across the input transducer (not shown) of SAW filter 160. The parallel combination of resistor 150 and inductor 152 are of values selected such that, in combination with the output impedance of FET I32 appearing at 3 0 the drain (D), the impedance of this circuit supplies the source impedance seen by SAW filter 160.
It may be shown that by using simple, tuned matching networks, the total insertion loss (IL) of the complete SAW filter is approximately:
2GaGs 2 5 IL = (I) (Ga + Gs)2 where: Ga is the real part of the acoustic admittance; and Gs is the real part of the source and load admittances.
1 0 Also, it may be shown that the triple transit response (TTR) of the complete filter is defined by 2 Ga Gs 2 Ga2 2 TTR = ~ (2) 1 5 (Ga + Gs)2 (Ga + Gs)2 Using the relationships set forth by equations (1) and (2), one can compute that for a triple transit response of 30 dB, relative to the main signal, an insertion loss of 12 dB can be achieved.
2 0 Amplifier circuit 170 is constructed in a manner similar to that of amplifier circuit 130. Amplifier circuit 170 is is comprised of dual gate FET
amplifier 172, preferably the same as FET 132, which has one gate (G1) coupled through resistor 174 to the output of op amp lI2 and through capacitor 176 to ground. The other gate (G2) of FET 172 is coupled to the 2 5 output of SAW filter 160 for receiving the filtered and amplified IF
signal the output therefrom, and is coupled to ground through the parallel combination of resistor I80, variable capacitor 182 and inductor 184. The source (S) of FET 172 is also coupled to ground through the parallel combination of resistor 186 and capacitor 188. The drain (D) of FET 172 is 3 0 coupled to the supply voltage +VCC through the parallel combination of resistor 190 and inductor 192 while also being coupled to ground through variable capacitor I94. The output of FET 172 is provided through variable capacitor 196 also coupled to the drain (D) of FET I72.
The voltage at gate (G1), as determined by the output of op amp 112, 3 5 again controls the level of gain of FET 172. The IF signal output from 20~~~~
SAW filter I60 is amplified at the determined gain level by FET 172 with the output voltage appearing at the output of variable capacitor 196. The parallel combination of resistor 180 and inductor 182 are of values selected such that, in combination with the input impedance of FET 172 appearing at the gate (G2), the impedance of this circuit provides the proper load for the output impedance of SAW filter 160.
The IF signal output from amplifier 170 is provided as an input to downconverter 20. In Figure 2B, portions of downconverter 20 are illustrated in further detail. The IF signal is provided as an input to a 1 0 mixer FM IF system 200 through a balanced input network comprised of capacitors 202, 204 and 206 and variable inductor 208. System 20 in the preferred embodiment is a high performance monolithic low power FM IF
system incorporating a mixer/oscillator, two limiting intermediate frequency amplifiers, quadrature detector, muting, logarithmic received 1 5 signal strength indicator (RSSI), and voltage regulator. Such a device is sold by Signetics Corporation of Sunnyvale, California under Part No. NE/SA 605.
The input IF is provided through the balanced input network to two input ports of mixer 210. A third input port receives a lower 2 0 frequency IF reference signal provided by oscillator 212 through driver 214.
Mixer 210 mixes the IF signal with the IF reference signal to provide a lower frequency IF signal which is output therefrom to filter 216.
Filter 216 is a bandpass filter, typically a crystal filter, with removes out of band frequencies from the IF signal. The filtered IF signal is output from 2 5 filter 216 to an input of IF amplifier 218.
Amplifier 218 includes a decoupling network comprised of capacitors 220 and 222 coupled thereto for proper IF decoupling.
Amplifier 218 amplifies the IF signal and provides the amplified IF signal as an output through resistor 224 to filter 226. Filter 226 is again a 3 0 bandpass filter, also typically a crystal filter, which removes out of band frequencies from the IF signal. The filtered IF signal is output from filter 226 to an input of IF amplifier 228.
The filtered IF signal output from filter 226 is also provided as an output to digital signal processing hardware (not shown) for 3 5 demodulation and correlation of I and Q samples of the encoded digital PCTIUS ~-~~.4 8 ~b 2 IPEAIUS 2 2 ..~ UN 1992 data ~ of which the IF signal is comprised when the received signals are CDMA signals. It is further envisioned that the signal output from filter may be further mixed with a lower frequency signal and filtered (by components of downconverter 20 not shown) to provide the user baseband signal for digital processing.
Amplifier 218 also provides an output of the amplified IF signal to a logarithmic received signal strength indicator, RSSI 228, which accurately measures the power of the IF signal over a 90 dB range. RSSI 228 provides an output of a linear signal, RSSI OUT, indicative of measured 1 0 logarithmic signal power. The output of RSSI 228 is coupled to the noninverting input of op amp 100 of integrator 22, while also being coupled to ground through parallel resistor 230 and capacitor 232. The RSSI OUT signal is thus provided as an output to integrator 22 where the AGC signal is generated as discussed above.
1 5 When telephone 10 is in the FM mode of operation, for dual mode telephones, the signal output from filter 226 is further processed as an FM
signal and not a digital signal. The signal output from filter 226 is also coupled to an input of IF amplifier 234.
Filters 216 and 226 need to be wide passband filters for eliminating 2 0 out of band frequencies in the CDMA mode of operation. However, additional filtering is required for the when telephone 10 is in the FM
mode of operation. Thus, additional filters (not shown) need to be added to the filtering arrangement with these filters being of a narrow passband tuned to the designated RF channel to which telephone 10 is assigned for 2 5 FM communications. It is envisioned that the additional filters would be selected from a bank of narrow passband filters in response to a filter selection signal corresponding to the FM channel of use. These additional filters may be switched into the circuit to provide additional filtering to that of filters 216 and 226, or having filters 216 and 226 switched out of the 3 0 circuit with the appropriately selected additional filters from the bank of filters providing the necessary filtering.
Amplifier 234 also includes a decoupling network comprised of capacitors 236 and 238 coupled thereto for proper IF decoupling.
Amplifier 234 amplifies the IF signal and provides the amplified IF signal [QCPA31PA.J25J
PCTNS 9i/08g62 _ _ .,.
IPEA/US ~,u~ ;~~
is 2~J~~38 as an output to quadrature detector 240. The other output of amplifier 234 is coupled to quadrature detector 240 and also AC coupled to a tuned quadrature network comprised of capacitors 242, 244, 246 and inductor 248.
The output of quadrature detector 240 is coupled across parallel coupled resistor 250 and capacitor 252 as the audio signal, UNMUTED AUDIO.
Quadrature detector 240 also provides an output to mute switch 254.
Mute switch 254 also has an input for receiving a control signal, MUTE IN, which controls whether the audio output therefrom is muted or unmuted. The output of mute switch 254 is coupled across parallel 1 0 coupled resistor 256 and capacitor 258 as the audio signal, MUTED AUDIO.
It can be seen from the Figures 2A and 2B, analog circuitry may be used to provide closed loop automatic gain control in the processing of both analog (FM) and digital (CDMA) signals. Such a circuit implementation eliminates the necessity to have both analog and digital 1 5 circuitry in a dual mode signal processing environment. Furthermore, the use of analog techniques in gain control of digital signals provides for faster gain control than over conventional techniques.
The circuit of the present invention provides for a low cost, low power implementation of an automatic gain control circuit for various 2 0 radio designs. Having accurate measurement of signal strength and linear control over gain over a relatively large bandwidth, typically in excess of 80 dB, the circuit is particularly applicable to the CDMA cellular environment where gain control is a critical element in the CDMA
telephone. The advantages of the present invention overcome many of 2 5 the deficiencies of other techniques for gain control, particularly those experienced in the cellular telephone environment.
The previous description of the preferred embodiments is provided to enable any person skilled in the art to make or use the present invention. The various modifications to these embodiments will be 3 0 readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without the use of the inventive faculty. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
3 5 WE CLAIM:
[QCPA31PA.J25]
Claims (37)
1. A closed loop automatic gain control (AGC) circuit comprising:
a first amplifier having a signal input, a gain control input and an output, said first amplifier signal input capable of receiving an input signal;
a filter having an input and an output, said filter input coupled to said first amplifier output;
a second amplifier having a signal input, a gain control input and an output, said first amplifier signal input coupled to said filter output;
a received signal strength indicator having an input coupled to said second amplifier output, and an output;
an integrator having a pair of inputs and an output, one of said integrator inputs capable of receiving a reference signal and another one of said integrator inputs coupled to said received signal strength indicator output; and a compensation circuit having an input coupled to said integrator output, and an output coupled to said first and second amplifier gain control inputs.
a first amplifier having a signal input, a gain control input and an output, said first amplifier signal input capable of receiving an input signal;
a filter having an input and an output, said filter input coupled to said first amplifier output;
a second amplifier having a signal input, a gain control input and an output, said first amplifier signal input coupled to said filter output;
a received signal strength indicator having an input coupled to said second amplifier output, and an output;
an integrator having a pair of inputs and an output, one of said integrator inputs capable of receiving a reference signal and another one of said integrator inputs coupled to said received signal strength indicator output; and a compensation circuit having an input coupled to said integrator output, and an output coupled to said first and second amplifier gain control inputs.
2. The circuit of claim 1 wherein said first and second amplifiers are variable gain amplifiers having a gain determined by a compensated gain control signal provided by said compensation circuit at said first and second amplifier gain control inputs.
3. The circuit of claim 1 wherein said compensation circuit comprises:
an op amp having a noninverting input capable of receiving a reference voltage, an inverting input capable of receiving an uncompensated gain control signal provided by said integrator, and an output; and a nonlinear feedback network coupled between said op amp output and said inverting input.
an op amp having a noninverting input capable of receiving a reference voltage, an inverting input capable of receiving an uncompensated gain control signal provided by said integrator, and an output; and a nonlinear feedback network coupled between said op amp output and said inverting input.
4. The circuit of claim 1 wherein said integrator comprises:
an op amp having a noninverting input capable of receiving a measurement signal provided by said received signal strength indicator, and an inverting input capable of receiving said reference signal, and an output; and a capacitive feedback network coupled between said op amp output and said inverting input.
an op amp having a noninverting input capable of receiving a measurement signal provided by said received signal strength indicator, and an inverting input capable of receiving said reference signal, and an output; and a capacitive feedback network coupled between said op amp output and said inverting input.
5. The circuit of claim 1 wherein said received signal strength indicator comprises measurement means for, receiving an input signal from said second amplifier, measuring logarithmic power of said input signal, and providing a corresponding linear uncompensated gain control signal.
6. The circuit of claim 5 wherein said received signal strength indicator further comprises:
frequency conversion means for translating the frequency of said input signal to a lower frequency;
filter means for filtering undesired frequency components from said input signal; and amplifier means for amplifying said input signal at a predetermined gain.
frequency conversion means for translating the frequency of said input signal to a lower frequency;
filter means for filtering undesired frequency components from said input signal; and amplifier means for amplifying said input signal at a predetermined gain.
7. The circuit of claim 1 wherein:
said first and second amplifiers each comprise a FET
amplifier each having a first and second gates, and a drain, each of said first and second amplifier FET amplifier first gate forming a respective first and second amplifier gain control input, each of said first and second amplifier FET
amplifier second gate each forming a respective first and second amplifier signal input, and each of said first and second amplifier FET amplifier drain forming a respective first and second amplifier output; and said filter comprises a bandpass filter.
said first and second amplifiers each comprise a FET
amplifier each having a first and second gates, and a drain, each of said first and second amplifier FET amplifier first gate forming a respective first and second amplifier gain control input, each of said first and second amplifier FET
amplifier second gate each forming a respective first and second amplifier signal input, and each of said first and second amplifier FET amplifier drain forming a respective first and second amplifier output; and said filter comprises a bandpass filter.
8. The circuit of claim 7 wherein said bandpass filter comprises a surface acoustic wave filter.
9. The circuit of claim 7 wherein said compensation circuit comprises:
a first op amp having a noninverting input capable of receiving a reference voltage, an inverting input capable of receiving an uncompensated gain control signal provided by said integrator, and an output; and a nonlinear feedback network coupled between said first op amp output and said first op amp inverting input.
a first op amp having a noninverting input capable of receiving a reference voltage, an inverting input capable of receiving an uncompensated gain control signal provided by said integrator, and an output; and a nonlinear feedback network coupled between said first op amp output and said first op amp inverting input.
10. The circuit of claim 9 wherein said integrator comprises:
a second op amp having a noninverting input capable of receiving a measurement signal provided by said received signal strength indicator, and an inverting input capable of receiving said reference signal, and an output; and a capacitive feedback network coupled between said second op amp output and said second op amp inverting input.
a second op amp having a noninverting input capable of receiving a measurement signal provided by said received signal strength indicator, and an inverting input capable of receiving said reference signal, and an output; and a capacitive feedback network coupled between said second op amp output and said second op amp inverting input.
11. The circuit of claim 1 wherein said received signal strength indicator comprises measurement means for, receiving an input signal from said second amplifier, measuring logarithmic power of said input signal, and providing a corresponding linear uncompensated gain control signal.
12. A closed loop automatic gain control (AGC) circuit comprising:
amplifier means for receiving an input signal which is susceptible to variations in signal power, receiving a control signal, amplifying said input signal at a gain level determined by said control signal and providing a corresponding amplifier means output signal, said amplifier means comprising:
compensation means for receiving said control signal and generating a corresponding compensation signal according to predetermined compensation characteristics;
input amplification means for, receiving an input signal and said compensation signal, amplifying said input signal at an input gain level determined by said compensation signal and providing a corresponding input amplification means output signal;
filter means for receiving and filtering said input amplification means output signal; and output amplification means for, receiving said filtered input amplification means output signal and said compensation signal, amplifying said filtered input amplification means output signal at an output gain level determined by said compensation signal and providing a corresponding output amplification means output signal as said amplifier means output signal;
measurement means coupled to said amplifier means for measuring logarithmic signal power of said amplifier means output signal and providing a corresponding linear measurement signal; and integration means for receiving said measurement signal, receiving a reference signal which corresponds to a desired signal power of said output signal, integrating with respect to time a difference between said measurement signal and said reference signal and providing said control signal.
amplifier means for receiving an input signal which is susceptible to variations in signal power, receiving a control signal, amplifying said input signal at a gain level determined by said control signal and providing a corresponding amplifier means output signal, said amplifier means comprising:
compensation means for receiving said control signal and generating a corresponding compensation signal according to predetermined compensation characteristics;
input amplification means for, receiving an input signal and said compensation signal, amplifying said input signal at an input gain level determined by said compensation signal and providing a corresponding input amplification means output signal;
filter means for receiving and filtering said input amplification means output signal; and output amplification means for, receiving said filtered input amplification means output signal and said compensation signal, amplifying said filtered input amplification means output signal at an output gain level determined by said compensation signal and providing a corresponding output amplification means output signal as said amplifier means output signal;
measurement means coupled to said amplifier means for measuring logarithmic signal power of said amplifier means output signal and providing a corresponding linear measurement signal; and integration means for receiving said measurement signal, receiving a reference signal which corresponds to a desired signal power of said output signal, integrating with respect to time a difference between said measurement signal and said reference signal and providing said control signal.
13. The circuit of claim 12 wherein said measurement means comprises a received signal strength indicator circuit.
14. The circuit of claim 12 wherein said integration means comprises:
an op amp having a noninverting input capable of receiving said measurement signal and an inverting input capable of receiving said reference signal, and an output; and a capacitive feedback network coupled between said op amp output and said inverting input.
an op amp having a noninverting input capable of receiving said measurement signal and an inverting input capable of receiving said reference signal, and an output; and a capacitive feedback network coupled between said op amp output and said inverting input.
15. The circuit of claim 13 wherein said integration means comprises:
an op amp having a noninverting input capable of receiving said measurement signal and an inverting input capable of receiving said reference signal and an output; and a capacitive feedback network coupled between said op amp output and said inverting input.
an op amp having a noninverting input capable of receiving said measurement signal and an inverting input capable of receiving said reference signal and an output; and a capacitive feedback network coupled between said op amp output and said inverting input.
16. The circuit of claim 12 wherein said input amplification means and said output amplification means each comprise a dual gate FET amplifier.
17. The circuit of claim 12 wherein:
said compensation means generates said compensation signal according to predetermined gain compensation characteristics;
and said input amplification means and said output amplification means gain in dB is a linear function of said control signal over a predetermined gain range.
said compensation means generates said compensation signal according to predetermined gain compensation characteristics;
and said input amplification means and said output amplification means gain in dB is a linear function of said control signal over a predetermined gain range.
18. The circuit of claim 12 wherein said input signal contains information in a predetermined one of digital and analog form.
19. A method for providing closed loop automatic gain control over a high dynamic range comprising the steps of:
compensating a control signal according to predetermined compensation characteristics so as to provide a compensated control signal;
amplifying an input signal at a gain determined by said compensated control signal, said amplification of said input signal comprising the steps of:
receiving said input signal;
receiving said compensated control signal;
amplifying said input signal at a first gain level determined by said compensated control signal;
providing a first amplified signal corresponding to said first gain level amplified input signal;
filtering said first amplified signal;
amplifying said filtered first amplified signal at a second gain level determined by said compensated control signal;
providing an output signal corresponding to said second gain level amplified filtered first amplified signal;
measuring log signal power of said output signal;
providing a measurement signal corresponding to measured signal power of said output signal;
integrating with respect to time a difference between said measurement signal and a reference signal; and providing said control signal corresponding to a result of integrating said measurement signal and reference signal difference.
compensating a control signal according to predetermined compensation characteristics so as to provide a compensated control signal;
amplifying an input signal at a gain determined by said compensated control signal, said amplification of said input signal comprising the steps of:
receiving said input signal;
receiving said compensated control signal;
amplifying said input signal at a first gain level determined by said compensated control signal;
providing a first amplified signal corresponding to said first gain level amplified input signal;
filtering said first amplified signal;
amplifying said filtered first amplified signal at a second gain level determined by said compensated control signal;
providing an output signal corresponding to said second gain level amplified filtered first amplified signal;
measuring log signal power of said output signal;
providing a measurement signal corresponding to measured signal power of said output signal;
integrating with respect to time a difference between said measurement signal and a reference signal; and providing said control signal corresponding to a result of integrating said measurement signal and reference signal difference.
20. The method of claim 11 wherein said compensation characteristics are gain characteristics.
21. The method of claim 11 wherein said measurement signal is a linear signal corresponding to said measured log signal power.
22. The method of claim 14 wherein said step of filtering comprises bandpass filtering said first amplified signal.
23. A linear closed loop automatic gain control (AGC) circuit comprising:
amplifier means for receiving an input signal which is susceptible to variations in signal power, receiving a control signal, amplifying said input signal at a gain level in dB as a linear function of said control signal and providing a corresponding amplifier means output signal wherein said amplifier means comprises:
input amplification means for, receiving said input signal and said control signal, amplifying said input signal at an input gain level in dB as a linear function of said control signal and providing a corresponding input amplification means output signal;
filter means for receiving and filtering said input amplification means output signal; and output amplification means for, receiving said filtered input amplification means output signal and said control signal, amplifying said filtered input amplification means output signal at an output gain level in dB as a linear function of said control signal and providing a corresponding output amplifier means output signal;
measurement means coupled to said amplifier means for measuring logarithmic signal power of said amplifier means output signal and providing a corresponding linear measurement signal; and integration means for receiving said measurement signal and a reference signal, integrating a difference between said measurement signal and said reference signal, and providing as a result of said integration said control signal.
amplifier means for receiving an input signal which is susceptible to variations in signal power, receiving a control signal, amplifying said input signal at a gain level in dB as a linear function of said control signal and providing a corresponding amplifier means output signal wherein said amplifier means comprises:
input amplification means for, receiving said input signal and said control signal, amplifying said input signal at an input gain level in dB as a linear function of said control signal and providing a corresponding input amplification means output signal;
filter means for receiving and filtering said input amplification means output signal; and output amplification means for, receiving said filtered input amplification means output signal and said control signal, amplifying said filtered input amplification means output signal at an output gain level in dB as a linear function of said control signal and providing a corresponding output amplifier means output signal;
measurement means coupled to said amplifier means for measuring logarithmic signal power of said amplifier means output signal and providing a corresponding linear measurement signal; and integration means for receiving said measurement signal and a reference signal, integrating a difference between said measurement signal and said reference signal, and providing as a result of said integration said control signal.
24. The circuit of claim 23 wherein said measurement means comprises a received signal strength indicator circuit having an input coupled to said amplifier means and an output coupled to said integration means.
25. The circuit of claim 23 wherein said integration means comprises:
an op amp having a noninverting input coupled to said measurement means and an inverting input for receiving said reference signal, and an output; and a capacitive feedback network coupled between said op amp output and inverting input.
an op amp having a noninverting input coupled to said measurement means and an inverting input for receiving said reference signal, and an output; and a capacitive feedback network coupled between said op amp output and inverting input.
26. A method for providing linear closed loop automatic gain control over a high dynamic range comprising the steps of:
amplifying an input signal at a gain in dB as a linear function of a control signal, said step of amplifying of said input signal comprising the steps of:
receiving said input signal;
receiving said control signal;
amplifying said input signal at a first gain level in dB
as a linear function of said control signal;
providing a first amplified signal corresponding to said first gain level amplified input signal;
filtering said first amplified signal;
amplifying said filtered first amplified signal at a second gain level in dB as a linear function of said control signal;
providing an output signal corresponding to said second gain level amplified filtered first amplified signal;
measuring log signal power of said output signal;
providing a linear measurement signal corresponding to measured log signal power of said output signal;
integrating with respect to time a difference between said measurement signal and a reference signal; and providing as a result of integrating said control signal.
amplifying an input signal at a gain in dB as a linear function of a control signal, said step of amplifying of said input signal comprising the steps of:
receiving said input signal;
receiving said control signal;
amplifying said input signal at a first gain level in dB
as a linear function of said control signal;
providing a first amplified signal corresponding to said first gain level amplified input signal;
filtering said first amplified signal;
amplifying said filtered first amplified signal at a second gain level in dB as a linear function of said control signal;
providing an output signal corresponding to said second gain level amplified filtered first amplified signal;
measuring log signal power of said output signal;
providing a linear measurement signal corresponding to measured log signal power of said output signal;
integrating with respect to time a difference between said measurement signal and a reference signal; and providing as a result of integrating said control signal.
27. The method of claim 26 wherein said step of filtering comprises a bandpass filtering said first amplified signal.
28. The circuit of claim 1 wherein said reference signal corresponds to a desired signal power of said amplifier means output signal.
29. An automatic gain control circuit comprising:
variable gain amplifier means for receiving an input signal and a control signal, amplifying said input signal in dB
as a linear function of said control signal, wherein said variable gain amplifier means comprises:
first amplifier means for receiving said input signal and said control signal, amplifying said input signal at a gain in dB as a linear function of said control signal and providing a resultant first output signal;
filter means for receiving and filtering said first output signal;
second amplifier means for, receiving said filtered first output signal and said control signal, amplifying said input signal at a gain in dB as a linear function of said control signal and providing a resultant second output signal as said variable gain amplified means output signal;
measurement means coupled to said variable gain amplifier means for measuring logarithmic signal power of said variable gain amplifier means output signal and providing a corresponding linear measurement signal; and integrator means for receiving said measurement signal and a reference signal, integrating with respect to time a difference between said measurement signal and said reference signal, and providing said control signal.
variable gain amplifier means for receiving an input signal and a control signal, amplifying said input signal in dB
as a linear function of said control signal, wherein said variable gain amplifier means comprises:
first amplifier means for receiving said input signal and said control signal, amplifying said input signal at a gain in dB as a linear function of said control signal and providing a resultant first output signal;
filter means for receiving and filtering said first output signal;
second amplifier means for, receiving said filtered first output signal and said control signal, amplifying said input signal at a gain in dB as a linear function of said control signal and providing a resultant second output signal as said variable gain amplified means output signal;
measurement means coupled to said variable gain amplifier means for measuring logarithmic signal power of said variable gain amplifier means output signal and providing a corresponding linear measurement signal; and integrator means for receiving said measurement signal and a reference signal, integrating with respect to time a difference between said measurement signal and said reference signal, and providing said control signal.
30. The circuit of claim 29 wherein said measurement means comprises a received signal strength indictor circuit having an input coupled to said second amplifier means and an output coupled to said integrator means.
31. The circuit of claim 30 wherein said integration means comprises:
an op amp having a noninverting input coupled to said received signal strength indicator circuit output and an inverting input for receiving said reference signal, and an output; and a capacitive feedback network coupled between said op amp output and inverting input.
an op amp having a noninverting input coupled to said received signal strength indicator circuit output and an inverting input for receiving said reference signal, and an output; and a capacitive feedback network coupled between said op amp output and inverting input.
32. A closed loop automatic gain control (AGC) circuit comprising:
a variable gain amplifier having a gain control input, a signal input, and an output, said amplifier having a linear gain control region wherein when a gain control signal within a predetermined range is applied to said gain control input, gain in dB of said amplifier a linear function of said gain control signal and providing an amplifier output signal;
a power detector having an input coupled to said amplifier output and an output, said power detector providing a power detector output signal which varies linearly with power in dB
of said amplifier output signal; and an integrator having a pair of inputs and an output, one of said integrator inputs coupled to said power detector output, another one of said integrator inputs for receiving a reference signal, and said integrator output coupled to said gain control input of said amplifier, wherein said integrator generates said gain control signal and when said gain control signal is within said predetermined range said gain control signal directly controls said amplifier gain.
a variable gain amplifier having a gain control input, a signal input, and an output, said amplifier having a linear gain control region wherein when a gain control signal within a predetermined range is applied to said gain control input, gain in dB of said amplifier a linear function of said gain control signal and providing an amplifier output signal;
a power detector having an input coupled to said amplifier output and an output, said power detector providing a power detector output signal which varies linearly with power in dB
of said amplifier output signal; and an integrator having a pair of inputs and an output, one of said integrator inputs coupled to said power detector output, another one of said integrator inputs for receiving a reference signal, and said integrator output coupled to said gain control input of said amplifier, wherein said integrator generates said gain control signal and when said gain control signal is within said predetermined range said gain control signal directly controls said amplifier gain.
33. The AGC circuit of claim 32 further comprising:
an additional variable gain amplifier disposed between said amplifier and said power detector, said additional amplifier having a signal input coupled to said amplifier output, a gain control input coupled to said integrator output and an output coupled to said power detector input, said additional amplifier also having a linear gain control region wherein when a gain control signal within a predetermined range is applied to said additional amplifier gain control input gain in dB of said additional amplifier is a linear function of said control signal and providing an additional amplifier output signal.
an additional variable gain amplifier disposed between said amplifier and said power detector, said additional amplifier having a signal input coupled to said amplifier output, a gain control input coupled to said integrator output and an output coupled to said power detector input, said additional amplifier also having a linear gain control region wherein when a gain control signal within a predetermined range is applied to said additional amplifier gain control input gain in dB of said additional amplifier is a linear function of said control signal and providing an additional amplifier output signal.
34. The AGC circuit of claim 33 further comprising:
a filter disposed between said amplifier and said additional amplifier, said filter having an input coupled to said amplifier output and an output coupled to said additional amplifier input.
a filter disposed between said amplifier and said additional amplifier, said filter having an input coupled to said amplifier output and an output coupled to said additional amplifier input.
35. The AGC circuit of claim 32 wherein said integrator comprises:
an op amp having a noninverting input coupled to said power detector output, and an inverting input for receiving said reference signal, and an output coupled to said amplifier gain control input; and a capacitive feedback network coupled between said op amp output and said inverting input.
an op amp having a noninverting input coupled to said power detector output, and an inverting input for receiving said reference signal, and an output coupled to said amplifier gain control input; and a capacitive feedback network coupled between said op amp output and said inverting input.
36. The AGC circuit of claim 33 wherein said integrator comprises:
an op amp having a noninverting input coupled to said power detector output, and an inverting input for receiving said reference signal, and an output coupled to said amplifier gain control input and said addiitonal amplifier gain control input; and a capacitive feedback network coupled between said op amp output and said inverting input.
an op amp having a noninverting input coupled to said power detector output, and an inverting input for receiving said reference signal, and an output coupled to said amplifier gain control input and said addiitonal amplifier gain control input; and a capacitive feedback network coupled between said op amp output and said inverting input.
37. The AGC circuit of claim 34 wherein said integrator comprises:
an op amp having a noninverting input coupled to said power detector output, and an inverting input for receiving said reference signal, and an output coupled to said amplifier gain control input and said additional gain control input; and a capacitive feedback network coupled between said op amp output and said inverting input.
an op amp having a noninverting input coupled to said power detector output, and an inverting input for receiving said reference signal, and an output coupled to said amplifier gain control input and said additional gain control input; and a capacitive feedback network coupled between said op amp output and said inverting input.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US620,092 | 1990-11-30 | ||
| US07/620,092 US5107225A (en) | 1990-11-30 | 1990-11-30 | High dynamic range closed loop automatic gain control circuit |
| PCT/US1991/008962 WO1992010028A1 (en) | 1990-11-30 | 1991-11-27 | High dynamic range closed loop automatic gain control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2093638A1 CA2093638A1 (en) | 1992-05-31 |
| CA2093638C true CA2093638C (en) | 2002-01-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002093638A Expired - Lifetime CA2093638C (en) | 1990-11-30 | 1991-11-27 | High dynamic range closed loop automatic gain control circuit |
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| EP (1) | EP0559840B1 (en) |
| JP (1) | JP3280022B2 (en) |
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Families Citing this family (100)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5283536A (en) * | 1990-11-30 | 1994-02-01 | Qualcomm Incorporated | High dynamic range closed loop automatic gain control circuit |
| US5796772A (en) * | 1991-05-13 | 1998-08-18 | Omnipoint Corporation | Multi-band, multi-mode spread-spectrum communication system |
| US5790587A (en) * | 1991-05-13 | 1998-08-04 | Omnipoint Corporation | Multi-band, multi-mode spread-spectrum communication system |
| US5815525A (en) | 1991-05-13 | 1998-09-29 | Omnipoint Corporation | Multi-band, multi-mode spread-spectrum communication system |
| US5887020A (en) * | 1991-05-13 | 1999-03-23 | Omnipoint Corporation | Multi-band, multi-mode spread-spectrum communication system |
| US5694414A (en) * | 1991-05-13 | 1997-12-02 | Omnipoint Corporation | Multi-band, multi-mode spread-spectrum communication system |
| JPH05160653A (en) * | 1991-12-09 | 1993-06-25 | Yamaha Corp | Automatic gain controller |
| BR9302276A (en) * | 1992-06-10 | 1994-01-11 | Motorola Inc | TRANSMITTER AND PROCESS TO TRANSMIT SIGNALS OF VARIABLE DEVIATION LEVELS |
| FI93159C (en) * | 1992-09-23 | 1995-02-27 | Nokia Mobile Phones Ltd | A method for controlling a radio frequency amplifier of a radiotelephone and a control system according to the method |
| US5329547A (en) * | 1993-03-11 | 1994-07-12 | Motorola, Inc. | Method and apparatus for coherent communication in a spread-spectrum communication system |
| US5410741A (en) * | 1993-03-23 | 1995-04-25 | Motorola Inc. | Automatic gain control of transponded supervisory audio tone |
| AU681642B2 (en) * | 1993-03-26 | 1997-09-04 | Alps Electric Co., Ltd. | Power amplifier bias control circuit and method |
| JP2948054B2 (en) * | 1993-05-21 | 1999-09-13 | アルプス電気株式会社 | Transceiver |
| US5339046A (en) * | 1993-06-03 | 1994-08-16 | Alps Electric Co., Ltd. | Temperature compensated variable gain amplifier |
| US5408697A (en) * | 1993-06-14 | 1995-04-18 | Qualcomm Incorporated | Temperature-compensated gain-controlled amplifier having a wide linear dynamic range |
| US5603113A (en) * | 1993-06-16 | 1997-02-11 | Oki Telecom | Automatic gain control circuit for both receiver and transmitter adjustable amplifiers including a linear signal level detector with DC blocking, DC adding, and AC removing components |
| US5412686A (en) * | 1993-09-17 | 1995-05-02 | Motorola Inc. | Method and apparatus for power estimation in a communication system |
| US5465398A (en) * | 1993-10-07 | 1995-11-07 | Metricom, Inc. | Automatic power level control of a packet communication link |
| US6094575A (en) * | 1993-11-01 | 2000-07-25 | Omnipoint Corporation | Communication system and method |
| US6005856A (en) * | 1993-11-01 | 1999-12-21 | Omnipoint Corporation | Communication protocol for spread spectrum wireless communication system |
| US6088590A (en) * | 1993-11-01 | 2000-07-11 | Omnipoint Corporation | Method and system for mobile controlled handoff and link maintenance in spread spectrum communication |
| ZA95605B (en) * | 1994-04-28 | 1995-12-20 | Qualcomm Inc | Method and apparatus for automatic gain control and dc offset cancellation in quadrature receiver |
| US5469115A (en) * | 1994-04-28 | 1995-11-21 | Qualcomm Incorporated | Method and apparatus for automatic gain control in a digital receiver |
| US5530716A (en) * | 1994-06-30 | 1996-06-25 | Motorola, Inc. | Method and apparatus for identifying a coded communication signal |
| JP2885267B2 (en) * | 1994-07-15 | 1999-04-19 | 日本電気株式会社 | Digitally modulated signal receiver |
| US5953370A (en) | 1994-09-09 | 1999-09-14 | Omnipoint Corporation | Apparatus for receiving and correlating a spread spectrum signal |
| US5629956A (en) * | 1994-09-09 | 1997-05-13 | Omnipoint Corporation | Method and apparatus for reception and noncoherent serial correlation of a continuous phase modulated signal |
| US5757847A (en) | 1994-09-09 | 1998-05-26 | Omnipoint Corporation | Method and apparatus for decoding a phase encoded signal |
| US5963586A (en) | 1994-09-09 | 1999-10-05 | Omnipoint Corporation | Method and apparatus for parallel noncoherent correlation of a spread spectrum signal |
| US5627856A (en) * | 1994-09-09 | 1997-05-06 | Omnipoint Corporation | Method and apparatus for receiving and despreading a continuous phase-modulated spread spectrum signal using self-synchronizing correlators |
| US5754585A (en) | 1994-09-09 | 1998-05-19 | Omnipoint Corporation | Method and apparatus for serial noncoherent correlation of a spread spectrum signal |
| US5832028A (en) * | 1994-09-09 | 1998-11-03 | Omnipoint Corporation | Method and apparatus for coherent serial correlation of a spread spectrum signal |
| US5692007A (en) | 1994-09-09 | 1997-11-25 | Omnipoint Corporation | Method and apparatus for differential phase encoding and decoding in spread-spectrum communication systems with continuous-phase modulation |
| US5659574A (en) | 1994-09-09 | 1997-08-19 | Omnipoint Corporation | Multi-bit correlation of continuous phase modulated signals |
| US5881100A (en) | 1994-09-09 | 1999-03-09 | Omnipoint Corporation | Method and apparatus for coherent correlation of a spread spectrum signal |
| US5648982A (en) * | 1994-09-09 | 1997-07-15 | Omnipoint Corporation | Spread spectrum transmitter |
| US5548616A (en) * | 1994-09-09 | 1996-08-20 | Nokia Mobile Phones Ltd. | Spread spectrum radiotelephone having adaptive transmitter gain control |
| US5856998A (en) * | 1994-09-09 | 1999-01-05 | Omnipoint Corporation | Method and apparatus for correlating a continuous phase modulated spread spectrum signal |
| US5680414A (en) | 1994-09-09 | 1997-10-21 | Omnipoint Corporation | Synchronization apparatus and method for spread spectrum receiver |
| US5610940A (en) * | 1994-09-09 | 1997-03-11 | Omnipoint Corporation | Method and apparatus for noncoherent reception and correlation of a continous phase modulated signal |
| US5754584A (en) | 1994-09-09 | 1998-05-19 | Omnipoint Corporation | Non-coherent spread-spectrum continuous-phase modulation communication system |
| US5566201A (en) * | 1994-09-27 | 1996-10-15 | Nokia Mobile Phones Ltd. | Digital AGC for a CDMA radiotelephone |
| TW294867B (en) * | 1994-12-23 | 1997-01-01 | Qualcomm Inc | |
| US5689815A (en) * | 1995-05-04 | 1997-11-18 | Oki Telecom, Inc. | Saturation prevention system for radio telephone with open and closed loop power control systems |
| US5832022A (en) * | 1995-06-02 | 1998-11-03 | Omnipoint Corporation | Method and apparatus for controlling the modulation index of continuous phase modulated (CPM) signals |
| US5745484A (en) * | 1995-06-05 | 1998-04-28 | Omnipoint Corporation | Efficient communication system using time division multiplexing and timing adjustment control |
| US5689502A (en) * | 1995-06-05 | 1997-11-18 | Omnipoint Corporation | Efficient frequency division duplex communication system with interleaved format and timing adjustment control |
| US5802046A (en) * | 1995-06-05 | 1998-09-01 | Omnipoint Corporation | Efficient time division duplex communication system with interleaved format and timing adjustment control |
| US5959980A (en) | 1995-06-05 | 1999-09-28 | Omnipoint Corporation | Timing adjustment control for efficient time division duplex communication |
| US6940840B2 (en) * | 1995-06-30 | 2005-09-06 | Interdigital Technology Corporation | Apparatus for adaptive reverse power control for spread-spectrum communications |
| ZA965340B (en) | 1995-06-30 | 1997-01-27 | Interdigital Tech Corp | Code division multiple access (cdma) communication system |
| US7072380B2 (en) * | 1995-06-30 | 2006-07-04 | Interdigital Technology Corporation | Apparatus for initial power control for spread-spectrum communications |
| US7929498B2 (en) | 1995-06-30 | 2011-04-19 | Interdigital Technology Corporation | Adaptive forward power control and adaptive reverse power control for spread-spectrum communications |
| US7123600B2 (en) | 1995-06-30 | 2006-10-17 | Interdigital Technology Corporation | Initial power control for spread-spectrum communications |
| US6885652B1 (en) | 1995-06-30 | 2005-04-26 | Interdigital Technology Corporation | Code division multiple access (CDMA) communication system |
| US6049535A (en) | 1996-06-27 | 2000-04-11 | Interdigital Technology Corporation | Code division multiple access (CDMA) communication system |
| US7020111B2 (en) | 1996-06-27 | 2006-03-28 | Interdigital Technology Corporation | System for using rapid acquisition spreading codes for spread-spectrum communications |
| US5715526A (en) * | 1995-09-08 | 1998-02-03 | Qualcomm Incorporated | Apparatus and method for controlling transmission power in a cellular communications system |
| US5627857A (en) * | 1995-09-15 | 1997-05-06 | Qualcomm Incorporated | Linearized digital automatic gain control |
| US5982824A (en) * | 1995-12-18 | 1999-11-09 | Lucent Technologies, Inc. | Method and apparatus for automatic gain control |
| US5974041A (en) * | 1995-12-27 | 1999-10-26 | Qualcomm Incorporated | Efficient parallel-stage power amplifier |
| US5872481A (en) * | 1995-12-27 | 1999-02-16 | Qualcomm Incorporated | Efficient parallel-stage power amplifier |
| JPH09270723A (en) * | 1996-03-29 | 1997-10-14 | Alps Electric Co Ltd | Ic for reception circuit for portable telephone set |
| US5809400A (en) * | 1996-06-21 | 1998-09-15 | Lucent Technologies Inc. | Intermodulation performance enhancement by dynamically controlling RF amplifier current |
| JPH1065568A (en) * | 1996-08-21 | 1998-03-06 | Oki Electric Ind Co Ltd | Radio equipment |
| KR100193843B1 (en) * | 1996-09-13 | 1999-06-15 | 윤종용 | Digital automatic gain control method and apparatus of mobile communication system transceiver |
| JP3475037B2 (en) * | 1997-03-14 | 2003-12-08 | 株式会社東芝 | transceiver |
| US6236863B1 (en) | 1997-03-31 | 2001-05-22 | Oki Telecom, Inc. | Comprehensive transmitter power control system for radio telephones |
| US6069525A (en) * | 1997-04-17 | 2000-05-30 | Qualcomm Incorporated | Dual-mode amplifier with high efficiency and high linearity |
| US6185431B1 (en) | 1997-06-18 | 2001-02-06 | Oki Telecom, Inc. | Mobile station closed loop output power stability system for weak signal conditions |
| JPH1155131A (en) * | 1997-08-06 | 1999-02-26 | Nec Corp | Radio transmission power controller |
| US6259682B1 (en) * | 1997-11-25 | 2001-07-10 | Uniden America Corporation | Closed loop transmitter with improved stability and accuracy over a wide range of power levels having means for maintaining constant loop gain |
| US6160803A (en) * | 1998-01-12 | 2000-12-12 | Golden Bridge Technology, Inc. | High processing gain spread spectrum TDMA system and method |
| US6008698A (en) * | 1998-05-18 | 1999-12-28 | Omnipoint Corporation | Amplifier with dynamically adaptable supply current |
| US6137354A (en) * | 1998-05-18 | 2000-10-24 | Omnipoint Corporation | Bypassable amplifier |
| US6081161A (en) * | 1998-05-18 | 2000-06-27 | Omnipoint Corporation | Amplifier with dynamatically adaptable supply voltage |
| US6259901B1 (en) | 1998-07-03 | 2001-07-10 | Mobile Communications Tokyo Inc. | Radio-frequency power amplifier of mobile communication equipment |
| US6069526A (en) * | 1998-08-04 | 2000-05-30 | Qualcomm Incorporated | Partial or complete amplifier bypass |
| US6484017B1 (en) | 1998-09-07 | 2002-11-19 | Lg Information & Communications, Ltd. | Up converter of base station transmitter in wireless communication system and method of controlling outputs thereof |
| US6208873B1 (en) * | 1998-11-23 | 2001-03-27 | Qualcomm Incorporated | Method and apparatus for transmitting reverse link power control signals based on the probability that the power control command is in error |
| US6947469B2 (en) | 1999-05-07 | 2005-09-20 | Intel Corporation | Method and Apparatus for wireless spread spectrum communication with preamble processing period |
| US6121831A (en) * | 1999-05-12 | 2000-09-19 | Level One Communications, Inc. | Apparatus and method for removing offset in a gain circuit |
| JP3592980B2 (en) * | 1999-06-29 | 2004-11-24 | 株式会社東芝 | Transmission circuit and wireless transmission device |
| WO2001022575A1 (en) * | 1999-09-23 | 2001-03-29 | Wey Chia Sam | Method and apparatus for providing a constant loop bandwidth of a power control loop system at different power levels |
| US6553212B1 (en) * | 1999-11-01 | 2003-04-22 | Nokia Networks Oy | Method and apparatus for improving loop stability and speed of a power control loop |
| US7400870B2 (en) * | 2001-10-30 | 2008-07-15 | Texas Instruments Incorporated | Hardware loop for automatic gain control |
| JP3796204B2 (en) * | 2002-07-31 | 2006-07-12 | 松下電器産業株式会社 | Multi-carrier transmission signal peak suppression method and multi-carrier transmission signal generation circuit having peak suppression function |
| US7129753B2 (en) * | 2004-05-26 | 2006-10-31 | Infineon Technologies Ag | Chip to chip interface |
| TWM278180U (en) * | 2004-09-14 | 2005-10-11 | Inventec Appliances Corp | Circuit structure of mobile phone capable of dynamically controlling power |
| DE602005013687D1 (en) * | 2004-10-18 | 2009-05-14 | Nxp Bv | SIGNAL RECEIVER AND MOBILE COMMUNICATION DEVICE |
| US8920343B2 (en) | 2006-03-23 | 2014-12-30 | Michael Edward Sabatino | Apparatus for acquiring and processing of physiological auditory signals |
| US8126094B2 (en) | 2009-01-07 | 2012-02-28 | Skyworks Solutions, Inc. | Circuits, systems, and methods for managing automatic gain control in quadrature signal paths of a receiver |
| US8536950B2 (en) * | 2009-08-03 | 2013-09-17 | Qualcomm Incorporated | Multi-stage impedance matching |
| US8102205B2 (en) | 2009-08-04 | 2012-01-24 | Qualcomm, Incorporated | Amplifier module with multiple operating modes |
| CN103067035B (en) * | 2011-10-24 | 2015-11-18 | 联发科技股份有限公司 | Slice transmitter front-end circuit and correlation technique |
| US9065691B2 (en) | 2011-10-24 | 2015-06-23 | Mediatek Inc. | Sliced transmitter front-end |
| CN103580634A (en) * | 2013-10-29 | 2014-02-12 | 中国电子科技集团公司第四十一研究所 | Automatic gain controller in audio signal analysis |
| CN104320097B (en) * | 2014-09-10 | 2017-06-20 | 浙江迪元仪表有限公司 | The ultrasonic signal auto gain control method of fast and stable |
| RU2614345C1 (en) * | 2015-12-21 | 2017-03-24 | Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Поволжский государственный технологический университет" | Method of exapanding dynamic range in radio systems |
| FR3088157A1 (en) | 2018-11-06 | 2020-05-08 | Parrot Faurecia Automotive Sas | ELECTRONIC DEVICE AND METHOD FOR RECEIVING A RADIOELECTRIC SIGNAL, INTEGRATED CIRCUIT IMPLEMENTING SUCH A DEVICE |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3325738A (en) * | 1964-02-17 | 1967-06-13 | Avco Corp | Signal to noise ratio controlled squelch circuit |
| US4263560A (en) * | 1974-06-06 | 1981-04-21 | The United States Of America As Represented By The Secretary Of The Navy | Log-exponential AGC circuit |
| US4560949A (en) * | 1982-09-27 | 1985-12-24 | Rockwell International Corporation | High speed AGC circuit |
| US4602218A (en) * | 1985-04-30 | 1986-07-22 | Motorola, Inc. | Automatic output control circuitry for RF power amplifiers with wide dynamic range |
-
1990
- 1990-11-30 US US07/620,092 patent/US5107225A/en not_active Expired - Lifetime
-
1991
- 1991-11-27 AU AU12416/92A patent/AU652807B2/en not_active Expired
- 1991-11-27 EP EP92904567A patent/EP0559840B1/en not_active Expired - Lifetime
- 1991-11-27 DE DE69131074T patent/DE69131074T2/en not_active Expired - Lifetime
- 1991-11-27 ES ES92904567T patent/ES2129445T3/en not_active Expired - Lifetime
- 1991-11-27 BR BR919107139A patent/BR9107139A/en not_active IP Right Cessation
- 1991-11-27 AT AT92904567T patent/ATE178437T1/en not_active IP Right Cessation
- 1991-11-27 WO PCT/US1991/008962 patent/WO1992010028A1/en active IP Right Grant
- 1991-11-27 DK DK92904567T patent/DK0559840T3/en active
- 1991-11-27 CA CA002093638A patent/CA2093638C/en not_active Expired - Lifetime
- 1991-11-27 RO RO93-00674A patent/RO113696B1/en unknown
- 1991-11-27 JP JP50428192A patent/JP3280022B2/en not_active Expired - Fee Related
- 1991-11-27 HU HU9301576A patent/HU214918B/en unknown
- 1991-11-29 MX MX9102309A patent/MX9102309A/en unknown
- 1991-12-04 TW TW080109524A patent/TW216471B/zh not_active IP Right Cessation
-
1993
- 1993-05-17 FI FI932238A patent/FI114762B/en not_active IP Right Cessation
- 1993-05-27 BG BG97790A patent/BG61293B1/en unknown
- 1993-05-28 NO NO931949A patent/NO306840B1/en not_active IP Right Cessation
- 1993-05-31 KR KR1019930701621A patent/KR100190976B1/en not_active IP Right Cessation
-
1998
- 1998-12-28 HK HK98116161A patent/HK1014809A1/en not_active IP Right Cessation
-
1999
- 1999-04-30 GR GR990401187T patent/GR3030105T3/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| EP0559840B1 (en) | 1999-03-31 |
| HK1014809A1 (en) | 1999-09-30 |
| HUT66966A (en) | 1995-01-30 |
| ES2129445T3 (en) | 1999-06-16 |
| CA2093638A1 (en) | 1992-05-31 |
| EP0559840A4 (en) | 1994-11-23 |
| DK0559840T3 (en) | 1999-10-11 |
| ATE178437T1 (en) | 1999-04-15 |
| WO1992010028A1 (en) | 1992-06-11 |
| MX9102309A (en) | 1992-07-08 |
| NO931949L (en) | 1993-06-17 |
| BG61293B1 (en) | 1997-04-30 |
| DE69131074D1 (en) | 1999-05-06 |
| NO306840B1 (en) | 1999-12-27 |
| EP0559840A1 (en) | 1993-09-15 |
| HU9301576D0 (en) | 1993-11-29 |
| FI114762B (en) | 2004-12-15 |
| NO931949D0 (en) | 1993-05-28 |
| AU1241692A (en) | 1992-06-25 |
| DE69131074T2 (en) | 1999-11-11 |
| US5107225A (en) | 1992-04-21 |
| RO113696B1 (en) | 1998-09-30 |
| KR100190976B1 (en) | 1999-06-15 |
| FI932238A0 (en) | 1993-05-17 |
| TW216471B (en) | 1993-11-21 |
| FI932238A (en) | 1993-05-17 |
| BR9107139A (en) | 1993-11-16 |
| JPH06505138A (en) | 1994-06-09 |
| GR3030105T3 (en) | 1999-07-30 |
| AU652807B2 (en) | 1994-09-08 |
| JP3280022B2 (en) | 2002-04-30 |
| BG97790A (en) | 1994-04-29 |
| HU214918B (en) | 1998-07-28 |
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