CA2097350C

CA2097350C - Asynchronous transfer mode (atm) transmission test cell generator

Info

Publication number: CA2097350C
Application number: CA002097350A
Authority: CA
Inventors: Shahrukh S. Merchant
Original assignee: American Telephone and Telegraph Co Inc
Current assignee: AT&T Corp
Priority date: 1992-08-17
Filing date: 1993-05-31
Publication date: 1998-12-22
Anticipated expiration: 2013-05-31
Also published as: DE69318773D1; DE69318773T2; CA2097350A1; EP0583920B1; EP0583920A1; JPH06224904A; US5457700A; JP3319827B2

Abstract

ATM test cells are generated and inserted into an ATM combined data stream in such a manner that a desired average insertion rate is maintained. Thedesired average insertion rate is obtained by enabling generation of and insertion of test cells into each idle cell of the ATM combined data stream so long as the actual number of test cells being inserted does not exceed a number that should have been inserted.

Description

20973~ 0 Asynchronous Transfer Mode (ATM) Trqrl~m:c~ion Test Cell Generator Technical Field This invention relates to packet tr~ncmi~sion and, more particularly, to S the ~,~.nel~tion of test cells.
Back~round of the Invention Arran~e...~ are known for gene.a~ g and inserting signal test pattern~
or se~luences to evaluate the ~.rullllance of tr~n~mi~sion facilities. Such prior known arr7n,~...Pul. typically inserted the test pattern or sequence at some 10 p~f-t~ - . . .i n~A place in a particular data stream at some unirollll rate.In more l~cehtly developed tr~n~mi~ ls, for example, asyllcl~unous ll~nsr~r mode (ATM) systems, it is np~cess~ry to evaluate the ~lfullllance of so-called logical ch~nn~l~, each of which compri~es an individual packetized data stream. A plurality of such logical channpl~ form a colllbih~ed data 15 stream which is typically tr~n~mitted over a single tran~mi~ic~n "-e~ The ATMtr~nsmi~sion is on a so-called cell basis, whe~ein each cell comprises a fixed length packet. If there are no data to fill the fixed length packet, a so-called idle cell is inserted. ~ddition~lly~ the individual packets or cells of any particular logical ch~nnel in the combined data stream are not in any pledll~ulged or pre~lloc~ted 20 position relative to individual packets or cells in other logical ch~nnels They are only in a predeh~...u-~A. sequence relative to the other pac~ts, i.e., cells, in their individual logical ch~nnPl Conse~uently, there is no fixed bandwidth to insert a test pattern or sequence as in the prior known arrangelllcnl~. The test pattern, i.e., the test cell, in an ATM system can only be inserted when there are idle cells or when 25 there are no useful cells being inputted, both hereinafter referred to as test cell insertion opp~llu~y intervals. Such test cell insertion ~llunity interv~ls typically occur non-unifollllly. However, it is desirable to insert the desired test cell at some predetP. rminPA average rate. Rec~use of the non-unifolm nature of oppollullilies for inserting the test cell in ATM systems, prior arran~ .-- nl~ do not 30 operate satisfactorily.
S~mmqry of the Invention The problems related to prior test cell generation and insertion arr~ng~ ..en~ and their rel~tion~hip to ATM systems are overcome in sy~t~,.lls having non-unifollll opportunities for test cell insertion, by enabling test cell insertion into ~7350 each test cell insertion opportunity interval in the combined data stream so long as the - actual number of test cells being inserted does not exceed a number that should have been inserted. In this manner, a desired predetermined average test cell insertion rate is obtained in a combined data stream having non-uniformly occurring idle cells.
In an embodiment of the invention, the desired average rate of test cell insertion in the combined data stream is obtained by generating a first indication that a predetermined number of cell intervals has occurred, i.e., a representation that a predetermined number of test cell insertions has actually occurred, and in response to the first indication and to the second indication, generating a test cell insertion enable signal so long as the number of test cells that should have been inserted exceeds the number of test cell insertions that have actually occurred.
In an exemplary embodiment of the invention, the desired average rate of test cell insertion for the combined data stream is obtained by employing a programmable counter to yield the first indication upon the occurrence of a predetermined number of test cells and a programmable counter to yield the second indication upon the predetermined number of test cells actually having been inserted. Each of these counters is reloaded with a particular initial count after completing its particular counting cycle.
The particular initial counts for each of the test cell and cell counters is initially programmed upon provisioning the desired test cell bandwidth. Then, the effective test cell insertion bandwidth is defined as (n/m)x(C), where C is the cell clock rate and it is desired to insert "n" test cells in "m" cell intervals. This is realized by loading "n-1 " in the test cell counter upon completion of its counting cycle and "m-l " in the test cell counter upon completion of its counting cycle.
In another embodiment of the invention, the particular initial counts of the cell counter and the test cell counter may be controllably changed in order to adaptively adjust the average rate of test cell insertion.
In accordance with one aspect of the present invention there is provided apparatus for inserting test cells in a data stream comprising: means for detecting test cell insertion intervals in the data stream and for generating a test cell insertion control signal only upon detection of a test cell insertion interval, means responsive to a cell clock signal and a first control signal for detecting an average rate of test cells being - 2a-inserted into the data stream and for generating a test cell insertion enable control signal when said detected average rate of test cell insertion is equal to or less than a predetermined value and for generating a test cell insertion disable control signal otherwise; means responsive to said test cell insertion control signal and said test cell 5 insertion enable control signal for generating said first control signal only when said detected average rate of insertion is equal to or less than said predetermined value; and means responsive to said first control signal for generating test cells and for inserting said generated test cells into the data stream, wherein said predetermined average test cell insertion rate is obtained.
l O In accordance with another aspect of the present invention there is provided a method for inserting test cells in a data stream, comprising the steps of: detecting test cell insertion intervals in a data stream; generating a test cell insertion control signal only upon detection of a test cell insertion interval; in response to a cell clock signal and a first control signal, detecting an average rate of test cells being inserted into the data stream; generating a test cell insertion enable control signal when said detected average rate of test cell insertion is equal to or less than a predetermined value and for generating a test cell insertion disable control signal otherwise; in response to said test cell insertion control signal and said test cell insertion enable control signal, generating said first control signal only when said detected average rate of insertion is equal to or less than said predetermined rate of value; and in response to said first control signal, generating and inserting test cells into the data stream, wherein said predetermined average test cell insertion rate is obtained.
Brief Description of the Drawin~
In the drawing:
FIG. I shows, in simplified block diagram form, a test cell generator arrangement including an embodiment of the invention.
Detailed Description FIG. I shows, in simplified block diagram form, test cell generator arrangement 100 including an embodiment of the invention. A received ATM cell stream is supplied via path 101 to idle detect unit 104 and buffer 107. The received ~ ~ ~ 7 .~ 5 ~

ATM cell stream cont~in~ a contin-lo~l~ stream of ATM cells which, in general, include idle cells and non-idle cells. For the pull~oses of this explanation, it is ~c~ ~ that the inromin~ ATM line rate is 155.52 Mb/s, which is known as the STM-l rate, although the invention is not limited in this regard. The ATM cell S stream is -,~...p~iG~l by a Bit/Word clock which, ~lc~nding on the particular imple.~ ;on, may be a clock at the bit rate of the ATM cell stream if the imple..~. ~t~l;on is a serial one or, more typically, a sub-multiple of the ATM cell stream bit rate if the data are carried on a parallel bus. The Bit/Word Clock issupplied via path 102 to sub-cell timing unit 117. In ~l(lition, a Cell Clock is10 present, which provides infol.n~;on that identifies the bollnd~ries of the fixed-length cells. The Cell Clock is supplied via path 103 to sub-cell timing unit 117, test cell counter 119, cell counter 120 and control counter 121. The Bit/Word Clock and Cell Clock are derived from the line rate, in this ex~mpl~ the STM-l rate of 155.52 Mb/s, in a known f~Qllion Idle detect unit 104 makes a ~i~t~ ;n~l;on~ based on the con~ of the header of the cell, wh~lLer an inroming cell is an idle cell. This is achieved in a known fashion by cGI~aling the rece;~ed cell header to an e~t~d idle cell pattern.
For example, an ATM idle cell has a distinct header as defined in CCITT
Reco.. lel-cl~tiQn I.361 entitled B-ISDN ATM Layer Specific~tion Idle detect unit 20 104 generates an active idle cell inllir~tion signal (logic 1) when it detects such an idle cell. The resl~lting idle cell indicati~n signal is supplied via path 131 to AND
gate 114, where it is combined with a Test Cell Insert Enable signal (i.e., a second control signal) supplied via path 115 from control counter 121 to produce a Test Cell Insert Control signal (i.e., a first control signal). The Test Cell Insert Control signal 25 is supplied via path 111 to test pattern ge~-e~ o~ 110, selector 105 and test cell counter 119. If the Test Cell Insert Control signal is active (i.e., a logic 1) then, and only then, does seleclor 105 choose an assembled test cell being supplied from test cell asse~bler 113 to be supplied as an output to path 109. If the incoming cell is not idle, or if the Test Cell Insert Enable signal is not active (i.e., a logic 0), then 30 select- r 105 simply passes the signal on path 108 from buffer 107, and which signal is a delayed version of the inroming ATM cell stream, as an output to path 109.
This is in accordance with the function of this aTr~ngement~ whereby generalion and insertion of test cells only occurs when idle cells are present on the incoming data stream; otherwise the cells of the incoming data stream are to be passed through35 tran~ e,llly. The cells from buffer 107 are llnrh~nged except for the fixed delay inserted by buffer 107. Buffer 107 is necessary since it takes come part of a cell 209~3S0 time f0 the idle detect unit 104 to make the ~3et~ tion whether the incoming cell is an idle cell.
Under some con(litiQn~t it may be known a priori that the incoming ATM cell stream on path 101 does not contain any useful ATM cells. For example, 5 incoming ATM line may be ~ conl;nu~l or disabled. In such a sinl~tion, every cell interval is a test cell insertion op~.lunil~, reg~nlless of whether or not it is an idle cell interval.
This con-lition can readily be ~cco.. n-1~ted by simply forcing the output of idle detect unit 104, carried on path 131, to be always active, regardless of 10 whether an idle cell has actually been detecte~l Thus, this situation is not treated as a se~te con~lition he.~,.nart~
When enabled by the Test Cell Insert Control signal, test pattern ~nel~alo~ 110 creates the text signal that is to be inserted into the payload of the individual test cells. A typical ...~nil;,al~l;on of test pattern ~,enerator 110 gel~ eS
15 a pseudo-random bit sequence, so~ es called a PN pattern, which sequence conl;n-,es across s~lcces~ive test cells. However, any suit~ble test pattern, fixed or cyclical, may be used for this pull~ose and this invention is not liînited in this regard.
The test pattern created by test pattern gen~.~lor 110 is inserted into the payload of the test cell. In ~1-1ition, supplen-c..~.y info.lll&tion such as a sequence number or 20 an e..o. detrctiQn code based on the test pattern may also be inserted into the payload of the cell. For the pul~oses of this expl~n~tion and without so limiting the scope of this invention, it may be assumed that these auxiliary functions are incorporated into test pattern generator 110.
Test cell header gen~ or 112 g~ -e.i~les the header of the test cell, 25 which typically co~.~;tin~ routing and destination infs...-~tion, other inrc,.lllalion related to oper~tion~ and l-,ainlellance, and a header error ~l~t~ction and correction code. The test cell header is supplied on path 106, while the test pattern and other paylo~d info.~lion are supplied on path 118 to test cell assembler 113, where they are coll-b-ncd into a test cell. The seqllencing of this test cell assembly is ~.ru~ ed 30 by sub-cell timing unit 117, which synchronizes the test cell creation and assembly to the incoming Bit/Word Clock and Cell Clock, and sends timing control signals via paths 128, 129 and 130 to coordinate test cell header gen~,~alOl 112, test pattern ge.~ or 110 and test cell assembler 113, ~s~eclively, that create the various COIllpOllelltS of the test cell. The resul~ing test cell is supplied via path 116 to 35 selector 105 and, in turn, is supplied as an output to path 109 when the Test Cell Insert Control signal is active.

The arr~ngem~nt of the test cell counter 119, cell counter 120 and control COwlt,. 121, shown in FIG. 1, are central to the variable bandwidth insertion car~bility of test cell ~nelator arr~ngem.ont 100. This combin~ion of count~s 119, 120 and 121 produces, the Test Cell Insert Enable signal, in response to the Test Cell S Insert Control signal. If the average rate of test cell insertion is lower than or equal to the desired pf~ete ..-;nYl rate, twe Test Cell ~sert Enable signal is kept active, thereby enabling test cell insertion at every op~llullily (i.e., during eveîy idle cell interval). If the average rate of test cell insertion is greater than the desired pr~te~ ned rate, the Test Cell Insert Enable signal is made in~;li~e, thereby 10 ~IllpOlalily disabling the insertion of any test cells and re~3ucing the average test cell insertion rate. This fee~lb~c~ process is described in more detail below.
Assume that as a starting con~litiQn coun~s 119 and 120 are loaded with the values n-1 and m-1, l~,~,~;lively, and the desired test cell insertion rate is n/mxC, where C is the Cell Clock rate, i.e., the number of cells per unit time on an 15 input or output line of the system. Since, the test cell insertion rate cannot exceed the total line rate, n must be less than m. ~ ~tches 122 and 123 are pro~
initially, by controller 124 (not shown), for eY~mrle, to the values n-1 and m-1, ~,.,~;li./ely, to effect the desired test cell insertion rate. Counters 119 and 120 are relr~ 1 with these values from latches 122 and 123, respectively, when coullte..7 20 119 and 120, which are shown for illustration as "countdown-mode" countel~" count down to zero. That is to say, countels 119 awd 120 are loaded with their l~,s~ ivcly initial count values at the end of their lc~,pecLi~e count cycles.
Assume further that control counter 121 is initially set to ~ro. Control counter 121 is shown as an Up/Down counter, which inc~ell~ , when it receives an25 active signal on its hlw~llent (INCR) control path 126 and dec~,mellLs when it lccei~.es an active signal on its decle.lle.lt (DECR) control path 125. If control counter 121 ,~cei~,s active signals on its incl~ llt path 126 and its decl~ lt path 125 ~im~ n~ously~ it retains its previous count value. All of count~,l., 119, 120 and 121 operate syncl~unously with the Cell Clock supplied via path 103.
Let one "co~lnting cycle" for cell counter 120 be defined as m cell intervals. Then, over one counting cycle of m cells, cell counter 120 will cycle once, and then, supply an active output to in.,l~ ent path 126, since it counts down by one for every Cell Clock interval. Control counter 121 will incl~l~lent in response to the active state supplied on path 126, thereby activating the Test Cell Insert Enable 35 signal, and insertion of test cells will then co.. ~nce with the following counting cycle, as described above.

203~3~ 0 Let us first consi(ler the case when there are suffi~ient idle cells on the in-~oming ATM cell strea-m-- on path 101 so that all n desired test cells may beinserted in one counting cycle of cell counter 120. Then, after the first n such idle cells in the coundng cycle of cell counter 120, n test cells will have been inserted.
S Test cell counter 119 counts these test cell insenions, since it is only enabled when the Test Cell Insen Control signal supplied via path 111 is active which, in turn, is only activated when a test cell is actually insened. Thus, when test cell counter 119 counts down to zero at the nth test cell insertion, it supplies an active output to decle.l,ent path 125. This dec,en~el ls the control counter 121 back to zero, which 10 dc.actival.~s the Test Cell Insen Enable signal, thereby disabling funher test cell insertion for that collnting cycle of cell counter 120. At the co~ ncem~nt of the next counting cycle, cell counter 120 once again supplies an active output via path 126 which in~ nls control counter 121. Then, the test cell insenion cycle repeats, with n test cells being inserted every m cell intervals. This achieves the 15 desired test cell rate of n/mxC. The "counting cycle for test cell counter 119, h~.~;ror, is n test cell insertions.
However, as m~ntiont~A earlier, the presence of idle cells is not gu~.~ ed at all times, since the occupancy of cells in a packetized cell stream is st~ti~tir~l in nature. Thus, ~lthough the average rate of idle cells on input 101 must, of course, be at least equal to the average test cell insertion rate over an extended period of time, there is no guarantee that this con-1ition will be met over a shorter interval, such as one co--nting cycle of cell counter 120. Some retention of this il~....~l;on, i.e., the fact that all n test cells were not insened in m cell intervals, is nee~e~l, lh~.erol~, to ..~in~i.in the desired ~ ele-..~ ul average test cell insertion rate over t~ shortages in test cell insertion oppollullilies in the forrn of idle cells. This retenti- n of info....~l;on is provided by control counter 121. If, during one counting cycle of cell counter 120, n test cells have not been inserted, then control COW1te1 121 is not decl~l"ented and simply co..l;n~.es to be inclementedfurther with each suGces~ co~nting cycle of cell counter 120. Since the Test Cell 30 Insert Enable signal is active wllel~e~e. the count value of control counter 121 is greater than one, test cell insertion is continllQusly enabled. This allows test cell insertion at a rate lc~ uily greater than the desired ~lede~....;~-ed average rate of n/mxC. Once the inciden~e of idle cell oc~;w,~ince has increased, the dec,~ ent rate of the control counter 121 then tell-po,~ily excee l~ its inclelllenl rate until such tirne 35 as the additional test cell insertion catches up with the desired pre~ete....i n~d average rate ~quired and control counter 121 once again is decrernented to zero.

20~73~ 0 The ~ sizes of COull~e.s 119, 120 and 121 is d~tel~ed by obsel~ g that (a) the smAl4st test cell insertion rate possible is with n = 2, m = M, or 2/mxC, and (b) the smAll~st inc~ t in test cell insertion rate possible is l/mxC.
The system r~ui~nl on these-two ~ D~et~ that yields the larger value for M
5 will dete. . . ~; ne the size of cell counter 120. Typically, the value of M is in.;~ciascd to the next larger power of 2 for common impk..~. n~l;on~ of countel~ with binary logic.
Similarly, the mA~;.. size, N, of test cell counter 199, may be det~llllined by obsel~ing that the largest test cell insertion rate possible, while still 10 mAint~ininp the resolntion of test cell rates, is N/MxC.
The mL~imum size, K, of control counter 121 may be detelll~ined by the burstiness and loading of the traffic e~pected Under con-litione of high loading and high bul~ ~ss, control counter 121 may need to retain several accum~ ted counting cycles during which in~llfficient test cells were ~neldted.
In FIG. 1, an Overflow Alarm signal is shown as being supplied on path 127, which is a;livat~l should control counter 121 overflow. This Alarm Overflowsignal may, for eYAnlrle7 be p.~ces~d by controller 124 and either raise an alarm to an op~,lalor or adaptively lower the test cell insertion rate cell, as described below.
Since n cells are inserted at the first n opp~llu~ilies every m Cell Clock 20 times, and n and m are both progl~nable, test cell gcnclalul ~rrangem~nt 100 also provides, control over the burstiness of the gene~ted test cell traffic. As an example, if the desired test cell insertion rate were 25% of the line capacity, i.e., 0.25C, this could be gel~ela~d with n = 2, m = 8, or with n = 50, m = 200, etc., limited only by the si~ of co~n~e.~ 119 and 120. These values of n and m would give the same 25 average test cell insertion rate (0.25C in this example), but the bul~ ness of the resulting traffic varies ~ignifirAntly. In particular, this feature may be used as an enhanced test to verify the pf rv. .~nce of the system or n~ lwol~ under test in the pl~scn~c of traffic with the same average rates, but with differing peak rates.
Since latches 122 and 123 may be pro~i.. ed and may even be 30 repro~a~,ed while the circuit is operational, the invention as shown is particularly suitable to adaptive control of the test cell insertion rate. As an e~mple~ if control counter 121 were to overflow and cause an alarm, one of the actions that controller 124 could take is to reduce the test cell insertion rate adaptively, within prescribed bounds or per a prescribed schedule.

209~S~

In a remote loc~tion, reception of test cells is detectç~3 and, then, the ~ce;~od test pattern is cG~ d, in well known f~hion, to the expected test pattern to detel~ine if there are errors.

Claims

Claims:

1. Apparatus for inserting test cells in a data stream comprising:
means for detecting test cell insertion intervals in the data stream and for generating a test cell insertion control signal only upon detection of a test cell insertion interval;
means responsive to a cell clock signal and a first control signal for detecting an average rate of test cells being inserted into the data stream and for generating a test cell insertion enable control signal when said detected average rate of test cell insertion is equal to or less than a predetermined value and for generating a test cell insertion disable control signal otherwise;
means responsive to said test cell insertion control signal and said test cell insertion enable control signal for generating said first control signal only when said detected average rate of insertion is equal to or less than said predetermined value; and means responsive to said first control signal for generating test cells and for inserting said generated test cells into the data stream, wherein said predetermined average test cell insertion rate is obtained.

2. Apparatus as defined in claim 1 wherein said means for detecting test cell insertion intervals includes means for detecting idle cells in the data stream and for generating said test cell insertion control signal indicating that an idle cell has been detected.

3. Apparatus as defined in claim 2 wherein said combined data stream is an asynchronous transfer mode (ATM) combined data stream.

4. Apparatus as defined in claim 2 wherein said means for detecting said average rate of test cell insertion and for generating said test cell insertion enable control signal includes means responsive to said cell clock signal for generating a first indication that a first predetermined number of cell intervals of the data stream has occurred, means responsive to said first control signal and to said cell clock signal for generating a second indication indicative that a second predetermined number of test cells has been inserted into the data stream during said first predetermined number of test cell intervals and means responsive to said first indication and said second indication for generating said test cell insertion enable control signal when said predetermined second number of test cells has not been inserted during said first predetermined number of cell intervals.

5. Apparatus as defined in claim 4 wherein said means for generating said first indication comprises first counter means for yielding said first indication upon counting said first predetermined number, said means for generating said second indication comprises second counter means for yielding said second indication upon counting said second predetermined number and said means for detecting said average rate of test cell insertion and for generating said test cell insertion enable control signal comprises counter means supplied with said first and second indications for generating said test cell insertion enable control signal to enable generation and insertion of test cells so long as a count of said first indications is greater than a count of said second indications.

6. Apparatus as defined in claim 5 wherein said first predetermined number is not less than said second predetermined number.

7. Apparatus as defined in claim 5 wherein said counter means for generating said second control signal is an up/down counter.

8. Apparatus as defined in claim 7 wherein said first counter means comprises a programmable counter programmed to count said first predetermined number and said second counter means comprises a programmable counter programmed to count said second predetermined number.

9. Apparatus as defined in claim 8 further including means for adjusting said first predetermined number and/or said second predetermined number.

10. Apparatus as defined in claim 9 further including means for adaptively adjusting said first predetermined number and/or said second predetermined number.

11. A method for inserting test cells in a data stream, comprising the steps of:detecting test cell insertion intervals in a data stream;
generating a test cell insertion control signal only upon detection of a test cell insertion interval;
in response to a cell clock signal and a first control signal, detecting an average rate of test cells being inserted into the data stream;
generating a test cell insertion enable control signal when said detected average rate of test cell insertion is equal to or less than a predetermined value and for generating a test cell insertion disable control signal otherwise;
in response to said test cell insertion control signal and said test cell insertion enable control signal, generating said first control signal only when said detected average rate of insertion is equal to or less than said predetermined rate of value; andin response to said first control signal, generating and inserting test cells into the data stream, wherein said predetermined average test cell insertion rate is obtained.

12. The method as defined in claim 11 wherein said step of detecting test cell insertion intervals includes the step of detecting idle cells in the data stream and wherein said step of generating a test cell insertion control signal generates said test cell insertion control signal indicating that an idle cell has been detected.

13. The method as defined in claim 12 wherein said combined data stream is an asynchronous transfer mode (ATM) combined data stream.

14. The method as defined in claim 12 wherein said step of generating said test cell insertion enable control signal includes the steps of in response to said cell clock signal, generating a first indication that a first predetermined number of cell intervals of said data stream has occurred, in response to said first control signal and said cell clock signal, generating a second indication indicative that a second predetermined number of test cells has been inserted in the data stream and in response to said first indication and said second indication generating said test cell insertion enable control signal when said predetermined second number of test cells has not been inserted during said first predetermined number of cell intervals.

15. The method as defined in claim 14 wherein said step of generating said first indication yields said first indication upon counting said first predetermined number, said step of generating said second indication yields said second indication upon counting said second predetermined number and said step of generating said test cell insertion enable control signal in response to said first and second indications generates said test cell insertion enable control signal to enable generation and insertion of test cells so long as a count of said first indications is greater than a count of said second indications.

16. Apparatus as defined in claim 15 wherein said first predetermined number is not less than said second predetermined number.

17. Apparatus as defined in claim 15 further including a step of adjusting said first predetermined number and/or said second predetermined number.

18. Apparatus as defined in claim 17 further including a step of adaptively adjusting said first predetermined number and/or said second predetermined number.