CA2097762A1

CA2097762A1 - Disk drive controller with a posted write cache memory

Info

Publication number: CA2097762A1
Application number: CA002097762A
Authority: CA
Inventors: Dennis J. Alexander; Ryan A. Callison; Ralph S. Perry
Original assignee: Dennis J. Alexander; Ryan A. Callison; Ralph S. Perry; Compaq Computer Corporation
Current assignee: Compaq Computer Corp
Priority date: 1992-06-05
Filing date: 1993-06-04
Publication date: 1993-12-06
Also published as: EP0582370A2; US5586248A; ATE172038T1; EP0582370A3; DE69321426D1; DE69321426T2; EP0582370B1

Abstract

ABSTRACT

DISK DRIVE CONTROLLER WITH
A POSTED WRITE CACHE MEMORY

A disk array controller includes a local microprocessor, a bus master interface, a compatible interface, buffer memory and a disk interface. The controller includes a DMA controller between the microprocessor, the bus master interface, the compatibility interface and the buffer memory DMA
controllers are also provided between the disk interface and the buffer memory. One of these DMA
channels includes an XOR engine used to develop parity information used with the disk array. The various DMA
controllers are cycled to allow access to the buffer memory and the disk interface. A posted write memory system is connected as a selectable disk drive to the disk interface. The posted write memory system includes mirrored, parity checked and battery backed semiconductor memory to allow posted write data to be retained during power down conditions with only a very small change of data loss.

Description

2~977~2 DISK DRIVE CO~ITKOLLER WITH
A POSTED WRITE CACHE MEMORY
The present invention relates to controllers used with hard disk drive ~ystems used with computers, and more par~icularly to posted write operations o~ the controller.

Personal computers have been getting ever faster and more powerful at a rapid rate. Signi~icant portions of this advance are due to the increased speeds and data widths of the microprocessors currently available. Microprocassors have gone from 8 bit data widths and operating fr~quencies of 1 ~Hz to 32 bit data widths and basic clock rates of 33 MHz. Memory techniques have been developed to, in the greatest part, allow memory system speeds to keep up with the speed of the microproce~sor. ~owever, the sa~e speed increases are not true for the various input/output and mass storage ~ystems. The various peripheral devices are often now seen a~ limi~ations to the actual speed of a qiven computer sy~tem. If for instance, the personal computer is utilized prlmarily for word processing applications, then higher disk performance ~5 is more important then proces~or speed in mo~t cases and relative increase in ~he disksubsys~em performance will be ~uch ~ore directly perceived then a given increase in the micr~processor capabilities.

2 n 9 r~ r~ ~; 2 In the past few year6, ~ new type of mass data storage 6ubsystem has emerged ~or improving the data transfer performance. This sub6y~tem is generally known a~ a disk array 6ubsystem. One reason for wanting to build a disk array 6ubsystem is to create a logical device th~t has a very high data transfer rate.
~his may be accomplished by ganging multiple ~tandard disk drives together and transferring data to or from these drives to the 6ystem ~emory. If n drives are ganged together, then the effective data transferred rate is increased in an amount #lightly less than n times. This technique, called ~striping, n originated in the supercomputing environment where a transfer of large amounts o~ ~ata to and ~rom secondary storage is a frequent requirement. With this approach, the n physical drives become a single logical devices and may be implemented either through software or hardware.
A number of reference articl~s on the design of disk arrays have been published in recent years. These include "Some Design Issues of Disk Arrays" by Spencer Ng April, 1989 IEEE; "Disk Array Systems" by Wes E.
Meador, April, 1989 IEEE; and ~A Case for Redundant Arrays of Inexpensive Disks (RAD) n by D. Patterson, G.
Gibson and R. Catts, Report No. UCBICSD 87/391, December, 1987, Computer Science Division, Unlversity of California, Berkeley, California.
In general these previous techniques have used several controller boards which could access ~ultiple drives o~er a small computer system interface (SCSI).
Multiple SCSI controller boards were used, with ~ultiple drives connected to each controller board.
Software resident in the host computer itself performed the operation of data distribution and control of the various controller boards and of the specific drives on a given controller board. The host computer was also required to do various parity operations reguired as preferred in the techniques to reduce the amount of space related to error correction versus artual data ., : ~

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storage. Thus, while high disk transfer rates could be developed, ~he host computer was still ti~d up performing various control functlons.
Recent personal computers have developed bus architQctures which are capable of sustaining devices which are called ~bus masters.~ A bus master may take control o~ the computer sy6tem at certaln times and transf2r data between the bus master and the system ~emory without requiring the oervice of the main or host processor. The ~us ~ster can then release the bus back to the host processor when the transfers are not necessary. In this ~anner coprocessing tasks can be developed. Especially cuitable for ~uch coprocessing tasks are graphical displays, network interfacing and hard disk subsystem control. The various buses or architectures are exempli~ied by the Micro Channel Arc~itecture (MCA) developed by International Business Machines Corporation ~IBM) or the Extended Industry Standard Architecture (EISA). A
copy of the ~ISA specification, provided as Appendix 1 to U.S. Patent No. 5,101,492, which is hereby incorporated by reference, ~xplains the requirements of an EISA system. Thus it became obvious to place a local processor on a separate board which could be inserted into these busses ~or disk coprocessing functions. However, it then became critical, particularly when combined with the disk arrays, to allow optimal data transfer capabilities without otherwise slowing down the various devices and capabilities.
To this ~nd Compaq Computer Corporation developed a disk array controller with improved parity d~velopment. The disk array controller was incorporated in a product referred to as the Intelligent ~rive Array or IDA, which was sold in or about December, 1989 and thereafter. The system operated as a bus master in a personal computer. To this end there was a local processor to handle and : : : ~ ,. . :.

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control operations in the di k array controller. The local processor interfaced with ~ bu6 ~6ter controller and with a data transfer controller. The data transfer controller also interfaced with the bus ~aster controller. The bus master controller wa~ used to provide disk 6ubsystem access to the host computer 6ystem for transferring disk commands and data.
A ~econd avenue of obtaining and returning data and commands to the host sy~tem was through a compatibility controller. The compatibility controller was also linked to the tr~nsfer controller.
Additionally, up to 8 individual hard disk drives, which have integrated device controllers, were linked to the transfer controller. Finally, an amount of transfer buffer m~mory was coupled to the transfer controller.
The transfer controller operated as a direct memory access (DMA) controller having four ~ain channels. The main channels were connected to the bus master controller the local processor, the compatibility controller and a disk interface controller. The disk channel was broken down into four subchannels. One o~ the disk ~ubchannels included an XOR subsystem to allow ef~icient development of the parity information preferahly used for data protection.
The data which was transferred between the host system and the disk array was contained in the buffer RAM and was shuttled to and from th~ buffer RAM by the transfer controller under control of the local processor and the bus master controller. By properly organizing the transfers parity data could be rapidly obtained.
Eventually the need for even higher throughputs then that provided by the IDA was needed as applications grew larger and local area networks (LANs) became larger, the IDA being primarily used in a file server on the LAN.
One technique for improving system performance was the use of disk ~aching prvgramq. An amount of main ~" .. :: : - .

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~emory was utilizsd as a cache for disk data. Because the ~ain ~emory was 6ignificantly faster than the disk drive, if the desired data was present in the cache, greatly improved performance resulted. In fact, this i~ a ma~or feature u~ed on the file server when running network operating systems. While disk caching can be readily ~pplied to rsad operations, it is ~ignificantly more difficult to utiliæe with write ~perations. A
technique known ~s write posting saves the write data in a cache and returns an operation complete indicator before the data is written to the disks. Then, during a less active time the data is actually written to the disk. However, thi~ technique has one major danger, namely the loss of data which the user believes has been written to the disk drive. If the data was in the posted wTite cache and p~wer was lost, the data was not actually written, even though the user had been informed of a completion. This data loss may not be noticed for a long period and may cause numerous undetected errors.
Therefoxe this technique, while providing major benefits, i~ generally considered unacceptable for many u~es, such as on the file servers in LANs, where the data loss could be critical. Therefore the technique is not generally used and potential performance increases are lost in an area where even incremental increases were desirable.

The present invention provides secure write posting capability to a disk controller to allow the write posting perfsrmance increase to be used in critical 6ituation~ ~uch as file servers. A cache of mirrored, parity-checked, battery-backed semiconductor memory is provided to serve as a write posting cache.
Write data i~ provided to the cache and a complete indication is returned. Should the power be lost, the battery-backup feature retains the data in the memory for a cer ain period. The parity checking allows ~ ... :: ,, -,: :~ . .' , 2B977~2 determination of errors pr~or to ~ctual ~torage of the data on the disk dri~e. When an error i~ obtained, the mirroring eature allows access to an exact copy of the data 80 that valid data i~ still ~vailable for 6torage ~5 by the disk drive. The co~bination of battery backup, ` mirroring and parity checking provides a cache having sufficient data security to allow use in evan very critical environments.
In the preferred embodiment the posted write cache is utilized on a develop~ent of the controller in the IDA. The cache includes an interface which allows it to emulate a conventional integrated drive electronics (IDE) disk drive. This allows a simple connection to the drive channel ~upport of the IDA. The controller software then has control of data transf~r with the posted write cache by its normal, high speed operations.

A better understanding of the present invention ~0 can be obtained when the following detailed description of the preferred embodiment i~ considered with the following drawings, in which:
Figure 1 is block diagram of a disk array controller incorporating the present invention;
Figure 2 is a block diagram of the transfer controller of Figure l;
Figures 3, 4 and 5 are more detailed block diagrams of portions of the transfer controller of Figur~ l;
Figure 7 ls a timing diagra~ of portions of ~he circuitry of the transfer controller of ~igure 1;
Figures 6 and 8~21 are 6chematic diagram~ of portions of the transfer ~ontroller of Figure 1, including XOR circuitry;
Figures 22-24 are schematic illustrations of diagrams of portions of the interface to the posted write memory of Yigure l;

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2~77~2 Figure 25 i~ a block diagram of the posted write ~emory of Figure 1;
Figures 26-33 are ~chematic diagrams of portions o~ the posted write memory of Figure 25; and S Figures 34-37 are ~chematic illustrations of data flow in the di~k ~rray controller of Figure 1.

Referring now to Figuxe 1, the letter D general represents a disk array controller incorporating the present invention. The disk array controller D has a local processor 30, preferably a V53 manufactured by NEC. The local processor 30 has address bus UD, data hus UD and control bus UC outputs. The data bus UD is connected to a transceiver 32 who~e output is the local data bus LD. The address bus UA is connected to the inputs of a buffer 34 whose outputs are connected to the lccal data bus LD. The local processor 30 has associated with it random access memory (RA~) 36 coupled via the data bus UD and the address bus UA.
The RAM 36 is connected to the processor control bus UC
to develop proper timing signals. Simil~rly, read only memory (ROM) 38 is connected to the data bus UD, the processor address bus UA and the processor control bus UC. Thus the local processsr 30 has its own resident memory to control its operation and for its data storage. A programmable array l~gic (PAL) device 40 is connected to the local processor control bus UC and to the pr~cessor address bus UA to develop additional control signals utilized in the disk array controller D.
The local pr~cessor address bus UA, the local data bu~ LD and the local processor control bus UC are also connected to a bus master integrated controller (BMIC) 42. The BMIC 42 serves the function of interfacing the disk array contr~ller D with a standard bus, such as the EISA or MCA bus and acting as a bus master. In the preferred embodiDent the BMIC 42 is interfaced with the EISA bu~ and i5 the 82355 provided by Intel. Thus by - ': , ; ~ , : . , ~ , ~ :

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this connection with the local processor nddress bus U~, the local data bus LD and the control bus UC the BMIC 42 can interface with the local processor 30 to allow data and control information to be passed between the host system ~nd the local processor 30~
Add$tionally, the local data bus LD and local processor control bus UC are connected to a transfer controller 44. The transfer controller 44 will be explained in more detail, but is generally a specialized, multichannel direct memory access (DMA) controller used to transfer data between the transfer buffer RAM 46 and the various other devices present in the disk array contrcller D. For example, the transfer controller 44 i~ connected to the BMIC 42 by the BMIC
data lines BD and the BMIC control lines BC. Thus over this interface the transfer controller 44 can transfer data from the transfer buffer ~AM 46 through the transfer controller 44 to the BMIC 42 if a read operation is requested. If a write operation is requested data can be transferred from the BMIC 42 through the transfer controller 44 to the transfer buffer RAM 46. The transfer controller 44 can then pass this information from the transfer buffer ~AM 46 to disk array A.
The transfer controller 44 includes a disk data bus DD and a disk address and control bus DAC. Th~
di~k data bus DD is connected to transceivers 48 and 50. The disk address and control bus ~AC is connected to two buffers 64 and 66 which are used for control signals between the transfer controller 44 and the disk array A. The outputs of th~ transceiver 48 and the buffer 64 are connected to two disk drive port connectors 52 and 54. These port connectors 52 and 54 are preferably developed according to the integrated devic~ interface utilized for hard disk unlts a copy of which i8 attac~ed as ~ppendix A. Two hard disks 56 and 58 can be connected to each connector 52 or 54. In a similar fashion, two connector~ 60 and 62 are connected 20977~2 ~9_ to the ~utputs of ~he transceiver 50 ~nd the buEfer 66.
Thu5 in the preferred embodiment 8 disk drives can be connected or coupled to the transfer controller 44. In this way the various dat~, ~ddress and control ~ignal S can pas6 between the trans~er controller 44 and the particular disk drives 56 ~nd 58, for exampl~.
A prGgra~mable array l~gic (PAL) device block 67 is connected to the disk address and control bus DAC
and receives inputs from a control latch 908 (Fig. 23).
The PAL block 67 is used to map in a posted write cache memory 71 as a di6k drive as indicated by the control latch 908 and map out the actual disk drive. A
transceiver 73 and ~ buffer 75 are connected to the disk data bus D~ and the disk address and control bus DAC, respectively, to allow data and control information to be passed with the transfer controller 44.
In the preferred embodiment a compatibility port controller 64 is ~lso connected to the EISA bus. The compatibility port controller 64 is connected to the transfer controller 44 over the compatibility data lines CD and the compatibility control lines CC. The compatibility port controller 64 i~ provided 50 that software which was written for previous computer systems which do not have a disk array contxoller D and its BMIC 42, which is addressed over a EISA specific space and allows very high throughput6, can operate without requiring rewriting of the software. Thus the compatibility port controller 64 emulates the various control ports previously utilized in interfacing with hard disks.
The transfer controll~r 44 is itself comprised o~
a series of separate circuitry blocks as shown in Figure 2. There are two main units in the transfer controller 44 and these are the RAM controller 70 and the disk controller 72~ The RAM controller 70 has an arbiter to control which of the various interface devices have access to the RAM 46 and a multiplexer so . ~
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2 0 9 ~ 7 ~ 2 that data can be passed to and from the buffer RAM 46.
Likewise, the difik controller 72 includes an arbiter to determine which of the various devices has access to the integrated disk interface 74 and includes multiplexing capability to allow data to be properly transferxed back ~nd ~forth through the integrated disk interface 74.
There are basically seven DMA channals present in the transfer controller 44. One DMA channel 76 is assigned to cooperate with the ~MIC 42. ~ second DMA
channel 78 i6 designed to cooperate with the co~patibility por~ controller 64. These two devices, the BMIC 42 and the compatibility port controller 64, are coupled only to the RAM 46 through their appropriate DMA channels 76 a~d 78 and the RAM
controller 70. The BMIC 42 and the compatibility port controller 64 do not have direct access to the integrated disk interface 74 and the disk array A. The local processor 30 is connected to the RAM controller ~0 70 through a local processor RAM channel 80 and connected to the disk controller 72 through a local processor disk channel 82. Thus the local processor 30 connects as both the buffer RAM 46 and the disk array as desired.
Additionally, there ar~ four DMA disk channels 84, 86, 88 a~d 90. These four channel~ 84-90 allow information to be independently and simultaneously passed between the disk array A and the RAM 46. It is noted that the fourth DMA/disk channel 90 also includes XOR capability 80 that parity operations can be readily performed in the transfer controll~r ~4 without requiring computations by the local processor 30.
Figure 3 is a block diagram of the R~M controller 70 showing the ~arious bl~cks in the RAM controller 70 and the signals related to each of the blocks. ~n arbiter 100 receive~ input~ relating to the various DMA
channels which can request data from the transfer buffer memory 46. With this information, as well as ' ~

2Q~7762 ~ 11--~asic clocking signal CLK, the arbiter 100 produces acknowledqed ~ignal6 to the v~riou~ 3MA channels to indicate that they ~re ~ctive and can ~ccess ~he buffer RAM 46~ The arbiter 100 al60 produce6 grant signals which nre connected to a RAM direction multiplexer 102, which has an output connected to a RAM control block 104. ~he RAM direction multiplexer 102 receives inputs which indicate t~e direction o~ dat~ transfer or each appropriate DMA channel. Preferably the direction bits is high or 1 for a write to the transfer bu~fer RAM 46 and low or 0 for a read. Thus based on the active devices as indicated by the arbiter 100, the RAM
direction multiplexer 102 provides the RAMDIR signal to the RAM controller 104. With this signal and the CLK
signal the RAM controller 104 produces ROE* and RWE*, respectively the RAM output ~nable and RAM write enable, ~ignals which are applied to the transfer buffer RAM 46 to allow its proper operation.
Additionally, the arbiter 100 produces an encoded 3 bit multiplexer signal which is supplied to a RAM
address ~ultiplexer 106 and a RAM data ~ultiplexer 108.
These multiplexers 106 and 108 respectively ~ultiplex the addresses provided by the particular DM~ channel to the transf r buffer RAM 46 and the data being 6upplied from the DMA channel to the transfer buffer RAM 46.
Data being read fro~ the transfer buffer R~M 46 tG a particular DMA channel is routed in a bus (not shown) within the transfer controller 44, with tha particular DMA c~annel latchi~g the data at the appropriate time.
Details of the arbiter 100 and the RAM controller 104 will be provided.
Shown in Figures 4 and 5 are more detailed views of the BMIC DMA channel 76, the CPC DMA channel 78, the lvcal processor RAM channel sn ~ the loc~l processor disk channel 82, the disk DMA channels 84, 86 and 88, the parity or disk 3 DMA channel 90 and the disk controller 72. These blocks indicate the various signals which are provided to and from the particular ,; - , , , : ~
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2~91~6?~ -block and are provided to develop and indicate the interconnection between the various blocks and the appropriate ~ignals. The n i6 used for the DMA
channel~ 84, 86 and 88 with the value n having the value of 0, 1 or 2 depending upon the particular disk channel desired. ~hese three disk channels 84, 86 and 88 are identical in construction ~nd operation.
The arbiter 100 ie shown in more detail in Figure 6. The local processor 30 has the highest priority in the arbitration ~cheme. To this end, a ~ignal referred to as UPDRQ or local processor DM~ request i6 provided to the input of an inverter 120. The output of the inverter 120 i~ referred to as the UGNTB* signal and is provided to the inverting input of a D~type flip-flop 122. ~he clocking signal for the flip-flop 122 is provided by the CLK signal, which in the preferred embodiment is a 20 MHz 6ignal. The noninverted output of the flip-flop 122 is the UPDACK signal or local processor DMA acknowledge. The UGNTB* signal is also connected to the input of an inverter 124, whose output is the UGNT signal to indicate that the local processor 30 has been granted access.
The compatibility port controller ~4 has the second highest priority. The CDRQ siqnal to indicate its data request is connected to one input of a 2 input NAND gate 12~, whos0 other input is the ~GN~B* signal.
The output of the NAND gate 126 is the CGNTB* ~ignal, which is provided to the inverted D input of a D-type flip-flop 128 and to the input o~ an inverte~ 130. The output of the inverter is the CGNT signal. The noninverted output of the flip-flop 128 is the CREQDLY
signal, which indicates that the request has been acknowledged. The flip-flop 128 is clocked by the CLK
signal.
The CDRQ signal is al~o supplied to the input of an inverter 132 whose output is connected to one input of a 4 input AND gste 134. The AND gate 134 is associated with the BMIC 42, which has third priority.

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One of the inputs to the AND gate 134 i6 the ~DRQ
signal to indicate a data request from the 8MIC 42.
6econd ~nput i6 the output of ~n inverter 136 whose input receives the BCHB ~ignal, which indlcate~ that the appropriate channel in the BMIC 42 i5 requesting the data transfer. The fourth input n~ the AND gate 134 is connected to the output of the inverter 120 so that i~ the looal processor i~sues a request it can override the reque~t of the ~MIC 42. The output of the AND gate 134 i~ the ~GNT ~ignal or 8MIC grant signal and i6 connected to the input of an inverter 138. The output of the inverter 138 i~ connected to the inverted D input of a D-type flip-~lop 140 whose clocking input is connected to the CL~ ~ignal. The noninverted output of the flip-flop 140 is the BREQDLY signal which is used to indicate that the BMIC 42 request has been acknowledged.
The DODRQ signal which in~icates that the disk O
DMA channel is reguestin~ a data transfer is connected to one input of a 4 input NAND gate i42. One of the inputs to the NAND gate 142 is connected to the output of inverter 144, whose input is the BDRQ signal. The ^~
other two inputs to the NAND gate 142 are the output of the inverters 120 and 132. ~he output of the NAND yate 142 is the DOGNTB* signal which is provided to the inverted D input of a flip-flop 146 and to the input of an inverter 148. The ~utput of the inverter 148 is DOGNT signal. The clocking signal for the flip-flop 142 is provided by the CLK signal and the noninverted output of the ~lip-flop 146 produces the DODACK signal.

The DlDRQ signal, indicating a request for data transfer ~ro~ the disk DMA channel 1 is provided as one input to a 5 input NAND gate ~50. One of the inputs to the NAND gate 150 is the oukput of an inverter 152 who~e input is the DODRQ ~ignal. The remaining three inputs to the NAND gate 150 are connected to the outputs of the inverters 1~0, 132 and 144. The output ; :~

2 ~ 6 2 of the N~ND gate 150 i6 the DlGNTB~ ~ignal, which is provid~d to the inverted D input of a D-type ~lip-flop 154 and to the input of an inverter 156. The output of tbe inverter 156 i8 the DlGNT signal. The clocking signal of the flip-flop 154 i6 provided by ~he CLK
signal, while the noninverted output produces the DlDACK ~ignal.
The D2DRQ siynal, which indicates a DMA request by the third channel o~ the DMA to disk transfer unit is connected to one input of a 6 input NAND gate 158. One input to a NAND gate 158 i8 connected to the output of a i~verter 160 whose input is the DlDRQ signal. The remaining four inputs to the NAND gate 158 are connected to the ~utput of the inverters 120, 132, 144 and 152. The output of the NAND gate 158 is the D2GNTB* signal which is provided to the inverted D
input of a D-type flip flop 162 and to the input of an inverter 164. The output of the inverter is the D2GNT
signal to indicate a grant request to the third channel. The clocking signal for the flip-flop 162 is provided by the CLK signal and the noninverted output produces the D2DACK signalO
The D3DRQ signal which indicates that the final DMA/disk channel i~ requesting information supplied as one input to a 7 inpu~ NAND gate 1~6. One sf the inputs to the N~ND gate 166 is provided by the output of an inverter 168 whose input is connected to the D2DRQ signal. The remaining five inputs to the NAND
gate 166 are provided by the outputs of the inverters 120, 132, 144, 152 and 160. Thus the fourth channel of the DMA to disk transfer system has the lowest priority. ~he output o the NAND gate 166 is the D3GNTB* ~ignal which i~ provided to the inverted D
input of a D-typ~ flip-flop 170 and to ~he input of an inverter 172. The output of the inverter 172 is a D3GNT signal, with clocking signal provided to the flip-flop 170 being the CLK signal. The noninverted output of thP flip-flop 170 produces the D3DACK signal.

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The arbiter 100 also produces a 3 bit binary code which is supplied to various multiplexers for properly multiplexing RAM write data and transfer buffer RAM
addre6ses. This multiplexer encoding is developed by the outputs of thrQe D-type flip-flops 174, 17~ and 178. The D-type input of the flip-flop 174 i6 connected to the output of a 4 input N~ND gate 180 whose four inputs receive the UGNTB* signal, the BGNTB*
signal, DlGNTB~ 6ignal and the D3GNTB* siynal. The D
input of the second flip-flop 176 is connected to the output of a ~ input NAND gate 182. The ~our ~ignals provided to the inputs of the NAND gate 182 are the CGNTB* ~ignal, the BGNTB* signal, the D2GNTB* signal and the D3GNTB* signal. The D input to the third ~lip-flop 178 is connected to the output of a four input NAND gate 184. The four ~ignals provided to the NAND ~
gate 184 are the DOGNTB* signal, the DlGNTB* signal, the D2GNTB* signal and the D3GNTB* ~ignal. The three flip-flops 174, 176 and 178 are clocked by the CLK
signal.
Because the DNA transfers can be both read and write transfers to the transfer ~uffer memory 46 it is --necessary to know which direction the transfer is to go, is it to be a xead or is it to be a write. There is a bit in a register associated with each particular DMA channel which indicates the direction of the transfer and the RAM direction multiplexer 102 multiplexes the proper direction bit to form the RAMDIR
signal. The RAMDIR ~ignal is provided to the D input of a D-type flip-flop 200 (~ig. ~). The clocking input to the flip-flop 200 is provided by the CLK signal, which is also provided to the input of an inverter 202.
The output ~f the inverter 202 is connected to one input of a 2 input NAND gate 204 whose other input is ~5 connected to the noninverted output of the flip-flop 200. The output of the inverter 204 is the RWE*
signal, which is supplied to the write enable input of the memory devices forming the transfer buffer RAM 46.

, , : , .
, , ' , 20~7762 The inverted output of the flip-flop 200 i6 connected to ~ five series ~nverters 206, 208, 210, 212 nnd 214.
The output of the final inverter 214 in the string is the ROE~ ~ignal which is provided to the output enable inputs of the memory device6 forming the transfer ` buffer RAM 46.
The circuitry of the D~ channels 84, 86 and 88, which are the disk DMA channels 0, 1 and 2, is shown in Figs. 9 and 10. A 16 bit loadable up counter 220 is used to store and develop the transfer buffer RAM 46 address for the DMA transfer from the transfer buffer 46 to the disk array ~. The parallel inputs to the counter 220 are provided from the UDI~15..0> signals, which are the input form of the local data bus LD. In this description a bidirectional bus, particularly a data bus, dev~loped internally in the transfer controller 46 has input and output directions, and are referred to using su~fixes of the letters I and O
appropriately. These values are loaded when a low level ~ignal appears on the LA* signal, which is based on an address decode of the address provided by the local processor 30. A particular register in the transfer controller 44 is addressed by the local processor 30 by means of the local data lines L~ and the loc~l processor control bus UC. Because the local data lines LD are developed through a transceiver 32 from the data lines UD and the address lines UA, 8 bits of address information is still present on these lines during portions of the cycle. This address information, combined with a control signal in the local processor control bus UG, i5 used to develop an address for a selecti~n of a register in the transfer controller 44. One of these registers is the particular disk DMA channel address counter 220. The carry input to the counter 220 is connected to a SETCRY
signal which is provided by a register writable by the local processor 30 to indicate whether a carry is to be utilized for various counters. The clocking signal for ,,' :' ' - :' .
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20!'77~2 the address counter 220 is provided by the output of an inverter 222 whose input i~ the DNACK si~nal. Thus each time the disk channel i5 granted control of the transfer buffer RAM 46 the address counter increments.
It is also necessary to know the number sectors to be tran~ferred and the number of words in a particular 6ector for the disk. ~o this end a disk channel transfer down counter 224 is connected to the local processor data bus UDI<15.. 10> lines 60 that 6 bits are ^~
provided to this transfer counter 224. Additionally, the lower 10 bits UDI~9..0> ~re provided to the inputs of a 10 bit latch 226. The inverted load input of the down counter 224 and the inverted enable input of the latch 2~6 are connected to the LC* signal, ~hich is an indication that the number of transfers and words to be transferred has been provided to the disk channel. The clocking signal for the trans~er counter 224 is provided by the output of an inverter 228 whose input is the DnDACK signal. This signal indicates that a word has been transferred to the disk array A. The down counter 224 has a O detection inverted output which is connected to the input of an inverter 230, whose output is the XFODET signal which is used for developing an interrupt to the local processor 30 to indicate that the requested operation has been completed. It is noted that the transfer down counter 224 is enabled for down ~ounting only during certain intervals based on a down count disable input provided by the ~CODET* ~ignal, which i5 an indication that the sector ~ize or word count has decremented to O and thus it is appropriate to decrease the number sectors or word block6 being transferred.
A specific word counter i5 developed using the latch 226, whose outputs are connected to the inputs of a loadable down counter 232, which is the disk channel word counter, preferably the number o~ words to be tran~ferred in a given sector. The clocking input to '; ;: ~, ' ' . ; -2Q~62 this counter 232 is the WCCLK* signal produced by the inverter 228. Additionally, the SETCRY signal is provided to the counter 232 for carry purposes. The counter 232 also has a 0 detection output 60 that when this output is connected to the inverted input of a latch 234, the latch 234 having the DnDACK 6ignal provided to the invarted gating input, the output signal is a latched version of the 0 detaction of the counter 232. The inverted output of the latch 234 produces the WCODET* signal which is used to enable the transfer counter 224 to be decremented. The WCODET*
signal is also provided to the input of an inverter 236 whose output is the WCODET signal.
The inverted 0 detector output is also connected to the inverted D input of a D-type flip-flop 238, whose clocking input is the DnDACK signal. ~he inverted output oP the flip-flop 238 i6 provided to one input of a 2 input OR gate 240, the other input being connected to the SETCRY signal. The output of the OR
gate 240 is connected to one input of a 2 input AND
gate 242, whose other input is connected to the LC*
signal. The output of the AND gate 242 is connected to the inverted load input of the counter 232. In this case, whenever the tran~fer c~unt values are loaded by the local prooessor 30 or count down to 0, the counter 232 is reloaded on the next transfer in a disk cycle.
The inverted set input of the flip-flop 238 is connected to the RSTDCH* signal, the RESET disk channel signal.
The RSTDCH ~iynal i6 produced as the output of~an inverter 244 whose input receive~ the RSTDC~* signal.
The RSTDCH* signal is produced by the output of a 2 input AND gate 246, one of whose inputs receives the LA* signal and the other of whose inputs is c~nnected 35 to the output of a inverter 248. The input of the inverter 248 is the RST signal which indicates that the host computer system is being reset. ~hus whenever new address values are provided to the disk channel or the -, : , . , ,:. :: . . :- . . . .
:, :: , . ., - :

: .. ..
.

2~77~2 system is reset the RSTDCH* signal goes low to clear the channel.
Each disk channel 84, 86 and ~8 includes staging re~isters for disk reads and disk writes to allow for the asynchronous operations between the transfer buffer RAM 46 and the di~k array A. In this manner the transfer buf~er RAM 46 can be multiplexed between the numerous channels to allow more simultaneous operation of the various channels. For information being read from the disk array, the disk data input lines DDI<15..0> are provided to the D input of a 16 bit flip-flop 250. The clocking input to the flip-flop 250 is provided ~y the output of a 2 input NAND gate 252 whose inputs are the DnDACX and the DnDIR signals.
Thus i~ the disk array A is responding and a disk read operation is reguested, data is strobed into the disk read register 250. The data outputs of the flip-flop 250 are provided to the transfer buffer RAM multiplexer 108 for presentation to the transfer buffer RAM 46.
Similarly, a disk write register is developed using a 16 bit flip-flop 254. The D inputs to the flip-flop 254 are connected to the RAM data inputs R~I<15..0>.
The clocking signal of the flip-flop 254 is provided by a delayed version of the output of a 2 input OR gate 256. On~ input to the OR gate 256 is the DnDIR signal to indicate transfer direction, while the other input is the ADRCLX* signal which is provi~ed as the output ~f the inverter 222. The output of the ~lip-~lop 254 is provided to th~ disk controller and multiplexer 72 for presentation to the disk data lines DD whan appropriate.
Control loyic is also ass~ciated with each disk DMA channel and is 6hown in Fig. 10. This logic provides the various request signals necessary to institute a transfer from the RAM 46 to the transfer controller 44 and bstween the disk array A and the transfer controller 44. Also the logic develops the '~

2~9~7~

interrupt provided to the local processor to indicate transfex operation completion.
Prior to commencing operation it i~ ~ppropriate ~o first understand how the hard disk unit and the disk array A function. Various controls and commands are sent to the particular hard disk which performs the indicated command or operation and then returns an interrupt signal to indicate that the command has been proces~ed and completed or that the hard disk unit is ready to transfer data. This is particularly true in read operations where data iQ being obtained from the hard disk unit. Write operations, where data is being written to the hard disk unit, can commence without this interrupt because data is initially just provided to the ~ector buffer RAM located on the hard disk unit.
Interrupts are developed in that case only after the first of the requested sectors is available from the disk drive's buffer memory. Thus to perform a read operation the local processor 30 issues a command to the particular hard disk through the local processor disk channel 82. The hard disk drive performs the operation and then indicates to the transfer controller 44 by means of an interrupt that a data bl~ck is ready.
The local processor 30 will have previously programmed the particular DMA channel for operation by first supplying the proper address in the transfer buffer RAM
46 and providing the transfer and word count information. Once the transfer and word count information hax been provided, the channel is enabled for operation pending receipt ~f the interrupt from the hard disk.
In a write operation the local proGessor 30 provides the commands through the local processor disk channel 82 to set up the hard disk for the receipt of data. The local processor 30 then sets up the address value in the disX channel and then provides the count information. Because the direction bit will have been set to indicate a write to disk, upvn receiving the . - : . ;: !, ' ' ' :- : ' ' :

2~ 977 62 o2 1--count information the transf~r will automatically co~men~e to the bard di6k unit.
The interrupt ~ro~ the disk ~rray A, the DINT
~ignal, is provided to the D input of a D-type flip-. 5 flop 260. The clocking input to the flip-flop 260 i6 provided by the output of ~n inverter 262, wh~se input i6 connected to the CLX ~ignal. The n~ninverte~ output o~ the ~lip-flop 260 i~ provided to the D input of a second D-type flip~flop 264, whose ~lDcking input is also connected to th2 output of the inverter 262. The noninverted output of the inverter 264 ~nd 260 are provided as the two inputC to a 2 input AND gate 266, whose input is provided to the D input of a ~-type ~lip-flop 268. The flip-1Op 268 is clocked ~y the output of the inverter 262. The low true or inverted clear inputs to the three flip-flops 260, 264 and 266 are connected to the LC* ~ignal so that they are cleared when a count value i obtained, thus readying the control logic for operation upon the receipt of the interrupt or to detect an interrupt if one is already present.
The noninverted output ~f the flip-flop 268 is provided to the clocking input of a D-type flip-flop 270. The D input of the flip-flop 270 is provided by the noninverted output of ~ D-type flip-flop 272. The D input to the flip-flop 272 is connected to a 1 or high l~gic level, while the clocking input is provided by the LC* ~ignal. The inverted clear input of the flipofl~p 272 is c~nnected to t~e ~utput of an inverter 274, whose input is connected to the output of a 2 input NAND gat~ 276. One inpu~ to the NAND gate 276 is the RSTDCH* signal~ which indicates that the channel is being reset. The second input to the NAND gate 276 is the DnDONEB* signal which indicates t~at the desired transfer has been c~mpleted. The DnDONEB* ~ignal is provided by the inverted output of a D-type flip-flop 278.

. . . . . .

,~

2~97~

The D input to the flip-flop 278 is connected to the output of a 2 input OR gate 280. One input to the OR gate 280 i6 connected to the noninverted output of the flip-flop 272 while the other input ~s connected to the noninverted output of the flip-flop 27~. The clocking signal ~or the flip-flop 278 i~ provided by the output of a three input NAND gate 282. The inputs to the NAND gate ~re the DnDACK signal, the XFODET
signal and the WCODET signal. Thus, whenever both counters 224 and 232 have counted down to O and the disk a~knowledge signal i6 r~ceived, then this is an indicati~n that the transfer i8 dsne and the DnDONE
signal is developed at the noninverted output of the flip-flop 278. This ~ignal i~ also provided as one input to a 2 input AND gate 284. The second input to the ~ND gate 284 is the DIMASK signal, that is the disk interrupt mask signal, which is the output of a register accessible to the local processor ~0. The output of the AND gate 284 i8 the LDINT interrupt which is provided to the local processor 30 to indicate that the transfer has been completed.
The DnDIRB* ~ignal is provided to the D input of a D-type Slip-flop 286. The clocking input to the flip-flop 2~6 is the LC* ~ignal. The inverted output of the flip-flop 28~ is provided as one input to a 2 input NAND gate 288. The second input to the NAND gate 288 is the inverted output of the ~lip-flop 270. The output o~ the NAND gate 288 is the XFEREN or tran~fer enable signal. Thus it can be sePn that when data is being written to the disk array A, the transfer is enabled immediately upon writing the counter value, whereas in a read operation the transfer is not enabled until the interrupt is received back from the hard disk. The flip flops 286 and 270 have their inverted clear inputs connected to the output of a 2 input NOR
gate 290. One input to the NOR gate 290 is connected to the output of a 2 input AND gate 292. The inputs of the AND gate 292 receives the ~CODET signal and the ... ..

, 7 ~i 2 DnDAC~ signal, 60 that the transfer i6 halted at each zeroing of the word counter ~32. The transfer of the next block in either the read or write case i6 initiat~d when ~he next interrupt i6 received from the disk array A. This triggering a~6umes that the local proceqsor 30 has cleared the disk array interrupt from the pr~vious interrupt or, in the preferred case, that the di8k drive ha~ cleared the int~rrupt itself.
The output of the NAND gate 288, the XFEREN
signal, is connected to the D input of a D-type flip-flop 294. The clocking input of the flip-flop 294 is provided by the output of an invcrter 296, whose input receiveC the CLK 6ignal. The noninverted output of the flip~flop 294 i6 connected to khe 3 input D-type flip-flop 298, whose clocking ~ignal i6 provided by theoutput of the inverter 296. The noninverted output of the flip-flop 298 and the noninverted output of the flip-flop 294 are provided to the inputs of a two input AND gate 300, whose output is connected to the D input o a D-type fllp-flop 302. The clocking input of the flip-flop 302 is provided by the output of the inverter 296. The inverted clear inputs to the three flip-flops 294, 298 and 302 are provided by the output by the NOR
gate 290. Thu~ the output of the AND gate 300, when transfer operation is enabled, is latched by the flip-flop 302 until the word count is completed, the transfer is done or the channel is reset.
The noninYerted output of the flip-flop 302 is provided as one input to a four input NAND gate 304.
One input to the NAND gate 304 is ~he DnDIRB* signal that is the inverted direction signal. A third input to the NAND g2te 304 provided by the ~oninverted output of a D-type flip-flop 306. The D input of the flip-flop 306 is connected to th~ inverted output of the flip-flop 306 with the inverted clear input being connected to the RSTDCH* 6igna}. The cl~cking input of the flip-flop 306 i~ connected to the output of a two input NOR gate 308. One input to the NOR gate 30~ is ~: .

~ O ~ 7 1~ 2 the DnACX signal, while the other input is the noninverted output of a D-type flip-flop 310. The D
input of the flip-flop 310 i8 the DnDGNT ~ignal which .i8 an indication that the particular DMA channel has acces6 to the disk array A. The clocking input of the flip~flop 310 i~ connected to the CLR signal. The fourth input to the NAND gate 304 is connected to the inverting output of the flip-flop 310.
The noninverted output o~ the flip-flop 302 is also one input to a second f~ur input NAND gate 312.
The DnDIR ~ignal is one input to the NAND gate 312 while the inverted output sf the flip-flop 310 is a third input to the NAND gate 312. The fourth input to the NAND gate 312 is provided by the inverted ~utput of lS the ~lip-flop 306, which indicates that the reading channel i6 actiYe. The outputs of the NAND gates 304 and 312 are connected to the inputs o~ a two input NAND
gat~ 314 whose output is the DREQlN signal. This output is connected to the D input of a D-type flip-flop 316. The clocking signal for the flip-flop 316 is CHCLK signal which is the clocking signal used to advance the particular DMA disk channel having access to the disk ~rray A. The output of the flip-flop 316 is the DnREQ ~ignal which is an indication that the particular disk channel i requesting a transfer of data with the disk array A.
The noninverted output of flip-~lop 302 is also provided as one input to a 3 input NAND gate 31~. The second input to the NAND gate 318 i the inverted output of the flip-flop 306, while the t~ird input is the DnDIRB* signal. The noninverted output of ~he flip-flop 306 and DnDIR signals are the two inputs to a 2 input NAND gate 320. The outputs of the NAND gates 318 and 320 are provided as the two inputs to a 2 input NAND gate 322 whose output i5 provided to the D input of a D-type flip-flop 324. The clocking signal for the flip-flop 324 i5 provided by the CLK signal and the noninverted output i~ the DnDRQ signal which indicates :. ~. .. : :,. .::: . .

2~77~2 that a RAM data transfer reguest i~ pPnding. The DnACK
~ignal i~ provided ~s one input to a 2 input NOR gate 326, whose other input i~ the RSTDCH signal. The output of the NOR gate 326 i~ provided to the inverted clear input of the flip-flop 324 ~o that when ~ word has been transferred or the cbannel i5 reset the transfer request i8 cleared until the next CLX cycle.
Thus request6 alternate between the flip-flops 316 and 324 based on the toggling of the flip-flop 306. In this manner the data is properly provided in the data staging registers before being transferred to the transfer buffer RAH 46 or the disk array A.
The parity channel 90 is configured slightly differently then the other three disk channels 84, B6 and 8~ because of the need to include the parity generation circuitry~ Like devices are numbered the same between the two sets of circuitry, with a prime indicating parity channel device. Transfer counter 224' (Fig. 11) and word register 226' and counter 232' circuitries are generally the same except that the clocking signals are slightly diff~rent. The clocking ignal provided to the counter 224 and counter 232 are provided by the output of an inverter 330. The input to the inverter 330 is provided by the output of a 2 input NAND gate 332. One input t~ the NAND gate 332 is provided by the output of a 2 input NAND gate 334. The inputs to the NAND gate 334 ar~ the D3DACK signal and the PARWRR* signal. The PARWRR~ ~ignal is active low when the parity data is to be written into the transfer buffer RAM 46. The second input to the NAND gate 332 is provided by the output of a 2 input NAND gate 336.
The two inputs to the NAND gate 336 are the PX signal and the PARWRR signal. The PX signal is described later.
As a further difference the 6econd input to the two input OR gate 244 is received from the inverted output of a D-type flip-flop 338. The inverted D input of the flip-flop 338 is connected to the inverted 0 :
., , ~

:

i 2~7~ ' detection output of the counter 232', while the inverted 6et input of the flip-flop 338 i6 connected to the RSTPCH* signal. The clocking input to the flip-flop 338 iB connected to ~he output of the NAND gate 332, which is different from the flip-flop 238 which receives its clocking input from the DnDACR signal.
The data handling portion of the parity channel 90 is also different. Data is received from the disk data channel lines DDI<15..0> to the inputs of a 16 bit flip-flop 340. The clocking signal for ~he flip-flop 340 is provided by the ~utput of an inverter 342 whose input receives the D3DACK signal. The inverted reset inputs of the counters 224' and 232' and the flip-flop 340 are provided by the output o~ an inverter 344, whose input is the RST signal. The output of the inverter 344 is also connect~d to one input of a 2 input AND gate 346 whose other input receives the LD3A*
signal, which indicates that the transfer bu~fer RAM
address for this parity channel 90 is being loaded.
Tha output of the AND gate 346 is the RSPCH* signal and is provided to the input of an inverter 348, whose output is the RSTPCH signal. The output of the flip-flop 340 is provided to one input of a 16 bit 2 to 1 multipl~xer 350. The output of the ~ultiplexer 350 is provided to the multiplexer which multiplexes data to the transfer buff~r RAM 46. The select input of the multiplexer 350 is provided by the output of a 2 input NAND gate 352, whose inputs are the PAREN signal and the PARDIR signal. The PAREN signal indicates when high that the parity mode operation is enabled, while the PARDIR signal indicates whether the parity information is to be written to the transfer ~u~fer RAM
46 or to the disk array A. The output of the NAND gate 352 is also provided to the input of an inverter 354 which has the PARW2R signal as its output.
The second channel input of the multiplexer 350 is provided by the output on a 16 bit flip-flop 356 whose inputs are con~ected to the output of a second 16 bit 2 ~ - ~

2 a ~ 2 to 1 ~ultiplexex 358r The clocking signal for the flip-flop 356 i~ provided by a delayPd version of the DACKCLK ~ignal. The delay i6 provided so ~hat the read data provided from t~e RAM has ~ufficient time to pass through ~arious devices before appearing at the flip-flop 356. The D~CKCLK signal i~ produced at the output of a buffer 391. ~he input of the buffer 391 i5 connecte~ to a two input OR gate 390. One input of the OR gate 390 receive~ the CLK signal, while the second input i~ conn~cted to the output of an inverter 389.
The inverter 38~ receive~ the D3ACR ~ignal. The multiplexer 35~ has the A channel or first inputs connected to the transfer buffer RAM data bus RDI<15..0>, while the channel B inputs are connected to the output of 16 parallel XOR gate~ 360. ~he 16 bits of the transfer buffer R~M data bus RDI<lS..0> are provided to one input of the XOR gates 360, while the 16 bits ~utput by the flip-flop 356 are provided to the second input of the XOR gates 360. The select input for the multiplexer 35~ is provided by the PAREN
si~nal. Thus in this manner the data which was developed on the previous access is combined with the presently received information from the transfer buffer RAM 46 by the XOR gates 360 and provided back to the flip-flop 356 for storage when parity operation is enabled. Thus by ~ucceQsively bringing data from each of the desired chan~el~ for which parity inPorma~ion is developed into the parity channel, the parity data is cumulatively developed in the Plip-flop 356. When all of the desired channels have been read and parity information developed, then this information can be written to the transfer buffer RAM 46 or the disk array A as desir~d. The outputs of the flip-flop 356 are also provided to the multiplexer which supplies data to the disk array data bus DD. Finally, the ~utputs of the flip-flop 356 are provided to a 16 bit equal to zero comparator or detector 362. The clocking signal for the zero detector 362 is provided by the output of ., ~ ..... . .

~7762 an inverter 364 whose input ie connected to the PX
6ignal. The inverted reset input of the compari~on detector 362 i8 connected to the RSTPCH~ signal. The compari~on detector has two output~, the EQUAL output and the EQUALB* ~ignal which indicates that the value provided from the flip-flop 356 iB not equal to 0. The equal value ie 6upplied to a register which can be read by the local proce~sor 30 to determine if a valid parity operation has developed or error~ have occurred.
The 0 value is an indication that no error had developed because when parity data is XOR'd with identical parity data a 0 value results.
The inverted reset input o~ the flip-flop 356 is provided by the output of ~ three input AND gate 366.
One input to the AND gate 366 is the RSTPCH* sign~l. A
second input i6 received from the inverted output of a D-type flip-flop 368. The inverted D input of the flip-~lop 368 is connected to the output of a two input NAN~ gate 370. The inputs to the N~ND gate 370 are the PARWRR signal and the PXCB Qignal provided as the noninverted output of a D-type flip~flop 388~ The clocking signal for the flip-flop 368 is the PRCLK
signal which is provided as the clock signal ~or the flip-flop 356. The third input to the ~ND gate 366 is provided by the inverted output of a D-type flip-flop 372. The inverted D input of the flip-flop 372 is provided by the output of a two input NAND gate 374 whose inputs are the ~ARDIRB* signal and the PAREN
signal. The clocking input to the flip-flop 372 is provided by ~he output of an inverter 376 whose input receive6 the D3DGNT signal.
The inverted ~et inputs of the flip-flops 360 and 372 are provided by the output of a two input AND gate 378. One input to the AND gate 378 is the RSTPCH*
signal. The other input is connscted to the inverting output of a D-type flip-flop 380. The inverted clear input of the flip-flop 380 i~ connected to the RSTI*
~ignal output by the inverter 344, while the clocking - - . . : , . .
::: : :~ : . . : .
,: - ,. , ~ : , : , : : .
- .,. , : ::
~ , ." , . ~:

2~9~7~2 input i~ received ~rom the output of an inverter 382, whose input i5 ~onnected to the PRCLK signal. The D
input of the flip-flop 380 is connected to the noninverting output of a D-type flip-flop 384. The D
input of the Plip-flop 384 receives the P0 ~ignal which indicates that first transfer buffer block is being accessed. The clocking input to the flip-flop 384 is produced by the output of an inverter 386 whose input receives the DACKCLK signal. This output of the inverter 386 is also provided by the clocking input of a second flip-flop 3~8 whose D input receives the PX
signal and whose noninverted output develops the PXCB
~ignal. The inverted clear inputs of both flip-flops 384 and 388 are connected to the RSTPCH* 6ignal. In this way the flip-flop 56 is cleared prior to receiving the data from the first block during parity operation. If this clearing operation were not performed erroneous parity data could be developed.
Addressing information is stored differently in the parity channel 90 because four separate blocks can be combin~d by the parity channel 90 for determining parity operation. As a result ~our separate addresses must be capable of being ~tored. The local processor data inputs UDI<15..0~ are provided to the inputs of four separate 16 bit up counters 400, 402, ~04 and 406.
These up counters 400, 402, 404 and 406 represent, respectively, parity blocks 3, 2, 1 and 0 in parity channel operation. The clocking input Por all four up count2rs 400-406 i~ provided by the DACRCLX signal while the SETCRY ~ignal is provided to the carry input of all four counters 400-406. The inverted load înput to the counter 406 receives the LD3A* signal which indicates that the addres~ values for conventional disk DMA channel operation of the parity channel 90 i5 being loaded into the parity channel 90. The inverted load input for the counter 40~ receives the LDPAl* signal which is indication that the Pirst additional parity channel address is being provided. The inverted load 203~ 77 ~2 input of the count~r 40~ receives the LDPA2* signal, which is an indication that the addressing for the ~econd ~dditional parity channel iR being provided.
The inverted load input signal for the counter 400 is provided by the LDPA3* signal which is an indication that the final parity address location i5 being provided. The inverted reset input for ~11 four counters 400-406 receives the RSTI* signal indicating a parity channel re6et.
The count input of the counter 406 is connected to the ~utput of a two input AND gate 408. The inputs to the AND gate 408 are the P0 and PL* signal. The P0 ~ignal indicates that this particular P0 counter is bein~ indicated by the XOR state machine which tracks through the four counters 400-406 as appropriate for parity operations. The PL* signal is an indication, where high, that the state machine will be advancing and this is the next to the last parity address. The last address is repeated to allow the parity data to be written to the transfer buffer RAM 46 if desired. The count input for the counter 404 is provided by the output of a two input AND gate 410. The two inputs to the AND gate 410 are the PL* signal and the P1 signal which indicates that counter 1 is selected. The count input to the count~r 402 i6 provided by the output of a two input AND gate 412 whose inputs are the P2 and PL*
signals. Similarly, the count input for the counter 400 is provided by the output of a two input ~ND gate 414 whose inputs are the PL* ~nd P3 signals. The output~ of the four counter~ are provided as the four inputs to a 16 bit 4 to 1 ~ultiplexsr ~16 whose selection inputs are the SP~ and SP0 6ignals, which are a binary encoded v~rsion of the selected parity address count~r. The output o~ the counter ~ultiplexer 416 is the address signal for the parity DMA channel so and is provided to the multiplexer which supplies addresses to the transfer buffer RAM address bus RA.

, . . . - , ::: .: :. ~;, - . - :
~, .: ;,;, , . . . : . . . :, 2Q~77~

The control logic for the parity channel is ~imilar to the contr~l lo~ic fox the conventional DMA
channel 84, 86 and 88 except that necessary parity related ~ignals ~nd gates have been added. There are a few differences relating to the addition of the parity circuitry. The two input NOR gate 290' (Fig. 12) which i5 providing the ~lear 6ignal for the flip-flops 270', 286', 294', 29&' and 302' receives inputs of the output of t~e two input N~ND gate 276' and the output of a three input AND gate 420. The three inputs to the AND
gate 420 are the WCODET ignal, the WCCLX signal and the PARWRR* signal. The input to the fir~t of the transfer enable flip-flops 294' is connect~d to the output of a three input NAND gate 422 comparison to ~he two input NAND gate 288 used in the disk DMA channels 84, 86 and 88. Two of the inputs are connected to the inverted output of the flip-flops 270' and 286', with the third input being connected to the output of a two input NAND gate 424 which receives as an input the noninverted output of the ~lip-flop 272' and the PARWRR
signal. A third difference is that instead of the NOR
gate 30a, a three input NOR gate 427 is used to provide the clocking signal to the flip-flop 306'. The inputs to the NOR gate 427 are the output of a two input ~ND
gate 426, whose inputs are the B3ACK and PARENB*
signal; the noninverted output of the flip-flop ~10 and the output of a two input AND gate 425, whose inputs are the PX and PARWRD ~ignal~. Additionally, the control circuitry i5 different in that the clear signal provided tv the D3DRQ ~lip-flop 324' is provided by the output of a three input NOR gate ~28. One input of the NOR gate 428 is effectively the RSTPCH ~ignal while a second input is provided by the ~utput of a two input AND gate 430. The two ~ignals provided to the AND gate 430 are the D3ACK signal and the PAR~NB* signal. The third input to the MOR gate 42~ is provided by the output of a two input AMD gate 432 which receives the ERDDRQ signal and the ~CX* ignal, the outpu~ of the ~9~62 inverter 386. Further, the ~lip-flop 286' has its D
input ~onnected to the PD3DIRB* ~ignal, while the PD3DIR and PD3DIRB* signals replace the DnDIR ~nd DnDIRB* signal~ to NAND gate6 304', 312', 318' and 320'. The PD3DIR signal is produced as the output of a three input OR gate 285 (Fig. 11). The three inputs to the OR gate 285 are the D3DIR signal and the outputs of two AND gates 287 and 289. The two inputs to the AND
gate 287 are the PL and D2ACK ~ignals, while the three inputs to the ~ND gate 289 are the PX and PARWRR
~ignals and the output of the OR gate 390. Thus the PD3DIR signal allows the parity channel to change direction 5~ that the parity result may be written to the transfer buffer RAM 46. The PARWRD signal is the output of an inverter 43~ (Fig. 13). The input of the inverter 438 is connected to the output of a two input NAND gate 440 whose inputs are the P~REN and PARDIRB*
signal.
The output of the NAND gate 440 is also connected as one input to a two input NAND gate 442 the output of which is connected to one input o~ a two input AND gate 436. The se~ond input of the AND gate 436 is inverted and receives the PXB* si~nal. The output of the AND
gate 436 is the ERDDRQ ~ignal. The second input to the NAND gate 442 i~ produced as the ou~put of a three input AND gate ~44. One input to the AND gate 444 is provided by the output of a three input N~ND gate 446 whose inputs are the PARWRR signal, the X~0DE~ signal and the WCODET signal. A ~econd input to the AND gate 44~ is provided by the output of a three input NAND
gate 448 whose input ~ignals are the EQUAL8* sign~l which indicates that the comparison detector did not deter~ine an eguality9 the EINTEN signal which indicat~s that the equal determination interrupt is enabled and based on the result of the equal comparison, and the PARWRR sisnal. The output of the NAND gate 448 i~ also provided to the input of an inverter 450 whose output is the NTEQINT ~ignal, the 2~7762 not equal interrupt signal, which is provided to the local processor 30 if desired and ~ot ma6ked. The third input to the AND gate 444 i~ connected to the inverted output of a D-type flip-flop 452. The output of the AND gate 444 is connected to the inverted D
input of the flip-~lop 452 and the PX signal provides the clocking input to the ~lip-~lop 452. The flip-flop 452 ha~ its inverted ~et input connected to the RSTPCH*
signal.
As previously indicated the parity channel 90 can cooperate with up to four 6eparate transfer buffer segments for performing p~rity operations. The desired number of parity channels to be utilized i~ stored in a flip-flop 451 (Fig. 15) whose inputs are connected to local data bus LD and whose clocking input receives the LDPC~ signal~ which is an indication of the local processor 30 accessing the parity channel register.
Bits 2 and 3 of the data bus provide the PARCNT<1> and PARCNT<0> signals which are binary representation of the number of parity blocks or channels to be utilized in operation. The PARCNT81* and PARCNTB0* ignals are, respectively, the inverses of the two signals. The ~lip-flop 451 al60 contains the PARDIR, PAREN and EINTEN values which are provided as outputs o~ the flip-flop 451. The RST1* signal, the PAREN signal and the LDPC* 6ignal are provided as thr~e inputs to a three input AND gate 452 whose output is the SRST*
signal. Thi~ signal is u~ed to reset the ~tate machine used in the parity channel 90 50 that should this register be rewritten then the state machine automatically b~gins operation aceording to the new values.
The PARCNTcl> and PARCNT<0> signals are connected to the input~ of a two input AND gate 454 whose output is the PCNT3 signal which indicates that four buffers are to be utilized in parity operation. The P~RCNT<0>
signal and the PARCNTBl* signal are provided as the input to ~ two input AND gate 456 who~e output is the - . :
, . ~, . . :

.:

~0~477~2 PCNTl oignal which indicates t~at two buffer~ are to be used for parity operations. The P~RCNT<l> and PARCNTBO* signal are provided as the inputs of a two input AND gate 45R who~e output i8 the PCNT2 ~ignal, which indicates that three buffers ~re to be used. The PARCNTB1~ and PARCNTBO~ signals Are provided as the inputs to a two i~put NAND gate ~60 whose output is the PCNT* ~ignal and i8 connected to the input of an inverter 462 whoGe output i6 the ~CNTO ~ignal which indicates that only a single buffer is to be used.
Thus if the parity operation is not enabled, the SRST*
signal is always low and thersfore the state machine never advances. The parity channel 90 works in such a way that $he last of the buffers being utilized receives the parity information if the parity information is being written to the transfer buff r memory 46. Thus in 50me cases when parity operations are being performed the last buffer must receive two successive accesses during transfers to the buffer RAM
46 and thus the state machine should not advance under those conditions.
The state machine is developed using four D-type flip-flops 470, 47~, 474 and 476. Additionally, a fifth D-type flip-flop ~78 indioates that a redrive to the previous channel is required. The set inpu~ to the PO flip-flop 470 and the clear input to the remaining four ~lip-flops are inverted ~nd receive the SRST*
signal to reset operation to the ~irst buffer. The clock ~or all Pive ~lip-10ps 470-478 is pr~vided by the DACKCLK siynal. The D input of the PO flip-flop 470 is connected to the output of a two input ~AND gate 480 whose inputs are the PXB* signal and the PCNTO*
signal. Thus if parity operation is enabled and only one buffer is being utilized then the state machine stays at PO. The output o~ the PO ~lipwflop 470 is the PO signal.
The D input o~ th~ P1 flip-flop 472 is connected to the output of a tw~ input NAND gate 482. One input 2 ~ 2 to the NAND gate 482 is provided by the output of a two input NAND gate 484 whose inputs are the P0 ~ignal and the P~NTO* signal. ~hi~ NAND gate 484 i6 u5ed to advance the 6tate machine from pointing to buffer 0 to point to buffer 1. The second input to the NAND gate 482 i~ provided by the output of a three input NAND
gate 486 whose input~ are the Pl signal, the PCNT1 ~ignal and tha PXB* ~ignal. Thi6 NAND gate 486 i5 used to keep the state machine at the ~tate indicating that io Pl buf~er i5 being acces~ed in case only two buffers are being used in the parity operation. The D input to the P2 flip-flop 474 is connected to the output of a two input NAND gate 4 8 ~ . The f irst input to the NAND
gate 488 is provlded by the output of a two input NAND
gate 490 whose inputs are the Pl and PARCNT<l> signal~
This NAND gate i5 used to transfer from state Pl to state P2. The second input to NAND gate 488 is provided by the output of a three input NAND gate 492 whose inputs are the P2 signal, P~NT2 ~ignal and the PXB* signal. This NAND gate term is used to ke~p the state machine pointing to th~ P2 buffer for write to transfer buffer RAM 40 operations. The D input to the P3 flip-flop 476 is connected to the output of a two input NAND gate 494. One input to the NAND gate 494 is provided by the output of a two input NAND gat~ 496 whose inputs are the P2 signal and the PCNT3 signal.
The s~cond input to the NAND gate 494 is provided by the output of a three input NAND gate 498 whose inputs are the P3 signal, the PCNT3 signal and the PXB*
signal. Thus the ~tate machine successively coun s through the number of buffers enabled and repeats the last buffer enable befor~ recycling to the first buff~r.
The PXB* signal is produced by the inverting output of the PX ~lip-flop ~78, the noninverting output of which is the PX signal. The D input of the flip-flop 478 i~ connected to the output of a three input NAND gate 500. One input to the NAND gate 500 is - .

.

2~97762 ~onnected to the output of A two input N~ND gate 5~2 whose input6 are connected to PXB* signal and the PCNT0 signal. The second input to the NAND gate 500 is connected to a three input AND gate 504 whose inputs ~re the outputs o~ the N~ND gates 486, 492 and 498.
The third input to the NAND gate ~00 is provlded by the output of a two input OR gate 506. One input to the OR
gate 506 is a PARDIR signal 80 that if data i~ to be written to the trAnsfer buff~r RAM 46 the output is high. The 6econd input to the OR g2te 506 is provided by the output of a three input NOR gate 508. One input to the NOR gate 508 is provided by the output o~ a two input AND gate 510. The inputs to the AND gate 510 are the P2 and P~NT3 cignals. The second input to the NOR
gate 508 is provided by the output of a two input AND
gate S12. The inputs to the AND gate 512 are the Pl and PCNT2 signals. The third input to the NOR gate 502 is the output of a two input ~ND gate 514, whose inputs are P0 and PCNTl ~ignal. Thus the PX signal goes high when it is time to use the final buffer a second time for the write to transfer buffer RAM 46 operation.
The output of the three input NOR gate 508 is al~o connected to one input of a two input NOR gate 516.
The second input to the NOR gate 516 is connected to the PARDIRB* signal, the inverted PARDIR signal. The output of the NOR gate 516 is provided to the D input of a D-type flip-flop 518 whose noninverted output is the PL ~ignal, whose inverted output is the PL* ~ignal and which is clocked by the DACKCLK signal. The inverted clear input of the flip-flop 518 i5 connected to the SRST* signal. The SP0 and SPl signals used to control the address multiplexer 416 are produced by two D-type flip-flops 520 and 522. The clocking inputs to both flip-flops 520 and 522 receive the DAC~CLK signal while the inverted clear inputs receive the SRST*
signal. The D input to the SP0 flip-flop 5~0 receives the output of a two input OR gate 524 which has its inputs connected to the outputs of the NAND gates 482 , , , , .,; :
: , , . ., . ~ .

- 2~7767 ~nd 494. The D input to the flip-flop 522 i~ connected to the output of ~ two input OR gate 526 whose inputs are connected to the output~ of the two input NAND
gates 488 ~nd 494.
. 5 Figures 22, 23, 24 and 25 illustrate th~ manner in which the disk DMA channels 84, 86, 88 and the parity cha~nel 90 can be utilized in transferring data between the transfer buffer ~AM 46 and the disk drive array A
or parity data back to the trans~er buffer RAM 46. The various transfers are developed by having the l~cal processor 30 appropriately program the transfer controller 44, particularly the,parity channel or XOR
channel 90, to perform the operations. The timing of the parity channel 90 is such that parity operations from the buffer RAM occur at a very hiqh rate, ultimately in ~uccessive cycles of the CLK signal if no other requestor or requesting access to the transfer buffer RAM 46. The RAM parity operations are done at high speed in a very short period of time without the need for the local processor 30 to perform operations other than simply setting up the parity channel 90 for operation and enabling its operation. This dramatically increases the speed of the parity operation used in the disk array controller D
according to the present invention.
Figure 16 illustrates in more detail the various blocks used in developing the disk controller 72. A
disk clock blocX 550 receives the CLK signal and produc~s two clock signals, the CHCLK signal which advances the DMA channel having rights to access the disk array A and the CMDCLK signal which supplies the proper strobe pulse timing for use over the disk addres~ and control bus DAC. The CHCLK signal is supplied to the disk ~tate machine 552 which, with input~ of the local ~icroprocessor request ignal UREQ
and the parity channel request signal D3REQ, cycles through the various disk channel requesters to ., , : . .; ~:, ~

2~977~2 determine which requester hAs ~ccess to the disk array A. The disk controller 72 also includes ~ regi~ter 554 for receiving data from the local processor data bus UDI for m~sking of~ interrupts received from the variou~ di6k drives in the driVQ array A. This interr~pt block 554 receive~ th~ various interrupts and combines them with ~he ~asking signals to produce an interrupt signal referred to as DRPLINT, which combined is with the various interrupts produced by the disk channels 84, 86, 88 and 90 to form interrupt request ~ignal presented to the loc~l processor 30.
A register 556 is provided for the local processor 30 to communicate directly with the disk drive array so that command information and status information can be provided to and received from the particular disk.
This register 556 includes the appropriate registers and latches to select a particular disk and provide a particular register address to the ~elected disk. This register block 556 contains the direction information of the transfer, that is, whether data is to be written to the disk drive or read from the disX drive as indicated by the UDDIR signal.
A register 558 is provided to store direction value and appropriate disk drive requested for each disk channel 84-90. Additionally, a register 560 is provided for maskinq the interrupts provided by the disk channels 84-90 having an output of the DMASK<30>
signals, which are provided to the appropriat~ disk channel to mask off interrupts from that channel.
Additionally, this register 560 contains the SETCRY
register bit for the developing of that signal. A disk register address multiplexer 562 i5 provided to address the data register, which has an a~dress of 0, during disk channel operations and to allow the register indic~ted in the direct register to be access~d under local processor 30 control. A data multiplexer 554 i5 provided to ~ultiplex the data signals from the various dis~ channels 84-90 and the local pro~essor channel 82 .
:' ~, .. . ...

.

2~97~

to ~he di~k ~rray data bus DD. ~he multiplexer 564 is driven by the signal~ provided by the state ~achine 552 to select the appropriate input. A multiplexer 566 is provided, ~nd will be described in more detail, for selecting the devlce select, command ~trobe, acknowledgement 6ignal and other 6ignal6 u~ed in communicating with the diek array A. A disk interrupt multiplexer 568 i6 provided so that based on input received from the disk channel device register 558, the interrupts received from the disks can be routed to the appropriate disk channel 84-90 for receipt and for triggering operation of the transfer operations.
The clock circuitry 550 is shown in detail in Fig. 18. The CLX signal is used to clock a series of 15 D-type flip-flops 580, 582, 584, 586 and 588. The CLK
signal is also provided to an inverter 590 whose output is connected to the clocking input of a D-type flip-flop 592. The RSTI* signal is provided through two inverters 594 and 596 to the inverted clear inputs of 20 the flip-flops 580-588 and 592. The D input to the flip-flop 580 is provided by the output of a two input AND gate 598. Qn~ input of the AND gate 598 is provided by the inverted output of the flip-flop 584 while the other input to the AND gate 598 is provided by the output of an inverter 600, whose input is connected to the inverted output of the flip-~lop 586.
The noninverted output of the flip-flop 580 is provided as one input to a 2 input ~ND ~ate 602 whose second input is the output of the inverter 600. The output of the AND gate 602 i~ provided to thP D input of a the flip-flop 582, whose noninverted output is connected to the one input of a 2 input A~D gate 604. The second input of the AND gate 604 is provided by the connected to the inverter 600. ~he output of the AND gate 604 is connected to the D input of the flip~flop 5g4. ThP
noninverted DUtpUt of the flip-flop 584 i~ connected to one input of a 2 input NAND gate 606. The other input of the NAND gate 606 is connected to the output of the :

2a~7~62 inverter 600. The output of the NAND gate 606 is provided to the D input of the flip-flop 586. The noninv~rted output of the flip-flop 586 i~ the CHCLK
signal.
The output of the inverter 600 i6 also provided to ` the D input of the ~lip-flop 588. The noninverted output of tho flip-flop 588 i8 provided as one input to a 2 input AND gate 608, the other input of which recei~es the OlltpUt ~f the inverter 600. The output sf the AND gate 6Q~ is provided to the D input of the flip-flop ~92. The output of the flip-flop 592 is the CMDCL~ ignal. The various wave forms of the CLK, CHCLK and CMDCLK signals are ~hown in Fig. 7. Thus it can be 6een that the CHCLK signal divides the CLK
signal by 5, in the preferred embodiment to approximately a 4 ~Hz signal7 The ~MDCLK ~ignal has a rising edge 1 1/2 CLK signal cycles after the rising edge of the CHCLK signal and a falling edge 1/2 CLK
signal cycle before the next rising edge of the CHCLK
signal. In this way the CMDCLK signal is used to ga~e command strobes to the disk drive~ and insure that the command ~ignal is present sufficiently after a settling ^~
time and is removed prior to the next requestor being given control of t~e disk channel.
The disk controller state machine 552 is ~hown in detail in Fig~ 17. The state maohine 552 controls which of the disk channels 84-90 or local processor 30 has access to the disk array A. In general, the di~X
channel 0-3 or 84, 86 and 8B ~re rotated so that a different channel has access every 250 nsec in the preferred embodiment. This is because th~ cycle time of the particular disk drive is 750 nsec and thus by providing this rotatiDn the drives can be accessed in an interleaved fashion without over ~tepping the response times or turnaround times of a single drive.
~f the parity channel 90 i~ alsG transferring information then a four way rotation is used. If the local processor 30 desires to transfer information with , . . ~ - ; .
" ~ ,' ' :

2~977G2 one of the di~k drives in the ~rray A, then the local processor 30 has priority and is inserted into the next available ~lot in ~he rotation and the rotation of ~he disk DMA channels 84-90 i6 delayed one ~lot. A ~eries of four paired flip-flops 610 ~nd 612, 614 and 616, 618 and 620 and 622 and 624 are used to determin~ the present and previous disk DMA channel 84-90 having access to the di~k ~rray A. A 6ingle flip-flop 626 is used to indicate that the local processor 30 is requ~sting access to th~ ~rray A. The flip-flops 610-fi26 are all cloc~ed by the CHCLX ~ignal.
The ~REQ ~ignal is connected to an in~erter 628 whose output is ~he UREQI* ~ignal. Additionally, the UREQ signal i~ pr~vided as one input to a 2 input AND
gate 630 whose output is connect~d to the D input of the flip-flop 626. The inverted output o~ the flip-flop 626 is connected to the ~econd input of the AND
gate 630 60 that the local processor 30 can only obtain 1 access to th~ disk array A in succession. The noninverting output of the flip-~lop 626 is the UDISK
signal, while the inverted output is also connected to the input of an inverter 632 whose output is the UDISKI
signal. Various combinatorial logic is provided to the D inputs of the flip flops 610, 614, 61~ and 622 to advance the state machine to the appropriate DM~
channel. The logic equations are as follows:
D_DDMAO = DDMA3 UREDI* DDMAOI*
+ UREQI* DDMA2I DDMAOI* D3REQI*
+ UDISKI ~ WDDMA3 + UDISKI WDDMA2 o D3REQI*
+ UREQI* START

D DDMAl = DDMAOI ~ UREQI* DDMAlI*
+ UDISKI WDDMAO
D_DDMA2 - DDMAlI o UREQI* DDMA2I*
+ UDISKI WDDMAl .. . . , -: ~
. - .:
... .

2097~ fi2 -~2-D DDMA3 = DDMA2I o UREQI* DDMA3I* D3REQ
~ UDISXl D3REQ WDDMA2 The first ter~ in the input equation for the flip-flop 610, the D DDMAO equation, i5 u6ed in a normal rotation from the parity channel 90 to the disk channel 84. The second ter~ is used to rotate from the third disk channel 88 to the ~irst di~k channel 84 if the parity channel 90 i6 not requesting a transfer. Both of these two terms are ~ependent upon the local processor 30 not reguesting transfer. The third and fourth terms o~ the equation are ~ed t~ rotate if the local processor 30 was the last user of the disk array A. The final term is used upon system reset to start the rotation.
15The equations for the second and third DMA
channels, the D DDMAl and D DDMA2 equations, are less ~-complex in that the ~irst term relates to the rotation from the previous channel if the local processor 30 is not requesting the channel and the second term is used if the lo~al processor 30 was the last user of the channel. The final equation is used for passing control to the parity channel 90 and is the D DDMA3 equation. There are two additional qualifiers in each term and indicate that the parity channel 90 must actually be requesting a tr~nsfer otherwise it i5 not included in the rotation.
An exemplary transfer ln flip-flop 610 and 612 pair will be illustrated and described, with the signal transfers for the ~ther three channels being identical.
The output of the ~lip-flop ~10 is the DDMAO channel indicatinq that disk channel 84 is t~e channel having control ~f the disk array A. The inverting output of the flip-flop 610 is provided an inverter 632 whose output i5 the DDMAOI signal~ The inverting output of the flip-flop 610 is also connected ~o the inverting input of the flip-flop 612. The inverting output of the flip-flop 612 is the ~DDMAO* signal while the noninverted output is the WDDMAO signal. Thus it can , .
. .

2~97~2 be 6een that there is a one channel slot delay between the ~lip-flops 610 and 612, so that the previous state is stored and a rotation can properly continue when the local processor 30 has interrupted the rotation. The RSTI~ ~ignal is provided to the clear input of the flip-flop 610 ~nd the set input of the flip-flop 612.
The START ~ignal i5 provided as the output of a input NOR gate 634. One input of the NOR gate 634 is provided by the output of a 4 input NAND gate 636. The DDMAOI~, DDMAlI*, DDMA2I~, and DDMA3I* ~ignals are the input6 to the NAND gate 636. The second input to the NOR gate 634 is provided by the output of a four input NAND gate 638. The four inputs to the NAND gate 638 are the WDD~AO*, WDD~l*, WDDMA2* and WDDMA3* signals.
Thus the start ~ignal i~ active only when the system has just been reset.
The multiplexer 566 is shown in detail in Fig. 15.
The five disk requestor acknowledge signals are developed by the outputs of five AND gates 650, 652, 20 654, 656 and 658. One input to each of the ~ND gates 650-65R iS provided by the output of an inverter 660, whose input is connected to the output of a previous inverter 662, whose input is connected to the CMDCLK
signal. The ~econd input to the AND gate 650, whose output i~ the DDOACK ignal for DMA/disk channel O or 84, is connected to the output of a 2 input AND gate 664. The output of the AND gate 664 is the DDGNT<O>
signal and the inputs are the DDMAO and DOREQ signals.
Thus when the state machine i~ in a state such that disk chan~el 84 i6 accessed and it is requesting data, then a grant signal is indicated and an acknowledgement is prepared.
The input to the AND gate 652, whose output is the DDlACK 6ignal is provided hy the output of a ~ input AND gate 666 whose output is the DDGNT~1> signal and whose inputs are the DDM~l and DlREQ ~ignals. A two input AND gate 668 has inputs of the DDMA2 and D2REQ
signals and has an output siqnal which is referred to . , ~ ., ,:

24~4~7~2 as the DDGNT<2~ signal and i8 connected to the ~econd input of the ~ND gate 654 which produces the DD2ACX
~ignal. A two input AND gate 670 has input ~ignals of the DDMA3 and D3REQ ~ignals, an~ an output of the DDGNT<3~ signal, which i6 connected to the Recond input of the AND gate 656, whose output i6 referred to as the DD3ACK signal. A tWQ input AND gate 672 has inputs of the UDISK and UREQ 6ignals to indica~e that the local prOCeSBOr 30 i8 r~questing acce~s and has received a slot. The output of the AND gate 672 is the UDGNT
signal and is connected to the 6econd input of the AND
gate 658, whose output is referred to as the UDDACK
signal to indiGate that the local proceesor disk acknowledge has been granted.
Two signals DIOR* and DIOW*, the read and write strobes to the disk drives, and a signal referred to as DEN*, the enable signal for the disk drives are produced using the CMDCL~ ~ignal. The DIOR* signal is produced as the output of a 2 input NAND gate 674. One input to the NAND gate 674 is the CMDChK signal and the other input is the output of a 5 to 1 multiplexer 676.
The inputs to the multiplexer 676 are the direction signals ~or the various disk channPls and local process~r disk re~uest channel, with the selection being based on which channel is granted access. The output of the multiplexer 676 is also provided as one input to a 2 input OR gate 678. The second input to the OR gate 678 is provided by thP output o~ a second ~ultiplexer 680 which has inputs of the inverses of the direction signals of ~he ~ive particular disk requestors, with the multiplexer ~election being based on the ~rant signals. The output of the multiplexer 680 is ~lso provide~ ~s one input to a 2 input NAND
gate 682. The other input to the NAND gate 682 is provided by the CMDCLK signal. The output o~ the NAND
gate 682 i5 the ~IOW* signal. The CMDCLK ~ignal is provided as one input to a 2 input NAND yate 684 whose . :
. ~ ` ' .

2a~762 other input reoeives the output of the OR gate 678.
The output of the NAND gate 6~4 is the DEN~ signal.
Three 5 to 1 ~ultiplexer6 686, 688 and 690 are used to multiplex the deaired Bevice code for the particular disk channel requester. The fiva grant signal6 are provided as the select inputs to the multiplexers 686-690, with the three bit of the device codes as the data inputs. The outputs, the CS~2..0>
6ignals, are ~upplied t~ three to eight decoders (not ~hown) which provide a low true signal to allow acceæsing of the proper disk drive which ~as been selected by the particular channel during its phase.
The local proc2ssor RAM DMA channel 80 is partially shown in Fig. 20. The RAM address for the data for which the local proce~sor 30 i5 requestin~ a trans~er is stored in a 16 bit up counter 700. The 16 bits of the local processor data line UDI<15..0> are provided to the D inputs of the counter 700, with the inverted load input being conn~cted to the output of a 2 input OR gate 702. One input to the OR yate 702 is the RBUSY signal. The ~ec~nd input is the LRA* signal which is provided based on the address decode and timing signals in the local pr~cessor control bus UC.
The inverted reset input of the counter 700 is provided by the output of a inverter 70~ whose inpuk is connected to the RST signal. The count input o~ the counter 700 is connected to the output of a Dtype flip-flop 706. The input oP the D-type ~lip-flop 706 is connected to bit zero o~ the internal ver6ion of the local processor data bus UDI<0>. The clocking input to the flip-~lop 706 is provided by the output of a 2 input OR gate 708. One input to the OR gate 708 is the RBUSY signal, while the other input is the LRCTR*
~ignal. The LRCTR* ~ignal is active low when the local processor 30 is accessing the direct to RAM contr~l register. Thus the counter 700 can be set to repeatedly access the same address or can increment to provide a full transfer of information.
-:,: ,:, . . .

', - ' : ~ , 77g2 A D-type flip~flop 710 bas ~ts D input connected to the UDI<1> ~ignal ~nd its clock input connected to the output of the OR gate 708. ~he noninverted output of the flip-flop 710 is the URDIR signal, which is the direction 6ignal for the transfer with the local processor 30. The ~nvertecl output of the flip-flop 710 is provided ~s one input to ~ 2 input NAND gate 712.
The second input to ~he NAND ga e 712 i5 the UPDAC~
6ignal, which i6 nl~o provided to the input of an inverter 714. The output of the inverter 714 is connected to the clocking input of the counter 700 so that the counter 700 is clocked each time tbe local -processor 30 receives a 610t to access the transfer buffer memory 46. The output of the NAND gate 712 is buffered and provided to the clocking input of a 16 bit flip-flop 716. The flip-flop 716 is used to receive data from the transfer buffer RAM 46 and provide it to the local processor 30. To this end the ~ inputs of the flip-flop 716 are connected to the transfer buffer RAM data bus RDI<15..0> and the outputs o~ the flip-flop 716 are connected to a multiplexer which provides data to the local data bu~ LD. The multiplexer is used to pro~ide data to the local processor 30 because the local processor 30 can, in addition to receiving data through this from the transfer buffer RA~ 46 or the disk array A, also read the r2gisters contai~ed in the transfer controller ~4. As a result, a great number of data signals must be multiplexed to the local processor 30.
Data to be present2d to the transfer buffer RAM 46 frDm the lvcal processor 30 is stored in a 16 bit flip-flop 718. The clocking signal for the flip-~lop 718 is the L~DATA* signal, which is an address decode based on the local processor 30 accessing this register. The D
inputs to the flip-~lop 718 ar~ connected to the 16 bits of the local processor data bus UDI, while the 16 bits of output ar~ connected to the multiplexer which provides data to the transfer buffer RAM 4~.

, -.. , ~ . :

~776~

The LRA* signal i provided as one input to a 2 input OR gate 7200 The other input tG the OR gate 720 is provided by the URDIR 6ignal. The output of ~he OR
gate 720 i~ provided as one input to a 3 input AND gate 722. The secQnd $nput of the AND gate 722 i~ provided by the output of a 2 input OR gate 724. The two inputs to the OR g~te 724 ~re the URDIR signal and the RRDATA*
signal, which indica~es that the local processor 30 i5 reading information provided from the transfer buffer RAM 46 and ~tored in the flip-flop 716. The third input to the AND gate 722 ~5 provided by the output of a 2 input OR gate 726. One input to the OR gate 726 is the LRDATA* signal, while the second input i~ supplied by the inverted output of the flip-~lop 710. When the local processor 30 writes an address, the LRA* signal is asserted and if the URDIR signal is configured for a read from the transfer buffer RAM 46, a pre-fetch request is generated.
The output of the AND gate 722 is connected to the clocking input of a D-type flip-flop 728. The D input of the flip-flop 728 is connected to a high signal level and the noninverted output is connected to one input of a 2 input AND gate 730. The ~econd input to t~e AND gate 730 is the XUPDRQ* signal. The inv~rted clear input of the flip-flvp 728 is provided by the output of a 2 input ~ND gate 732. One input to the AND
gate 732 is the XUPDRQ* signal, while the other input is the output of the inverter 704 which indicates a system reset. The output of the AND gate 730 is provided to the D input of a D-type flip-flop 734. The clocking input of the flip-flop 734 is provided by the output of a inverter 736 whose input is connected to the CLK signal. The noninverted output of th~ flip-flop 734 is connected to one input of a 2 input ~ND
gate 73~, the other input of which receives the XUPDRQ*
signal. The output of the AN~ ~ate 738 is connected to the D input of a D-type flip-flop 740 whose clocking input receive~ the CLK ~i~nal. The output of the flip-'' ' '; .' 2~77~2 flop 740 i~ the UPDRQ signal, while the inverted output i6 the XUPDRQ* signal. The UPDRQ signal indicates that the .ocal processor 30 ha~ a pending request.
The output of the AND gate 722 i5 also provided to the clocking input of a D-type flip-flop 742. ~he D
input of the flip-flop 742 ia connected to a high logic level while khe ~o~inverting output is the ~3USY 6ignal which i~ connected to one input of a 2 input AND gate 744~ The 6econd input of ~he ~ND gate 744 i6 the RWAITEN ~ignal which indicates that this is one of the locations for which local processor 30 should be held if the operation is not ready for the actual operation of the local processor 30. The output of the AND gate 744 is provided to the D input of a latch 746. The gating input of the latch 746 is provided by the output of a 4 input AND gate 748. The four inputs to the AND
gate 748 are the LRCTR* signal, the LRA* signal, the output of the OR gate 724 and the output of the OR gate 726. An inverted output of the latc~ 746 is the RWAIT*
signal which places the local processor 30 in a no~
ready or wait state.
The inverted clear input of the latch 74~ is provided by the output of a 2 input AND gate 750. The output of this AND gate 750 is also provided to the inverted clear input of the flip-flop 742. One input to the AND gate 750 is provided by the output of the inverter 704, while the other input is connected to the inverted output of a D-type flip-flop 752. The inverted clear input of the ~lip~flop 752 is c~nnected to the output o~ a 2 input AND gate 754. One input to the AND gate 754 is connected to the output of the inverter 704 while the other input is connected to the inverted output of a D- ype flip-flop 756. The clock input of the flip-flop 756 i connected to the output of an inverter 758 whose input is connected to the CLX
signal. The clocking input of flip-flop 752 is connected to the CLK signal. The D input of the flip-flop 756 i~ connected to the noninverted output of the .

2~7, ~i2 flip-flop 752, whose D input i~ connected to the noninverting output of ~ D-type flip-flop 760. The inverted clear input of the flip-flop 760 i~ connected to the output of the AND gate 750. The D input of the flip-flop 760 i6 connected to ~ high or lcgic level 1, while ~he clocking inpuk i6 connected to the output of an inverter 762, whose input i~ connected to the UPDACK
signal. The RWAIT* ~ignal thus ~oes active when data is not yet available from the transfer buffer RAM 46 when reading or the previously written data has not yet been written and ~hus to prevent a overriding of data~
Thus the local processor 30 has a direct access to the transfer buffer RAM 46.
The local processor disk channel 82 is shown generally in Fig. 21. The local processor 30 can pass information directly to a register in the particular disk drive selected in the disk array A. The actual register to be selected and the disk drive to be selected is stored in a register located in the di~k controller 72 as previously discussed. The UDDIR*
signal, which indicates the inverse of the direction of the transfer, is provided to one input to a 2 input OR
gate 760. The ~econd input to the OR gate 760 is the RDDATA* ~ignal, whi h indicates that a data read from the flip-flop 716 has been requestPd. The output of the OR gat~ 760 is the G RD* signal which is provided to one inp~t of a 2 input AND gate 762. The second input to the AND gate 762 is the G WR* signal. The G WR* signal i5 provided as the output of a 2 input OR
-30 gate 764. One input to the OR gate 764 is the UDDIR
signal, while the other signal is the LDDATA* ~ignal which indicates that data is being loaded into a flip-~lop 77~ for temporary ~torage before being be written to the di6k array A. The output of the AND gate 762 is provided to the clocking input of a D-type flip-~lop 766. The D input to the flip-flop 766 is conn~cted to a high level while the noninverted output i~ connected to the D input o~ ~ D-typ~ flip-flop 768~ The clocking - ~ : . , ~ : -:, - .

2~97762 input to the flip-flop 768 is the UDCLK signal which is provided as the output o~ a inverter 770 whose input is the CLK signal. ~he inverted clear inputs of the flip-flop 766 and 768 are provided by the ~utput of a 2 input NOR gate 772. One input to the NOR gate 772 is the RST signal while ~he other input i6 connected to the noninverting output of ~ D-type flip-Plop 774. The inverted clear input to the flip-flop 774 i~ connected to th~ ~5T~* ~ignal which i5 low when the system is being reset. The clocking ~ignal for the flip-flop 774 is the CLX ~ignal, while the D input i~ conn~cted to the output of a 2 input AND gate 776. One input to the AND gate 776 is the REQ PEND signal which indicates that a request is pending, while the other input i5 the REQ IN ~ignal which indicates that request has been received. The RE QIN signal is provided as the noninverting output of the flip-flop 7S8.
The 16 bit flip-flop 778 has as its input the 16 bits from the local process data bus UDI<15..0>. The clocking input to the flip-flop 778 is the G WR* signal while the outputs are provided to the multiplexer which multiplexes data to the disk array A. Thus this is a register to which the local prscessor 30 writes data which i8 to be transferred to the disk array A.
A 16 ~it flip-flop 7Z0 is used to receive the data from the disk array A over the disk data bus DD, specifically the DDI<15..0> lines and to provide infor~ation Prom the noninverting outputs to the multiplexer which provides data to the local processor 3Q. The clocking input to the flip-flop ~80 is connected to the output of a 2 input NAND gate 782.
The inputs to the NAND gate 782 are the ~DDACK signal and the UDDIR ~ignal. Thus when a read reguest i5 pending and the local processor 30 receives its Xlot the data is stored in the register ~84 pending reading by the local pr~sessor 30.
The ~E~ IN signal is provided to the J input of the J-R Plip-flop 78~. The clocking ~ignal for the .

2~97~g2 flip-fl~p is provided by the CLX 6ignal, while the K
input receives the CLR PD signal which i6 provided as the output of a 2 input AND gate 786. ~he inputs to the AND gate 786 are the UREQ signal, which indicates the local processor 30 request, and the noninverted output of A D-type flip-flop 788. The clocking signal for the flip-flop 788 is the CLK signal, while the D
input receives the UREQX* ~ignal. The noninverted output oP the ~lip-flop 784 i6 the R~Q PEND ~ignal which is provided to the input of the AND gate 776.
The inverted output of the flip-flop 784 is the REQ? END* ~ignal and is provided as one input of a 2 input AND gate 790. The second input is provided by the output of a 2 input OR gate 792 and is referred to as the PF PEND* ~ignal. The output of the ~ND gate 790 is provided to one input of a 2 input NOR gate 794.
The second input to the NOR gate 794 is the UREQ
~ignal. The output of the ~OR gate 794 is connected to the D input of a D-type flip-flop 796. The output of the inverter 770 is connected to the clocking input of the flip-flop 796, whose inverted clear input is connected to the RSTB* signal. Additionally, the inverted clear inputs of the flip-flops 784 and 7&6 are al60 connected to the RST~* signal. The noninverted output of the flip-flop 796 is provided to the J input of a J-K flip-flop 798. Th~ clocking input to the flip-~lop 798 is the CHCLK ~i~nal, so that requests are advanced based on a disk channel slot allocation. The K input to the flip-flop 798 i~ the UDGNT ~iqnal which indicates that ~cces~ has been granted to the local processor 30. The inverted clear input to the flip-flop 798 receives the RSTB* signal. The noninverted output of the flip-flop 798 i6 the UREQ ignal, while the inverted output is the REQX* signal.
The input~ to the 2 input OR gate 792 are the UDDI~* 6ignal and the inverted output of a J-K flip-flop 800. The inverted clear input to the flip-flop 800 receives the RSTB* signal, while the clocking input ~9~7~2 receives the CLX ~ignal. The ~ input to the flip-flop 800 iB connected to the output of a 2 input OR gate 802. One input to the OR gate 802 i~ the CLR PD
signal, which is the output of the AND gate 786. The cecond input to the OR gate 802 iB the output of a two input AND gate 804. One input to the AND gate 804 is the UDDIR* signal, while tl~e other input ~s connected to the noninverting output of the flip-flop 800, which is re~erred to as the SY LD signal. The J input to the flip-flop 800 receives the PF_IN ~ignal which is provided by the noninverting output of a D-type flip~
flop 806. The clocking ignal for the flip-flop 80~ is the UDCLK signal while the D input is connected to the noninverted output of a D type flip-flop 808. The D
input of the flip-flop 808 is connected to ~ logic levPl high signal while the clocking input is connected to the LDDACTR* signal which is an indication that the processor has loaded a device ~ddress into the register in the disk controller 72. The inverted clear inputs 20 of the flip-flops 806 and 808 are provided by the output of a 2 input NOR gate 810. One input of the NOR
gate 810 receives the RST signal while the other input is conn~cted to the output of a D-type flip-flop 812.
The inverted clear input to flip-flop 812 receives the RSTB* signal, while the clocking input is connected to the CLK ~ignal. The D input of the flip-flop 812 is connected to the output of a 2 input AND ~ate 814. The inputs to the AND gate 814 are the PF IN signal and the SY LD ~ignal.
A wait signal is al~o produced by the l~cal processor ~isk channel 82 60 that ~hould the local processor 30 try to acces~ the data ports 778 ~nd 780 before the data has obtained or before it is written to the disk array A, the proces~or 30 is held until the previ~us operation is completed so that valid data is ready or valid data i~ not over written. The DWAIT*
signal is produced at the inverting output of a latch 820~ The D input to the latch ~20 is connected to the :

2~3~7 7 ~2 output of a 2 inp~t ~ND gate 822. ~ne input to the AND
gate 822 is the D~AITEN signal which indicates ~hat the local processor 30 i~ trying to access one of the two data registexs 780 or 778. q'he second input to the AND
gate 822 is t~e DBUSY signal which is produced as the output of a three input NAND gate 824. The three inputs to the N~ND gate 824 ~re the UREQX* signal, the PF? END* signal, and the REQ PEN~* signal. The gating input of the latch 820 is connected to the output of a three input AND gate 826. The three inputs to the AND
gate 826 are the G RD* signal, the LDDACTR* signal and the G WR* signal. Therefore the output of the latch 820 is active whenever an access is made to one of the registers associatad with the di~k channel 82.
The inverted clear input to the latch 820 is provided by the inverted output of a D-type flip~flop 828. The inverted clear input to the flip-flop 828 is connected to the RSTB* signal, while the clocking input receives the CLK signal. The D input of the flip-flop 828 is connected to the noninv2rted output of a D-tvpe flip-flop #30. The D input of the flip-flop 830 is connected to a logic level high ~ignal with a clocking input provided by the output of an inverter ~32 whose input receives the UDDACX ~ignal. The inverted clear input of the flip-flop 830 is provided by the output of a 2 input AND gate 834~ One input to the ~ND gatç 834 is the RSTB* signal, with the other input connected to the inverting ~utput of the flip-flop 828, the signal being referred to as the CLR WAIT* signal. Thus the wait state cleared whenever the disk array and disk controller have accessed the particular data port of interest.
The detailed ~chematics of the BMIC ch~nnel 76 and the oompatibility port channel 78 have not been provided but based on the indicated and provided schematics and details relating to the particular bus master interfac~s ~imilar DMA controller channel and logic c~n be readily developed.

- - . . ~, .

~Q~47~62 Referring now to Figure 22, the buffer 73 is shown in ~ore detail. ~he buffer 73 includes tw~ ~ bit parity generator/checker transceivers 900 and 902. The direction inputs of the parity checkers 900 and 902 provided by the IRL or RE~D ~gnal on the DAC bus. One port of the transceivers 900 ~nd 902 receives the DD<0..15~ signal~ while the o~her port receives the DATA<0~.17> signals. The D.~TA bus i5 an internal data bus used to connect the po6ted write memory 71 to the DD bus. Preferably the posted write memory 71 is contained on a daughterboard or module which connects to the disk controller D, ~o that it i~ available as an option. Bit positions 16 and 17 of the DA~A ~us are the two particular parity bits utilized in conjunction with thi6 bus. The inverted parity error outputs of the transceivers 900 and g02 are referred to as the PERR<1> and PERR<0> signals, respectively, which are pulled up by reaistors 904 and 906. These signals then indicate, when low, that parity errors have developed during read operations over the DATA bus.
Figure 23 illustrates a six bit D-type flip-flop 908 utilized in the disk controller D to select which of the various disk channels the posted write memory 71 replaces. In the preferred emb~diment as shown in Figure 1 the transfer controller 44 provides 8 disk channels for data transfer. However, this presents a proble~ when ~ disk drives in an array A are actually utilized in addition to the posted wr~te memory 71, all of which are coupled to the disk chann~l. To resolve ~0 this problem, the posted write ~emory 71 is designed to replace, on a selective basis, one of the actual disk units in the array A, without requiring the knowledge of this replacement by the trans~er controllar ~4, so that then the local processor 30 need o~ly indicate to the transfer controller 44 to use a particular selected device on the disk channel, with the replacement actually being made on the DAC bus itself. In this manner the transfer controller 44 need not be '' :; ' ;

2~9776~
;55-redesigned. ~owever, if desired, it is of cour~e under~tood that a ninth channel could be readily added to the ~ransfer controller 44 to provide a ~pecific channel for the po~ted write memory 71.
The flip-flop 908 i~ connected to the LD<5.. 0>
signals to receive ~ix bits of data from the local processor 30. Th~ clock input to the flip-flop 908 is provided by the output of ~ two input OR gate 910, ~ne of who~e inputs iB the IOW* 6ignal and the other of which i6 the CACHECF* ~ignal. The IOW* ~ignal goes low to indicate input/output write operations of the local processor 30 and the CA~IECF* ~ignal goes low when the flip-flop 908 is addressed. Therefore, when both CACHECF~ and IOW* signals go low to indicate an access to the flip-flop 908, on the rising edge the data i6 latched in. The inverted clear input to the ~lip-flop 908 is connected to the RST* signal. The outputs of the flip-flop 908 are the CLRERR* ~ignal, which is used to clear parity error indications from the posted write memory 71; the CACHE FAILED signal, which is used to drive an LED present on the disk controller D to allow the local processor 30 to visually indicate a failure;
the CACHE EN signal, which indicates that the cache or posted write memory 71 6ystem is enabled; and three bits of a bus referred to as the CACHE ASGN or cache assigned bus which determines which of the particular 8 disk channels the posted write memory 71 is to replace.
Figure 24 illustrates three specific PAL devices used to form the PAL bl~ck 67 which changes the various control signals in the D~C bus as necessary to allow inclusion of the posted WTit~ memory 71 as an extra disk device. A first P~L 9~2 is used to interleave the interrupt signal received from the posted write memory 71, which indicates comple~ion of ~n operation, with t~e various interrupts coming from the disk array A.
To this ~nd the DINTc7..0> Gignals from the disk drives, a signal referred to as the CACHE_INT or posted write memory 71 interrupt ~ignal, the CACHE EN signal -: ~ , . . , . , ~

2~97762 and the CACHE ~SGN<2..0> 6ignal6 are provided to the PAL 912. The output6 of t~e PAL 912 ~re the DRINT*<7..0> signals which ~re provided to ~he transfer controller 44 to ~ndicate the actual interrupts for the desir~d or appropriate channel. The equations of the PAL 912 is as shown below:
DRINT~0~ e CACHE_ASGN<2~ o CACHE ASGN<l>* 3 CACHE ASGNcO~* ~ CACHE EN o CACHE INT*
+ CACHE EN~ DINT<O>*
~ CACHE EN o CACHE ASGN<O> DINT<O~*
+ CACHE EN c CACHE ASGN<l> DINT<O>*
CACHE EN ~ CACHE ASGN<2> ~ DINT<O>*
~ DINT<O>* CACHE INT*
DRINT<l> = CACHE ASGN<2>* CACHE ASGN<1~* o CACHE ASGN~O> ~ CACHE EN CACHE INT*
_ + CACHE EN* DINT<1>*
+ CACHE EN C~CHE ASGN<O~ * ~ DINT<1>*
~ CACHE EN o CACHE ASGN~1> DINT<l>*
+ CACHE EN o CACHE ASGN<2> ~ DINT~1~*
+ DINT<l>* CACHE INT*
DRINT<2> = CACHE ASGN<2>* CACHE ASGN<1> -CACHE ASGN<O>* CACHE EN ~ CACHE INT*
+ CACHE EN* o DINT<2>*
~ CACHE EN ~ CACHE ASGN<O> ~ DINT<2>*
+ CACHE EN ~ CACHE ASGNsl>* DINT<2>*
+ CACHE EN CACHE ASGN<2> ~ DINT<2>*
+ DINT<2>* ~ CACHE INT*
DRINT<3> = CACHE ASGN<2>* o CACHE ASGN<l> -CACHE ASGN<O~ CACHE EN ~ CACHE_INT*
+ CACHE EN* DINT~3>*
+ CACHE EM 9 CACHE ASGN<O>* ~ DINT<3>*
CACHE EN CACHE ASGN<l>* ~ DINT<3>*
+ CACHE EN CACHE ASGN<2> ~ DINT<3>~
+ DINT~3>* ~ CACHE INT*
DRINT<4> = CACHE ASGNc2> CACHE ASGN<1>* -CACHE_ASGN<O~* CACHE_EN CACHE_INT*
~ CACHE EN* DINT<4~*
+ CACHE_EN CACHE ASGN<O> ~ DINT<4>*

~:
.-.
:.: ' ,; ' '- ~ ~ .

2~97762 + CACHE_EN CACHE_ASGN<1> DINTc4>*
+ CACXE EN ~ CACHE ASGN<2>* DINT<4>*
+ DINT<4>* CACHE INT*
DRINT<5> = C~CHE ASGN<2> CACHE_ASGN<l>* o CACHE ASGN<0> o CACHE EN CACHE INT*
+ CACHE EN* DINT<5>*
CACHE_EN C~CHE ASGN<0>~ DINT<5>*
+ CACHE EN CACHE ASGN<1> DINT<5>*
~ CACHE EN CACHE ASGN<2>* DINT<5>*
+ DINT<5>* ~ CACHE INT*
DRINT<6> = CACHE ASGN<2> CACHE_ASGN<1> ~
CACHE ASGN<0>* CACHE EN CACHE_INT*
CACHE_EN* DINT~6>*
+ CACHE EN ~ CACHE ASGN<0> DINT<6>*
+ CACHE_EN ~ CACHE_ASGN<1>* o DINT<6>*
+ CACHE EN o CACHE ASGN<2>* ~ DINT<6>*
~ DINT~6>* CACHE INT*
DRINT<7> = CACHE ASGN<2> ~ CACXE ASGN<l> -CACHE_ASGN<0> CACHE_EN ~ CACHE_INT*
+ CACHE EN* DINT<7>*
+ CA~HE EN CACHE ASGN<0>* DINT<7>*
+ CACHE EN CACHE_ASGN<1>* DINT<7>*
+ CAC~E_EN ~ CACHE_ASGN~2~* DINT<7>*
~ DINT~7>* ~ CACHE INT*
2~ :
~ wo other PALs 9~4 and 916 are used to interleave the posted write ~emory 71 to the appropriate drive select signals, to develop the various olttput enable sig~als for the buffers 48, 50 and 73 and to develop the posted write memory read parity error signal. A
first PAL 914 receives the CACHE ASGN62..0~ signals;
the CACHE EN signal; the ENCS~ sig~al, which indicates that the device celect signals are active; the DA~3>
signal, which when high indicates a high order c~mmand type in the IDE prvtocol; the DEL signal which indicates that a data tran~fer over the DD bus is occurring; and the DSc2..0> or 3 bits of the drive select ~ignals ~rom the transfer co~troller d4~ The 2~7~'' PAL 914 then provides the DCSO*c7..~ signals or the top foux device ~ignal~ ~d the DBOEN*<2..0~ or output enable signal6 for the buffers 73, 50 and 48, respectively. The equations of the P~L 914 are shown b~low:
DCSOc7~ = DS<2> DS~ DS<0> o CACHE EN* ENCS
DA3~
DS~2> o DS<l> o DS<0> o CACHE EN -CACHE ASGN<2>* ENCS DA3*
+ DS<2> DS<l> DS<0> CACHE EN -CACHE ASGN<1>* ENCS DA3*
DS<2~ DS<l> DS<0> o CACHE EN -CACHE ASGN<0>* ENCS DA3*
DCS0<6> = DS<2> DS<1> DS<0>* CACHE EN* -ENCS o DA3*
+ DS<2> DScl> DS~0>* CACHE EN -CACHE ASGN<2>* ENCS DA3*
+ DS<2> DS<l> DS<0>* CACHE EN -CACHE ASGN<1>* ENCS DA3*
+ DS<2> DS<l> DS<0>* CACHE EN -CACHE ASGNcO> o ENCS DA3*
DCS0<5> = DS<2~ ~ DScl>* DS<0~ o CACHE EN* -ENCS ~ DA3*
I DS<2~ ~ DS<1>* o DS<0> ~ CACHE EN o CACHE ASGN<2>* o ENCS DA3*
-- DS<2> DS~l>* ~ DS<0> o CACHE EN -CACHE_ASGN<1> ENCS ~ DA3*
DS<2> DS<l>* ~ DS<0> CACHE EN -CACHE ASGN<0>* ENCS DA3*
30 DCS0<4> = DS<2> ~ DS<1>* ~ DS<0>* CACHE EN* -ENCS ~ DA3*
+ DS<2> DS<1>* ~ DS<0>* CACHE EN -CACHE ASGN<2>* ENCS DA3*
+ DSc2~ DS~l>* DS<0>* CAC~E EN o CACHE ASGN<l> ~ ENCS o DA3*
-DS<2> DS<l>* o DS<0~* ~ CACHE EN -CACHE_ASGNcO> ENCS DA3*

~, ,,, : :
, `~ 2~9~7~2 DBOEN<2> = DS~2>* DS<l>* DS<0> CACHE EN -CACHE ASGN<2>* CACHE ASGN<l>*
CACHE ASGN<0> DEL ~ ENCS
~ DS<2>* DS<l> DSC0>* Q CHE EN -CACHE ASGN<2>~ ~ CACHE ASGN<l> -CACHE ASGN<0>~ 9 DEL ^ ENCS
+ DS<2~ ~ DS<l> DS<0> ~ CACHE EN -CACHE ASCN<2>* Q CHE ASGN<l> -CACHE ASGN<0> DEL ~ ENCS
~ DS<2> DS<l>* DS<0~* CACHE EN -CACHE_ASGN<2~ ~ CACHE ASGN<l>* -CACHE ASGN<0~* DEL ENCS
DS<2> DS<l>* ~ DS<0> CACHE EN -CACHE ASGN<2~ CACHE ASGN<l>~ -. CACHE ASGN~0> DEL ENCS
+ DS<2> ~ DS<l> DS<0~* CACHE EN
CACHE ASGNC2> CACHE ASGN<l>
CACHE ASGN<O>~ DEL ENCS
+ DS<2> DS<l> DS<O> CACHE EN -CACHE_ASGN<2> CACHE ASGN~l> -CACHE ASGN<0> DEL ENCS
DBOEN<l> = D5<2> ~ CAC~!E EN* DEL ENCS
+ DS<2> CACHE EN CACHE ASGN<2>* DEL
ENCS
~ DS<2> DS~l> CACHE EN ~
CACHE ASGN<l>* DEL ENCS
+ DS<2> ~ DS<0> C CACHE EN -CACHE ASGNC0>* DEL ~ ENCS
~ DS<2> DS<l~* CACHE EN
CACHE_ASGNCl> DEL ENCS
+ DS<2> DS<0>* ~ CACHE_EN -CACHE ASGN<0> DE~ ENCS
DBOEN<0> = DS<2>* CACXE_EN* ~ DEL ~ ENCS
+ DS<2~* ~ CACHE EN ~ CACHE ASGN<2> DEL
-ENCS
DSc2>* ~ DSCl> CACHE_EN -CACHE ASGNcl>* DEL ENCS

2~977~j2 + DS~2~* DS<0> CACHE EN -Q CHE ASGNcO>* DEL ~ ENCS
DS~2>* DS<l>* ~ CACHE EN -CACHE ~SGN<l~ DEL ~ ENCS
~ DS<2>* DS<0>* CACHE EN
CACHE ASGNC0> DEL ENCS

The second PAL 916 al~;o receives the CACHE ASGN<2..0>~ DS<2..0>~ CACHE EN~ ENCS* and DA~3>
signals. From these 6ignals, the PAL 916 produces the DCS0*<3..0> signals and the CACHE CS* or cache ~elect signal. Further, the PAL 916 r~ceives the PERR~l..0>
signals and produces the TERR or read parity error signal which is provided to the local processor 30 interrupt inputs. The eguations the PAL 916 are shown below:
DCS0<3> = DS~2>~ DS~l> DScO> CACHE EN*
ENCS DA3*
+ DS<2>* DS<l> DS<0> CACHE EN -CACHE ASGN<2> ENCS DA3*
+ DS<2>~ 6 DS<l> DS<0> CACHE EN -CACHE ASGN<l>* ENCS ~ DA3*
+ DS<2>* ~ DS<l> DS<0> CACHE EN
CACHE ASGN<0>* ENCS DA3*
25 DCS0<2> ~ ~S<2~* DS<l> DS<0>* D CACHE EN* -ENCS DA3~
+ DS<2>* ~ DS<l> DS<0~* CACHE EN s CACHE ASGN<2~ ENCS DA3*
~ DS<2>* ~ DS<l~ ~ DS<0~* CACHE EN -CACHE A5GNcl>* ENCS ~ DA3*
+ DS<2>* DS<1> DS<0~* o CACHE EN
CACHE ASGN<0> ENCS DA3*
DCS0<1> = DSc2>* DS<l~* e DS<0> CACHE EN* -ENCS DA3*
~ DS~2>* DS<l>* DS~0> CACHE EN s CACHE ASGN<2~ ENCS ~ DA3*
DSC2~* ~ DS<l>* q DS<0> CACHE EN
CACHE ASGN<l> ENCS DA3*

2a~7~i2 + DS<2>* o DS<l>~ ~ DS<0> CACHE EN -CACHE ASGN<0>* o ENCS o DA3~
DCSO<O>= DS<2~* D5cl>~ ~ DSCO~ CACHE EN* -ENCS DA3 *
+ DS~2>~ DS<l>~ ~ I)SCO>~ CACHE EN .
CACHE A5GN~2~ o ENCS DA3*
+ DSc2>* DS<1>* o DS<0>* Q CHE EN -CACHE ASGN<l> o ENCS DA3~
+ DS~2>* D DS~l>* o DS<0>~ C~CHE EN o CA~HE ASGN<0> o ENCS DA3*
CACHE CS = DS<2>* D5<1>* ~ DS<0> CACHE EN -CACHE ASGN<2>* CACHE ASGN<l>* -CACHE ASGN<0> ENCS DA3*
-t DS~2>* DS~l> DS~O>~ CACHE EN
CACHE ASGN~2>* CACHE ASGN~l>
C~CHE ASGN<0>* ENCS DA3*
DS~2>* DS<l> DS<0> CACHE EN -CACHE ASGN<2>* CACHE ASGN<1> -CACHE ASGN<0> o ENCS DA3*
~ DS<2> ~ DS<l>* DS~0>* o CACHE EN -CACHE ASGN<2~ CACHE_ASGN~l>* -CACHE ASGN~0>* ENCS ~ DA3*
+ DS~2~ DS<l>* o DS<0> CACHE EN -CACHE ASGN<2> CACHE_ASGN<l>* -CACHE ASGN<0> o ENC5 ~ DA3*
+ DSc2~ ~ DS<l> DS<0~* CACHE EN -CACHE ASGN<2> CACHE ASGN<l> -CACHE ASGNcO>* ~ ENCS g DA3*
+ DS<2> DS<l> DS<0> o CACHE EN -CACHE ASGN<2> CACHE ASGN<l>
CACHE ASGN<0> ~ ENCS DA3*
TERR = PERR<1>* PERR<0>*

Therefor2, reYi2wing the PAL equations, it can be se~n how the l~cal processor 30 properly 6ets the posted write memory assigned disk channel ~o that it replaces that particular disk drive in the array A for both the interrupts and the ~elect signals.

2~776~
-62~

Referring now to Figure 25, a block diagram of the posted write ~emory 71 i6 ~hown. A cycle control block 920 receives the various 6ignalfi from the buffer 75 which are provided ~rom th2 DAC bus. ~hese are the 6ignal~ sufficient to determine if particular cycles, such as the data or command read/write cycles, are occurring and to return the. various error, interrupt and other signal6. The cycle control 920 provides outputs to an address counter 922, various control latches 924, a parity generator/detector transceiver 926 and to data latches 928. The addxess counter 922 is provided to allow latching and autoincrementing capabilities to allow DMA Qperations with the transfer controller 44 to occur easily. The control latches 924 are provided to allow the local processor 30 to set various states and conditions of the posted write memory 71. The parity generator/detector transceiver 926 is used to provide the parity detection ~or write operations and to develop an internal dat~ bus in the 0 posted write memory 71 referred to as the INTDATA bus.
The devices address counter 922, control latches 924, and the parity generator/detector transceiver 926 are connected to the INTDATA bus. The outputs of ~he address counter 922 and of the control latche~ 924 are provided to an address multiplexer and control block 930. The address multiplexer and control block 930 also receives outputs from the cycle control 920. The address multiplexer and control block ~30 provides the output enable (OE*), write ~nable (WE*), row address select (RAS3 ~nd column address select (CAS) signals to a dynamic randsm access memory ~DRAM~ array 932 and provides the memory addresses to the DRAM array 932 over an MA bus. The data latches 928 provide the data to and from the DRAM array 932. The DRAM array 932 preferably is comprised of a mirr3red bank of dynamic random acces~ semiconductor memories which also include sufficient capacity for parity checking. More details on the DRAM array 932 will be provided below.

;, , , , :" : : " -~ " :, : ;
, - ~ :~:: . . .
. :

2~7~
63~

A power control block 934 i6 connected to a ~eries of batteries ~36 to provide battery power and determines w~ether the batteries 936 or the power provided by the computer 6ystem i8 provided to the DRAM
array 932.
Portions o~ ~he cycle control 920 are shown in Figuxes 26 and 27. Referring first to Figure 26, a PAL
940 receives the IR~* ~ignal, which indicates a read operation on the disk channel; the IWL* signal, which indicates a write operation on the disk channel; the CACHECS* 6ignal, whic~ indicates that an operation to the posted write memory 71 i~ being performed; and the DA<2..0> 6ignals or device addresses to address the particular regist~r~ being simulated in the posted 15 write memory 71. The PAL 940 provides 8 output signals corresponding to read/write pulses to the four addresses associat~d with the posted write memory 71.
For example, address 0 is the data port, while address 1 provides the lower 16 bits of the address to the 20 address counter 922, address 2 provides the upper 8 bits of the address for the address counter 9~2 and miscellaneous control bits in an 8 ~it latch, and address 3 is used to place the backup batteries 936 in standby.
The ADDROWR* signal is provided to the clock input of a D type flip-flop 942. The D and inverted pre~et inputs are connected to ~ logic high level and the non-inverted output provides the P~RITE signal. The inverted clear input is connected to the ~R_RST*
signal. The ADD~ORD* signal is provided as the clock input to a D-type flip-flop g44, whose D and inverted preset inputs are connected to a logic high level and whose inverted clear input is connected to the RD ST*
signal. The inverted output of the flip-~lop 944 is the PRD* ignal and i provided as one inpu~ to a 2 input NAND gate 946. The ~DDR2WR* signal is provided to the clock input of a D-type flip-flop 948, whose D
and inverted preset inputs are connected to a logic : : .
,~

~.977G2 high level and whose inverted clear input i8 connected to the RD RST* signal. The inverted output of t~e ~lip-flop 948 i6 the PPRE~ ~ignal, which is provided as the second input to the NAND gate 946, whose output i6 the PREAD signal, which indicates that a read of the posted write RAM 71 has been posted.
~ signal referred to ~F RCO* is provided to the clocking input of a D-type ~lip-flop 950. The RCO*
~ignal is a refresh counter signal which appears or pul~es when it i6 appropriate ~or ~he dynamic memories in the DRAM array 932 to receive the next refresh cycle. The D and inverted preset inputs of the ~lip-flop 950 are connected to a logic high level and the inverted clear input is connected to the REF_RST*
signal. The no~ inverted output is the PREF signal, which indicates that a refresh is pending or needs to be performed.
Referring now to Figure 27, the PWRITE and PREAD
signals are provided as the two input~ to a 2 input O~
20 gate 952, whose output is provided to an inverter 954, whose output in turn is the CACHE INT signal which indicatec that an operation i5 being performed on the posted write memory 71 and which is provided to the PAL
912. The PWRITE signal is provided t~ one input of ~n 8 input D-type flip-flop 956. The clocking signal ~o the flip-flop 956 is provided by the CLX or local proces~or clock signal, while the inverted clear input receives the RST* signal. The output of the flip-flop 956 associated with the PWRITE signal input provides the WR1 signal, which is connected t~ a sPc~nd input of the flip-flop 956. The seco~d associated ~utput of the flip-flop 956 provides the WR2 signal. The WRl and WR2 signal~ are provided as the two inputs to a 2 input N~ND gate 958, whose output is the SPW* signal which provides a signal to indicate that ~ write reguest has been synchronized to the local clock.
The PREAD signal is provided as on~ input to the flip-flop 956, the associated output being the RD1 ~ :

2as7~g2 ~ignal and being connected to ~ 6econd input on the flip-flop 956. The associ~ted output of the ~econd input iB the RD2 ~ignal, with the RD2 and RDl signals being provided as the two input6 to a 2 input NAND gate 960, ~hose output ~s the SPR* signal. In this manner a slmilar signal i~ provided during read operations. The PREF signal is provided a8 one input to the flip-flop 956, the associated output being the REFl signal and being connected to a second input of the flip-flop 956.
The second associated output i8 the REF2 ~ignal, which along with the REFl cignal is provided as the two inputs to a 2 input NAND gate 962. The ou~put of the NAND gate 962 i~ the SPREF~ ~ignal.
A ~ignal re~erred to as POWER G40D~, which when active low indicates that the power being supplied to the disk controller D by the computer system is satisfactory, i6 provided as one input to the flip-flop 956. The associated output is the NOPWR1 signal, which is provided to the final input to the flip-flop 956.
The as~ociated output is the NOPWR2 signal and along with the NOPWR1 signal are provided as the two inputs to a 2 input NAND gate 954, whose output is the SPBADPWR* signal. These SPW*, 5PR*, SPREF* and SPBADPWR* signals are used to provide synchronized signals for the particular opPrations in a ~tate machine used to control the po6ted write ~emory 710 Five main signals are used to indi~ate the particular state of the cycles of the posted write memory 71~ The five signals are ref~rred to as the S1, S2, S3, S4 and S5 ~ignals and are provided as ~ive of the outputs of an 8 bit D type ~lip-flop 966. The Sl signal output is related to an input which receive~
SRST* or state machine reset ~ignal. ~he ~2 output is provided from an input which reoeives ~ signal which is the output of a 2 input AND gate 9~8, whose inputs are SRST* and S1 signals. The S3 signal is provided at an output whose input receives the output of a 2 input AND
gate 970, whose inputs are the S2 ~ignal and the SRST*

. . : : , :

2~3~2 ~66-~ignal. The S4 ~ign~l i6 provided by an output whose associated input receiv~s ~he output of a two input AND
gate 972, who~e lnputs are the S3 ~ignal and SRST~
signal. The S5 ~ignal i6 provided by an output whose related input receives the S4 ~ignal. Thus in this manner once th~ ~tate machine has started it proceeds to count Sl, S2, S3, S4 ~nd S5 ~nd then to continuously cycle through that phase as long as the SRST~ ~ignal is not in an active l~w state.
The flip-flop 966 i~ used to produce two additional signals referred to as the DP1 and DP2 signals. The POWER GOOD signal is provided to one input of the ~lip-flop 966, whose associated output i5 provided in return to anot~er input of the flip-flop 966. This associated output is the DPl signal, which is again provided to an input of the flip-flop 966.
The associated output is the DP2 ~ignal. The DP1, DP2, Sl-S5, SPW*, SPR*, SPREF* and SPB~DPWR* signals are provided to a cycle generation P~L 974. The PAL 974 produces signals referred to as C~SI*, the basic CAS
signal for the DRAM array 932; the R~SI* signal, which is the basic RAS signal for the DRA~ array 932; the ASEL vr address ~elect signal used to select RAS or CAS
addresses; the REFRESH* signal to indicate that a re~resh operation is occurring, the READ* ~ignal, which indicates that a read operation i~ ~ccurring; the WRITE* signal which indicates that a write operation is occurring; the POWEROFE* ~ignal which indicates that read, write and refresh operations are completed, the power is not good and thos ~perations will be blocked until good power is returned; and the SRST* signal.
The equations for the PAL 974 are shown below.
RASI = S1 S4* R~AD
+ S1 9 S4* ~ WRITE
+ S1 ~ C~K* S4~ c REFRESH
RASI S4* REFRESH
~ S2 PWROFF
CASI = S3 ~ READ

. ~ i .

~ 2~977~2 S3 ~RITE
+ S1 S3~ REFRESH
+ SPREF SPW* 5PR* o Sl o READ~ -WRITE* ~ PWROFF~ RST*
+ S1 PWROFF
ASEL ~ READ S2 S4*
~ WRITE ~ S2 S4~
READ ~ SPR Sl ~ PWROFF~ WRITE~ REFRESH~ -RST~
+ READ S5* ~ RST*
WRITE - SPW ~ SPR* S1 PWROFF* READ* -REFRESH* RST*
+ WRITE S5* RST*
REFRESH = SPREF SPW~ ~ SPR~ S1 o READ* o WRIT~* o P~ROFF* RST*
~ REFRESH ~ S5* RST*
PWROFF = SPBADPWR SPREF* SPW* SPR* S1 o REFRESH* W~ITE* READ* RST*
~ PWROFF S5~ RST*
~ PWROFF DP1* ~ RST*
+ PWROFF DP2* o RST*
SRST = SPR* SPW* SPBADP~R* SPREF* -PWROFF*
~ REFRE5H S4 + PWROFF S4 DPl ~ DP2 + WRI~E o S4 ~EAD S4 ~ RST*

Therefore it can be seen that th~ state machine ~tays with the Sl-S5 signals in a low state ~fter reset and until one of the start æignals is received. At that time it cycles thr~ugh the five states and returns to the ~ero state until the next signal is received to initiate an operation.
A PAL 976 is used to provide the various reset pulses ~or the parti~ular cycle types, to control the counting of the address count~r 922, to control which . . ,~

2~77~

direction the data i~ going, to drive ~he output enable input of the parity qenerator~detector transceiver 926 ~nd to provide a DMA reque~t (DREQ) signal to indicate that data i5 Mvailable. The PAL 976 receives the REFRESH*, READ*, WRIT~* ~nd POWEROFF* signal6, the S3 and S4 signals, the ADDR0RD~ ~ignal, the RST~ signal, the DIR signal and the AUTO INC ~ignal to indicate that the ~ddress counter 922 is to auto increment. The PAL
976 provides the WR RST*, RD_RST* and REF RST* ~ignals, the READ DATA~ 6ignal, the DATA DIR signal, the DATA OE* signal and the INC ADDR signal. The equations for the PAL 976 are 6hown below.
WR RST = WRITE S3 S4* ~ TEST RST
RD_RST = READ S3 S4* + TEST_RST
REF RST - REFRESH S3 ~ S4* + PWROFF ~ TEST RST
READ DATA = READ ~ S4 DATA DIR = ~DDR0RD* DIR*
DATA OE = WRITE DIR ~ ADDR0RD DIR*
INC ADDR = AUTO_INC READ o DIR~
+ AUTO INC WRITE
Figure 27 provides details on the address counter 922, the control latches 924, the parity generator/detector 926 and the data latches ~28. The DATAc0..17> 6ignals are provided fro~ the buffer 73 to the B port of the parity gener~tor/detector 926 and to the A port of data latches 928. The direction signal for the data latches 9 8 is provided by the ADDR0RD*
signal, while the output en~ble signal is provided by the DATA OE* signal. The closking ~ignal for the A to B direction of the bi-direction~l latching transceiver 928 is provided by the output of a 2 input OR gate ~78.
one input of the OR gate 978 receives the IWI* signal which is an indication of ~ write operation. The second input to the OR gate 978 is provided by the CACHECS* 6ignal to indicats that operations directed to the posted write memory 71 are occurring. The clocking signal for the B to A direction of the latches 928 is provid~d by the READ DATA* sign~l. The B port of the : ~

2~977~, data latches 928 develop the RAM DATA<0..17> bus which is provided to the DRAM ~rray 932.
The parity generator/detector 926 has its two error outputs, one for each particular byte received at its ~ input, provided to the two inputs of ~ 2 input~
NAND gate 982. The output of ~he NAND gate 982 is the WR ERR cignal, which i~ provided to logic which generates an interrupt to the local processor 30 to allow prompt response to write parity errors. The parity gPnerator/detector 926 has its direction input connected to the output of a 2 input NAND gate 984 whose inputs receive the ADDRlRD* and ADDR2RD* ~ignals so that when command or address information is being received the data is transferred rom the DATA<0..17>
15 signals to the INTDATA~0.... 15> signals. The data is :-transferred to the DATA~0.. .17~ ~ignals during read operations.
The INTDATA<0.~15~ signals are provided to the address counter 922 and the control latches 924. The address counter 922 is developed using a 16 bit loadable counter 986 chained to a 8 bit loadable counter 988. The load signal for the counter 986 is connected to the ADD~lWR* signal, while the load signal for the 8 bit counter 988 is connected to the ADDR2WR*
signal. A signal referred to as the ~NC_ADDR signal developed by the PAL 976 is provided to the clocking input of the counter 986. The ripple carry ~utput of the counter 986 is provided to the clocking input of the count owner 98~ so that a 24 bit counter develops.
Thu~ each time a data read or write operation occurs and the autoincrement feature is enabled, the INC ADDR
signal pulses and the address counter 922 advances.
The count outputs of the counters 986 and 988 ~orm the CADDR<0..23> ~ignals or cache address bus.
As it may be desirable for the lo~al pr~cessor 30 to at times determine the address actually present in the counter 922, a 16 bit buffer 990 and 2n 8 bit buffer 992 are connected between the CADDR and INTDATA

", ' ~ -`

2~377~2 buses. The counter 990 has its output enable input connected to ~he ADDRlRD* signal, while the buffer 992 has its output en~ble ~ignal connect~d to t~e ADDR2RD*
6ignal. In addition, the two most significant bits of the buffer 9~2 are connected to ~ignals referred to as B12 ~nd ~34, which indicate the ~tatus of ~ome of the batteries 936 as will be described below. The outputs of the buffer 990 axe connected to the 16 bits of the INTDATA bus while t~e outputs of the buffer 992 are connected to the lower byte o~ the INTDATA bus.
Control latches 924 are developed by an 8 bit D-type ~lip-flop 994. The clocking input to the flip-flop 994 i~ provided by the ~DDR2WR* signal and the upper byte of the INTDATA bus is connected to the D
inputs. The most signiPican~- bit of the ~lip-flop 994 is the HIRROR ~ignal, 80 that the second hal~ or mirrored half of the DRAM array 932 can be ~orced to provide duplicate storage of data during write operations. ~he next most ~ignificant bit is the TEST
signal for testing functions. The next less significant bit is the AUTO INC bit, while bit positions 4 and 2 are unused and bit position 3 is the DIR signal. These ~ignals are also provided to six inputs of an 8 bit buffer 996. The two least signific~nt bits of the buffer g96 receive the B56 and B78 ~ignals, which are the remaining two battery indication ignals. The outputs of the buffer 996 are c~nnected to upper byte of the INTDATA bus. The ADDR2~D* signal is provided to the inverted output enable input of the buffer 996.
Figure 29 illustrates in more detail the address multiplexer and control circuitry 930 and the DRAM
arr~y 932. A 10 bit 2:1 ~ultiplexer 998 receives at its O inputB bits 0 9 of the C~DDR bus and as its 1 input bits 9-18 of the CADDR bus. ~he ASEL signal is connected to the select input and the output of the multiplexer 998 is the RAM ADDR<0..9> signals which are provided to the address inputs of the DR~M modules in , :, ,. :.:: :

2~Q77~2 the DRAM array 932 . A 3: d decoder 1000 receives at its three ~elect inputs bit~ 19, 20 ~nd 21 of the CADDR
bus, ~t its positive enable input the REFRESH~ signal and at its inverted enable input the READ* ~ignal. The 8 outputs of the decoder 1000 are the RAMOE*<0.. 7>
signals which are then active only during read operations and not during refresh operations or write operations.
The mirror bit i6 used to force write6 to the i0 mirror portion o~ the DRAM array 932 to ~llow enhanced data protection. A 3:8 decoder 1002 receives at its three select inputs bits 19-21 of the CADDR bus, at its positive enable input the ~EFRESH* signal and at its inverted enable input the WRITE* signal. The four least significant decoded outputs, that is, YO..Y3, produce the RAMW~*~0..3> ~ignals. A second 3:8 decoder 1004 receives at it~ two low select inputs the 19 and 20 bits of the CADDR signal and at its most ~ignificant select bit the output of a two input OR gate 1006~ The two inputs to the OR gate 1006 are the MIRRO~ signal and bit 21 of the CADDR bus. The enable input receives the ~EFRESH* signal, while the inverted enable input receives the WRITE* signal. For the decoder 1004 the four most significant outputs are utilized to develop the RAMWE*~4..7> signals~ By this arrangement, if the mirror bit is ~et by the local processor 30, data is automatically copied to both banks or halv~s of the DRAM array 932 during write operations, thus cimply allowing mirroring ~f the data.
The DRAM array 932 ~as two banks, 932A and 932B.
Bank 932B is considered as the mirror bank, while bank 932A is considered to be the original ~ank. The power for both banks is provided by a signal referred to as VOUT, whose generation is described below. Preferably 35 the DRAM array 932 is formed using 16 512K x g bit memory chips, preferably the Toshiba TC514900-~LL-100 devices which are self~refreshing. The nin~h bit allows parity information to be stored to allow - - ~

2~77~2 detection of many ~emory error~. Thus two of these chips are used to develop the 16 data and 2 parity bits Por each address valu~. The use of the 16 c~ips provides 8 ~bytes of total memory or 4 ~bytes of mirror~d memory. The ~emory devices of bank 932A
receive the RAS*~0~ and CAS~<0> signal~, while the memory devices of bank 932B receive the RAS*~1> and CAS~<1> signal6. The RAMOE~<0..3~ and RAMWE*<0..3>
signals are provided to the four chip pairs in banX
10 932A, while the RAMOE*<4.. 7> and RAMWE*<4.. 7~ ~ignals are provided to the four chip pairs in bank 932B, to allow ~election of the proper chip. TherePore the arrangement of the DRAM array 932 provides mirrored, parity checked, battery backed up memory to hold posted ~5 write data. This triple combination provides security of the posted write data during most, lf not all, problem cases, particularly temporary loss of power, 50 that posted write operations can be used comfortably and confidently in critical applications such as file servers.
When a parity error is detected during a read operation, the local processor 30 is interrupted. The local processor 30 can then load the mirror address into the address counter 922 ~nd access the data ~rom the mirror bank 932B. The block of data can then be retrieved from the mirror bank 932B, the error condition can be noted and diagnostics can be performed if desired.
Figure 30 shows the arrangement of the batteries 936. Preferably eight individual three volt lithium cells 936A-936H are utilized to form the battery 936.
The ground or negative conne~tions of the ~atteries 936A-936H are oonnected together to produce and develop a signal referred to as BAT GND. Each of the positive 35 terminals of the batteries 936A-936H is independent.
Charge limiting resistors 1020 and 1022 are connected in series between the 5 volts supply and thP anode of a Schottky diode 1024. The cathode o~ the diode 1024 is - ~ -:: . : : . :~ , . .-:
: : , ; , : ~ : : :.. , . :

.
, ~ :
-,. :, ~

2~77~2 connected to the positive terminal of the battery 936A, this ~ignal being referred to as the Bl signal. This path allows charging of the battery 936A. The anode of a Schottky diode 1026 is connected to ~he Bl signal and has it6 cathode connected to a ~ignal referred to as VBATT. Similarly, charge limiting resifitors 1028 and 1030 are connected between the 5 volts ~upply and the anode of a schottky diode 1032, whose cathode ic connected to the positive terminal o~ the battery 936B, which connection i6 referred to 85 the B2 fiignal- The B2 signal i~ connected to the anode of a Schottky diode 1034, whose cathode is connected to the VBATT signal.
A similar arrangement of resistors and Schottky diodes is provided for the batteries 936C-936H, with the signals at the positive terminals of the bat~eries 936C-938H being the B3, B4, B5, B6, B7 and B8 signals.
Referring now to Figure 31, the BAT GND signal is provided to the source of an N-channel enhancement MOSFET 1036 and to one terminal of a resistor 103~.
The drain of the MOSPET 1036 is connected to ground, while the gate is connected to the second terminal of the resistor 1038 and to the drain of a P-channel enhancement MOSFET 1040. The source of the MOSFET 1040 is connected to a signal referred to as the CTLVCC or control logic VCC signal. The CTLVCC ~ignal is connected to one terminal of a capacitor 1042, who~e other terminal is connected to ground. The CT~VCC
signal is connected to the cathodes o~ Schottky diodes 1044 and 1046. The anode of the diode 1044 i~
connected to the +5 signal, while the anode of the diode 1046 is connected to the VOUT signal. In this manner the CTLVCC ~ignal is provided in any event to allow power up of the system. The CTLVCC ~ignal is connected to one terminal of a resi~tor 1048 whose second terminal i~ connected to the gate of the MOSFET
1040 and the dra7ns Qf N-channel enhancement MOSFETs 1050 and 1052. The ~ource of the MOSFET 1050 is connected to groundj whilP the gate receives a signal _ ., - :, . . .

7 6 ~

referred to as POWER ~OOD which, when high, indicates that the +5 volt6 being received by the disk controller D is satisfactory. In thi6 ~anner when the POWER GOOD
6ignal is present, the ~OSFET 1050 i6 activated, the MOSFET 1040 is activated ~nd then the MOSFET 1036 is activated, 60 that the BAT GND signal iB effectively coupled to ground through the ~OSFET 1036. Thi6 allows char~ing of the batteries 936 when the power iB good.
rhe CTLVCC sign~l is provided to ~ne terminal of a resistor 1053, whoee ~econd terminal produces the VREF
signal and is connected to one terminal of a resistor 1054. The other t~rminal of ~he resi~tor 1054 produces the BREF signal and i~ connected to one terminal o~ a resistor 1056. The 6econd terminal of the resistor 15 1056 i5 connect~d to the control input of a reference diode 1058 and to vne terminal of a resistor 1060. The second terminal o~ the resistor 1060 produces the VREF2 signal and is connected to one terminal of a resistor 1062, whose second terminal is connected to ground.
The anode of the diode 1058 is connected to ground while the cathode is connected to the VREF signal. One terminal of a resistor 1064 is connected to the VREF
signal and the other terminal is connected to the cathode of a Schottky diode 1066, whose anode is 25 connected to the +5 eignal. A resistor 1068 receives at one terminal the VREF ~ignal and has its second terminal connected to the inverting input of a comparator 1070. The non inverting inpu~ of the comparator 1070 is connected between resistors 107~ ~nd 30 1074, the resistor ~072 cQnnected to the +5 signal and the resistor 1074 connected to ground. Thus the resistors 1072 and 1074 provide a voltage divider, while the resistor 1068 provides a reference voltage to the comparator 1070. A resistor 1076 is connected - 35 between the +5 ~upply and the output of the comparator 1070 to ~ct as a pull-up. The output of the comparator 1070 is also connected to the parallel combination of capacitor 1078 and a resistor 1080, which act as a 2~977fi'' ~75-hystere~i~ feedback for the comparator 1070. The output of the comparator 1070 is ~urther connected to one input of a two input OR gate 1082 whose second input is connected through a rQsistor 1084 to ground.
~he output of the OR gate 1082 i~ the POWER GOOD
signal. Thus when the ~5 supply reaches a level B0 that the divider signal provided to tha comparator 1070 exceeds the reference voltage provided by the diode 1058, the power i~ considered good.
The POWER GOOD si~nal i~ al60 provided as one input to a two input NAND gate 1086. The Gecond input of the NAND gate 108fi receives the ADDR3RD ~ignal. The POWER GOOD signal is further connected to one input of -a two input NAND gate 1088 whose second input is xeceives the ADDR3WR signal. The output of the NAND
gate 1086 is provided as one input to a two input NAND
gate 1090, while the output of the NAND gate 1088 is provided as one input to a two input NAND gate 1092.
The output of the NAND gate 1090 is connected to the second input of the NAND gate 1092 and is referred to as the BATON signal, while the output of the NAND gate 1092 is connected to the ~econd input of the NAND gate 1090. Thus in this manner the MAND gates 1086, 108~, 1090 and 1092 form a simple latch circuit which is set ~5 by a pulse to the ADDR3RD signal and cleared by a pulse to the ADDR3WR sign~l. In this way the local processor 30 need only provide a command to the trans f er controller 4~ to re~d the address 3 register ~o set the BATON ~ignal and provide a write operation to the address 3 reyister to clear the BATON signal.
The BATON signal is used to provide a turn on circuit and grounding circuit to allow the batteries 936 to remain connected to ground and power the DRAM
array 932 during times when power is not being received to the disk controller D. The cutput of the NAND gate 1090 i5 provided to one terminal of a resistor 1094, whose second terminal is connected to the gate of an N-channel enhancement MOSFET 1096. The source of the . .

2~977~

, ~j IIOSF~ 1096 i~ oQnne~t~ ~o g~ound while th8 ~r~ln ~ç3 ~onnQce~ to tl~e ~ou~c~ oP th~ ~08FE~ 1052. q!h~ g~te o~ ~ho ~IOSF~ 1052 r~oQlveÆ a sigm~l r~fQrr4d to a~ t~e ~D ei~nAl, ~ich i~ pxo~dod by the e~utpu~ o~ a .. 5 clompnr~tor 1098. When po~iv~ or nlgl~, ~a BA~_GOOD
s~n~l lndlc~t~o th~t tho b~tt~ry volt~g~ p~ov~ed by 'ch~ ~att~ry g36 i~ ~u~flolent to o~sable th8 op~rat~on o ~ D~ ~rrny s3a. ~ ro~ or 1100 1~ ~onn~ct~d betwoen th8 ou~put o~ com~a~st~r 109a ~nd th~
14 C~LvCC ~ign~l to Det al~ pull~up, vhile r~ tors lloZ
and 1104 o.r~ connectQd ln ~rl~ wsen th~ output and th~ non-~nv~rt~ input of t21~ Compara~or 10~8. A
r~si~tor ~106 l~ oonn~o'cod ~etwo-n tho non-~ nv~e~t~d lnput o~ t~e oonwar~tor lQ9~ ~nd groun~ emd 1~ in para~lel wlth a oapaolto~ l1o~ re~l~tor 1110 i8 conneot~A bet~resn th~ non-~nv~t~d input o~ th~
oo~parator 1098 and the VBA~r ~ign~ V~FZ sl~nal 1~ proYided to the nog~ti~ra lnput o~ the ao~par~tor 1098. ~n thl~ nner th~ ~o~nparator 109a ~er~orm~ æ
~etermin~'cior~ to ~heth~ar t'n¢ hat'cery volt;~g~ ~lng prov~d~d ~y th~ battery g36 ls ~ur~lclent to powç~r the DRA~ ~r~y 932 . I~ ~o~ the BA~ C00D ~gnal iB hl~h, ~o that tll~ MO~F~T 10S2 iB ~ctlv~ted~ re~ore 1~ thQ
lAtCh r ~111 aot~vated, th~n ohould power bQ re~ovQ~ an~l t~e ~Ol~ ~D slyn~l nc3 lon~E b~ truo, l:~cause th~
BA~_cooD el~t al i~ 8t~ ive and ths latcn L 2~a~ e BATON
~lgns~l ~ct~Y~todJ th~n t3~e ~oltage provldeà at t}l~ gato o~ ~o ~lOSFE~r 10~0 is st~ll gr~un~ an~ tl~r~So~ t~
b~ttcr~s are ~t~ll grou:~d~d ~h~ough ~OSF~ 1036.
~o ~houl~, ho~v~r, ~i~er tr,e b~t~ y volt~ç~o bo too lo~
o~ bett~ ta~u3 bs tu~rlod o~, a~ indicated ~y ATON slgn~l ~lns~ l~w, th~n on~ o~ th6 M08P~T~
'1095 ~72 lo~a le rl~t ~tiv~ and th~r~f~re ~ MoSF~T
10~0 i5 ~l~o not ~ctlvo. Iihl~ ln turn ~ ts ln l:ho 3~ l50~FICT î036 b~ng turn~d ~f, B0 ~at tll~ ~a~t~r~ 936 ~lo not recel~ve ~y3~ g~oun~l ~nd thul~ can not provide power ~c~ the D~Uf array ~32. ~hlr3 oa~ d0~rAblQ to prev~nt the ~ttorl~s 936 ~c~n ~ls~hargins~ too deeply 2Q~7~6~

and to reduce di6chargin~ during certain power off conditicns, particularly when valid data i6 not present in the DRAM array 932 And it can be ~afely powered off.
It is also necessary to develop the VOUT æignal which i8 provided to the DRAM array 932 to power the memory cells. The development of ~hi6 VOUT ~ignal i~
shown in Figure 32. A Schottky diode 1120 has its anode ~onnected to the ~5 volt line and its cathode connected to one terminal of a resis~or 1122. The second terminal of the resistor 1122 is connected the VBATT 6ignal and to one ter~in~l of a resi~tor 1124.
The second terminal of the resistor 1124 is connected to the control input of a voltage reference diode 1126 and to one terminal of a resistor 1128. The anode o~
the diode 1126 and the second terminal of the resistor 1128 are connected to the drain of an N-channel enhancement MOSFET 1130, whose source i8 connected to ground and whose gate receives the POWER GOOD signal.
The cathade of the diode 1126 is connected to the VBATT
signal. Therefore if the power is considered good, then the reference diode 1126 is active, limiting the voltage provided to the batteries 936A-H to prevent overcharging and to provide a stable voltage reference.
A switching voltage regulator 1134, preferably a Linear Technologies LT1073, is used to allow development ~f the VOUT signal ~rom the VBATT signal if the power is not good. A capacitor 1132 is connected between the VBATT signal and ground. The VBATT signal is conneeted to a resistor 1136, whose second terminal is connected to the auxiliary gain block output of the switching regulator 1134 and to one terminal of a resistor 1138. The second terminal of the resistor 1138 is connected to the sense input of the switching regulator 1134 and to one terminal of a resistor 1140.
The second terminal of the resistor 1140 is connected to a resistor 1142, which is ronnected to graund, and to the ~ource of an N-channel enh~nc~ment MOSFET 1144 A resist~r 1146 is connected between the YBATT signal 20977~2 and the current limit input of the cwitching regulator 1134. An i~ductor ~148 i8 connected between the voltage input of the ~witching regulator 1134 and the ~witahed output of the switching regulator 1134. The VBATT ~ignal i6 also connected to the volt~ge input of the ~witching regulator 1134. The ~witahed output of the switching regulator 1134 i8 alBo connected to the ~node o~ a Schottky diode 1150, whose cathode is connected to the VOUT ~ignal. A resi~tor 1152 has one io terminal connected to the ~et input of the switching regulator 1134 and a ~econd terminal connected to the source of t~e MOSFET 1144 and ~ first terminal of a resistor 1154. The second terminal of the resistor 1154 is connected tv the drain of the MOSFET 1144 and one terminal of ~ resi~tor 1156. The second terminal of the resistor 1156 is connected to the VOUT signal to provide voltage feedback. The gate of the MOSFET 1144 is connected to the POWER GOOD 6ignal. Therefore the resistor 1154 is removed from the feedback circuitry if the +5 supply is good, but utilized if battery power is being used. Therefore if the POUER GOOD signal is present, the switching regulator 1134 has its e~fective output voltage limited to a value less than 5 volts, preferably 4.7 volts, so that the diode 11~0 is reverse biased and the switching regulator 1134 is effe~tively out of circuit. If the power is not good, the MOSFET
1144 opens and the voltage is regulated at VOUT to 5 volts. Further, ~he reference diode 1126 is disconnected to reduce power drain on the batteries 30 936A-R.
The VOUT æignal can also ~e developed more directly from the +5 signal. The POWER GOOD signal is provided to one t~rminal of the resistox 1160. The second terminal of the resistor 1160 is connected to the first terminal of a resistor 1162, whose second terminal is connected to the base of an NPN transistor 1164. The emitter of the transistor 1164 is connected to the anode of a diode 1166 whose cathode is oonnected , . . .: ~ . ,.

~,:, ; : ~
, ~ .

,27~977~2 to ground. ~he collector of the transi~tor 1164 is connected to the gates of two P-channel enhancement mode MOSFETs 1168 ~nd 1170 ~nd to one terminal of a resistor 1172. The ~econd terminal of the resistor 1172 is connected to the VOUT signal and to the sources .of the MOSFETs ~168 and 1170, whose drains ~re connected to the +5 6ignal. The source6 of the MOSFETs 1168 and 1170 nre also connected to the VOUT signal.
In thi~ manner, if the POW~R GOOD 6ignal i6 true or active, the transistor 1164 is turned on ~o that a low voltage is applied to the gates of the MOSFETs 1168 and 1170, which th~n are turned on so that the +5 volt signal is transmitted directly to the VOUT signal to power the DRAM array 932, and th~ switching regulator 1134 output is not utilized.
If the power is not good then, it is ~ppropriate to continuously ground the column and row address strobes from the DRAM array 932 so that the memory devices enter self-refresh mode. This is done as shown in Figure 33. The POWER GOOD ~ignal is provided to one terminal of a resistor llBO, whose second terminal is connected to one terminal of a resistor 1182. The second terminal of the xesistor 1182 is connected to a base of an a NPN transistor 1184, whose emitter is connected to the anode of a diode 1186, whose cathode is conn~ted to ground. The collector of the transistor 1184 is connected to one terminal of a capacitor 1188 whose second terminal is connected to ground. The collector of the transistor 1184 is also connected to one terminal of a resistor 1190 whose second terminal is connected to the VOUT signal.
Further, the collector of the tran istor llR4 is connected to the gates of two N-channel enhancement MOSFETs llg2 and 1194. The sources of the MOSFETs 1192 and 1194 are connected to ground. The drain o~ the MOSFET 1192 is connected to the CASI* signal, to a resistor 1194 whose other terminal is connected to the CAS*<9> signal and to one terminal of a resistor 1196 - ~ , ~ ,, .., :
: ~ , ' ,' ,, ~ , .. . .

2~n77 6 2 whose second terminal i6 connected to the CAS*<l>
6ignalO In a ~imilar ~anner the drain of the MOSFET
1193 is connected to the RASI* ~ignal one terminal of a resi~tor 1198 whose ~econd terminal i~ connected to the RAS~c0> ~ignal and to one terminal of a resistor 1200 whose second terminal is connected to the RAS*<l>
~ignal. In thi6 ~anner when the power is not good the MOSFETs 1192 and 1193 are activated ~o that the CASI~
signal ~nd RASI* ~ignal are clamped to ground. When 10 the power i~ good, the ~OSFETs 1192 and 1193 are turned off and the R~SI* and CASI* aignals can noxmally be provided to the DRAM array 932.
It is also desirable to monitor the ~tatus of the batteries 936 ~o that the local processor 30 can 15 dete~mine if ~nd when the battery cells 936A-936H go bad. The circuit is shown in Figure 33. The BREF
signal is provided to the inverting inputs of a ~eries of comparators 1202, 1204, 1206, 1208, 1210, 1212, 1214 and 1216. The ground terminals of the comparators 20 1202-1216 are connected to the drain of an N-channel enhancement MOSFET ~218, whose source is connected to ground and whose gate receives the POWER_GOOD signal.
The power terminals to the co~parators 1202-1216 are connected to the cath~de of a Schottky diode 1220 whose anode i~ connected to the +5 ~ignal. The ~5 ~ignal is also provid~d to the anode of a Schottky diode 1222 whose output cathode is used to develop a pull up ignal for the outputs of the comparators 1202-1216.
The non-inverting input o~ the comparator 1202 receives the Bl signal, while the non-inverting inpu~ of the comparator 1204 receives the B2 6ignal. In a similar fashion the comparators 1206-121S receive at their positive or non-inverting inputs the B3, B4, ~5, B6, B7 and B8 ~ignal~. In thiC ~anner the comparators 1202-1216 are used to compare each of the individualbatteries 936A-936H with a reference volta~e to determine i~ any of them are going bad. The outputs of the comparators 1202 and 1204 are connected together .. : : : : - .: ~ :

20~77~2 and to one terminal of a resi6tor 1224 ~nd provide the B12 ~ignal to the ~uffer 992. Similarly, the outputs o~ the comparators 1206 ~nd 1208 are connected together and are pulled up to the diode 1222 by a resi6ter 1226 : 5 and are referred to as the ~34 signal, which is also provided to the buffer 9~2. Similarly the outputs of the comparators 1210 ~nd 1212 are connected together to produce the BS6 signal, which ic pulled up by a resistor 1228 to th~ diode 1222. Finally, the 10 comparators 1214 and 1216 have their outputs connected together to produc~ the B78 ~ignal, which is pulled up by a resistor 1230 to the voltage of the ~iode 1222.
The B56 and B78 signals are provided to the buffer 996 for pos6ible reading by the local processor 30.
Basic operation of the posted write memory 71 is as follows. Assume the power is good, the battery ~36 is being charged and turned on and all portions are enabled. The local processor 30 directs the transfer controller 44 to write the desired address information and control settings, including mirroring and auto incrementin~ to address registers 1 and 2. The transfer controller 44 activates the DA<2..0> signals, provides the data and provides the proper DS<2..0>
signals as programmed. The data is then latched into 25 the address counter 922 and the control latches 924.
The local microprocessor 30 then instructs the transfer controller 44 to transmit a block of data to the posted write me~ory 71. The transfer controller initiates the series of operations, ~ach having a DAc2..0> signal value of 0, the proper DSc2..0> signal value ~nd providing IWL signal pulses on each operation. The data is transferred to the data latches 928 and the state machine proceeds through a WRITE sequence, appropriately driving the proper RAS*, CAS*, OE* and WE* signals, with the address counter 922 incrementing with each transfer. Because mirroring was selected, the data is written into both DRAM banks 932A and 932B.
Assume now that power is lost. As the BATON signal was , 2~7~2 high and a suming a proper battery level, ~he DRAM
array 932 remains powered by the batteries 936 ~nd enters 6el~-refresh ~ode, Ev~ntually power returns, with the DRAM array 932 now being powered by the +5 ~upply again and the batteries g36 rechargin~. The loc~l microprocessor 30 ~gain instructs the transfer controller 44 to load values into the address counter 922 and control latches 924, this time for a read operation. This is performed and then the transfer controller 4~ i8 instructed to read a block of data from the DR~M array ~32, ~or purposes of this example, the final active d~ta. The local microprocessor 30 then instructs the transfer controller 44 to write to the address 3 register. The write operation turns off the BATON signal. Now if the power is lost, the DRAM
array 932 is not powered, but as no data was present, no data is lost and a discharge cycle of the batteries 936 is saved.
Assuming the read operation produced a parity error, as indicated on the TERR signal, the l~cal micropr~cessor 30 then instructs the transfer controller 44 to write a new address to the address counter 922, so that the mirror bank can be accessed.
The block read operation is repeated. If no errors occur, the data has been succes fully retrieved, even though power failed momentarily and a portion of the DRAM array 932 failed. Thus even under these conditi~ns data has not been lost.
Other general operations can be requested and the exact ~ignals present can be developed based on the above Betailed description.
Thus the disk array controller D of the present invention provides both a very ef~icient and high speed method of transferring data between the disk array A
and the host computer system under control of the local processor 30, allowing efficient parity operations which do not require large amounts of processor time, : . , ~77~h either ~y the local procesaor 30 or the host sy6tem, and allowing secure posted write cache operations.
The foregoing disclo~ure and descript$on of the invention are illustrative and explanatory thersof, and various changes in the si~e, 6hape, material6, component~, circuit elements, wiring connections and contacts, as well ~s in the details of the illustrated circuîtry and construction ~ay be made without departing from ~he spirit of the invention.

:. . ~ : . ~ . . ~ . ............. .: :

. -: . . : . ~:

Claims

1. A disk drive controller for transferring information between a host computer and at least one disk drive, power to the controller being provided from an external source, the controller comprising:
means for receiving data from the host computer to be written to a disk drive;
semiconductor memory means for storing said received data prior to transfer to a disk drive, wherein said semiconductor memory means is organized in a mirror configuration and said received data is stored in both portions of said mirror configuration;
battery means;
means connected to said battery means and said semiconductor memory means for providing power to said semiconductor memory means from said battery means when power is not being provided to the controller;
means for transferring said received data to said semiconductor memory means; and means for transferring said received data from said semiconductor memory means to a disk drive.

2. The controller of claim 1, wherein said semiconductor memory means further contains parity information and wherein said means for transferring from said memory means to a disk drive includes means for indicating the presence of a parity error when transferring data from said semiconductor memory means and transferring data from said mirror portion after receiving said parity error indication.

3. The controller of claim 1, wherein said semiconductor memory means has an interface similar to the interface of the disk drives.

4. The controller of claim 3, wherein the disk drives are arranged in a disk drive array, and are connected to a disk drive bus, said semiconductor memory means additionally being connected to said disk drive bus.

5. The controller of claim 4, further comprising:
buffer memory for storing data to be transferred to or transferred from said disk drive bus;
means coupled to said buffer memory for transferring data between said disk drive bus and other locations, and wherein said means for transferring said received data to said semiconductor memory means and said means for transferring said received data from said semiconductor memory means to a disk drive utilize said buffer memory and said buffer memory data transfer means in performing transfers.

6. The controller of claim 1, further comprising:
means coupled to said battery power providing means to disable providing of power to said semiconductor memory means when power is not being provided to the controller.

7. The controller of claim 6, wherein said disabling providing power means selectively disables providing power.

8. The controller of claim 6, wherein said disabling providing power means is connected to said battery means and disables providing power when said battery means voltage is below a predetermined level.

9. The controller of claim 8, wherein said disabling providing power means further selectively disables providing power.