CA2097874A1 - Programmable microprocessor booting technique using fifo memory - Google Patents
Programmable microprocessor booting technique using fifo memoryInfo
- Publication number
- CA2097874A1 CA2097874A1 CA2097874A CA2097874A CA2097874A1 CA 2097874 A1 CA2097874 A1 CA 2097874A1 CA 2097874 A CA2097874 A CA 2097874A CA 2097874 A CA2097874 A CA 2097874A CA 2097874 A1 CA2097874 A1 CA 2097874A1
- Authority
- CA
- Canada
- Prior art keywords
- host computer
- microprocessor
- fifo memory
- slave processor
- programmable microprocessor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000006870 function Effects 0.000 abstract 1
- 238000011022 operating instruction Methods 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
- G06F9/3879—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4405—Initialisation of multiprocessor systems
Abstract
A computer system includes a host computer and at least one programmable slave processor boots the slave processor simply and inexpensively by using a first in first out (FIFO) memory connected between the host computer and the slave processor. Specifically, the computer system includes a host computer, a programmable microprocessor (the slave processor) controlled by the host computer, a FIFO memory connected between the host computer and the microprocessor, and means for providing a boot program and/or boot data from the host computer to the microprocessor through the FIFO memory. When the boot program functions, operating instructions for the microprocessor are read into the microprocessor's own random access memory (RAM).
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/922,116 US6438683B1 (en) | 1992-07-28 | 1992-07-28 | Technique using FIFO memory for booting a programmable microprocessor from a host computer |
US07/922,116 | 1992-07-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2097874A1 true CA2097874A1 (en) | 1994-01-29 |
CA2097874C CA2097874C (en) | 1998-08-25 |
Family
ID=25446522
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002097874A Expired - Fee Related CA2097874C (en) | 1992-07-28 | 1993-06-07 | Programmable microprocessor booting technique using fifo memory |
Country Status (4)
Country | Link |
---|---|
US (1) | US6438683B1 (en) |
EP (1) | EP0581698A1 (en) |
JP (1) | JPH06161968A (en) |
CA (1) | CA2097874C (en) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69727465T2 (en) | 1997-01-09 | 2004-12-23 | Hewlett-Packard Co. (N.D.Ges.D.Staates Delaware), Palo Alto | Computer system with memory control for burst mode transmission |
EP1061439A1 (en) | 1999-06-15 | 2000-12-20 | Hewlett-Packard Company | Memory and instructions in computer architecture containing processor and coprocessor |
EP1061438A1 (en) * | 1999-06-15 | 2000-12-20 | Hewlett-Packard Company | Computer architecture containing processor and coprocessor |
US6751658B1 (en) | 1999-10-18 | 2004-06-15 | Apple Computer, Inc. | Providing a reliable operating system for clients of a net-booted environment |
US7089300B1 (en) * | 1999-10-18 | 2006-08-08 | Apple Computer, Inc. | Method and apparatus for administering the operating system of a net-booted environment |
US7383424B1 (en) | 2000-06-15 | 2008-06-03 | Hewlett-Packard Development Company, L.P. | Computer architecture containing processor and decoupled coprocessor |
US7730155B1 (en) | 2002-10-01 | 2010-06-01 | Apple Inc. | Method and apparatus for dynamically locating resources |
US20040103272A1 (en) * | 2002-11-27 | 2004-05-27 | Zimmer Vincent J. | Using a processor cache as RAM during platform initialization |
US20050038958A1 (en) * | 2003-08-13 | 2005-02-17 | Mike Jadon | Disk-array controller with host-controlled NVRAM |
US7774774B1 (en) * | 2003-10-22 | 2010-08-10 | Apple Inc. | Software setup system |
US8019985B2 (en) | 2004-12-30 | 2011-09-13 | St-Ericsson Sa | Data-processing arrangement for updating code in an auxiliary processor memory |
US7356680B2 (en) * | 2005-01-22 | 2008-04-08 | Telefonaktiebolaget L M Ericsson (Publ) | Method of loading information into a slave processor in a multi-processor system using an operating-system-friendly boot loader |
JP2007213292A (en) * | 2006-02-09 | 2007-08-23 | Nec Electronics Corp | Method for starting multiprocessor system and slave system |
KR101430687B1 (en) * | 2007-09-28 | 2014-08-18 | 삼성전자주식회사 | Multi processor system having direct access booting operation and direct access booting method therefore |
EP2141590A1 (en) * | 2008-06-26 | 2010-01-06 | Axalto S.A. | Method of managing data in a portable electronic device having a plurality of controllers |
US9542172B2 (en) | 2013-02-05 | 2017-01-10 | Apple Inc. | Automatic updating of applications |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4407016A (en) | 1981-02-18 | 1983-09-27 | Intel Corporation | Microprocessor providing an interface between a peripheral subsystem and an object-oriented data processor |
US4975904A (en) | 1984-06-01 | 1990-12-04 | Digital Equipment Corporation | Local area network for digital data processing system including timer-regulated message transfer arrangement |
US4975905A (en) | 1984-06-01 | 1990-12-04 | Digital Equipment Corporation | Message transmission control arrangement for node in local area network |
US4847812A (en) | 1986-09-18 | 1989-07-11 | Advanced Micro Devices | FIFO memory device including circuit for generating flag signals |
DE3639571A1 (en) | 1986-11-20 | 1988-06-01 | Standard Elektrik Lorenz Ag | METHOD AND CIRCUIT ARRANGEMENT FOR CHARGING A SECONDARY COMPUTER |
US5155833A (en) * | 1987-05-11 | 1992-10-13 | At&T Bell Laboratories | Multi-purpose cache memory selectively addressable either as a boot memory or as a cache memory |
US5136713A (en) * | 1989-08-25 | 1992-08-04 | International Business Machines Corporation | Apparatus and method for decreasing the memory requirements for bios in a personal computer system |
US5210875A (en) * | 1989-08-25 | 1993-05-11 | International Business Machines Corporation | Initial bios load for a personal computer system |
-
1992
- 1992-07-28 US US07/922,116 patent/US6438683B1/en not_active Expired - Fee Related
-
1993
- 1993-06-07 CA CA002097874A patent/CA2097874C/en not_active Expired - Fee Related
- 1993-07-23 EP EP93420315A patent/EP0581698A1/en not_active Ceased
- 1993-07-26 JP JP5183658A patent/JPH06161968A/en active Pending
Also Published As
Publication number | Publication date |
---|---|
US6438683B1 (en) | 2002-08-20 |
CA2097874C (en) | 1998-08-25 |
EP0581698A1 (en) | 1994-02-02 |
JPH06161968A (en) | 1994-06-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CA2097874A1 (en) | Programmable microprocessor booting technique using fifo memory | |
AU636651B2 (en) | Personal computer processor card interconnect system | |
EP0945788A3 (en) | Data processing system with digital signal processor core and co-processor | |
EP0840234A3 (en) | Programmable shared memory system and method | |
EP0902370A3 (en) | Dual storage controllers | |
AU5941990A (en) | Memory card tray for portable computer | |
AU4922490A (en) | Virtual computer system having improved input/output interrupt control | |
CA2330693A1 (en) | Control system, display, host computer for control, and data transmitting method | |
EP0623875A3 (en) | Multi-processor computer system having process-independent communication register addressing. | |
CA2044119A1 (en) | Disk operating system loadable from read only memory using installable file system interface | |
EP0374074A3 (en) | Computer system having efficient data transfer operations | |
HK1028459A1 (en) | Direct memory access (dma) transactions on a low pin count bus. | |
PH31356A (en) | Command delivery for a computing system for transfers between a host and subsystem including providing direct commands or indirect commands indicatingthe address of the subsystem control block. | |
AU5029896A (en) | Memory testing in a multiple processor computer system | |
WO2001057660A3 (en) | Virtual rom for device enumeration | |
CA2191555A1 (en) | Smart Card Message Transfer Without Microprocessor Intervention | |
HK57295A (en) | Accessing an option board in a computer system. | |
CA2145106A1 (en) | Intelligent Memory-Based Input/Output System | |
WO1997050063A3 (en) | Portable, secure transaction system for programmable, intelligent devices | |
IE800897L (en) | Logic system | |
EP0335812A3 (en) | Secondary processor initialization scheme | |
WO1998030948A3 (en) | Apparatus and method for operably connecting a processor cache to a digital signal processor | |
EP0299075A4 (en) | Processing unit having at least one coprocessor. | |
JPS53137644A (en) | Managing system for hospital information | |
TW369632B (en) | Computer system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
MKLA | Lapsed |