CA2100341C - High speed data detection and clock recovery in a received multi-level data signal - Google Patents

Abstract

An arrangement for high speed data detection and clock recovery in a multilevel data signal is disclosed wherein the received signal waveform is sampled at periodic preselected locations (Fig.1) and the samples so obtained are compared to set values representing the expected levels at those locations (D0, D1-D16). If within a permitted tolerance range (30) over a given window of time, an indication of the presence of data is determined. Further, if such correlation is determined to occur at a periodic rate, symbol timing (clock) recovery is also indicated (42, 44, 51-54). A further embodiment with a dual recovery capability is also disclosed and described.

Description

wo 92/14324 21 0 0 3 4 1 Pcr/uss2/00538 HIGH SPEED DATA DhTECTION AND CI~CK RECOv~ IN A
V~ MULTI LEVEL DATA SIGNAL

Field of the Invention The present invention relates generally to radio data communication systems and, more particularly, to a fast data detect arrangement as well as symbol timing (clock) ~eco~ , for a multi-level data signal processefl in such radio data comm1lnic~tion 0 systems.

Background of the Invention Present day radio data comm11n;c~qtion systems typically 5 include a centrally located base station or central controller coupled to a host co ~ ter, which base or central controlled commllnir~tec to a plurality of system remote data terminal units over an o-~tho~ln~
comm-mication l~h~nne1. Co,l~elsely, the system remote data tenninal units co ~ te to the central site over a separate 20 inbound ch~nn~1.

Usually such commnni~tion is effected from the remote data telminal side in essenti~11y pseudo-automatic fashion. That is, the user/radio o~e~ator merely ~ttempts to access the communication 25 rh~nnel and transmit data by p11ching a button on the terminal itself.
If the rh~nne1 iB clear, the terminal unit commences to transmit upon activation of the push to talk button. If the ch~nnel iB
determined in u8e, the initiating radio terminal unit tries again some other time, usually on a r~ntlom baBiB. Provision iB made to, 30 for the most part, avoid destructive collisions that would otherwise occur when more than one radio data terminal attempts to transmit on a communication channel simultaneously. This avoidance is effected mainly by the est~hli~hment and use of a suitable operating wo 92/14324 2 Pcr/usg2/ooS38 2~ o~?, ~l protocol which in eSsenre deterInines the radio traffic rules for such system.

An early innovation in the radio data comml~nication requires 5 the central station or controller to insert "busy bits" in the traffic forming the outbound ch~nnel m~~sage stream and, in this m~nner, advise any of the radio data terinal units that in fact the inbound rh~nnPl ig in use ag in-lic~ted by the mere ~,~eEellca of the "busy bits".

Accordingly, in such radio data co_munication systems, it is obviously an objective to quickly identify the presence of data as well as to effect symbol timing (clock) ,acuvel~ in a minimum amount of time. These factors L~eclly impact the "throughput" or observable efficiency of the radio data communication system. In point of fact, 15 the time required to detect the mere presence of data on the inbound l-h~nnel constitutes a major contributor to the collision window. It will be a~ e~ ;~ted that it is critical, to say the least, that the modem at tbe base 8t~ti0n be able to detect data presence and then set the "busy bits" in the outbound mP~ssage screen in the least amount of 20 time. This optimi7-~tion of the co~ ion window obviously permits higher rh~nnPl throughput, in an essentially e~o~e~t;~ql rel~t;r-nchip. In optimi7ing this collision window, there are at least two major considerations, namely: 1) fast detect of the presence of a sperific h~eb~qntl mo~ ;Qn as well as 2) the detec~ion of the sy_bol 25 ~;mir~ center of the laceived waveforms.

S-lmm~ry of the Invention In a radio data commllnic~tion system operating with an 30 est~bli~he~l protocol and processing multi-level data signal information, a provision is made to receive such multi-level data signal wave forms and s~mple at a plurality of preselected locations on the racaived ~.avefo.~ to dete. llille if the same is at a permitted level at each of said preselected locations. If in fact correlation is 2l0n3~l determined at a given number of ~lccessive permitted locations, then using and relying on the saIne to in~ te the pres~nce of data. Then further deter...;..;.~g if such corre~ Qn llt~li7etl to detect the presence of data is occurring a~ a periodic rate, and if so, using and relying on 5 such to determine the ~cEe-~ce of symbol timing (clock) recovery.

Brief Desc~;l.lion of the Drawings The novel features which are believed to be characteristic of the 0 ~c~c~t invention are set forth with particularity in the appen~le~
im~, The invention itself, ho.. ~v~r, will be best unde~s~ood by reference to the following description when taken in conjunction with the drawings, in which:

FIG. 1 is a graphic ~ e ~t~tion of the bA~ebAnd eye pattern that may be e~ le~ in a multi-level FSK signal of a type used in the radio commllnic~tiQn ~r~m that lltili7es the present invention;

FIG. 2 is a block diagram of a fast data detect arrangement which may advantageously utilize the principles of the present invention;

FIG. 3 is a graphic represçnt~tion of the pelro~ nce of the data ~lQtectiQn arrangement that may be e,-~ect,ed from the present invçntiQn;

FIG. 4 is a graphic representation of the output of the adder ~f FIG. 2 for multi-level FSK modlll~tion which show presence of da~
and timine recv~e FIG. 5 is a graphic representation showing the rel~tinnchip of the symbol timing clock edge and the b~seb~n~l signal waveform;

wo 92/14324 ~ Q3 ~ 4 Pcr/usg2/oo538 FIG. 6 i8 another emhoAimsnt of the present invention showing a dual mode symbol timing (clock) 1acuvel~ arrangement lltili7in~ the prin~ples of the present invçnt;Qn~ and FIG. 7 is a timing guide diagram useful in the description of an underst~nAine of the symbol timing (clock) recove,.~ algorithm.

Description of a Preferred li~m~oAim~nt 0 In a multi-level FSK modlllAtiQn sien~qli~ information of the type cont~mplAte~ for use in a radio data communication system bere under consideration, certain pattern characteristics are readily evident. For çYAmple, a b~sebAn~l eye pattern is shown graphically in FIG. 1 which indicates certain minimum level cro~ings at predet~, 1lel loc~tiQns in the ~.avèfOllll. The b~seh~n~ data has been a1bil,a,;ly scaled such that peak deviation ,e~1e3cnts + 1Ø
Accordi,lgly, these ...i..i...~ level cro~sine~ may be eYpecte~l at +
1.0, +0.333, - 0.333 and -1Ø As such, they may be con~ ered as occurring at "valid" levels and, in point of fact"~l,r~ scnt symbol 20 centers. While here being described in te~ns of a 4-level FSK
mo~ tion~ it is to be understood that the present invention is equally applic~ble to any mod~ t;on te~ hnique that results in symbol centers that occur at fised points in time.

Retu,m,~ to the e~Ample as set forth in FIG. 1, the bA~ebAn~
w~vè~l ~ that is ~ecêived is shown as having the symbol centers (mi..;~ c~ùssillg pointg) at essentiAlly every 8 units of time along the hori7on~Ql axis and at essentially 4 levels of crossine~. This then l,e,~ s the sampling of such waveform at a sAmpline rate 8 times 30 the symbol rate. Accordingly, a detection algorithm may then be llt.li7~ 1 to ey~mine every 8 ss~mrle, i.e., at sample points of 9, 17, 25, etc., over a window length of n-symbols. These symbols may then be compared with the valid levels previously determined to within some permitted tolerance range ~. If such comp~rison indicates that the 4 5 PCr/US92/00538 2le~3~l ~mple level is within the allowed tolerance range with ,eel,ecl to the valid, or permitted levels, a score of 1.0 may be ~ign~l for that ~Pmrle, otherwi~e a score of zero (0) is applied. This cQrnpArison process is l,e,ro,.l,ed over the entire n-symbol length constraint, with 5 lesl)e~ ;ve scores at each of the s~lcces~ive symbol lor~tion~ being cl~mnl~tively ~ e 1 The resultant score may then be compared to some set n-~mher which is a~bil,arily A~igne~l to represent the ",;,,;,,~qlly rc~ ~,table threshold level.

0 The fo~e6oing may advantageously be lltili7e-3 in a generalized implçment~tion of the present invention as set forth in FIG. 2, suitable for ~' ;..g fast data detection for many different moflllls~iQ-I tsrhniques~ but certainly apFlicAhle to the illustrated 4-level FSK represçntefl in FIG. 1. A raw analog data is then sampled 15 at a rate of n so~ ,les (8 in the e~mrle under cQ~ eration). The ~Ample and data is then input to a tapped delay line as indicated generally at 20. The ta~e~l delay line may be taken for illustrative p~oses as having some 16 separate 6~o~lps of s~mrle~, i.e., 16 ~c 8 ~mple~ As further shown, the data line has a tap at selecte~
20 lor~ n~ -- i.e., in this inct~nce~ at every 8th sample location. These t~ e~l ssmple lor~t;onc are iclçntified at Do, Dl . . .Dl6 . The digital data at each of these taps is then comp~red with "m" reference values, "m" in the present eY~mple being 4 as previously described in connect;on with FIG. 1.
An m-level hysteresis comparator is used in the referenced CQ"~A' ;sons, shown generally in FIG. 2 as 22, 24 and 26. In the on-going c~ ;son process, if the derived data samples are within a particular range, i.e., a permitted tolerance range, the output of the 30 c~...l-~.ator will be set to produce a "1", otherwise it will be a zero (0).
The oul~lts of the respect;ve comp~rators 22, 24...26 are 8~lmme~1, in an adder 28, and the sum of the output thereof is comr~red to a predetermined threshold value set within an additional comp~rator 30. If the sum eYcee~ the set threshold value, the output of Wo 92/14324 ~ 3 ~ 6 Pcr/us92/00538 comparator 30 will again be a "1", otherwise it is zero (0). The output of comparator 30 is then l~t~he~l at symbol centers (every 8th sample in the present çYAmrle) and the l~tche-l output of latch 32 may be taken as the indicator that valid data has indee~l been ~letecte-l on the 5 communication ch~nnel.

Such data ~l~tection is thereby effecte~ within the window of 128 bits (16 taps x 8 bits, in the e~mrle under con~ eration). This .o~, c~cnts at least an order of magnitude in i~ rvvell.ent, being at 0 least one-tenth the time over that required for presently known co~,elltional techniques. Moreover, it is quite pos~ible that the data detect time factor may be reduced from the illustrated 16 symbol length even further, and in fact to as low as 10 symbols without a~l,-ac;atable degradation in perform~nce.
For illustrative purposes, FIG. 3 shows the output of the data detect arrangement shown in FIG. 2 for the ~~hosen 4-level FM
mo~ t;on prece~le-l by rAn~ m noise. The ~n~lo~ data was s~mrle-l at the .afe.ellced 8 samples per symbol and the constraint 20 length of the filter was the 16 symbol window, or some 128 samples.
As previously mentioned, the 4-level hyslelasis comparators looked for levels of +1.0, +0.333, -0.333, and -1.0 volts, tolerating an error of +
or - on the order of 0.15 volts. The threshold co~ ator 30 at the ou~t of adder 28 was set to go high when the input value was 75 25 I,e-ce-lt of mA~;...~, or in this case 12 out of the 16 symbol centers.
Also, for this eY~mple, the modulated data was prece~e~3 by some 224 noise samples, and included 256 samples (32 symbols) of preamble and 1580 sAmples (196 symbols) of packet data. Because the data detector was implçment,e-3 in a "look ahead" fashion, it was expected 30 and indeed did assert a logic "1" level after some 200 sAmples.

For timing (clock) .ecove- y, the output of threshold comparator 30 may be taken as the indicator of symbol timing (clock), which, as referenced, is used to clock symbols into a further latch 34. FIG. 4 wo 92/14324 7 Pcr/US92/00538 21~3 11 shows the output of adder 28 in FIG. 2 for 4-level FSK mod~ oIl Acco.dingly, the peaks co~e~pond to symbol centers and constitute the symbol timing clock as referenced at output of co~nr~rator 30 in FIG. 2. The data used in this e~amrle has a bz~seb~nA SNR of 5 al~lJ.o~ te1y 25 db.

The re1~qt;Qnship between symbol timing clock and bs~eb~nA
signal wavèfol~ is shown in FIG. 5. As will be noted, the rising edge of the sy nbol timin~ clock efre~ ~ively co~les~onA~ to symbols 0 centers' locations. Acco~ gly, it will be a~l,le~ teA that the mes~n.c and met~ oAo1ogy for the symbol timing ~ecuvérr eshibits a very fast attack as well as a very fast decay, which is optimal for the desired rapid acquisition c~qpphility.

Ho~ er~ even with the fo~e~oil,g, in mobile and portable commlmic~tions ellvi~o~msnt~ a leceived signal may well received may well experience noise, such as Rayleigh fading, which results in long periods where the b~seb~n~l signal is so co- ~ .,pted by such noise that the timing r~cuvel ~ m~tt oA as above described cannot well maintain a constant symbol timing clock. This may well result in loss of symbol synch.o..i7~tion and even timing relative to the frame synchro lization event.

To obviate this ~leletçrious effect, a further emhoAiment of the 25 l,-e~c.lt illvelllion is shown in FIG. 6 providing a dual l~co~,e ~F~hility. In thig implçm~nt~tion, a fast symbol timing clock lecovel r arrangement is indicated generally at 42, which arrangement may be considered as that already described in cQnnection with FIGs. 2, 4 and 5 and to that extent, constitutes the 30 fast timing ~ecuve~ ~ phase of the overall dual timing ~ec~ve~.y arrangement 40. The other phase, a slow symbol timing recovery with a relatively long time con~t~nt is shown generally at 44. The long time constant is effected to ms~int~in the phase of the symbol timing clock through long noise bursts. Once symbol w092/14324 - 21 00341 8 PCr/l'S92/00~38 synchroni7~tion is effected by the described fast timing reco~ery arrangement 42, a logic Plemçnt may be utilized to switch to the long - tIme constant recovery 44.

The slow t;ming recovery may be co~vP.. iently implemented using a conventional narrow band filter (not specifically shown) with certain ~i~nifi~nt additions. First, the slow symbol ~iming recovery is gated, as shown being applied over the line c(--nPctisn 46. When the gate is low, slow timing recovel.~ 44 rem~inc disabled. The rising 0 edge transition from the logic "0" to logic "1" initi~li7.es the slow recovel.~ operation and will rem~in operative as long as the gate i8 held high.

This slow timing recovery causes the filter elements (not 5 shown) to be initi~li7e~1 with data repres~nt~tive of the baseband signal and in phase with the symbol timing clock. Logic elem~nt~ 51, 52, 53 and 54 fonn a digital switch 50 based on the data detect output from the fast t;min~ rec~ve~ ~ 42 which selects the fast ~imi~g recuver~ clock sig~al if data detect is "0" and the slow timing recovery 20 clock signal if delayed data detect is "1". The delayed data detect signal is used to switch between the two timing clock sources, and to initialize the slow timing lecuver~ operation. The reason for the delayed data detect signal is that it is lm~l~sirable to switch to the slow timing re~ve~.~ operation until it has time to acquire proper 25 symbol *min~ ~,C~)vel~ synchronization. The amount of delay required ~Irill depend primarily on the particular slow timing recover~ imrlem~t~jon A timing diagram for this is shown in FIG. 7. As therein shown (FIG. 7 ), the transmit carrier represents the presence of the data bearing carrier on the radio ch~nnel st~r~ng 30 at a tirr e tl. At a time t2 later, the fast timing l ~cove~ y 42 l ec. vel s the symbol timing clock. At a time t3 later, the slow timing recovery 44 will start generating symbol timing clock pulses with the correct phase. At a time 4 later, the delayed RAD signal will go high, cau~ing the digital switch represented by 51-54 to switch from the fast A

wo 92/14324 9 Pcr/us92/00538 21~03~1 symbol t;ming lec~,vel~ clock to the slow symbol timing recovery clock data.

For a short ti_e after the 1088 of a data bearing carrier, the fast 5 delayed RAD signal will be held in the "1" state. Just prior this time, the occurrence of fast symbol timing lccove~ clock pulses will cease due to the lack of valid data. The slow timing leco~er~ element will still be generating clock pulses bec~ e of the long delay time. When the delayed RAD signal goes to the "0" state, the digital switch 50 will 0 select the fast symbol timing recove-, pulse strea_, for which there is no data present. Hence, the symbol clock pulse will then cease.

It will be appreri~te~ that an important feature of the present invention is the c~p~hility of simultaneously looking for several motl~ t;on signal waveforms. An eY~mrle of this would be a radio rh~nnel where 2 or 3 modulation techniques could be used and the base st~1;on is required to demodulate whichever is being used at a given time. The circuit as shown in FIG. 2, will easily be used to look for multiple modulation waveforms.
Further, it will also be noted that the impl~ment~tion of the present invention may be effected in a number of media. That is, in sol~wale, to either run on a microprocessor or a digital signal processor, or in firmware, or even in hardware as a custom circuit 25 llesi{~n- In any event, whatever the implementation, it will be a~p.ec;~te l that the data detection and symbol timing rec.~e~-~ as herein disclosed provides both apparatus and method which will provide pelro~ nce about ten times faster than that of presently known conventional meAnS. The increase speed of the data detect 30 provides an increased ~h~nnel contention control efficiency for the radio data communications ~h~nnel. The increase speed of the WO 92~14324 10 PCr/US92/00538 sy_bol timing recovel ~ reduces the required length of the symbol ~;ming recovt:r,y sequence precefling each packet in a radio ch~nnel, thus measurably increasing the radio ch~nnPl protocol efficiency.
s Accordingly, what is cl~ime~l is:

Claims (12)

WHAT IS CLAIMED IS:

1. An arrangement for high speed data detection and clock recovery in a receivedmulti-level data signal, including in combination:
means for receiving a multi-level data signal;
means for simultaneously sampling at a plurality of preselected locations on such received signal waveform comprising said multi-level data signal and determining if such samples are within a permitted tolerance range of an expected level at each of said preselected locations;
data detect indicator means for indicating the presence of data whenever a given but presettable level of correlation is determined as occurring between said samples and the expected levels at a given number of successive said preselectedlocations; and further means for indicating the presence of clock recovery when determining said correlation is occurring at a periodic rate.

2. A high speed data detection and clock recovery arrangement in accordance with claim 1 wherein said means for determining if each of said samples are within a permitted tolerance range of an expected level includes an m-level comparator at each of said preselected locations for comparing the level of the signal samples with a set programmable value corresponding to said expected level.

3. A high speed data detection and clock recovery arrangement in accordance with claim 2 wherein each of said m-level comparators are coupled to adder means, and wherein said adder means is coupled to a threshold comparator wherein the presence of data is determined if the cumulative score received from said adder means is within an arbitrary value set to represent a minimally acceptable threshold level.

4. A high speed data detection and clock recovery arrangement in accordance with claim 1 wherein the means for simultaneously sampling at a plurality of preselected locations includes applying the received signal waveform to a tappeddelay line having tap points at the desired sampling locations.

5. A high speed data detection and clock recovery arrangement in accordance with claim 1 wherein the multi-level data signal is a four level FSK modulation waveform, wherein the sampling rate is eight times the symbol rate, and the expected level at the respective preselected locations are +1.0, +0.333, -0.333 and -1.0 for a peak deviation set at a 1.0 level.

6. A method of effecting high speed data detection and clock recovery in a received multi-level data signal, including the steps of:
receiving a multi-level data signal; simultaneously sampling at a plurality of preselected locations on such received signal waveform comprising said multi-level data signal and determining if such samples are within a permitted range of an expected level at each of said preselected locations; and indicating the presence of data whenever a given but presettable level of correlation occurs between said samples and the expected levels at a given number of said preselected locations; and indicating the presence of clock recovery whenever said correlation is determined as occurring at a periodic rate.

7. A method of high speed data detection and clock recovery in accordance with claim 6 wherein the step of determining if said samples are within a permitted tolerance range of an expected level includes comparing the sample at each of said preselected locations with a set programmable value corresponding to said expected level.

8. A method of high speed data detection and clock recovery in accordance with claim 6 wherein the step of simultaneously sampling at a plurality of preselected locations includes the further step of applying the received signal waveform to a tapped delay line having tap points at the desired sampling locations.

9. A symbol timing recovery arrangement, with dual recovery capability, for a received data bearing carrier containing multi-level signal information, including in combination:
means for receiving a multi-level data bearing carrier;
fast symbol timing recovery means which includes means for simultaneously sampling at a plurality of preselected locations on the received signal waveformcomprising said multi-level data bearing carrier, determining if each of such samples are within a permitted range of an expected level at a given number of said successive preselected locations and, if so, determining whether such correlation is occurring at a periodic rate so as to denote the presence of symbol timing recovery;
slow symbol timing recovery means with a sufficiently long time constant to maintain the phase of the symbol timing clock thru long noise bursts; and logic means for initializing said fast symbol timing recovery means to acquire symbol timing recovery synchronization and then switching to said slow symbol timing recovery means which continues to operate for as long as a data bearing carrier is being received.

10. A symbol timing recovery arrangement in accordance with claim 9 wherein said slow symbol timing recovery means comprises gated narrow band filter means.

11. A symbol timing recovery arrangement in accordance with claim 10 wherein said slow symbol timing recovery means is disabled as long as the gate of said filter means receives a low level signal and is activated so long as said gate receives a high level signal.

12. A symbol timing recovery arrangement in accordance with claim 11 wherein the gating logic to said slow symbol timing recovery means is determined by a delayed data detect signal generated by said fast symbol timing recovery means.