CA2106418A1 - Cell resequencing system for a telecommunication network - Google Patents

Abstract

ABSTRACT
CELL RESEQUENCING SYSTEM FOR
A TELECOMMUNICATION NETWORK
A cell resequencing system for a resequencing section (RS) having two inputs (S1n) coupled to inlets (I2n) of a switching network (SN2) via transmission links (TLn) arranged in a link group (LG). The cells transmitted from the inputs to outlets (N2m) of the switching network are subjected to a first variable time delay and are then stored in latching means (R2m) for a second variable time delay prior to be released to an output of the section. This second delay is so chosen that for each cell the sum of the first and second delays is substantially equal to a predetermined constant time value.
The size of the latching means is determined by the difference between this predetermined constant time value and a fixed transfer delay (TD) below which no cell can be transmitted from an input to an outlet.
A method for correlating in phase two clock means (CK1/2) producing time stamp values (tA1,tA2/tB) is also claimed. The first clock means sends a first time stamp value (tA1) to the second clock means (CK2) which then generates a second time stamp value (tB). A time stamp compensation value (TTC) equal to the difference between the second and the first time stamp value is then determined at the location (A/B) of either the first or the second clock means. This time stamp compensation value is function of both the phase difference between the two clock means and the fixed transfer delay (TD).

Description

2 ~ 8 - 1 - M. VERHILLE - M. HENRION - M.
GE SOMER - B. PA~WELS 13~ 7-~-8 CELL RESEQUENCING SYSTEM FOR
~ TELECOMMU~ICATION N~TWQBK
- The present invention relates to a cell resequencing system for a resequencin~ sectian of a telecommunicatien network through which cells of communications are transmitted, s~id resequencing section having at least one input and at least one outPut and including at least one cell switching netw~rk having at least one inlet coupled t~ -said inPut and at least one outletg the cells transmitted from said input to said outlet being subiected to a ~irst variable time delay and said cell resequencing system including latching means coupled between said outlet and said outPUt and adapted to subiect said cells to a second ~`
variable time delay whlch is so chosen that for each cell ` 15 the sum o~ said first and second variabla time deley is sub~tantlallY equal to a predetermined constant ti~e value.
~aid predetermined constant time value determining the size o~ said latching means.
Such a cell resequencin3 system adapted to restore at the output the sequence with which the cells were supplied t~ the input is already knawn in the art, e.g.
~rom the published International Patent Application ~T~ ~ ~HENRION 17). Therein, the resequencing section only includes one cell switching network and all /5G 25 the cells suPplied to the inPut thereof receive a time st~mp value. When these cells arrive at the output, i.e.
aft~r the first variable time delaY which ~aY be di~ferent ~or each cell, they are latched in the latching ~eans '~ .

~ ~ Z~ 8 - 2 - H. YERHILLE - M. HENRION - M.
DZZ S~MER - B. PAUWZZ-LS 13-Z7-5-8 constituted bY a resequencing buffer and they are onlY
released therefrom when the predetermined constant time value is reached, i.e. after being latched for the seoond variable time delay.
In this known cell resequencing system it is obvious that the size o~ the latching means is Proportional to the predetermined constant time value and thus increases with the first variable time delay.
In case the First variable time delay becomes relatively large, e.g. because of the presence of a relatively long transmission link between the inPut of the resequencing section and the inlat of the switching network, the size of the latching means maY become unacceptably large.
~; 15 An obiect of the present invention is to provide a cell resequencing sYstem of the above known type but whereof the latching means remains of a reasonable size even if the first variable time delay becomes relatively large.
According to the invention, this obiect is achieved due to the fact that said resaquencing section has at least two of said lnputs each coupled to a distinct inlet via a distinct transmission link, said inputs and said ~ transmission links being arranged in a lin~ grouP, I Z5 that said cells are supplied at an ~ne of said inputs of said link grouP and are subiected to at least a fixed transfer delay durins their transfer from said input to said outlet, said fixed trans~er delaY forming part of s~id first variable time delay,~ and 30 ~hat the minimum size o~ said latching means is determined ~, by the difference between said predetermined constant time v~lue and said fixed transfer delay.
Because the size o~ the latching means is Z proportional to the predeter~ined constant ti~e v31Ue ~
l 3S reduoing the latter by the fixed transfer delay ln order to ,3 ,,~ .
., Z - ' .

~, ' .

2 ~ a~ A~

- 3 - H. VERHILLE - M. HENRION - M.
~E SOMER - B. PAUWELS 13-Z7-5-8 obt~in a new predetermined constant time value which is lower than the former one leads to maintain this size at an acceptable value. The former size of the latching means can thus almost ba maintained even if the fixed transfer delay is relatively large. e.g. because of relatively long transmission links.
Another characteristic feature of the present invention is that said fixed transfer delay i5 ~ substantially equal t~ the minimum transmission delay below i 10 which no cell can be transmitted over a trans~ission link - of said link group.
In practice. the fixed transfer delaY i5 preferably ~, set equal to this minimum transmission delay which is easier to detarmine~ e.g. by measurement or by engineering, 15 than a theorical absolute minimum transfer delay below --which no cell can be transmitted ~rom any input to any output of the resequencing section. Moreover, it can be provad that the di~farence between these two minimu~ dolays is negligible. The minimum transmission delay is thu~
pre~erably uscd as fixed transfer delay to determine the size of the latching means. ~;
In one embodiment of the invantion, said resequencing sectlon includes a plurality of switching networks interconnected by link groups of transmission links and said flxed transfer delay is substantially ~qual to the sum of the fixed trans~er delaYs of said link groups.
In ano~har embodiment of the invention, said .l telecommunication network lncludes a pluralitY of series 30 connected rssequencing sections. each saction includin~ a -~
~ link group of transmission links connected in serias with a ,i switching network.
~' Still in another embodiment of the invention. said resequencing section includes a plurality of parallel ~` 35 branchas~ each branch comprising at least one link grouP of ~ ~
', ,., ' '.' '' ,~ ' 2~4~.~
~: , .. .. .

- 4 - H. VERHILLE - M. HENRION - M.
DE SOM~R - B. PAUWFLS 13-27-5-8 transmission links, each link group being connected in series with a switching network, and said fixed transfer delay being sub~tantially equal to the lowest sum amongst the sums of the fixed transfer delays of the link groups ~f each branch.
A multilink geographically distributed telecommunication network includin~ relatively long transmission links arranged in link groups interconnecting switching networks and wherein the cells, even if they belong to a same communication, are dYnamicallY distributed over the transmission links of the link groups in order to obtain a better traffic distribution is already known, e.g.
from the European Patent Application EP 91201915.5 (VERHILLE 11). However. no cell resequencing system is j 15 mentioned in this known document.
As already mentioned, in order to perform the resequencing ~f the cells. each of the latter is associated to a first ti~e stamp value at the inPUts of the resequencing section and, at the output of this resequencing section, this first time stamp value is compared with an actual second time stamp value for determining the moment ~t which a cell maY be released from ; the latching means, the difference between the actual j second time stamp value and the ~irst time sta~p value being then equ?l to the original predetermined constant time value of which the fixed transfer delay is subtrac~ed.
~ This requires that the clock means used for ; ~enerating the time stamp values must be able to simultaneouslY generate identical time stamp v~lUe5 both at the inPutq and at the euput of the resequ~rcin~ section.
As the present telecommunication network operates with a Phase accuracy of about 100 nanosecond, the simultanaous generation of identical timQ stamp values maY
~1 be a problem, e.g. for a resequencins section including -~ 35 transmission links of several kil~meters. Sinee in that .
.: ' : ,;.

2 ~

- 5 - H. VERHILLE - M. HENRION - M
DE SOMER - B. PAUWELS 13-2;-5-8 case it is almost impossible to use common clock means for providing the time stamp values both at the inPuts and at the output of the resequencing section, a first idea i5 to ~ us~ t~o distinct clock meanss first clock means located at ; 5 the inputs and second clock means located at the output.
Obviously, these first and second clock means needs to be synchroni~ed with accuracy.
Although solutions are known for synchronizing two ~ clock means in frequency. none of these suggests to ; 10 synchronize them in phase with the accuracY required ~or - this type of application. Accurate phase sYnchronization is however imPOrtant in the present case since no precise cell resequencing oan be per~ormed if there is no common time Phase reference for both the first and the second time , 15 stamp values, i.P. if they cannot be accurately correlated in Phase or if their phase di~ference cannot be determined with accuracy. ConverselYJ it is not strictly necessary that the first and the second clock means are fully synchronous in frequencY as long as their phase difference ZO can be determined.
Another ob~ect o~ the Pre~ent inv~ntion is to ' provide a cell resequencing system of the abova known type `1 but which is adapted to a geographically distributed j multilink talecommunication network, l.e. which is able to operate on a relativelY large resequencing section.
According to the present invention 9 this other ob~ect is achieved due to th~ fact that said cell resequencing system ~urthar includess ; - first clock means producing successive first time stamp values which are associated to said cells at each of said inputs;
second clock means Producing -~ucc~ssiv~ second ti~e stamp values for controllin~ said latching ~aans; and - clock compensation means adaPted to compensate both said fixed trans~er d~lay and a clock phase shift between said ~.:
;~ ~;;k~
, .

. :'~' , .i .. ' ' ' " ,', . ' ' ', ':!`. . . . ' . . . . . .. .. .. , .

- 6 - H. VERHILLE - M. HENRIDN - M.
DE SOMER - B. PQUWELS 13-Z7-5-8 first and said second clock means.
In more detail, said clock compensation means perform said compensatiDn as a function of a time stamp compensation value which is substantially equal to the sum of a time stamp offset value and of said fixed transfer delay, said time stamp of~set value being substantially equal to the difference between a said first time stamP
value and a said second time stamp value simultaneously produced by said first and said second clock means respec~ively.
In this way, the phas~ difference between the first and the second clock means is expre~sed by means o~ the time stamp offset value.
Also another chara~teristic feature of the present -~ 15 invention is that clock compensation means are coupled between each of said inPuts and the transmission link coupled thereto.
Still according to the present invention, said res~quencing section further includes buffer means each couplad b~tween said clock compensation means and the j transmission link coupled thereto.
If the resequencing section starts from a switching node, the latter generally includes buffer means or outPut I queues located between the cutlets of its switching network ¦ 25 and the f~llowing transmission links. Because the cells I are in sequence at the outlets of this switching network but maY be sub~ected to a variable latching delay in the buffer means, the rese~uencing section starts at these outlets rather than at the outPuts of the switchins node.
In other words, the outlets of the switching network constitute the inpu~s of the resequencin~ section. In that l , , .
case huwever, the delay during which a call is latched in the bu~fer ~eans for~s part cf the above first variable tlme delaY-Furthermore, because some circuitry relative of a ~ ' :

, , .
, ,~ ,: ,, : ,: . : : ;: . i,. . . : . . - . . . . . . . . . .

2 ~

- 7 - H. VERHILLE - M. HENRION - M.
DE S0MER - ~. pAUWELS 13-27-5-8 - preceding cell resequencing system is generally located at the outlets of the switching network, th~ clock compensation means are preferablY located at these outlets, i.e. at the inputs o~ the resequencing section.
The Present invention al50 relates to a method ~r correlating in phase a first cloek means producing `. succ~ssive first time stamp values with a second clock means producing successive second time stamp values, both said clock means formin~ part of a telecom~unication `~ lO network and being interconne~ted bY at least one transmission link.
As alread~ mentioned, for resolving the above cell resequencing problem it is important to correlate in phase the two clock means with a relatively high accuracy. This phase correlation may either consist in synchronizing in phase the first and the second clock means or in determining their phase dif~erence which then will be taken into account for performing the cell resequencing.
, According to th~ invention. the method for Z 20 correlating in phase the two clock means is characterlzed in that said first clock means sends a then produced first : -time stamP value to said second clock means via said ,Z transmission link and that said second clock ~eans produces a second time st~mp value upon receipt of said first time ~l 25 stamp value wherebY a time stamp compensation value is i determined at the location of said s~cond olock means, said ! ~ime stamp compensation value beins substantially equal to the di~ference between said second and said ~irst tim~
I st~mp values and being function o~ both the phase shift . .
: 30 between said first and second clock means and ~ fixed j transfer delaY which is equal to the minimum delay neQd~d ~: :
for transmitting a time sta~P v~lue betweQn-said clock ~i means.
j AlternativelY~ upon rsceipt of said first time stamp ::
: . .
value, said second clock means i~mediately returns the then ..~ .~ . ' ~ :. -.. .
. .
Z , ~.

2 ~ 8 ::

'- - 8 - H. VERHILLE - M~ HENRION - M
~E_SOMER - ~. P~UWELS 13~2;-S-8 produced second time stamp value to said first clock means whereby said time sta~p compensation value is determined at the location of said first ~lock means.
; Another ~haracteristic ~eatura of the present method is that a time stamp offset value is determined at said ;` location of said first clock means, said time stamp offset value being equal to the difference between said second time stamp valua and the half of the sum of said first time stamp value and another first tim~ stamp value produced by said first clock means upon receipt of said second time ' stamp value from said second clock means, and corresponding '' to the difference between a said ~irst time stamp value and ;, ' a said seccnd tlme stamp value simultaneously produced by '~ said first and said second clock means respectively.
'~ 15 Also another characteristic feature of the Present '~ method is that said fixed transfer delay is determined at ' said location of,said first clock ~eans as being ,I substantially equal to the hal$ of the difference between said other first time st3mp value and said first time stamp value.
,~l In the Present invention, said fixed trans~er delay l is substantially,equal to the difference between said time Z' stamp comPensation value and said time stamP o~fset value, ~, and said first and sccond time stamp values are each Z5 carried by a cell of said telecommunication n~twork, said ' l cells being transmi,tted over said transmission link.
,~ As a result, the present method suits perfectly to ` the abo~e cell resequencing sYstem.
''~, , The above mentioned and other obiects and features ,~ 30 of the invention will become morQ apParent and the ~ inYention itself will be best understood by referring to l the followlng descriPtion of an embodiment taken in ,~ con~unction with the accompanYing drawings wherein: -Fig~ 1 shows a resequencing section RS including a ~; 35 cell resequencing system Cll~Cln/ClN, CKl, R21/R2m~R2M and .. ~ , ... .
'I ~ - .
. ~ .

2~5 ~

- 9 - H. VERHILLE - M. HENRION - M.
DE SOMER_=_B. PQ~ 13-27-~-8 CKZ according to the invention;
Fig. 2 shows a telec~mmunication network including at least one resequencing section as shown in Fig. l; and Fig. 3 is a time diagram of the transmissions of time stamp values tA1, tA2 and tB of two clock means CKl and CK2 to be correl~ted in phase according to the m~thod of the present invention.
The resequencing section RS shown in F19. 1 forms part of a multilink self-routing cell switching 0 telecom~unication network through which cells or packet of in~ormation are transmitted ~rom an input to an output (both not shown on Fig. 1). The telecommunication network includ~s at least two switching nod~s Nl 7 NZ interconnected ~ -by means of transmission links TLl~TLn~TLN.
In more detail. the switching node N2 has node inputs I21~I2n~I2N and node outPUts 021~02m~02M and includes an asynchronous cell switching natwork SN2 having inlets I21~I2n~I2N corresponding respectiv~ly to the like ~;~
named node inputs of N2, and has outlets N21~N2m~N2M. SN2 is able to transfer a cell received ~t anYone of its inlets to at least one of its outlets. Each outlet N21~N2m/N2M of SNZ is connected to a respective resequencing circuit R21~R2m~R2M including like na~ed latchlng means also called resequQncing buffers and used for storln~ the çells during j,~
Z5 ~ variable time dclay as will be expl~ined later. The outputs S21~S2m~S2M of the resequencin~ circuits R21~R2m~R2M correspond to the like named outputs ~ the resequencing section RS and are coupled to th~ node outputs 021~02m~0ZM via the series conne~ti~n of control units CZl~C2m~C2M and output queuQs Q21/Q2m~Q2M respectiv2ly.
Finally. the switching nods N2 is Provid~d with clock means . .
CK2 controllin~ the operation of both thc ~witching netwDrk SN2 and the resequencing cirçults R21~R2m/R~M.
The switching node Nl is similar to the switching nod~ N2 but onlY outlets Nll/Nln~NlN. res~quenclng circuits ~ . . .
.
~ . ~

.:

2 ~

- 10 - H. VERHILLE - M. HENRION - M.
DE SOMER - B. PAUWELS 13-Z7-5-8 Rll/Rln/RlN, switching outputs Sll/Sln/SlN which correspond to the like named inputs o~ the resequencing section RS, control units Cll~Cln/ClN, output queues Qll~Qln/QlN, node outputs 011/Oln/OlN and clock means CKl are shown.
The present multilink telecommunication network has a plurality o~ transmission links TLl, ..., TLn, ..., TLN
each interconnecting a node output Oll/OlnfOlN of the node Nl to the corresponding node inputs IZl/I2n/I2N of the node N2. This telecommunicaiton network is o~ the type disclosed in the European Patent APplication EP 91201915.5 (VERHILLE 11~ wherein the node outPuts Oll/Oln~OlN of Nl and thus also the transmission links TLl/TLn/TLN are arranged in a "link group~ LG. This means that the cells to be transmitted from Nl to N2 are dynamically distributed in Nl-ovar all these node outputs and thus also over these transmission links. This is also true for cells belonying to a same communication. A better use of the differant paths, e.g. transmission-links, which may be followed by the cells is so obtained.
Since the cells ~ollow different paths, theY are sub~ected to dif~erent delays during th~ir transfer through the telec~mmunication network. As a consequence, a cell recequencing needs to be performed, this cell rese~uencing consisting of supplying at an output S21~SZm/S2M of the resequencing section RS the cells in the same order or sequence as they were applied to the inPuts Sll~Sln~SlN of this section.
Based on the teaching of the International Patent APplication PCT~EP89/00941 (HENRION 17~ applied to t~e present case, a suitable cell rese~uencing method consists lns - associating to each cell arrivin~ at anY of the inputs Sll~Sln~SlN of the rese~uencing section RS a ~irst ti~e stamp value then generat~d by a time sta~p gen~rt~tor or clock means~

..--.

- 2 ~

- 11 - H~ VERHILLE - M. HENRION - M.
DE SOMER - B. PAUWELS 13-27-5-8 - receiving this cell in a resequencing buffer R21/R2m/R2M
a~ter a first variable time delay needed by the cell for being transferred fr~m the inPut S11/Sln~S1N to an outlet N21~N2m~N2M of the switching network SN2; and 5 - relaasing this cell from the resequencing buffer RZl/R2m~R2M t~ the eutput S21~SZm~SZM after a second variable time delay which so chosen that the sum of the first and the seccnd variable time delay is equal tc the predetermined c~nstan~ tim~ value i.e. only when thq clock 10 means generates a second time stamp value which is such that the difference between this second tima stamp value and the ~irst time stamp ~alue is equal te the . predetermined constant time value. :.
.-. However in the last mentioned patent application.
15 the cell resequencing operation is performed in a resequencing section RS which only includes one switching network SN2 i.e. between the inlets I21/I2n~I2N and the outputs S21/SZm/SZM and wherein both the fir~t and the second tlme stamP values are generated bY a same clock 20 means. e.g. CKZ.
It is known from that document that the size ~ the ~I resequencing buffers R21~R2m~R2M is proportional to thepradetermined constant time value and thus increases with the fir~t var~able time delay needed by the cell for being 5 25 transmitted from the inlets I21~I2n~I2N to the outlets ~ -N21~NZ~N2M of the switching network SN2. It is further ;: ~:
clear that the probability to succeed the cell resequencing operation al50 increases with this predetermined constant : .
time value. In theory the pr~determined constant time 30 value should be chosen at least equal to the maxi~um j transmission delaY required by anY cell to be transmitted 9 fro~ an inlet I21~I2n~I2N to an outlet N21~N2~N2M but such - ...
a large predet~rmined constant time value will raquire .:
.i~ r~l~tivelY large resaqu2ncing buffers R21/R2m~R2M. i j 35 Therefore in prac~ice the predetermined constant time i, . ..
.J ... - .
~`. ~ ,' .

d~. ~ 8 - 12 - H. VERHILLE - M. HENRION - M.
DE_SOMER - B. PAUWELS 13-Z7-5-8 value is so chosen that the probabilitY that the cell resequencing operation fails, i.e. that the variable delay incurred by a cell exceeds the predetermined constant time value~ is so small that is results in ne~ligeable cell 5 loss, whilst the size of the resequencing buffer remains acceptable, i.e. relatively small. Moreover, this known cell resaquencing method does not relate to a resequencing section RS of a multilink telecommunication network as mentioned above, nor to a resequencing section RS includiny lO relative long transmission links TL1~TLn/TLN, e.g. of several kilometers, arranged in a link group LG.
In ihe~present case how~ver, the resequencing section RS starts at the outlets Sll/Sln/SlN of the switching network SN1 of the nod~ Nl and includes, , 15 additionallY to the switching netwDrk SN2 and the J resequencing circuits R21/R2m/R2M, output qUQUes Qll~Qln~QlN and a link grouP LG of tra~smission links I TLl/TLn~TLN which ~ay imply short or long distances.
B~caus~ of the possible long distance between the 20 nodes Nl and N2, two distinct clock means CKl and CK2 are used instead of the above single common clock means controlllng both the inputs and the outputs o~ the resoquencing section RS. These clock means CKl and CKZ
hav~ to be synchroniz2d in phase or, if not, additional 1 25 means have to be Provided to determine their ralativ~ Phase ;I shlft or phase difference, i.~. their Phase decorrelation, wlth a r~lative high accur3cY.
`, The-~irst time stamp values are generated by the `l clock means CKl and ar~ associated to the incoming cells bY
30 control units C11/C1n~C1N each coupled to a distinct input S11~S1n/SlN of RS and controlled by CK1. Because the cells i to keeP in sequence are not all co~ming fro~ a single switching output S11~S1n~S1N of N1 but may arriYe at any input S11~S1n~S1N of the resequencing section RS, these ~i 35 cells ar~ in a ~relative" sequence at th~ level of these :~ .
.

2 ~ 8 - 13 - H. VERHXLLE - M. HENRION - M
DE SOMER - B. PAUWE~S 13-27-5-8 inputs Sll/Sln~SlN. Furthermore, because these cells maY
be subjected to differe~t delays in the different output queues Qll~Qln~QlN of Nl, the control units Cll~Cln~ClN
need to be located before these ~utput ~ueues Qll~Qln~QlN, ~; 5 the latter precedin~ the transmission links TLl~TLn~TLN.
The sec~nd time stamp values are generated by the clock means CK2 for controlling the operation of the resequencing circuits R21~R2m~R2M.
As already mentioned, the size of each resequencing 10 buffer R21~R2m~RZM is a function of the above first variable time delay which, in the present case, includes the latching delay caused by the outPut queue Qll~Qln/QlN, the transmission delay of the cell over the transmission link TLlTLn/TLN and the delay caused by the switching 15 network SN2. If the sum of these delays is to be taken into account for determining the size of each of the resequencing buffers R21/R2m~R2M, this size will become tou large, i.e. unaccepatable.
~1 To reduce this size, the first variable t~me delay j 20 could theoretically be rqduced by an ebsolute minimum transfer delay below which no cell can be transmitted from any inPut Sll~Sln/SlN of RS tc any outlet N21~N2m/N2M of SN2. However, for Prac~ical reasons, this theoreticaI
1 ab~olute minimum trans~er delay is replaced by a minimum `1 25 transmisslon delaY below which no cell can be transmitted ~! over a transmission link TLl/TLn~LN, i.e. between th~
ncde output Oll/Oln/OlN and the node inPUt IZ1~I2n/IZN
i raspectivaly. This minimum transmission delaY is easier to l determine, e.g. by measurement or by engineering, than the J 30 theorical absolute minimum transfer delay and ~he appr~ximation so performed is negligible. Further in this dascription, the minimum transmission delay will be referred to as fixed transfer delaY TD.
The first time stamps values generated by the clock ~-`1 35 means CK1 are thus compensated for the fixed transfer delaY
,., ' ', - 14 - H. VERHILLE - M. HENRION - M.
~E SOMER - B. PAUWELS 13-Z7-$-8 TD. This is performed bY time stamP compensation circuits prcvided in the like named control units Cll~Cln~ClN (not shown in detail). Each time stamp compensation circuit Cll~Cln~ClN adds to the first time stamp value generated by CKl the fixed transfer delay TD corresponding t~ the ~ transmissi~n link TLl~TLn~TLN respectively coupled thereto.
`I Instead of being provided in the contr~l units Cll/Cln~ClN, the time stamp compensation circuits may also be loeated between the transmission links TLl~TLn~TLN and the inlets I21~I2n~IZN of the switching network SN2.
H~wever in that case two handlings of the cells ar0 necessaryt a first in the control units Cll~Cln~ClN for associating first time stamp values to the cells and a second one in the se~arated time stamp ciDmpensation circuits for modifYing these ~irst time stamp values.
Al~o another solution is to loc~te a common time stamp compensati~n circuit at the level of the resequencing ;,, clrcuit R21~R2m/R2M. Although this solution is equivalent ;3 to the precedin~ ones in case o~ a single transmission link between Nl and N2, it becomes almost imPossible to imPlement in the case of a link group LG of transmission links TLl~TLn~TLN between these two nodes. Indaed, in that case, one ignores from which inlet I21~I2n~I2N of SNZ the cell is coming, i.e. to which fixed transfer delay th~
cell was sub~ected prior to reach this inlet. Thus, one al50 ignores which time stamp compensation has to be applied to each individual cell. As a consequence, a c~ll resequencing mechanism starting at th~ level o~
resequencing circuit R21~RZm~RZM should have no meaning.
l 30 The onlY possibility would then be to take into account a ;i minlmum fixed transfen delay TD ~hich is the l~west fixed l transfer delaY amonsst those corresponding to each o~ the `~ ~ individua} transmission links TLl/TLn~TLN of the llnk group LG. As a result, the sizes of all the resequencing buffers ; 35 R21~R2m~R2M o~ the node N2 are then determined by this ':

` 2 ~

- 15 - H. VERHILLE - M. HENRION - M.
D~ -snMER - B. PAUWEL$ 13-27-5-8 single minimum fixed transfer delay TD and are thus identical but not optimized.
Up to now it was considered th3t the two clock me~ns CKl and CK2 were in phase. From now, one will explain how to compensate a possible phas~ shift or Phase difference between the two clock m~ans, i.e. when thes~ clock means are not correlat~d in phase.
An example of a telacommunication network including several rese~uencing sections RSl. RS2 between an input IN
and an outPut OUT, e.g. the nod~ output 02m of ~he switching network N2, is shown in Fig. 2. This telecommunication network includes three parallel branches , through which a ce}l may be transmitted from IN to OUT.
,, Each branch includes at least ~ transmission llnk or a link grouP labell~d with a prefix L and a switch~ng node , labelled with a prefix N. The first Nl and th~ last N2 ;l switching nod2s of the telecommunication network are common ~ for the three branches.
,l The first resequencing section RSl of the telecommunication ne~work shown in Fig. 2 ~nly inoludes the switching node Nl. Since the cells are applied at the single node input IN and exit at anyone of the switchlng outputs Sll~Sln~SlN and so further at the node outputs Oll~Oln~OlN arranged in a link group LGI. this first ~`
resequancing section RSl between IN and Sll~Sln~SlN is simil3r and maY be compared to the one described in the ~
above mentioned International Pa~ent Application ~ ;
PCT~EP89~009~1 (HENRION 17). Moreover, although the cells ., .
are dynamicallY distribut~d over the switching ~utputs ¦ 3D Sll~Sln~SlN of Nl, they ~ppear in a rela~ive correct order ~; or sequence at thes~ outputs.
. ~ . .
It is to be not~d that instead of b~ing single node ~i outputs. Oll~Oln~OlN may als~ be Rach constitut~d b s~veral nods ouPuts of Nl~arranged in link groups ~i , i 35 Ll3~L15~Ll7 respectiv~lY. Th~se link groups L13~Ll5~L17 ,! ~ :. ' ;i ,1 , .,', '. ' ,' '.
j:',;~: '.

- 16 - H. VERHILLE - M. HENRION - M.
DE SOMER - B. PAUWELS 13-27-5-8 form together a common link grDup LGI of the output of N1.
Obviously, the same applies to the corresponding switching outputs Sll~S1n/SlN.
The second resequencing section RSZ of the telecommunication network includes the three parallel . branches. The first branch includes the series connection of L13, N3, L34, N4, L42 and N2, the second branch includes ; L15, N5~ L56, N6, L62 and N2 and th~ third branch includes : .L17, N7. L7Z and N2. The link groups L42, L6Z and L7Z are arranged in a bigger link group LGO arriving ~t the node , inputs of N2.
- The inPuts of th~ second resequencing section RSZ
are the switching outputs Sll~Sln/SlN of the switching network included in the node Nl and the outputs of RS2 are :
the switching outputs of the switching network included in , . .
the node NZ, the latter switching outPuts and the sw$tching networks of Nl and N2 being not shown in FigO Z. Within RSZ, none of the switching nodes needs to be Provided with control units for associating ~irst time stamp values to each cell, and only the switching node N2 needs to be ~ provided with a resequencing circuit RS2m controlled by : second time stamp values.
In an alternati~e e~bodiment, the telecommunication network is provided with a singl~ resequencing section constituted by the combination of RSl and RSZ in series.
In such an end- to- end cell resequencing system, the -switching node Nl needs only to be provided with ona ..
, control unit which associates a first time stamp value to ;l each cell arriving at the single input IN.
In the latter cases of one or two resequencing ,::
sactions~ the fixed transfer delay TD is chosen equal to a minimum fixed trans~er delay which is the lowest .~ transmission delay amonsst the three following values~ the sum c~ the mini~um transmission delaYs over L13, L34 and 35 L42 in series; the sum o~ the minimum transmission d~lays ...
.'~~ : ',. ' : ~j .. .

2 ~ 8 - 17 - H. VERHILLE - M. HENRION - M.
DE SOMER - B. PAUWELS 13-2Z~5-8 over L15, L56 and L6Z in series; and the sum of the mini~um transmission delays over L17 and L72 in series.
Alternatively, the second resequencing section RSZ
may also be replaced by several smaller resequencing sections each including a pair of a link group L and a switchin~ node N, i.e. L13, N3; L3~, N4; L42, N2; L15, N5;
; L5~, N6; L62, N2; L17, N7 and L72, N2. In such a section-by- section cell resequencing system, e~ch switching node Nl to N7 needs to be provided with resequencin~ circuits.
However, it has the advantage that the resequencing buffers of the individual switching nodes N3, N4, N5, N6, N7 and N2 are relativelY smaller than the single rese~uencing buffer of the switching node N2 in the above embodiments. Because of the Parallel branches, this section by- section cell resequencing system in not easy to i~plement in the present ¦ case. However, in a simplified version (not shown in ; ., ~
detall) o~ this telecommunication network, for instance including only one branch with the resequencing sections Nls L13, N3; L34, N4 and L42, N2 in series, each switching node Nl, N3, N4 and NZ ~ay include its own resequencing circuits. In such a simple section- by- section c~ll resequencing system, the resequencing of the cells is ¦ ; performcd in each resequencin~ sectiun by taking into account fixed transfer delay TD which is equal to the minimu~ transmission delay o~ any cell over each of the transmission links of the link group L ~orming part of this !', resequencing section, i.e. L13, L34 and L42.
As alreadY mentioned and by making again reference to Fig. 1, additionallY to the nec~ssity of comp~nsating the absolute transmission delaYs between the inputs .
Sll~Sln~S1N and the output 521~52m~S2M of a rssequencin~ -section RS by the fixed transfer delay TD in order to keeP
~, the resequencing buffers R21~R2m~R2M within an acceptable size~ another problem raises with a geographically distributed telecommunication network. Indeed, because of ' ' '.~:

. . .

2 ~

- 18 - H. VERHILLE - M. HENRION - M.
DE SOMER - B. PAU~LS 13-27-5-8 the relatively long transmission links TL1~TLn~TLN of the link group LG, it is difficult to provide a sin~le clock means which is able to generate simultaneously a same tim0 reference accurately synchronized in phase, i.e. a same time stamp value with typically lQO nano~iecond phase difference, both at the location of the time stamp ;~ compensation circuits and at the location of the resequencing circuits R21~R2m~R2M. Therefore, two clock : means CKl and CK2 are provided: CK1 bein~ associated to the control units C11~Cln~ClN of the sw~itching node N1 and CK2 being associated to the resequencing circuits R21/R2m/R2M
of the switching node N2. These two clock means CK1 and CK2 are synchronized in frequancY but not in phase and their mutual out-Phasing or relative Phase shift needci to ~` 15 be correlated for obtaining coherent time stamp values. `
The phase shift or phase difference betwe0n CKl and CK2 is expressed by a time stamp compensation or offset value TOC
as will be exPlained below.
j In the following part o~ the description, only one ;1 20 resequencing section RS as shown in-Fi~. 1 will be considered by waY of an examPle for describing the cell resequencin~ mechanism. This description can easilY be extended to a more comPlex telecommunication network, e.g.
as hown in Fig. 2, using either the section- by- sectian 25 cell resequencing, the end- ~o- end cell resequencing or a `
combination o~ both.
A common solution for the above two problems, i.e.
of the transmission delay compensation and of-the phase ,:
correlation or correctian of the out-phasing Df the two clock means, consists in performing an appropriate modificat~on on the first time stamp values generated by ~ ~h~ clock means CK1 and associated to each lncoming cell at ;~ thc-inputs S11~51n~SlN. This modification should compensate for both the fixed transfer delay TD and tha ;
~lme stamp offset value TOC.

1 ~ , .

~, ~

2 ~ 3 8 - 19 - H. VERHILLE - M. HENRION - M.
DE SOM~R - B. PAUWELS 13-27-5-8 The ~ixed transfer delay TD can be obtained aither by network engineering, i.e. by calculating it as a function of the physical length of the transmission link . :
;~ TLl~TLn/TLN, or bY measurement at an initialization time, i.e. without traffic on the measured transmission link TLl~TLn~TLN and without latching delays in th~ output queue ;~ Qll~Qln~QlN coupled thereto respectively.
For determining the time stamp offset value TOC, different approaches are possible and will be analYzed 10 below. --; A first approach consists in sYnchroni~ing in phase and in frequencY the clock means CK1 and CK2. The time stamp offset value TOC will then be reduced to zero since a ;~ sam~ tim~ stamp vaIue will at a sama moment, i.e.
simultaneously, be avall3ble at any Point of the network.
However, as already mcntioned, this i~ difficult to realize ! in practice because o~ the required high phase accuracY-e.g. of about 100 nanosecond, and of the long distancas, e.g. several kilometers, between the switching nodes Nl and N2.
A second approach consists in synchronizing in frequency the clock means CKl and CKZ and in determining their out-phaslng or phase shift, l.e. the compensatin~
time sta~P offset value TOC, at initialization time on the '~ 25 basis of pra-engineered network parameters. How~var, in this case the Pre-engineering is very oomplex and the pre-initialization and subsequent monltoring of the clock ; :, . .
phasc shifts for each teleco~munication network practically rules out this approach.
A third and preferred approach consists in , detarmining th~ phase shift between the clock ~eans CKl and ;~ CKZ which may run either ln a synchronou or in a ~-plesiochronous frequency node. In ~act, it is not strictly necess~ry that the clock m2ans CK1 and CK2 arR fully ~i~ 35 synch~onous in frequency as leng as we are able to ~ , , :~ , ' -:.
.~, ' .;, ~ ' 4~ 1 8 ' - 20 - H. VERHILLE - M. HENRION - M.
DE SOMER - B. PAUWELS 13-27-5-8 additionally determine their relative phase shift. In this approach, the phase shift between the clock means CK1 and CK2 is measured on a quasi- continuous basis and no pre-engineering is required.
A method for measuring the phase shift between the ; clock m~ans CKl and CK2 and subsequently determining a time stamp compensation value TTC in order to obtain a common compensation for both the transmission delaY and the phase shift is desoribed below by making raference to Fig. 3 which shows i~n example of time stamp values generated by the two clock means CKl and CK2.
In this example, the measurements are performed at a location A which corresponds to the transmitter end of a transmission link TL1fTLn/TLN of Fig. 1, i.e. at a node output Oll/Oln/OlN of the switching node Nl, and at a location B which corresponds to the receiver ~nd of a j transmission link TLl/TLn/TLN, i.e. at the looation of an inlet I21/I2n/I2N of the switching network SN2.
`i It is to be noted that the location A pre~errably corresponds to the switching outputs S11/Sln/SlN because the control units Cll/Cln/ClN controlled by the clock CKl I are already present at that location. However, the `! measurements-are then o~lY validely performed during the ~ -;i pre-initialization of the telecommunication net~ork. i.e.
without telec~munication trafic, so that the variable ~l latching delays in the output queues Qll/Qln~QlN are then ,I reduced to zero.
~, In the example given at Fig. 3, at the start of the measurement the clock means CKl. associated to the location A. generates a time stamp value O whila the cloek ~ean CK2. associated to the location B, simultaneously generates a time stamP value 25. In this example, the ti~e stamP
~: : offs2t value TOC is thus equal to 25 and th~ fixed transfer ~delay TD is set equal to 35O As a result, the time stamP
compansation value TTC, which is equal to the sum of the :1 .
1 : , :. . .

'~:

` 2 ~ d ~ 8 : :
- 21 - H. VERHILLE - M. HENRION - M.
DE SOMER - B. PAUWEL 13-Z7-5-8 ; time stamp offset value TOC and the fixed tr~nsfer delaY
TD, is equal to 60 and the following relation may be writtens TTC = TOC ~ TD (1) By means o~ telecommunication cells used as carriers over the transmission link TLl~TLn~TLN, the clock means CKl and CK2 exchange time stamP values. For instance, when the clock means CK1 generates a first time ~tamp value tAl =
30, the latter is sent to the clock means CKZ. While .~, . . .
10 receiving the time stamp value tA1, the clock me~ns CK2 generates a s~cond time stamp value tB = 90. This clock means ZcKz then immediately returns its Z3enerated tim~ stamp value, i.e. tB = 90, to the clock means CKl. While receiving the time stam~ value tB, the clock means CKl Z 15 gen~rates another first time stamp valu~ tA2 = 100.
¦ At the location A, the time stamp of~set value TOC
iç then determined ass :-TOC = tB - (tA1 + tA2)~2 (2) and the fixed trans~er delaY TD is determined ass ZO TD = (tA2 - tA1)~Z (3) ' Both at the locations A and B, the time stamP
compensation v~lue TTC maY be datermined as~
~ TTC = tA - tA1 (4) `3 The values of TOC and TD may be obtained in a ! 25 similar way at th~ location B. This procedure is obvious ~ and thcrefore not described in detail here.
-Z In case the two clock means CK1 and CK2 ar~ ~
synchronized in ~requency, the abov~ measurements needs to ;
;~ be performed only onc~, e.~. during the ini~ialization ~J 30 phase. Howeveri if these-clock means CK1 and CK2 operate in a plesiochronous mode. the continuous frequercy shift ~1 requires variable phase comPensation Para~eters and the Z~ ~ above measurement has to be rep~ated periodically.
l~ A~ already mentioned, ~he measurement should not be Z 35 af~ected by any significant variable delay component such ~:Z ',':
,,';i ' :.:, 2~3~ ~8 - 22 - H. VERHILLE - M. HENRION - M.
DE SOMER B. PAUWEL~ 13-27-5-8 as a latching delay in an output queue, e.g. prior to return a time sta~p value. Moreover, it i5 assumed that the transmission delay is the same from A tD B and from B
to A over a pred~termined transmission link TLl/TLn/TLN.
This assumPtion is however no longer necessary when onlY
the time stamp compensation value TTC is used for compensating simultaneously both the time stamp offset value TOC and the fixed transfer delaY TD fro~ A to B.
While the principles of the invention have been described above in connection with specific apparatus, it - is to be clearly understood that thls description is made only by way of example and not as a limitation on the scope of the invention.

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Claims (17)

1. Cell resequencing system for a resequencing section (RS) of a telecommunication network through which cells of communications are transmitted, said resequencing section having at least one input (S11/S1n/S1N) and at least one output (S21/S2m/S2M) and including at least one cell switching network (SN2) having at least one inlet (I21/I2n/I2N) coupled to said input and at least one outlet (N21/N2m/N2M), the cells transmitted from said input to said outlet being subjected to a first variable time delay and said cell resequencing system (C11/C1n/C1N, CK1;
R21/R2m/R2M, CK2) including latching means (R21/R2m/R2M) coupled between said outlet and said output and adapted to subject said cells to a second variable time delay which is so chosen that for each cell the sum of said first and second variable time delay is substantially equal to a predetermined constant time value, said predetermined constant time value determining the size of said latching means, characterized in that said resequencing section (RS) has at least two of said inputs (S11/S1n/S1N) each coupled to a distinct inlet (I21/I2n/I2N) via a distinct transmission link (TL1/TLn/TLN), said inputs and said transmission links being arranged in a link group (LG), that said cells are supplied at anyone of said inputs of said link group and are subjected to at least a fixed transfer delay (TD) during their transfer from said input to said outlet (N21/N2m/N2M), said fixed transfer delay forming part of said first variable time delay, and that the minimum size of said latching means (R21/R2m/R2M) is determined by the difference between said predetermined constant time value and said fixed transfer delay (TD).

2. Cell resequencing system according to claim 1, characterized in that said fixed transfer delay (TD) is substantially equal to the minimum transmission delay below which no cell can be transmitted over a transmission link (TL1/TLn/TLN) of said link group (LG).

3. Cell resequencing system according to claim 1, characterized in that said resequencing section includes a plurality of switching networks (N1, N3, N4, N2) interconnected by link groups (L13, L34, L42) of transmission links and that said fixed transfer delay (TD) is substantially equal to the sum of the fixed transfer delays of said link groups.

4. Cell resequencing system according to claim 1, characterized in that said telecommunication network includes a plurality of series connected resequencing sections (L13/N3, L34/N4, L42/N2), each resequencing section including a link group (L13, L34, L42) of transmission links connected in series with a switching network (N3, N4, N2).

5. Cell resequencing system according to claim 1, characterized in that said resequencing section includes a plurality of parallel branches (N1, L13/N3, L34/N4, L42/N2;
N1, L15/N5, L56/N6, L62/N2; N1, L17/N7, L72/N2), each branch comprising at least one link group (LGI; L13, L34, L42; L15, L56, L62; L17, L72; LGO) of transmission links, each link group being connected in series with a switching network (N1, N3, N4, N2; N1, N5, N6, N2; N1, N7, N2), and that said fixed transfer delay (TD) is substantially equal to the lowest sum amongst the sums of the fixed transfer delays of the link groups of each branch.

6. Cell resequencing system according to any of the previous claims, characterized in that said switching network (SN2) is adapted to transfer the cells from anyone of said inlets (I21/I2n/I2N) to at least one of said outlets (N21/N2m/N2M).

7. Cell resequencing system according to claim 1 characterized in that said cell resequencing system (C11/C1n/C1N, CK1; R21/R2m/R2M, CK2) further includes:
- first clock means (CK1) producing successive first time stamp values (tA1, tA2) which are associated to said cells at each of said inputs (S11/S1n/S1N);
- second clock means (CK2) producing successive second time stamp values (tB) for controlling said latching means (R21/R2m/R2M); and - clock compensation means (C11/C1n/C1N) adapted to compensate both said fixed transfer delay (TD) and a clock phase shift between said first and said second clock means.

8. Cell resequencing system according to claim 7 characterized in that said clock compensation means (C11/C1n/C1N) perform said compensation as a function of a time stamp compensation value (TTC) which is substantially equal to the sum of a time stamp offset value (TOC) and of said fixed transfer delay (TD), said time stamp offset value being substantially equal to the difference between a said first time stamp value and a said second time stamp value simultaneously produced by said first (CK1) and said second (CK2) clock means respectively.

9. Cell resequencing system according to claim 7, characterized in that clock compensation means (C11/C1n/C1N) are coupled between each of said inputs (S11/S1n/S1N) and the transmission link (TL1/TLn/TLN) coupled thereto.

10. Cell resequencing system according to claim 9, characterized in that said resequencing section (RS) further includes buffer means (Q11/Q1n/Q1N) each coupled between said clock compensation means (C11/C1n/C1N) and the transmission link (TL1/TLn/TLN) coupled thereto.

11. Method for correlating in phase a first clock means (CK1) producing successive first time stamp values (tA1, tA2) with a second clock means (CK2) producing successive second time stamp values (tB), both said clock means forming part of a telecommunication network and being interconnected by at least one transmission link (TL1/TLn/TLN; LG), characterized in that said first clock means (CK1) sends a then produced first time stamp value (tA1) to said second clock means (CK2) via said transmission link (TL1/TLn/TLN) and that said second clock means produces a second time stamp value (tB) upon receipt of said first time stamp value whereby a time stamp compensation value (TTC) is determined at the location (B) of said second clock means, said time stamp compensation value being substantially equal to the difference between said second and said first time stamp values and being function of both the phase shift between said first and second clock means and a fixed transfer delay (TD) which is equal to the minimum delay needed far transmitting a time stamp value between said clock means.

12. Method for correlating in phase a first clock means (CK1) producing successive first time stamp values (tA1, tA2) with a second clock means (CK2) producing successive second time stamp values (tB), both said clock means forming part of a telecommunication network and being interconnected by at least one transmission link (TL1/TLn/TLN; LG), characterized in that said first clock means (CK1) sends a then produced first time stamp value (tA1) to said second clock means (CK2) via said transmission link (TL1/TLn/TLN) and that said second clock means, upon receipt of said first time stamp value, immediately return a then produced second time stamp value (tB) to said first clock means whereby a time stamp compensation value (TTC) is determined at the location (A) of said first clock means, said time stamp compensation value being substantially equal to the difference between said second and said first time stamp values and being function of both the phase shift between said first and second clock means and a fixed transfer delay (TD) which is equal to the minimum delay needed for transmitting a time stamp value between said clock means.

13. Method according to claim 12, characterized in that a same transmission link (TL1/TLn/TLN) is used for transmitting said first time stamp value (TA1) from said first (CK1) to said second (CK2) clock means and said second time stamp value (tB) from said second to said first clock means, whereby said fixed transfer delay (TD) is substantially identical for transmitting both said first and second time stamp values.

14. Method according to claim 12, characterized in that a time stamp offset value (TOC) is determined at said location (A) of said first clock means (CK1), said time stamp offset value being substantially equal to the difference between said second time stamp value (tB) and the half of the sum of said first time stamp value (tA1) and another first time stamp value (tA2) produced by said first clock means upon receipt of said second time stamp value from said second clock means (CK2), and corresponding to the difference between a said first time stamp value and a said second time stamp value simultaneously produced by said first and said second clock means respectively.

15. Method according to claim 14, characterized in that said fixed transfer delay (TD) is determined at said location (A) of said first clock means (CK1) as being substantially equal to the half of the difference between said other first time stamp value (tA2) and said first time stamp value (tA1).

16. Method according to claim 15, characterized in that said fixed transfer delay (TD) is substantially equal to the difference between said time stamp compensation value (TTC) and said time stamp offset value (TOC).

17. Method according to claim 11, characterized in that said first (tA1) and second (tB) time stamp values are each carried by a cell of said telecommunication network, said cells being transmitted over said transmission link (TL1/TLn/TLN).