CA2108217C - Carrier phase lock detecting apparatus used in psk-modulated signal receiver for satellite communication system - Google Patents
Carrier phase lock detecting apparatus used in psk-modulated signal receiver for satellite communication systemInfo
- Publication number
- CA2108217C CA2108217C CA002108217A CA2108217A CA2108217C CA 2108217 C CA2108217 C CA 2108217C CA 002108217 A CA002108217 A CA 002108217A CA 2108217 A CA2108217 A CA 2108217A CA 2108217 C CA2108217 C CA 2108217C
- Authority
- CA
- Canada
- Prior art keywords
- signal
- psk
- multiplier
- carrier
- modulated signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
- H04L27/227—Demodulator circuits; Receiver circuits using coherent demodulation
- H04L27/2275—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses the received modulated signals
- H04L27/2277—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses the received modulated signals using remodulation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
- H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth
Abstract
In a PSK-modulating arrangement including a voltage controlled oscillator (VCO), a demodulator, a phase detector and a loop filter, a carrier phase lock detecting apparatus is equipped with the arrangement, the apparatus comprising a first multiplier for inversely modulating a demodulated signal by a reference carrier signal from the VCO, a second multiplier for multiplying the output of the first multiplier by an input PSK-modulated signal and a decision circuit for detecting carrier phase lock in response to the output of the second multiplier.
Description
f~
Carrier Phase Lock Detecting Apparatus used In PSK-modulated Signal Receiv~r for Satellite Communication System Background of the Invention The present invention relates to a carrier phase lock detecting apparatus in a PSK-modulated signal receiver for a satellite communication system.
In a satellite communication system, a carrier frequency used thereof inherently becomes to have offset due to a doppler shift, a drift of the local oscillator and/or residues in the automatic frequency control (AFC) on an earth side or on a satellite side. Especially, ;lO since a satellite earth station is usually intended to be reduced in size and price, a less stable oscillator '~
is applied, thus, inviting greater offset in the carrier frequency. Accordingly, in a receiver, various measures have been taken to achieve quick carrier frequency-and-phase acquisition to cope with such frequency offset.
For lnstance, a phase-locked loop (PLL) circuit, which is extensively used for carrier recovery in the receiver, is so configured that a voltage-controlled o~cillator (VCO) ln the PLL circuit, which outputs a reference carrier signal, is swept by frequency control until an incoming carrier is 'caught. Thus, even in the presence of a carrier frequency offset, carrier acquisition becomes possible. Further, to , ~ . .
. .
.
L r~
~ 2 --make a phase-locked time short and to cope with the carrier frequency offset, the PLL circuit is designed to have a widened loop bandwidth for the carrier acquisition period and, after the carrier acquisition, the loop bandwidth is switched to have a narrower ~,andwidth so as to facilitate keeping the carrier acquisition against a noise.
In a mobile satellite communication system, shadowing of receiving signals caused by buildings and other obstacles on a transmission path further invites erroneous operation in the vCo. Therefore, it is necessary to d~tect occurrence of the shadowing quickly as possible ,~nd thus to inhibit the control of the VCO on the basis o~ an erroneous phase difference detection signal during the shadowing period.
In order to switch the aforementioned loop-bandwidth in the PLL circuit and detect the shadowing in the mobile satellite communication, a carrier phase lock detecting function is provided to detect carrier phase lock condition.
Fig. 1 show a conventional PSK-modulated signal receiver including a prior art carrier phase lock detecting apparatus.
Carrier Phase Lock Detecting Apparatus used In PSK-modulated Signal Receiv~r for Satellite Communication System Background of the Invention The present invention relates to a carrier phase lock detecting apparatus in a PSK-modulated signal receiver for a satellite communication system.
In a satellite communication system, a carrier frequency used thereof inherently becomes to have offset due to a doppler shift, a drift of the local oscillator and/or residues in the automatic frequency control (AFC) on an earth side or on a satellite side. Especially, ;lO since a satellite earth station is usually intended to be reduced in size and price, a less stable oscillator '~
is applied, thus, inviting greater offset in the carrier frequency. Accordingly, in a receiver, various measures have been taken to achieve quick carrier frequency-and-phase acquisition to cope with such frequency offset.
For lnstance, a phase-locked loop (PLL) circuit, which is extensively used for carrier recovery in the receiver, is so configured that a voltage-controlled o~cillator (VCO) ln the PLL circuit, which outputs a reference carrier signal, is swept by frequency control until an incoming carrier is 'caught. Thus, even in the presence of a carrier frequency offset, carrier acquisition becomes possible. Further, to , ~ . .
. .
.
L r~
~ 2 --make a phase-locked time short and to cope with the carrier frequency offset, the PLL circuit is designed to have a widened loop bandwidth for the carrier acquisition period and, after the carrier acquisition, the loop bandwidth is switched to have a narrower ~,andwidth so as to facilitate keeping the carrier acquisition against a noise.
In a mobile satellite communication system, shadowing of receiving signals caused by buildings and other obstacles on a transmission path further invites erroneous operation in the vCo. Therefore, it is necessary to d~tect occurrence of the shadowing quickly as possible ,~nd thus to inhibit the control of the VCO on the basis o~ an erroneous phase difference detection signal during the shadowing period.
In order to switch the aforementioned loop-bandwidth in the PLL circuit and detect the shadowing in the mobile satellite communication, a carrier phase lock detecting function is provided to detect carrier phase lock condition.
Fig. 1 show a conventional PSK-modulated signal receiver including a prior art carrier phase lock detecting apparatus.
2~0 In Fig. 1, a PLL circuit arrangement includlng a VCO 1, a demodulator 2, a phase detector 3 and a loop filter 4 demodulates an incoming PSK-~odulated ,~,ignal and delivers demodulated data. For carrier phase lock detection, a unique word (UW) detecting circuit 5 and a ~rame synchronization circuit 6 are used. Thus, the frame synchronization signal from the circuit 6 is applied as a carrier phase lock detection signal to a frequency - 3 ~10821 7 swe~p control circuit 7. When frame synchroni~ation is established, the sweep control circuit 7 stops the sweep operation for the VCO 1. In this figure, an adder 8 adds the control signals from the loop filter 4 and the sweep " 5 control circuit 7. There also is a method utilizing forward error correction (FEC) technique for carrier phase lock detection.
According to prior art carrier phase lock detecting apparatus described above, there are the following a 10 disadvantages. As to the prior art utilizing the UW
detecting circuit, it takes a long ~ime for carrier phase lock detection since a frame unit including a UW is generally arranged to ha~e mass of a lot of bits.
Further, in a mobile satellite communication system, data 15 involving the UW are interleaved in long frame units for the purpose of diffusing burst errors, which are caused by the shadowing. In this case, frame synchronization is judged by detecting the interleaved UW in the frames.
Therefore, the prior art carrier phase lock detecting 20 apparatus utilizing the UW detecting circuit requires a longer time for carrier phase lock detection in the mobile satellite communication system. Incidentally, the interleaving frame length i~ determined by a ~hadowing time and a received power variation period. The other 25 disadvantages are that the prior art utilizing the detecting circuit requires a complicated circuit configuration and that the UW detecting circuit and . ~ .
~ 4 ~ 7 the fram~ synchronization circuit are additionally needed to a demodulating circui~ configuration.
On the other hand, the prior art utilizing the FEC
technique also has a disadvantage requiring a longer time for carrier phase lock detection because the FEC technique requires redundancy information for error correction.
Consequently, the prior art carrier phase lock detecting apparatus can not perform carrier phase lock detection in the desirably quick time.
..
Summary of the Invention It is therefore an object of the present invention to provide a carrier phase lock detecting apparatus capable of performing quicker carrier phase lock detection.
It is another object of the present invention to provide a carrier phase lock detecting apparatus which ;- has a less-complicated configuration and which can be equipped with a demodulating circuit configuration.
According to the present invention, there is provided a carrier phase lock detecting apparatus comprising a voltage-controlled oscillator for generating a reference carrier signal in response to a control signal; a demodulator ~or demodulating a received PSK-modulated signal in response to the reference carrier signal to deliver a demodulated signal; a phase detector ~or detecting a phase difference between the received PSK-modulated signal and the reference carrier signal on the ., .
_ 5 ~ 7 basis of the demodulated signal to deliver a phase difference signal; a loop filter for filtering the phase difference signal to deliver the control signal; delay means for delaying the received PSK-modulated signal to deliver a delayed PSK-modulated signal; a first multiplier for multiplying the demodulated signaI by the reference carrier signal to inversely modulate the demodulated signal;
a second multiplier for multiplying the output of the first multiplier by the delayed PSK-modulated signal; and decision means for determining carrier phase lock in response to the ou.put of the second multiplier.
Brief Description of the Drawings Fig. 1 is a block diagram showing a conventional demodulating arrangement including a prior art carrier phase lock detecting apparatus;
Fig. 2 is a block diagram showing an embodiment of the present invention;
Fig. 3 shows a circuit arrangement of a demodulator showing in Fig. 2;
Fig. 4 i9 a diagram showiny a characteristic of A
phase detector shown in Fig, 2; and Fig. 5 is a diagram explalnlng operation of the embodiment shown in Fig. 2.
Description of the Preferred Embodiment of the Invention Referring to Fig. 2, an additional circuit - 6 ~ 217 configuration 9 is équipped with the conventional PLL
circuit arrangement shown in Fig. 1. In Fig. 2, the PLL
circuit arrangement for carrier lock comprises a a voltage-con~rolled oscillator (~CO) 1 for outputting a reference carrier signal, a demodulator 2 for demodulating a digitally modulated two-phase PSX signal, a phase detector 3 for delivering the phase difference between the input signal and the output of the VCO 1 on the basis of the demodulated signal, and a loop filter 4 for filtering the output of the phase detector 3. The additional circuit configuration 9 for carrier phase lock detection comprises a delay circuit 10 for delaying the ' input signal, a multiplier 11 for multiplying the demodulated signal from the demodulator 2 by the reference carrier signal, a multiplier 12 for multiplying the output of the multiplier 11 by the signal delayed by the delay circuit 10, a filter circuit 13 for filtering the output of the multiplier 12, and a decision circuit 14 for giving a decision on whether the carrier phase has been locked or not by comparing the output of the filter circuit 13 with a preset threshold.
Next will be described the operatiorl oE this embodiment. The two-phase PSK ~ignal is inputted to the demodulator 2 after being limited in a frequency band : 25 and, as shown in FIG. 3, subjected to orthogonal detection wlth a reference carrier outputted from the VCO 1. The .' orthogonal demodulated signal obtained by this orthogonal .
.... . . . . , .. ; - ,. .... ~ . , .,. . ,~ . . ~ ... .
,. . . ~ : , . . . . ,, .. : , . .
....
.. . . .
~ Q~
detection is outputted to the phase detector 3. The phase detector 3 outputs an input signal and an error signal corresponding to the phase difference between the phase of the reference carrier outputted from the VCO 1 and the phase of the input signal. The error signal is suppressed of its high frequency component by the loop filter 4 and fed to the VCO 1. This phase lock loop controls the phase of the reference carrier signal from the VCO 1 in the direction of compressing the phase error relative to the input signal, and enables the two-phase PSK signal to be correctly demodulated.
This demodulating process will be explained with reference to equa~ions. Now, s(t) which is the PSK signal at time t is represented by Equation (1).
s(t) = A(t)ei(~ct+ ai(t)) .................... (1) Where, A~t) is a transmit data code ~d, ~c, the carrier frequency of the input signal and 9i(t), the phase of the input carrier signal. The reference carrier signal r(t) of the VCO 1 is represented by Equation (2).
r(t) = e~ C~+ Oo(t)) .... (2) Where, ~o(t) is the phase o~ the reference carrier.
The demodulator 2 detects the input signal S(t) and the reference carrier signal r(t) by complex multiplication to give a result represented by Equation (3).
s(t) ~ r(t) = A(t)e~ (t) - ao(t)) = A(t)ej~e(t) = A~t){cos~e(t) + jsin9e(t) } .... (3) Where, ~e(t) is ~i(t) - ~o(t), representing the phase difference between the input signal and the reference signal.
In the case of the two-phase PSK signal, because of the in-phase and quadr-phase demodulated signal in which the -real part A(t)cos~(t) and the imaginary A(t)sin~e(t) part are orthogonal to each other, the detection characteristic of the phase detector is what is illustrated in FIG. 4, providing the error signal e(t) represented by Equation (4) e(t) = A(t)sin~e(t) ~ SGN~A(t)cos9e(t)] .... (4) Where, SGN ~ ~ denotes the signum function (hard limiter). This error signal is filtered and fed to the VCO 1. The loop filter 4 selects a transfer function of the loop in order to determine the characteristic of the ; , loop. In this manner, the phase lock loop acts so as to reduce the phase difference between the input signal and the reference signal from the VCO 1 to zero.
Further, the output signal o~ th~ multlpl:Ler 11, when the demodula~ed signal from the demodulator 2 is in~ersely modulated by the multiplier 11 using the reference carrier outputted by the VCO 1, is represented by Equation (5).
{S(t)-r(t)}. r(t) = A(t)ej(~e(t) ~ ~ct- ~o(t)) .
; ' ' ' , .' ,,, .' . ~. .' ~ ' ' ~ . ,. ' . : !
9 ~ 2~7 Where the delay circuit 5 is a circuit to delay the input signal by the time it required for demodulation and inverse modulation. Next/ the multiplier 12 multiplies the input signal, whose delay has been adjusted, by the output of the multiplier 11 to output a signal y(t) represented ~y Equa~ion (6).
y(t) = A2(t)ei2~elt) = A tt)cos(2~e(t)) + jA2(t)sin(2~e(t)) ... (6) ~ When the carrier phase is synchronized in the PLh - 10 and the phase error ~ between the input signal and the :
i reference carrier outputted by the VC0 1 becomes smaller, cos 2~ and sin 2~ in the real and imaginary parts of the signal outputted by the multiplier 12 become 1 and 0, :
respectively. Thus, as the carrier phase is locked, :
signals of wh:ich Re y(t) is represented by d2 and Im y(t), by 0, are obtained from the real and imaginary parts of the output signal of the multiplier 12.
By respectively averaging these signals and : respectively comparing them with a proper threshold, the lock of the carrier phase can be detected. In detail, the output signals o~ the multiplier 7 are averaged by the low-pass filter circuit 13 90 as ~o minimlze erroneous detections and failures to detect even if the signal is low in signal-to-noise ratio. The decision circuit 14 gives a decision as to whether the carrier phase is locked , ~ . ,, , . - .. ,, , ~ . . .. . , : , ,, , . , , :, . . :.: :. : .. :
- lQ _ 2 ~ ~ 8 2 17 or not by comparison with the preset threshold. Thus, as illustrated in the explanatory diagram o~ FIG. 5, if carrier phase lock is detected at the point of time where the output signal level of the multiplier 12 surpasses the threshold, a state of phase lock will be affirmed.
Otherwise, it will be decided that no carrier phase lock is established. In Fig. 5, though only the signal Re is explained, the signal Im can be also applied to decisions on the basis of its value "zero" when the carrier phase is locked. It is easy to arrange a logic circuit receiving the two signals Re and Im to make the decision output.
Though the decision circuit 14 also detects the carrier phase lock at + ~ in Fig. 4, this detection does not mean right demodulating operation. In this case, the VCO 1 is further swept for accurate demodulating operation by another control signal based on UW detection, for example.
The present invention focuses the carrier phase lock detection.
In the embodiment of Fig. 2, on the basis of the quick carrier phase lock detection signal, ~ quick frequency sweeping control can be performed at the timing of catching an input carrier; ~ quick bandwidth switching of a loop filter can he per~ormed for establishlng carrier acquisition or Por maintaining carrier acquisition; and ~ quick holding o~ carrier and clock phase in~ormation and quick inhlbit of frequency control (AFC) can be effected in shadowing condition.
: :- :- . -: : - . ~ ~ :
.,,.. : .: : .. :: ~: ~:. ~ . .
As hitherto stated, the carrier phase lock detecting apparatus according to the preSent invention is capable of detecting carrier phase lock in a short period o~ time with a simpler configuration than the prior art utilizing the UW control circuit and the frame synchronism circuit.
':
: :
.
.
.
:~ :
According to prior art carrier phase lock detecting apparatus described above, there are the following a 10 disadvantages. As to the prior art utilizing the UW
detecting circuit, it takes a long ~ime for carrier phase lock detection since a frame unit including a UW is generally arranged to ha~e mass of a lot of bits.
Further, in a mobile satellite communication system, data 15 involving the UW are interleaved in long frame units for the purpose of diffusing burst errors, which are caused by the shadowing. In this case, frame synchronization is judged by detecting the interleaved UW in the frames.
Therefore, the prior art carrier phase lock detecting 20 apparatus utilizing the UW detecting circuit requires a longer time for carrier phase lock detection in the mobile satellite communication system. Incidentally, the interleaving frame length i~ determined by a ~hadowing time and a received power variation period. The other 25 disadvantages are that the prior art utilizing the detecting circuit requires a complicated circuit configuration and that the UW detecting circuit and . ~ .
~ 4 ~ 7 the fram~ synchronization circuit are additionally needed to a demodulating circui~ configuration.
On the other hand, the prior art utilizing the FEC
technique also has a disadvantage requiring a longer time for carrier phase lock detection because the FEC technique requires redundancy information for error correction.
Consequently, the prior art carrier phase lock detecting apparatus can not perform carrier phase lock detection in the desirably quick time.
..
Summary of the Invention It is therefore an object of the present invention to provide a carrier phase lock detecting apparatus capable of performing quicker carrier phase lock detection.
It is another object of the present invention to provide a carrier phase lock detecting apparatus which ;- has a less-complicated configuration and which can be equipped with a demodulating circuit configuration.
According to the present invention, there is provided a carrier phase lock detecting apparatus comprising a voltage-controlled oscillator for generating a reference carrier signal in response to a control signal; a demodulator ~or demodulating a received PSK-modulated signal in response to the reference carrier signal to deliver a demodulated signal; a phase detector ~or detecting a phase difference between the received PSK-modulated signal and the reference carrier signal on the ., .
_ 5 ~ 7 basis of the demodulated signal to deliver a phase difference signal; a loop filter for filtering the phase difference signal to deliver the control signal; delay means for delaying the received PSK-modulated signal to deliver a delayed PSK-modulated signal; a first multiplier for multiplying the demodulated signaI by the reference carrier signal to inversely modulate the demodulated signal;
a second multiplier for multiplying the output of the first multiplier by the delayed PSK-modulated signal; and decision means for determining carrier phase lock in response to the ou.put of the second multiplier.
Brief Description of the Drawings Fig. 1 is a block diagram showing a conventional demodulating arrangement including a prior art carrier phase lock detecting apparatus;
Fig. 2 is a block diagram showing an embodiment of the present invention;
Fig. 3 shows a circuit arrangement of a demodulator showing in Fig. 2;
Fig. 4 i9 a diagram showiny a characteristic of A
phase detector shown in Fig, 2; and Fig. 5 is a diagram explalnlng operation of the embodiment shown in Fig. 2.
Description of the Preferred Embodiment of the Invention Referring to Fig. 2, an additional circuit - 6 ~ 217 configuration 9 is équipped with the conventional PLL
circuit arrangement shown in Fig. 1. In Fig. 2, the PLL
circuit arrangement for carrier lock comprises a a voltage-con~rolled oscillator (~CO) 1 for outputting a reference carrier signal, a demodulator 2 for demodulating a digitally modulated two-phase PSX signal, a phase detector 3 for delivering the phase difference between the input signal and the output of the VCO 1 on the basis of the demodulated signal, and a loop filter 4 for filtering the output of the phase detector 3. The additional circuit configuration 9 for carrier phase lock detection comprises a delay circuit 10 for delaying the ' input signal, a multiplier 11 for multiplying the demodulated signal from the demodulator 2 by the reference carrier signal, a multiplier 12 for multiplying the output of the multiplier 11 by the signal delayed by the delay circuit 10, a filter circuit 13 for filtering the output of the multiplier 12, and a decision circuit 14 for giving a decision on whether the carrier phase has been locked or not by comparing the output of the filter circuit 13 with a preset threshold.
Next will be described the operatiorl oE this embodiment. The two-phase PSK ~ignal is inputted to the demodulator 2 after being limited in a frequency band : 25 and, as shown in FIG. 3, subjected to orthogonal detection wlth a reference carrier outputted from the VCO 1. The .' orthogonal demodulated signal obtained by this orthogonal .
.... . . . . , .. ; - ,. .... ~ . , .,. . ,~ . . ~ ... .
,. . . ~ : , . . . . ,, .. : , . .
....
.. . . .
~ Q~
detection is outputted to the phase detector 3. The phase detector 3 outputs an input signal and an error signal corresponding to the phase difference between the phase of the reference carrier outputted from the VCO 1 and the phase of the input signal. The error signal is suppressed of its high frequency component by the loop filter 4 and fed to the VCO 1. This phase lock loop controls the phase of the reference carrier signal from the VCO 1 in the direction of compressing the phase error relative to the input signal, and enables the two-phase PSK signal to be correctly demodulated.
This demodulating process will be explained with reference to equa~ions. Now, s(t) which is the PSK signal at time t is represented by Equation (1).
s(t) = A(t)ei(~ct+ ai(t)) .................... (1) Where, A~t) is a transmit data code ~d, ~c, the carrier frequency of the input signal and 9i(t), the phase of the input carrier signal. The reference carrier signal r(t) of the VCO 1 is represented by Equation (2).
r(t) = e~ C~+ Oo(t)) .... (2) Where, ~o(t) is the phase o~ the reference carrier.
The demodulator 2 detects the input signal S(t) and the reference carrier signal r(t) by complex multiplication to give a result represented by Equation (3).
s(t) ~ r(t) = A(t)e~ (t) - ao(t)) = A(t)ej~e(t) = A~t){cos~e(t) + jsin9e(t) } .... (3) Where, ~e(t) is ~i(t) - ~o(t), representing the phase difference between the input signal and the reference signal.
In the case of the two-phase PSK signal, because of the in-phase and quadr-phase demodulated signal in which the -real part A(t)cos~(t) and the imaginary A(t)sin~e(t) part are orthogonal to each other, the detection characteristic of the phase detector is what is illustrated in FIG. 4, providing the error signal e(t) represented by Equation (4) e(t) = A(t)sin~e(t) ~ SGN~A(t)cos9e(t)] .... (4) Where, SGN ~ ~ denotes the signum function (hard limiter). This error signal is filtered and fed to the VCO 1. The loop filter 4 selects a transfer function of the loop in order to determine the characteristic of the ; , loop. In this manner, the phase lock loop acts so as to reduce the phase difference between the input signal and the reference signal from the VCO 1 to zero.
Further, the output signal o~ th~ multlpl:Ler 11, when the demodula~ed signal from the demodulator 2 is in~ersely modulated by the multiplier 11 using the reference carrier outputted by the VCO 1, is represented by Equation (5).
{S(t)-r(t)}. r(t) = A(t)ej(~e(t) ~ ~ct- ~o(t)) .
; ' ' ' , .' ,,, .' . ~. .' ~ ' ' ~ . ,. ' . : !
9 ~ 2~7 Where the delay circuit 5 is a circuit to delay the input signal by the time it required for demodulation and inverse modulation. Next/ the multiplier 12 multiplies the input signal, whose delay has been adjusted, by the output of the multiplier 11 to output a signal y(t) represented ~y Equa~ion (6).
y(t) = A2(t)ei2~elt) = A tt)cos(2~e(t)) + jA2(t)sin(2~e(t)) ... (6) ~ When the carrier phase is synchronized in the PLh - 10 and the phase error ~ between the input signal and the :
i reference carrier outputted by the VC0 1 becomes smaller, cos 2~ and sin 2~ in the real and imaginary parts of the signal outputted by the multiplier 12 become 1 and 0, :
respectively. Thus, as the carrier phase is locked, :
signals of wh:ich Re y(t) is represented by d2 and Im y(t), by 0, are obtained from the real and imaginary parts of the output signal of the multiplier 12.
By respectively averaging these signals and : respectively comparing them with a proper threshold, the lock of the carrier phase can be detected. In detail, the output signals o~ the multiplier 7 are averaged by the low-pass filter circuit 13 90 as ~o minimlze erroneous detections and failures to detect even if the signal is low in signal-to-noise ratio. The decision circuit 14 gives a decision as to whether the carrier phase is locked , ~ . ,, , . - .. ,, , ~ . . .. . , : , ,, , . , , :, . . :.: :. : .. :
- lQ _ 2 ~ ~ 8 2 17 or not by comparison with the preset threshold. Thus, as illustrated in the explanatory diagram o~ FIG. 5, if carrier phase lock is detected at the point of time where the output signal level of the multiplier 12 surpasses the threshold, a state of phase lock will be affirmed.
Otherwise, it will be decided that no carrier phase lock is established. In Fig. 5, though only the signal Re is explained, the signal Im can be also applied to decisions on the basis of its value "zero" when the carrier phase is locked. It is easy to arrange a logic circuit receiving the two signals Re and Im to make the decision output.
Though the decision circuit 14 also detects the carrier phase lock at + ~ in Fig. 4, this detection does not mean right demodulating operation. In this case, the VCO 1 is further swept for accurate demodulating operation by another control signal based on UW detection, for example.
The present invention focuses the carrier phase lock detection.
In the embodiment of Fig. 2, on the basis of the quick carrier phase lock detection signal, ~ quick frequency sweeping control can be performed at the timing of catching an input carrier; ~ quick bandwidth switching of a loop filter can he per~ormed for establishlng carrier acquisition or Por maintaining carrier acquisition; and ~ quick holding o~ carrier and clock phase in~ormation and quick inhlbit of frequency control (AFC) can be effected in shadowing condition.
: :- :- . -: : - . ~ ~ :
.,,.. : .: : .. :: ~: ~:. ~ . .
As hitherto stated, the carrier phase lock detecting apparatus according to the preSent invention is capable of detecting carrier phase lock in a short period o~ time with a simpler configuration than the prior art utilizing the UW control circuit and the frame synchronism circuit.
':
: :
.
.
.
:~ :
Claims (5)
1. A carrier phase lock detecting apparatus comprising:
a voltage-controlled oscillator for generating a reference carrier signal in response to a control signal;
a demodulator for demodulating a received PSK-modulated signal in response to said reference carrier signal to deliver a demodulated signal;
a phase detector for detecting a phase difference between said received PSK-modulated signal and said reference carrier signal to deliver a phase difference signal;
a loop filter for filtering said phase difference signal to deliver said control signal;
delay means for delaying said received PSK-modulated signal to deliver a delayed PSK-modulated signal;
a first multiplier for multiplying said demodulated signal by said reference carrier signal;
a second multiplier for multiplying the output of said first multiplier by said delayed PSK-modulated signal;
and decision means for determining carrier phase lock in response to the output of said second multiplier.
a voltage-controlled oscillator for generating a reference carrier signal in response to a control signal;
a demodulator for demodulating a received PSK-modulated signal in response to said reference carrier signal to deliver a demodulated signal;
a phase detector for detecting a phase difference between said received PSK-modulated signal and said reference carrier signal to deliver a phase difference signal;
a loop filter for filtering said phase difference signal to deliver said control signal;
delay means for delaying said received PSK-modulated signal to deliver a delayed PSK-modulated signal;
a first multiplier for multiplying said demodulated signal by said reference carrier signal;
a second multiplier for multiplying the output of said first multiplier by said delayed PSK-modulated signal;
and decision means for determining carrier phase lock in response to the output of said second multiplier.
2. A PSK-modulated signal receiver comprising:
a voltage-controlled oscillator for generating a reference carrier signal in response to a control signal;
a demodulator for demodulating a received PSK-modulated signal in response to said reference carrier signal to deliver a demodulated signal;
a phase detector for detecting a phase difference between said received PSK-modulated signal and said reference carrier signal to deliver a phase difference signal;
a loop filter for filtering said phase difference signal to deliver said control signal, said loop filter having wide and narrow bandwidth characteristics;
delay means for delaying said received PSK-modulated signal to deliver a delayed PSK-modulated signal;
a first multiplier for multiplying said demodulated signal by said reference carrier signal;
a second multiplier for multiplying the output of said first multiplier by said delayed PSK-modulated signal;
and decision means for determining carrier phase lock in response to the output of said second multiplier, wherein said wide bandwidth characteristic is switched to said narrow bandwidth characteristic in response to the carrier phase lock determined by said decision means.
a voltage-controlled oscillator for generating a reference carrier signal in response to a control signal;
a demodulator for demodulating a received PSK-modulated signal in response to said reference carrier signal to deliver a demodulated signal;
a phase detector for detecting a phase difference between said received PSK-modulated signal and said reference carrier signal to deliver a phase difference signal;
a loop filter for filtering said phase difference signal to deliver said control signal, said loop filter having wide and narrow bandwidth characteristics;
delay means for delaying said received PSK-modulated signal to deliver a delayed PSK-modulated signal;
a first multiplier for multiplying said demodulated signal by said reference carrier signal;
a second multiplier for multiplying the output of said first multiplier by said delayed PSK-modulated signal;
and decision means for determining carrier phase lock in response to the output of said second multiplier, wherein said wide bandwidth characteristic is switched to said narrow bandwidth characteristic in response to the carrier phase lock determined by said decision means.
3. A PSK-modulated signal receiver comprising:
a voltage-controlled oscillator for generating a reference carrier signal in response to a control signal;
a demodulator for demodulating a received PSK-modulated signal in response to said reference carrier signal to deliver a demodulated signal;
a phase detector for detecting a phase difference between said received PSK-modulated signal and said reference carrier signal to deliver a phase difference signal;
a loop filter for filtering said phase difference signal to deliver said control signal;
delay means for delaying said received PSK-modulated signal to deliver a delayed PSK-modulated signal;
a first multiplier for multiplying said demodulated signal by said reference carrier signal;
a second multiplier for multiplying the output of said first multiplier by said delayed PSK-modulated signal;
decision means for determining carrier phase lock in response to the output of said second multiplier to deliver a carrier phase lock detection signal; and a sweep control means for controlling an oscillation frequency of said voltage controlled oscillator in sweep manner, wherein said sweep control means stops sweep control in response to said carrier phase lock detection signal.
a voltage-controlled oscillator for generating a reference carrier signal in response to a control signal;
a demodulator for demodulating a received PSK-modulated signal in response to said reference carrier signal to deliver a demodulated signal;
a phase detector for detecting a phase difference between said received PSK-modulated signal and said reference carrier signal to deliver a phase difference signal;
a loop filter for filtering said phase difference signal to deliver said control signal;
delay means for delaying said received PSK-modulated signal to deliver a delayed PSK-modulated signal;
a first multiplier for multiplying said demodulated signal by said reference carrier signal;
a second multiplier for multiplying the output of said first multiplier by said delayed PSK-modulated signal;
decision means for determining carrier phase lock in response to the output of said second multiplier to deliver a carrier phase lock detection signal; and a sweep control means for controlling an oscillation frequency of said voltage controlled oscillator in sweep manner, wherein said sweep control means stops sweep control in response to said carrier phase lock detection signal.
4. A PSK-modulated signal receiver as claimed in claim 3, wherein said loop filter has wide and narrow bandwidth characteristics and said wide bandwidth characteristic is switched to said narrow bandwidth characteristic in response to said carrier phase lock detection signal.
5. A carrier phase lock detecting apparatus as claimed in claim 1, wherein said decision means determines in response to a DC level contained in the output of said second multiplier.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4273934A JP2932861B2 (en) | 1992-10-13 | 1992-10-13 | Phase synchronization detection circuit |
| JP273934/1992 | 1992-10-13 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2108217A1 CA2108217A1 (en) | 1994-04-14 |
| CA2108217C true CA2108217C (en) | 1998-10-13 |
Family
ID=17534612
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002108217A Expired - Fee Related CA2108217C (en) | 1992-10-13 | 1993-10-12 | Carrier phase lock detecting apparatus used in psk-modulated signal receiver for satellite communication system |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US5533059A (en) |
| EP (1) | EP0593015B1 (en) |
| JP (1) | JP2932861B2 (en) |
| CN (1) | CN1066597C (en) |
| AU (1) | AU678773B2 (en) |
| CA (1) | CA2108217C (en) |
| DE (1) | DE69327500T2 (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3467888B2 (en) * | 1995-02-08 | 2003-11-17 | 三菱電機株式会社 | Receiving device and transmitting / receiving device |
| US5867503A (en) * | 1996-01-30 | 1999-02-02 | Mitsubishi Denki Kabushiki Kaisha | Digital sound broadcasting receiver and automatic phase controlling method therefor |
| GB2310091B (en) * | 1996-02-06 | 2000-06-07 | Nec Corp | Frequency sweep circuit |
| US5881110A (en) * | 1996-11-29 | 1999-03-09 | Sicom, Inc. | Carrier phase synchronization by reverse playback |
| JPH10233816A (en) * | 1997-02-21 | 1998-09-02 | Sharp Corp | Digital satellite receiver |
| JP3080601B2 (en) * | 1997-06-06 | 2000-08-28 | 株式会社ケンウッド | Carrier recovery circuit |
| JP3663565B2 (en) * | 1997-11-10 | 2005-06-22 | 富士通株式会社 | Carrier recovery circuit |
| JP3296421B2 (en) * | 1998-09-28 | 2002-07-02 | 日本電気株式会社 | Frequency estimation device |
| US6268780B1 (en) | 2000-04-26 | 2001-07-31 | National Semiconductor Corporation | Frequency synthesizer with digital frequency lock loop |
| KR20020056374A (en) * | 2000-12-29 | 2002-07-10 | 엘지전자 주식회사 | Frequency/phase auto comprehension apparatus using analog multiplier |
| US7292653B2 (en) * | 2004-03-10 | 2007-11-06 | Nortel Networks Limited | Carrier lock detector |
| JP4906919B2 (en) * | 2007-03-29 | 2012-03-28 | 株式会社アドバンテスト | Demodulator, test apparatus and electronic device |
| EP1976110B1 (en) | 2007-03-31 | 2014-01-01 | Sony Deutschland Gmbh | Circuit and method for processing an input signal |
| CN101630977A (en) * | 2009-08-19 | 2010-01-20 | 中兴通讯股份有限公司 | Device and method for locking demodulator phase in differential phase shift keying (DPSK) receiver |
| CN103647596A (en) * | 2013-12-31 | 2014-03-19 | 北京国电通网络技术有限公司技术服务中心 | Double-receiving and double-transmitting modulator-demodulator of satellite |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5821862B2 (en) * | 1976-11-11 | 1983-05-04 | 日本電気株式会社 | phase synchronized circuit |
| DE2826725A1 (en) * | 1978-06-19 | 1979-12-20 | Blaupunkt Werke Gmbh | Detection of discrete frequencies using phase locked loop - with low pass filter corner frequency regulated by comparator and threshold switch |
| US4259740A (en) * | 1979-03-07 | 1981-03-31 | Harris Corporation | Sequential detection system |
| JPS5720060A (en) * | 1980-06-19 | 1982-02-02 | Mitsubishi Electric Corp | Synchronous detector of four-phase phase-modulated wave demodulating circuit |
| JPS58221548A (en) * | 1982-06-18 | 1983-12-23 | Fujitsu Ltd | Phase locking circuit |
| JPS60130246A (en) * | 1983-12-19 | 1985-07-11 | Matsushita Electric Ind Co Ltd | Carrier recovery device |
| JPH0810879B2 (en) * | 1986-02-20 | 1996-01-31 | 富士通株式会社 | Demodulator |
| US5147329A (en) * | 1987-02-11 | 1992-09-15 | Brannon James K | Intravenous access devices |
| JPH0626353B2 (en) * | 1987-05-19 | 1994-04-06 | 日本電気株式会社 | Demodulator |
| EP0297774B1 (en) * | 1987-06-30 | 1994-06-08 | Nec Corporation | Phase controlled demodulator for digital communications system |
| JPH0748750B2 (en) * | 1988-11-15 | 1995-05-24 | 日本電気株式会社 | Synchronous demodulator |
| JPH03198554A (en) * | 1989-12-27 | 1991-08-29 | Nec Corp | Phase synchronizing detection circuit for carrier recovery |
| JPH0642685B2 (en) * | 1990-07-05 | 1994-06-01 | 日本無線株式会社 | Delay detection circuit |
| JPH05308387A (en) * | 1992-04-30 | 1993-11-19 | Nec Corp | Carrier phase synchronism detecting circuit |
-
1992
- 1992-10-13 JP JP4273934A patent/JP2932861B2/en not_active Expired - Fee Related
-
1993
- 1993-10-12 AU AU48985/93A patent/AU678773B2/en not_active Ceased
- 1993-10-12 CA CA002108217A patent/CA2108217C/en not_active Expired - Fee Related
- 1993-10-12 EP EP93116499A patent/EP0593015B1/en not_active Expired - Lifetime
- 1993-10-12 DE DE69327500T patent/DE69327500T2/en not_active Expired - Fee Related
- 1993-10-12 US US08/135,065 patent/US5533059A/en not_active Expired - Lifetime
- 1993-10-13 CN CN93120521A patent/CN1066597C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06177924A (en) | 1994-06-24 |
| EP0593015A1 (en) | 1994-04-20 |
| JP2932861B2 (en) | 1999-08-09 |
| AU4898593A (en) | 1994-04-28 |
| CN1092576A (en) | 1994-09-21 |
| CN1066597C (en) | 2001-05-30 |
| DE69327500D1 (en) | 2000-02-10 |
| CA2108217A1 (en) | 1994-04-14 |
| AU678773B2 (en) | 1997-06-12 |
| US5533059A (en) | 1996-07-02 |
| DE69327500T2 (en) | 2000-09-07 |
| EP0593015B1 (en) | 2000-01-05 |
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| EEER | Examination request | ||
| MKLA | Lapsed |