CA2110017A1 - Dqpsk delay detection circuit that produces stable clock signal in response to both i and q signals - Google Patents

Dqpsk delay detection circuit that produces stable clock signal in response to both i and q signals

Info

Publication number
CA2110017A1
CA2110017A1 CA2110017A CA2110017A CA2110017A1 CA 2110017 A1 CA2110017 A1 CA 2110017A1 CA 2110017 A CA2110017 A CA 2110017A CA 2110017 A CA2110017 A CA 2110017A CA 2110017 A1 CA2110017 A1 CA 2110017A1
Authority
CA
Canada
Prior art keywords
signal
zero
detection circuit
absolute value
stable clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2110017A
Other languages
French (fr)
Other versions
CA2110017C (en
Inventor
Kazuyoshi Nakaya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2110017A1 publication Critical patent/CA2110017A1/en
Application granted granted Critical
Publication of CA2110017C publication Critical patent/CA2110017C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0334—Processing of samples having at least three levels, e.g. soft decisions
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22—Demodulator circuits; Receiver circuits
    • H04L27/233—Demodulator circuits; Receiver circuits using non-coherent demodulation
    • H04L27/2332—Demodulator circuits; Receiver circuits using non-coherent demodulation using a non-coherent carrier

Abstract

A DQPSK delay detection circuit is provided that can securely reproduce stable clock signal. An absolute value circuit ABS calculates an absolute value of I signal. An absolute value circuit ABS calculates an absolute value of Q signal. Subtraction circuit generates a P signal according to the difference between the absolute values of I signal and Q signal. Zero-cross detection circuit detects zero-cross timing of the P signal to input it as a timing signal to the DPLL. The zero-cross timing of the P signal can be detected even when the data pattern of I or Q signal makes it impossible to detect the zero-cross timing from I and Q signal. Because the zero-cross timing of the P signal has a variation less than that of the zero-cross timing determined from I or Q signal, it is becomes possible to reproduce stable clock signals and in turn reliability of data demodulation can be improved.
CA002110017A 1992-12-07 1993-11-25 Dqpsk delay detection circuit that produces stable clock signal in response to both i and q signals Expired - Fee Related CA2110017C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP325879/1992 1992-12-07
JP4325879A JP2853491B2 (en) 1992-12-07 1992-12-07 DQPSK delay detection circuit

Publications (2)

Publication Number Publication Date
CA2110017A1 true CA2110017A1 (en) 1994-06-08
CA2110017C CA2110017C (en) 1998-07-07

Family

ID=18181636

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002110017A Expired - Fee Related CA2110017C (en) 1992-12-07 1993-11-25 Dqpsk delay detection circuit that produces stable clock signal in response to both i and q signals

Country Status (3)

Country Link
US (1) US5463664A (en)
JP (1) JP2853491B2 (en)
CA (1) CA2110017C (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6429986B1 (en) 1995-09-07 2002-08-06 International Business Machines Corporation Data storage to enhance timing recovery in high density magnetic recording
WO1997016002A1 (en) * 1995-10-25 1997-05-01 Philips Electronics N.V. Clock signal recovery system for communication systems using pulse amplitude modulation/quadrature amplitude modulation
US5802113A (en) * 1995-10-25 1998-09-01 Philips Electronics North America Corporation Clock signal recovery system for communication systems using quadrature amplitude modulation
JPH10215289A (en) * 1996-06-04 1998-08-11 Matsushita Electric Ind Co Ltd Synchronization device
US6011816A (en) * 1996-09-18 2000-01-04 Wireless Access Direct demodulation method and apparatus
US6081822A (en) * 1998-03-11 2000-06-27 Agilent Technologies, Inc. Approximating signal power and noise power in a system
US6493396B1 (en) * 1999-01-11 2002-12-10 Tellabs Operations, Inc Phase shift key burst receiver having improved phase resolution and timing and data recovery
CN1312875C (en) * 2004-01-05 2007-04-25 中兴通讯股份有限公司 PHS system position synchronous method based on digital lock phase ring and realizing device
US8605777B2 (en) * 2010-06-01 2013-12-10 Etron Technology, Inc. Circuit for recognizing a beginning and a data rate of data and method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4896336A (en) * 1988-08-29 1990-01-23 Rockwell International Corporation Differential phase-shift keying demodulator
US4879728A (en) * 1989-01-31 1989-11-07 American Telephone And Telegraph Company, At&T Bell Laboratories DPSK carrier acquisition and tracking arrangement

Also Published As

Publication number Publication date
CA2110017C (en) 1998-07-07
JP2853491B2 (en) 1999-02-03
US5463664A (en) 1995-10-31
JPH06177927A (en) 1994-06-24

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