CA2110310C - Bus monitor circuit for switching system - Google Patents
Bus monitor circuit for switching systemInfo
- Publication number
- CA2110310C CA2110310C CA002110310A CA2110310A CA2110310C CA 2110310 C CA2110310 C CA 2110310C CA 002110310 A CA002110310 A CA 002110310A CA 2110310 A CA2110310 A CA 2110310A CA 2110310 C CA2110310 C CA 2110310C
- Authority
- CA
- Canada
- Prior art keywords
- error
- packet
- data
- memory
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000012423 maintenance Methods 0.000 claims abstract description 9
- 230000004044 response Effects 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/18—Protocol analysers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/06—Generation of reports
- H04L43/067—Generation of reports using time frame reporting
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0823—Errors, e.g. transmission errors
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40032—Details regarding a bus interface enhancer
Abstract
In a switching system, a data bus which interconnects circuit modules, a switching network module and a control module for transporting packets between the interconnected modules. A bus interface (16) is connected to the data bus (13) for receiving a copy of every packet on the data bus. An error detector (18) determines whether the received packet contains an error, and produces an error detect signal and an error check result if the received packet is determined as having an error. In response to the error detect signal, the received packet, the error check result and time-of-day data are stored into a register (19) and transferred to one of the storage locations of a memory (20) to keep a list of error records. A
maintenance station (22) reads stored error records from the memory for identifying the source of errors.
maintenance station (22) reads stored error records from the memory for identifying the source of errors.
Description
NE-552 Zl 1 1 0 ~ 1 0 TITLE OF THE INVENTION
2 ''Bus Monitor Circuit for Switching System"
4 Field of the Invention The present invention relates generally to switching systems, and 6 more specifically to a maintenance system for keeping error records of a 7 switching system.
8 Description of the Related Art 9 In conventional switching systems where functional modules are interconnected by a data bus and packets are transported between the 11 modules over the data bus. When an abnormal condition occurs in the 12 system, a logic analyzer is brought into the system and hand-wired to the 13 data bus for monitoring the packets transported along the bus. However, 14 the use of the logic analyzer requires a special team of experts.
Additionally, the logic analyzer is not provided with a sufficient amount of 16 memory for storing records to be analyzed to allow identification of the 1 7 fault.
19 It is therefore an object of the present invention to provide a busmonitor circuit for monitoring packets on the data bus of a switching system 2 1 and keeping error records for maintenance purposes.
22 According to the present invention, there is provided a bus monitor2 3 circuit for a switching system. The switching system comprises circuit 24 modules, a switching network module, and a control module for controlling 2s the circuit modules and the switching module. All the modules are 26 interconnected by a data bus for transporting a packet between the 27 interconnected modules. The bus monitor circuit comprises a memory 28 having a plurality of storage locations, time-keeping means for generating29 time-of-day data, and an interface connected to the data bus for receiving a 3 0 copy of the packet therefrom. An error detector is provided for - 2 a~ 3~
determining whether the packet contains an error, and producing an error detect signal and an error check result if the packet is determined as having an error. In response to the error detect signal, the copy of the packet, the error check result and the time-of-day data are stored into one of the storage locations of the memory. A maintenance station is provided for reading stored contents of the memory.
In accordance with the invention, there is provided a bus monitor circuit for a switching system comprising a plurality of circuit modules to which lines and trunks are terminated, a switching network module, a control module for controlling said circuit modules and said switching network module, and a data bus interconnecting said circuit modules, said switching network module receiving packets from said circuit modules and switching the received packets between said lines and said trunks via said data bus under control of said control module, said circuit modules controlling said lines and trunks in response to a command signal from said control module, said packets each comprising a destination address, a source address, a data field and a frame check sequence (FCS), the bus monitor circuit comprising: time-keeping means for generating time-of-day data; an interface connected to said data bus for receiving a copy of a packet therefrom; an FCS
check means for receiving the frame check sequence of the copy of the packet and determining whether the packet contains an error, and producing an error detect signal and an error check result if said packet is determined as having an error; register - 2a -means for storing, when the packet is determined to have an error, the destination address, the source address and the data field of the copy of the packet, said error check result and corresponding time-of-day data to produce an error record; a memory having a plurality of storage locations for storing said error record into one of the storage locations of said memory in response to said error detect signal; and a mainten-ance station for reading stored error records from said memory.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will be described in further detail with reference to the accompanying drawings, in which:
Fig. 1 shows in block form a switching system embodying a bus motor of the present invention; and Fig. 2 shows the structure of signals transported on the data bus of Fig. 1.
DETAILED DESCRIPTION
Referring now to Fig. 1, there is shown a switching system according to the present invention. The switching system, inter-office trunks or transmission lines are terminated at a trunk circuit module 11 which controls the inter-office trunks in response to a command signal from a control module 10.
A subscriber lines are terminated at a line circuit module 12 which controls the subscriber lines in response to a command signal from the control module 10. Both of circuit modules 11 and 12 are connected to a data bus 13 to transfer data and speech signals to a switching network module 14 where these signals are switched between lines and trunks by way of the - 2b -data bus under control of the control module lQ in a manner known in the art. The control module 10 further provides an overall control of the system including maintenance and administrative tasks of the system. As shown in Fig. 2, the signal transported on the data bus 13 comprises a data signal 30 and a delimiter 31 which indicates the effective area of the data signal. The data signal is transmitted in packet format which begins with a destination address field (DA) followed by a source A 7l024-236 NE-552 2 11 ~ ~ 3 ~ ~
address field (SA), a data length field (LEN), a data field (DATA) and a 2 frame check sequence field (FCS) for detecting error bits.
3 According to the present invention, a bus monitor 15 is provided 4 which comprises a bus interface 16 connected to the data bus 13 for s receiving every packet transported on the data bus using a delimiter 31 as a 6 gate pulse and supplying the DA, SA, LEN and DATA fields of a copy of the 7 received packet to a register 19 and the FCS field of the packet to a known 8 FCS check circuit 18 as illustrated. A calendar and time-of-day clock source 9 17 is provided for generating date and time-of-day data. If an error is detected as a result of an FCS check, the FCS check circuit 18 produces an 11 error detect signal and applies it to the register 19 as an enable pulse to 12 store the DA, SA, LEN and DATA fields of the copy of the packet to 13 corresponding storage areas of register 19 and the result of the FCS check14 into a result area "R" of the register. At the same time, the date and time-of-day data are supplied to a "DATE ~ TIME" area of the register.
16 When register 19 is filled, all the stored error-containing data are 17 transferred from the register to a memory 20 as a first error record. When18 a subsequent packet is received from the data bus, a similar process is 19 repeated and stored into the memory 20 with an FCS check result and date and time-of-day data as a second error record if the subsequent packet is 21 determined as containing an error. If no error is detected by the FCS check 22 circuit 18, no record is stored in memory 20. As the process continues, the 23 memory 20 will be filled with a plurality error records as system diagnostic 2 4 data.
At appropriate time, all the stored error records are read from the 2 6 memory 20 by way of an interface 21 into a maintenance station, or video 27 display terminal 22 to provide a display of a list of error records on a video 28 screen. The displayed error records may be analyzed by maintenance 29 personnel to locate the source of the trouble.
8 Description of the Related Art 9 In conventional switching systems where functional modules are interconnected by a data bus and packets are transported between the 11 modules over the data bus. When an abnormal condition occurs in the 12 system, a logic analyzer is brought into the system and hand-wired to the 13 data bus for monitoring the packets transported along the bus. However, 14 the use of the logic analyzer requires a special team of experts.
Additionally, the logic analyzer is not provided with a sufficient amount of 16 memory for storing records to be analyzed to allow identification of the 1 7 fault.
19 It is therefore an object of the present invention to provide a busmonitor circuit for monitoring packets on the data bus of a switching system 2 1 and keeping error records for maintenance purposes.
22 According to the present invention, there is provided a bus monitor2 3 circuit for a switching system. The switching system comprises circuit 24 modules, a switching network module, and a control module for controlling 2s the circuit modules and the switching module. All the modules are 26 interconnected by a data bus for transporting a packet between the 27 interconnected modules. The bus monitor circuit comprises a memory 28 having a plurality of storage locations, time-keeping means for generating29 time-of-day data, and an interface connected to the data bus for receiving a 3 0 copy of the packet therefrom. An error detector is provided for - 2 a~ 3~
determining whether the packet contains an error, and producing an error detect signal and an error check result if the packet is determined as having an error. In response to the error detect signal, the copy of the packet, the error check result and the time-of-day data are stored into one of the storage locations of the memory. A maintenance station is provided for reading stored contents of the memory.
In accordance with the invention, there is provided a bus monitor circuit for a switching system comprising a plurality of circuit modules to which lines and trunks are terminated, a switching network module, a control module for controlling said circuit modules and said switching network module, and a data bus interconnecting said circuit modules, said switching network module receiving packets from said circuit modules and switching the received packets between said lines and said trunks via said data bus under control of said control module, said circuit modules controlling said lines and trunks in response to a command signal from said control module, said packets each comprising a destination address, a source address, a data field and a frame check sequence (FCS), the bus monitor circuit comprising: time-keeping means for generating time-of-day data; an interface connected to said data bus for receiving a copy of a packet therefrom; an FCS
check means for receiving the frame check sequence of the copy of the packet and determining whether the packet contains an error, and producing an error detect signal and an error check result if said packet is determined as having an error; register - 2a -means for storing, when the packet is determined to have an error, the destination address, the source address and the data field of the copy of the packet, said error check result and corresponding time-of-day data to produce an error record; a memory having a plurality of storage locations for storing said error record into one of the storage locations of said memory in response to said error detect signal; and a mainten-ance station for reading stored error records from said memory.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will be described in further detail with reference to the accompanying drawings, in which:
Fig. 1 shows in block form a switching system embodying a bus motor of the present invention; and Fig. 2 shows the structure of signals transported on the data bus of Fig. 1.
DETAILED DESCRIPTION
Referring now to Fig. 1, there is shown a switching system according to the present invention. The switching system, inter-office trunks or transmission lines are terminated at a trunk circuit module 11 which controls the inter-office trunks in response to a command signal from a control module 10.
A subscriber lines are terminated at a line circuit module 12 which controls the subscriber lines in response to a command signal from the control module 10. Both of circuit modules 11 and 12 are connected to a data bus 13 to transfer data and speech signals to a switching network module 14 where these signals are switched between lines and trunks by way of the - 2b -data bus under control of the control module lQ in a manner known in the art. The control module 10 further provides an overall control of the system including maintenance and administrative tasks of the system. As shown in Fig. 2, the signal transported on the data bus 13 comprises a data signal 30 and a delimiter 31 which indicates the effective area of the data signal. The data signal is transmitted in packet format which begins with a destination address field (DA) followed by a source A 7l024-236 NE-552 2 11 ~ ~ 3 ~ ~
address field (SA), a data length field (LEN), a data field (DATA) and a 2 frame check sequence field (FCS) for detecting error bits.
3 According to the present invention, a bus monitor 15 is provided 4 which comprises a bus interface 16 connected to the data bus 13 for s receiving every packet transported on the data bus using a delimiter 31 as a 6 gate pulse and supplying the DA, SA, LEN and DATA fields of a copy of the 7 received packet to a register 19 and the FCS field of the packet to a known 8 FCS check circuit 18 as illustrated. A calendar and time-of-day clock source 9 17 is provided for generating date and time-of-day data. If an error is detected as a result of an FCS check, the FCS check circuit 18 produces an 11 error detect signal and applies it to the register 19 as an enable pulse to 12 store the DA, SA, LEN and DATA fields of the copy of the packet to 13 corresponding storage areas of register 19 and the result of the FCS check14 into a result area "R" of the register. At the same time, the date and time-of-day data are supplied to a "DATE ~ TIME" area of the register.
16 When register 19 is filled, all the stored error-containing data are 17 transferred from the register to a memory 20 as a first error record. When18 a subsequent packet is received from the data bus, a similar process is 19 repeated and stored into the memory 20 with an FCS check result and date and time-of-day data as a second error record if the subsequent packet is 21 determined as containing an error. If no error is detected by the FCS check 22 circuit 18, no record is stored in memory 20. As the process continues, the 23 memory 20 will be filled with a plurality error records as system diagnostic 2 4 data.
At appropriate time, all the stored error records are read from the 2 6 memory 20 by way of an interface 21 into a maintenance station, or video 27 display terminal 22 to provide a display of a list of error records on a video 28 screen. The displayed error records may be analyzed by maintenance 29 personnel to locate the source of the trouble.
Claims (2)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A bus monitor circuit for a switching system comprising a plurality of circuit modules to which lines and trunks are terminated, a switching network module, a control module for controlling said circuit modules and said switching network module, and a data bus interconnecting said circuit modules, said switching network module receiving packets from said circuit modules and switching the received packets between said lines and said trunks via said data bus under control of said control module, said circuit modules controlling said lines and trunks in response to a command signal from said control module, said packets each comprising a destination address, a source address, a data field and a frame check sequence (FCS), the bus monitor circuit comprising:
time-keeping means for generating time-of-day data;
an interface connected to said data bus for receiving a copy of a packet therefrom;
an FCS check means for receiving the frame check sequence of the copy of the packet and determining whether the packet contains an error, and producing an error detect signal and an error check result if said packet is determined as having an error;
register means for storing, when the packet is determined to have an error, the destination address, the source address and the data field of the copy of the packet, said error check result and corresponding time-of-day data to produce an error record;
a memory having a plurality of storage locations for storing said error record into one of the storage locations of said memory in response to said error detect signal; and a maintenance station for reading stored error records from said memory.
time-keeping means for generating time-of-day data;
an interface connected to said data bus for receiving a copy of a packet therefrom;
an FCS check means for receiving the frame check sequence of the copy of the packet and determining whether the packet contains an error, and producing an error detect signal and an error check result if said packet is determined as having an error;
register means for storing, when the packet is determined to have an error, the destination address, the source address and the data field of the copy of the packet, said error check result and corresponding time-of-day data to produce an error record;
a memory having a plurality of storage locations for storing said error record into one of the storage locations of said memory in response to said error detect signal; and a maintenance station for reading stored error records from said memory.
2. A bus monitor circuit as claimed in claim 1, wherein the time-keeping means further generates a calendar date signal which is stored into said storage location of the memory in response to said error detect signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4-319572 | 1992-11-30 | ||
| JP4319572A JP2833387B2 (en) | 1992-11-30 | 1992-11-30 | Switch bus monitor circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2110310A1 CA2110310A1 (en) | 1994-05-31 |
| CA2110310C true CA2110310C (en) | 1999-07-13 |
Family
ID=18111765
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002110310A Expired - Fee Related CA2110310C (en) | 1992-11-30 | 1993-11-30 | Bus monitor circuit for switching system |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5659681A (en) |
| EP (1) | EP0601768B1 (en) |
| JP (1) | JP2833387B2 (en) |
| CA (1) | CA2110310C (en) |
| DE (1) | DE69331598T2 (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0149891B1 (en) * | 1994-12-22 | 1999-05-15 | 윤종용 | Bus status analyzer |
| AU715525B2 (en) | 1996-01-29 | 2000-02-03 | Vigilant Networks Llc | Packet network monitoring device |
| AU724885B2 (en) * | 1996-07-10 | 2000-10-05 | Vigilant Networks Llc | Method and system for characterizing terminations in a local area network |
| US6948100B1 (en) * | 1999-02-24 | 2005-09-20 | Hitachi, Ltd. | Computer system and method of handling trouble of computer system |
| US6820213B1 (en) | 2000-04-13 | 2004-11-16 | Stratus Technologies Bermuda, Ltd. | Fault-tolerant computer system with voter delay buffer |
| US6687851B1 (en) | 2000-04-13 | 2004-02-03 | Stratus Technologies Bermuda Ltd. | Method and system for upgrading fault-tolerant systems |
| US6691257B1 (en) | 2000-04-13 | 2004-02-10 | Stratus Technologies Bermuda Ltd. | Fault-tolerant maintenance bus protocol and method for using the same |
| US6735715B1 (en) | 2000-04-13 | 2004-05-11 | Stratus Technologies Bermuda Ltd. | System and method for operating a SCSI bus with redundant SCSI adaptors |
| US6708283B1 (en) | 2000-04-13 | 2004-03-16 | Stratus Technologies, Bermuda Ltd. | System and method for operating a system with redundant peripheral bus controllers |
| US6633996B1 (en) | 2000-04-13 | 2003-10-14 | Stratus Technologies Bermuda Ltd. | Fault-tolerant maintenance bus architecture |
| US6766479B2 (en) | 2001-02-28 | 2004-07-20 | Stratus Technologies Bermuda, Ltd. | Apparatus and methods for identifying bus protocol violations |
| DE50313247D1 (en) | 2002-07-18 | 2010-12-16 | Grieshaber Vega Kg | Bus station with integrated bus monitor function |
| EP1892885B1 (en) | 2002-07-18 | 2010-11-03 | VEGA Grieshaber KG | Bus station with an integrated bus monitor function |
| US20060277444A1 (en) * | 2005-06-03 | 2006-12-07 | Nicholas Holian | Recordation of error information |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4041253A (en) * | 1975-10-23 | 1977-08-09 | Stromberg-Carlson Corporation | Bus monitor circuit for detecting malfunction of telephone circuits connected in groups to a common bus |
| JPS5378747A (en) * | 1976-12-23 | 1978-07-12 | Toshiba Corp | Error display system |
| US4209846A (en) * | 1977-12-02 | 1980-06-24 | Sperry Corporation | Memory error logger which sorts transient errors from solid errors |
| SE430733B (en) * | 1980-03-24 | 1983-12-05 | Ellemtel Utvecklings Ab | SET UP AND DEVICE TO SAVE ERRORS IN A CALCULATION PROCESS |
| US4340776A (en) * | 1980-10-29 | 1982-07-20 | Siemens Corporation | Modular telecommunication system |
| JPS60136442A (en) * | 1983-12-26 | 1985-07-19 | Hitachi Ltd | Transmission system of packet switching data |
| US4672611A (en) * | 1984-04-20 | 1987-06-09 | Fuji Electric Company Ltd. | Serial transmission line monitoring device |
| US4967344A (en) * | 1985-03-26 | 1990-10-30 | Codex Corporation | Interconnection network for multiple processors |
| US4644533A (en) * | 1985-05-06 | 1987-02-17 | American Telephone & Telegraph Company | Packet switch trunk circuit queueing arrangement |
| US4949252A (en) * | 1985-10-17 | 1990-08-14 | Technology 80, Inc. | Computer channel analyzer with monitoring and selective display of predetermining events and related data |
| US5047977A (en) * | 1988-04-08 | 1991-09-10 | International Business Machines Corporation | Methods of generating and retrieving error and task message records within a multitasking computer system |
| US4932028A (en) * | 1988-06-21 | 1990-06-05 | Unisys Corporation | Error log system for self-testing in very large scale integrated circuit (VLSI) units |
| JPH0269037A (en) * | 1988-09-05 | 1990-03-08 | Fujitsu Ltd | Communication supervision system |
| JPH0496539A (en) * | 1990-08-14 | 1992-03-27 | Nec Corp | Address check system for packet exchange |
| US5297277A (en) * | 1990-08-31 | 1994-03-22 | International Business Machines Corporation | Apparatus for monitoring data transfers of an oemi channel interface |
| GB2250897A (en) * | 1990-12-04 | 1992-06-17 | Ibm | Error recovery in data communication systems. |
| US5253184A (en) * | 1991-06-19 | 1993-10-12 | Storage Technology Corporation | Failure and performance tracking system |
| US5351243A (en) * | 1991-12-27 | 1994-09-27 | Digital Equipment Corporation | Monitor for packets on a communications network |
-
1992
- 1992-11-30 JP JP4319572A patent/JP2833387B2/en not_active Expired - Lifetime
-
1993
- 1993-11-30 DE DE69331598T patent/DE69331598T2/en not_active Expired - Fee Related
- 1993-11-30 EP EP93309545A patent/EP0601768B1/en not_active Expired - Lifetime
- 1993-11-30 CA CA002110310A patent/CA2110310C/en not_active Expired - Fee Related
-
1995
- 1995-12-04 US US08/566,597 patent/US5659681A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| EP0601768A2 (en) | 1994-06-15 |
| EP0601768A3 (en) | 1995-09-06 |
| DE69331598D1 (en) | 2002-03-28 |
| JP2833387B2 (en) | 1998-12-09 |
| EP0601768B1 (en) | 2002-02-20 |
| DE69331598T2 (en) | 2002-11-28 |
| US5659681A (en) | 1997-08-19 |
| CA2110310A1 (en) | 1994-05-31 |
| JPH06169310A (en) | 1994-06-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |