CA2114457A1 - Multiprocessing System for Assembly/Disassembly of Asynchronous Transfer Mode Cells - Google Patents

Multiprocessing System for Assembly/Disassembly of Asynchronous Transfer Mode Cells

Info

Publication number
CA2114457A1
CA2114457A1 CA2114457A CA2114457A CA2114457A1 CA 2114457 A1 CA2114457 A1 CA 2114457A1 CA 2114457 A CA2114457 A CA 2114457A CA 2114457 A CA2114457 A CA 2114457A CA 2114457 A1 CA2114457 A1 CA 2114457A1
Authority
CA
Canada
Prior art keywords
cell
data
atm
assembly
bank
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2114457A
Other languages
French (fr)
Other versions
CA2114457C (en
Inventor
Kenji Yamada
Tatsuo Nakagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP1358793A external-priority patent/JPH07107992B2/en
Priority claimed from JP1361393A external-priority patent/JP2806726B2/en
Application filed by Individual filed Critical Individual
Publication of CA2114457A1 publication Critical patent/CA2114457A1/en
Application granted granted Critical
Publication of CA2114457C publication Critical patent/CA2114457C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5614—User Network Interface
    • H04L2012/5618—Bridges, gateways [GW] or interworking units [IWU]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly

Abstract

An assembly/disassembly system is comprised of a cell assembly and a cell disassembly, each assembly having one buffer memory with its memory area logically divided into a plurality of data areas (banks). The cell assembly receives TDM data to assemble ATM cells by storing the TDM data into the respective banks according to the virtual channels. When one of said banks stores the TDM data in the payload length of an ATM cell, an new bank (unused bank) is specified to store the TDM data successively. An ATM cell is formed by using the data read out from the bank where the TDM data is stored in the payload length of an ATM cell. The cell disassembly receives ATM cells from the ATM highway to disassemble the ATM cells into TDM data by using the buffer memory. The payload of a received cell is stored into an unused bank. A chain of the bank addresses each storing the payload of the received ATM cell is formed for each virtual channel of received ATM cells. According to a bank address read out from the chain corresponding to each channel of the TDM
highway, the data as the TDM data is read out from the buffer memory.
CA002114457A 1993-01-29 1994-01-28 Multiprocessing system for assembly/disassembly of asynchronous transfer mode cells Expired - Fee Related CA2114457C (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP13587/1993 1993-01-29
JP1358793A JPH07107992B2 (en) 1993-01-29 1993-01-29 Cell disassembly multiprocessor
JP1361393A JP2806726B2 (en) 1993-01-29 1993-01-29 Cell assembly multiplex processing equipment
JP13613/1993 1993-01-29

Publications (2)

Publication Number Publication Date
CA2114457A1 true CA2114457A1 (en) 1994-07-30
CA2114457C CA2114457C (en) 1997-09-23

Family

ID=26349405

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002114457A Expired - Fee Related CA2114457C (en) 1993-01-29 1994-01-28 Multiprocessing system for assembly/disassembly of asynchronous transfer mode cells

Country Status (5)

Country Link
US (1) US5412655A (en)
EP (2) EP0942621B1 (en)
AU (1) AU667250B2 (en)
CA (1) CA2114457C (en)
DE (2) DE69434705T2 (en)

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US5959993A (en) * 1996-09-13 1999-09-28 Lsi Logic Corporation Scheduler design for ATM switches, and its implementation in a distributed shared memory architecture
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US6430191B1 (en) 1997-06-30 2002-08-06 Cisco Technology, Inc. Multi-stage queuing discipline
US6819658B1 (en) 1997-07-15 2004-11-16 Comsat Corporation Method and apparatus for segmentation, reassembly and inverse multiplexing of packets and ATM cells over satellite/wireless networks
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US8121296B2 (en) * 2001-03-28 2012-02-21 Qualcomm Incorporated Method and apparatus for security in a data processing system
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Also Published As

Publication number Publication date
DE69434705T2 (en) 2007-04-12
DE69434705D1 (en) 2006-05-24
EP0614324A3 (en) 1995-04-12
AU5480894A (en) 1994-08-04
DE69427603D1 (en) 2001-08-09
CA2114457C (en) 1997-09-23
EP0942621A1 (en) 1999-09-15
EP0614324B1 (en) 2001-07-04
EP0614324A2 (en) 1994-09-07
DE69427603T2 (en) 2002-03-21
US5412655A (en) 1995-05-02
EP0942621B1 (en) 2006-04-19
AU667250B2 (en) 1996-03-14

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