CA2118131C

CA2118131C - Visual frame buffer architecture

Info

Publication number: CA2118131C
Application number: CA002118131A
Authority: CA
Inventors: Louis A. Lippincott
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 1992-04-17
Filing date: 1993-03-24
Publication date: 1999-03-23
Anticipated expiration: 2013-03-24
Also published as: AU4276493A; EP0656142A1; DE69325377T2; ES2134263T3; US5914729A; EP0656142B1; WO1993021623A1; CA2118131A1; JPH08502150A; US5546531A; DE69325377D1

Abstract

An apparatus for processing visual data is comprised of a first storage means for storing a first bit plane of visual data in a first format. A graphics controller is coupled to the first storage means by a data bus and through a storage bus. Means for receiving a second storage means for storing a second bit plane of visual data in a second format different from the first format is also provided. The receiving means is adapted to couple a second storage means to the graphics controller by a data bus and through a storage bus. Means for forming a merged pixel stream from visual data stored on the first and second storage means are also included.
Means, coupled to the graphics controller are provided for displaying the merged pixel stream. In a further embodiment, an apparatus for processing visual data is comprised of a first storage means for storing a first bit plane of visual data in a first format. A graphics controller is coupled to the first storage means by a data bus and through a storage bus. A second storage means coupled to the graphics controller by a data bus and through a storage bus is provided for storing a second bit plane of visual data in a second format different from the first format. Means for forming a merged pixel stream from visual data stored on the first and second storage means are also included. Means, coupled to the graphics controller, are provided for displaying the merged pixel stream.

Description

2 1 1 8 1 ~ 1 P~/l lS93/02773 . ~. ...
' ~I~~A~ FRAM13 331}FFER ARC~ITECT~5 Field of ~he Invention . .
This invention relates to video signal processing generally and particularly to systems for providing a .~:
digital signal representative of video and graphics information.

Back~round Of The Invention The:goal of attaining~an integrated video/graphics system (Integrated ~isual ~rchitecture) requires a system architect to balanc~ often conflicting requirements o~ video :~ ~ :subsystems and graphics subsystems.. For example, while increasing horizontal and vertical resolution.is beneficial to ~raphics images, in digital video s~systems increasing horizontal~and vertical resolution can actually be de~rimental to the~ overall image quality:. LiXewise, in graphics subsystems,~:the~pixel depth,: io~ the number Q~
si~ultaneous colors~available, ~is not as important as it is for;video~sys~ms. ~While it~may be hard to justify~the ~:
additiona~ system~aost of~:I6:~bit, near-true-color~pixels~for -:
the~graphics; sys~tem,;~a:~video system can arguably make use of leeper 24 bit: plxels~
: : ? ' T~e:pe~formance budget of a ~ideo processor in a digital~video subsystem during pl:ayback is diYided and used ;to~perfo~m two~task~: creating the video imzge from a ~
compressed data stream and opying/~caling the image to t~e display:buffer. The per~ormance budget of the video subsystem m~st be balanced between the copy/scale operation and the ~idQo d~comprassion operation. Both operations must :; SUB~ I I i ~JTE SHEET

~ .

WO93~21623 211;813~ PCl/VS93/0~7?3 f get performed thirty times a ~;econd for smooth, na~ural ~ motio2l video. The di~vision of the performance budget is usually done to worse case which results in an allocation of sufficient performance for a full screen motion video copy/scale operation with the rsmaining performanc:e being dedicated to the video decompression opera~ion. If the number o~ pixels ( and/or byte~ ~ that have to be written in the copy/scale operation are incr~ased, the performance of the video decompression necessari1y decreases. In ever increasing rssolutions, ~ for a given 1evel of video - t~chnology, a point will be reached where the video image start~; to degrade because the inf ormation content in the des::ompressed image is too low. Increasing the resolution be}rond this point would be analogou~ to playing }: ac}c a poor -~
"
copy vf a ~S tape on the most: expensive, highest-~uality TV --availa~le; the TV would reproduce the low-quality images perfectly.
Several f ormats hav~ be~n presented :f or storing pixel data in a video s~lbsystem~, ~One approach is to simply , : have 2~ bits of RGB information per pixel.~ This approach yi~alds the maximum Golor spac~ r~quired ~or video at the P~ensP of three bytes~per pixel. Depending on the number of pixe}s in the video subsystem, the copy~scale operation ould be overburdened A second approach is a compromise of the 2 4 bit sy~tem and is bas~d on 16 bits of RGB information per pixel. J
::
~. ~ Suc:h sy~te:m~; ha~7~3 less bytes for the copy/sc:ale operation :
but also hav~ 1~s~ coIor d~pt hr Additionally, since the ~:: 2 SU13~1~ JTE SHEEr W093J2~623 2~ -3 1 PCT/US93/02773 inten~ity and color information are encoded equally in thb R, G and B components of the pixel, the approar-h does not take advantage of the human eye's sensitivity to intensity and insen iti~ity to color saturation. O~her 16 bit systems have been proposed that encode the pixels in YUV format such a~ 6, 5, 5 and ~, 4, 4. ~lthough somewhat better than 16 bit RGB, the 16 bit YUV format does not come close to the performanc~ of 24 bit systems.
The 8 ~it CLUT provides a third pproach. This method uses ~ bits per pixel as an index in~o a color map that typically has 2~ bits of color space as the entry.
This approach has the advan~ages of low byte count and 24 bit color space. However/ since there are only 25~ colors available on the ~cr~en, image quality suffers. Techniques khat use adjacent pixels to "create" other colors have been demonstrated to have excellent image quality, even for still images~ However, this dithering tP~hni que ofte~ reguires complica~ed algorithms and l'custom" palette entries in the DAC as w~ll a~ almo~t exclusive use of the CLUT. The overhead o~ ~lnning the dithering algorithm must ~e added to the copy/scal~ operation.

:
on~ approach for storin~ pixel data in a video ~ subsystem has been to represent the intensity information I I i withimore bits ~ha~is used to reprecent the color sat~ration:in~ormation. The color information is sub ampled in m~mory and interpolated up to 24 bit~ per pixel by the display controller as the information is being displayed. -c ~;~ This ~o~h~iqu~ has the advantage of full color space while ~ ~ SIJB~I I I~TE SHII~

3 2 1~ 18 i 3 1 PCT/US93/02773 :

maintaining a low number of bits per pixel. All of the ;~
pixel depth/density tradeoffs are made in the color .-:
saturation domain where the effects are less noticeable.
Several variations of this method exist and have been implemented in a display processor from Intel. In the Intel system, pixel depths ypically range from 4.5 to 32 bits per :~
pixel.
Motion ~ideo on the Intel system is displayed in a 4:1:1 format called the "9 bit format". The 4:1:1 means there are 4 Y samples horizontally for each W sample and 4 Y samples ~rtically for each W sample. If each sample is 8 bits then a 4 x 4 block of pixel~ uses 18 bykes of information or 9 bits per pixel. Although image quali~y is quite good for motion video the 9 bit format may be deemed unacceptable for display of high-quality stills. In addition, it was found that the 9 bit format doPs not integrate well with graphics sub stems. Other variations.
of~th~ YUV subsampled approach include an 8 bit format.
As note~ above, the ~e~uirements for a graphics system include high horizontal and vertical resolution with shallow pixels~ A graphics system~in which the display was 1280 x 1024 with 8 bit clut pixels would likely me~t the ~ :
needs of all but the most dP~n~;ng applications. In contrastl, the requirements for the ~ideo system include the a~ility :to generate 24 bit true color pixels with a ~inimum of bytes in the disp}ay bu~fer. ~ video system in which the display was 640 x 512 x 8 bit (YUV interpolated to 24 bits SUBs I I I ulTE~ SHEET

WO93/21623 2 f 18131 PCT/US93/02773 and upsampled to 1280 x 1024~ would also meet the needs of most application~.
Systems integrating a graphics subsystem display buffer with a ~ideo subsy~tem display buffer generally fall into tw~ categories. The two types o~ approaches are known as Single Frame Buffer ~rchi~ectureg and Dual Frame Buffer Architectures.
Tha Single Fr ae ~uffer ~rchitecture ~SFBA) is the most straight forward approach and consists of a single graphics controller, a single DAC and a:single frame buffer.
In its sim~lest form, the SFBA has each pixel on the display represehted by bits in the display buffer that are consistent in their forma~ r~gardless of ~he m~";ng of the pixel on the di play. In other words, graphics pixels and ~-video pixels are indistin~li~ch~hle in the frame buf~er RAM.
The SFB~ graphics/vid~o subsy~tem, i.e. the SFBA visual ~
system, does not address the requiremen~ of ~he video subsystem very well. Fu~l ~creen mo~io~ vid o on the SFBA . .-:~ ~
:visual system requires updating every pixel in the display ; buffex (30 times~a: second~ which is most likely on the order of 1280 x ~024 by 8 bits. Even without the burden of writing over 3~0 M Bytes~per second to the display bufX@r, it has been established that 8 bit video by itself does not provide the r~quired Yideo quality9 This m.ans the SFBA
sys~em c:an ei~her move lap to 16 bits per pixel or implement the B bit YUV 5~lh~rled technique. Since 16 bits per pixal will yi~ld over 60 M Bytes per s~sn~ into the frame bu~îert it is clearly an unaGceptable alternativeO ~ visual system ;UE3~ ITE S~T

W~93~21623 2 1 1 8 1 3 1 PCT/USg3102773 -must be able to mix video and graphics together on a display which re~uires the display to show on occasion a single vide~ pixel located in between graphics pixels. Because of ~ -the need to mix video and graphics there is a hard and fast rule dictating that every pixel in the display buffer be a stand-alone, self-sustaining pixel on ~he screen. The very nature of the 8 bit YUV subsampled technique makes it nece~sary to have several 8 bit samples before one Yideo pixel can be generated, making the technique unsuitable for the SFBA ~isual system.
The second category of architec~ures integrating :~
video and graphics is the Dual Frame Buf~er Architecture ( DFBA) . The DFBA visual system involves mixing two otherwi8e ~ree~st~di rlg single frame buffer systems at the a.nalog back end with a high speed analog switch. Since the video and ~raphics subsystems are both single frame buffer designs each one can make the necessary ~tradeof~s in spa~ial r~solutlon and pixel dep~h with almosl: comp}ete disregard for the other subsystem. DFBA visual systems also include the ~eat~are of being loos~ly coup~ed. Since the only connection of ~he ~wo systems is in the final ou~pu~ stage, :
the two sub~ystems can be on different buses in the system.
The fact that the ~FBA video sub~ystem is loosely-coupled to the graphics su~system is usually the overriding reason su~h syst~ms, which have significant disadvantages, are typically ;~
employedO
DFBA desiqns typically operata in a mode that has ~he video ~ubsys~em genlocked to the graphiss subsyst~m.

WO93/21623 2 I ig i3 l PCT/US~3/02773 Genlocked in this c~se means having both subsystems start to display their first pixel at the same kime. If both subsystems are running at exactly the same hori~ontal line frequency with the same number of lines/ then mixing of the two .eparate video streams can be done wit~ very prPdictable results. -Since both pixel streams are running at the same time, the process can~be thought of as having ~ideo pixels underlaying the graphics pix~15. If a determination is made not to how a graphics pixel, then the video information will show through. In ~FBA designs, it is not necessary for the;two subsystems to have the same number of horizontal ~:
pixels. As an example, it is quite possible to have 352 video pixels underneath~lO24 graphics pixels. The Intel A~tion~e~ boards are DFB~ designs and can display an arhitra ~ nu~ber of video pixels while genlocked to an a~bitrary line rate graphics ~ubsystem. ~he only restrictions are that the frequency r~-~uired ta support the confisuration be within the 82750DB's 12NHz to 45Mhz range.
:; The decislon whether to show the ~ideo information or the graphics inf~rmation in DFBA visual systems is t ~ ically made on a pixel ~y pixel basis in the graphics subsy~tem. A te~h~ique often us~d is cal1ed "chroma keyingt'. Chroma keying involve~ detecting a specific color (or color ent~y in the CLUT) in the graphics digital pixel ream. Ano her approa~h referred to as "black dete t", uses the graphi~s analog pixel stream to detect black, since black is th~ easiest graphics l~vel to d~tect. In either ., ~: ~ .

~ : 7 sua~
~, W~3/21~23 : 2 1 1 8 ~ 3 1 PCT/US93/~2773 case, keying information is used to control ~he high-speed analog switch and the task of integrating video and graphics on the display is reduced ta painting the keying color in the graphics di play where video pixels are desired.
Intel's ActionMedia II~ product impl~ments chroma keying and black detect.
Ther~ are se~eral disadvantages to DFB~ visual systems. The goal of high-in~egration is of~en thwarted by the need to ha~e two separa~e, free-standing subsystems.
The c05t of having duplicate ~s, display buffers, and CRT
controll~rs is undesirable. The di~ficulty of genlocking and the cost of the high-speed analog switch are two more .
disadvantage In addition, placing the analog switch in the graphics path will have detrimental effects on ~h.
quality of the graphics display. This beromes an ever increasing prohlem as the spatial resolution and~or line rate of the graphics subsystem grows~ ~
It is an objec~ of the presen~ invention to provide an integrated sy~tem for storing and displaying ~raphics and video inform~tio~.
It is further object of the present in~ention to provide a sy~tem for storing and displaying eithex graphics or vid~o information, which sys~em can be easily upgraded !~
into an int~grated system for s~oring and displaying ~: graphics and vid o information by merely augmenting the system with additional mem~ryO

.
SU~3S ~ $~

093~2~6 3 2~ gl3 1 PCT/US93/~2773 Further objec~s and advantages o~ the invention will become apparent from the description of the invention which follows.

Summarv Of The Invention ~ In a preferred embodiment of the present inventi~n, an apparatus for processing visual data is ompris~d o~ a first storage mP~ for storing a first bit plane of visual data in a first format. A graphics ~: controller is cQupled to ~h~ first storage me~ by a data bus, and the graphics controller and the first storage m~n~
are coupled through a storage bus. Means for rec~iving a second ~torage r?~n~ for storing a second bit plane of visual data in a:~c~n~ format dif~erent ~rom the first format is also~provided. The r~ceiving means is adapt~d to couple a second ~torag~means to the graphics controller by a data bus. The receiving m~C is also adapted to couple : ~ ~the~s~cond:storage ~n-~ to the graphics controller through ::~
;the storage bus. The invention also includes ~A~ for formin~ a merged pixel str~am ~rom~vi~ual data stor~d on the irs~ storage r~n~ and ~isual data stored on the sec3nd -storage means.~ n~ :coupled to the graphics controller, are:provided for displaying th~ m~rged pix~l stream.
n~a further preferred embodiment, an apparatus or~proaessing visual data is comprised o~ a first storage means for storing a ~irst:~it plane of visual data in a ~- :

irst forma~. A graphics controller is coupled to the first storage m~ans by a data bus, and the graphics controller and .

WO 93/21623 2 1 1 ~ 1 3 1 P~/US93/~2773 ~

the f irst storage m~ans are coupled through a storage bus .
A second storage means for storing a second bit plane of ~isual data in a second format different from said first format is also provided. The second storage means is coupled to the gxaphiss controller by the data ~us. The second storage meaIls is also coupled to ~he graphics c~ntroller through the ~orage bus. Means for forming a m~rged pixel ~tream from visual data stored on the f irst storage mean~ and visual data stored on t~e second s~orage means are al50 included. ~eans, coupled to the graphics controller, are provided for displaying the merged pixel stream~

Brief Descri~tion Of The Drawin~s FigurP 1 is a block diagram illustr~ting the operation of a fixst preferred:emboAir~nt of the present in~nti~n~
,~ .
Figure 2 is a~ block diagram illustra~ing the opera~ion o~ a~ second: preferrecl em~odiment of the present in~ention.

:
Detailed Description O~ The Preferred Embodiment Referring now to Figure 1, there is shown a block : ~ ~ diagram illustrating the operation of an apparatus, designated generally 100 ~ for proces~ing vi~ual data ccordi~g to a ~irst praferred embo~iren~ of the present invention. The invention~ sho~m includes ~irst stvrage rn-~n::
110 for storing a first bit plane of visual data in a first ~:: 10 .

SU8~
;~ .

formàt. First storage means 110 is coupled to graphics controller 140 through storage bus 132. First storage means 110 and graphics controller 1~0 are also couplPd by data bus 130~ The invention also includes means 120 ~or receiving a second ~torage means for storing a second bit plane of visual data in a second format different from ~he first format. Means 120 is adapted to couple a second storage m~~n~ to graphics c~ntroller 140 through the st~rage bus ~:.
13~. Means 120 is also adapted; to couple the second storagei ~
:: .
means to graphics co~t~oller 140 by:data bus 130a. ~raphiss .controll~r 140 includes means for forming a merged pixel stream from ~isual data stored on said first and second storage mP~n~. Means 160 for displaying the merged pixel stream~is also pro~ided. Means 160:is coupled to graphics controller 140 by pixel~bus l~0. In~the preferred embo~ir~nt, data bus:130 and data bus 130a are separate 8 :bit ~uses.~ In an~a~lternative embo~;m~t,~a single 16 bit data~:~bus~may be:~ used ~to couple both ~irs~storage mP~n:~ 110-:
and~a~s~cond~storage~ç~:n~ to~graphics controller 140. Data bu~es~of~other;widths~may~also be:used.~
;Fisure l~shows a base;configuration of the pre~ent . -:in~ention~in which~ ~irst stora~e means llO is~ represented by ~ -RA~;BANK 0O :$'hi5 base configura~ion may operate~ in an 8-~it CWT mode. Thi~ mode~allows:operation of ~M BA~K 0 as a Single~Frame~ Buffer~Architecturc,~similar to a VGA or XGA
system~in 8~bits per pixel mode. The 8-bit CLUT mode allows for~;~operation of the base c~n~i~uration as a video only or graphics only~su~system~ The ba~e configuration may also 5~3BS ~ ll E SH~

~93/216~3 2 1 1 ~ PCT/US93~02773 --~ .' operate as a SFBA system with limited graphics/video integr tion (8 bits/pixel) as described in th~. Backgrou~d section above. In the 8-bit CLUT mode, the bandwidth of data bus 130 is the same as would be required for a stand alone 8 bit CLU~ gr~phics subsystem.
Means 120 for r~ceiving a second storage means allows the base configuration of the present invention to be ~asily upgrad d by the mere addi~ion of a second storage means to operate either as ~i) an integrated system for storing and displaying both graphics and video in~ormation ("the Dual Color Space Mode");, or as (ii) an expanded single frame buffer for storing and displaying either graphics only or video only in~ormation at a deepen~d pixel depth and/or increased resolution level ("~he ~Y~n~ed Single Frame Buffex Mode"), In tha Dual Color Space Mod~, a first typie " ~
: of visual data may ~e stored in first s~orage me~ 110 in a irs~ orma~, and a second:type of vlsual data may be stored ; ~ : ~ : : ~ : .
~ ;in~:a~second ~torage~means in a secon~ format which is ~ -, di~ferent ~rom the first fo~mat. For example, graphics data may~be stored in firs~ ~torage means 110 in ~GB ~ormat~ and video~data may:be stored in the~second storage ~An~ in Y W
ormat. In~the ~Yr~e~ Single Frame Buffer ~ode, first :~ storage means 110 and a s~cond storage ~e~ preferably provide!for operat1on of the s y5t2m as a video only system or a grap~ics only subsystem with 16 bits per pixel. The ~ n~ed Single Frame Buffer Mod~ may also operate as a SFBA
sy~tem with limit~d graphics/video integration (16 its/pixel~ as described in the Back~Lo~lld se~tion abovie.

SUIB~ 11 1 ulTE SH~ET

~ :

W~ g3/21623 2 1 ~$ 1 ~'i PCr/lJ~93/02773 ~ ~
~.,' . ! ;' I
~
Graphic:s controller 140 includes means for forming a mergec~ pixel stream from data in a first format stored on storage means 110 and data which may be storPd in a second format on a second ~;torage ~An~:, once a second storage means is received by ~L~n~ 120. According to a preferred s embodiment , when the bas~ syste~a is upgrade~ ( e . g ., when a seco~d storag~ nc: is received by m~ n~: 1;2 0 ) and operating in the Dual Color Space Mode, graphic:s data is stored in one ~o~ the storage means ~in 8-bit C~UT format, and video data is stored in the: other storage Tne~n~ as: 3 bit YUV data. The pre~erred format of the~ 8 bit YUV data in th Dual Color Space Mode is shown in Table I below, with each position being a ingl~ byt~
3 ~ Yb ~a Yc Ub Yd Vb Ye Uc ; ~ TABI.E I

In ~the Dual ~olor Space Mode, a first pixel s~ream :representing the ~ RGB graphics pixels (GP~) is processed in parallel with a second pixel stream representing YW video pixels. q~e:~two parallel pixel ~reams are stored in pa~alle 1 in a~co~ e with the format shown in Table II
below ~
Y P2 ~ ~ V 4 ~ 5 ~ P6 ~;P7 ~PB ~P9 Table: II

' The~ pixels generated by the vid~o suhsystem (VPn) ~-in the Dual Col~or Space ~ode~ ~are pr~fer~bly 24 bit RGB
values~ derived from 24 bit YW pixels. The 24 bit YIJV

: : sua~ TE s~r ~ - ~

W~93~21623 2 1 1 ~ 1 3 1 PCT/US93/~Z773 ~ -pixels ~re determined for each video pixel VPn in accordance with the formula ~hown in Table III below:
, .
Y=Y~ ~ U-Ua , and V--V~ for VP1; J
Y-~5Ya+-5Yb, U=.75U~.25Ub~ and ~T= q 7 5V~3+ . 2 5Vb for VP2;
Y~Yb, U=oSU~+~5Ub~ and V-.5V~+.5Vb for VP3;
Y ~5Yb+-5YC~ U=~2 5U3~ ~ 75Ubr and V=.25V ~.75Vb fo~ VP4;
YaYC, U=Ub, and V=Vb for VP5, and so on.
: TABLE III :.
: Other subsampling techn;ques may b~ used to b~ild the .
RGB values.
: In the preferred embodiment, chroma keying is ~pr~fera~ly use~ on the graphics pixel stream is used to :determine whether to show a graphics pixel or a video pixel.
In~the eY~mrle of Table II, if GP3 and GP4 held pixel values e ~ al to the chroma key value, then the:merged graphics and video pixel stream (the visual pixel s~r~am) provided ~o the :: :
DAC~would have the format shown in Ta~le IV below: .

GP1 ~Pz ~P3 VP4 GP~ GP6 GP7 GP8 GP~
TART.F~ V
Refèrrin~ now to Figure 2, there i~ shown a blsck diagram lllustrating~the:operation~of an apparatus, : desig~ated~generally 200, for processing vi~ual da~a ~acGording to a ~econd pr~ferred~embodiment of the present :invention. ~e i~vention~shown includes;first storage 2l0 for stori~g a first bit plane of visual data in a first : format. Fir~t storage~means:2lO is coup~ed to graphics contro}ler 240 through:storag~ bus 232~ ~irst storage , ~
4 :-SlJE~ l}E SHE~T

; ' : .

~W0 93/21623 ' 2 1 1 8 1 3 1 P~/US~3/0~773 ; .

means 210 and graphics controller 240 are also ::oupl d by data bus 230. The invention also includes second storage -:
means 220 for storing a second bit plane of visual data in a sec:ond forma~ differerlt from the first format. Second storage means 220 is couE~led to graphics controller 240 .
through storage bus 2 3 2 . Second storage means 2 2 0 and graphics colltroller 240 are also coupled by data bus 230a.
Graphics controller 240 includes means for foxming a merged ~.
pixel s~r~am from visual data stored on said f lrst and second storage means. Means 260 for displaying the merged pixel stream is alao provided. Means 260 is coupled to graphics controller 240 by pixel bus 250. In ~he preferred , e~odiment, data bus 230 and data bus z30a are separate eight bit buse~ ~ In an alternative embo~; mQ~t, a single 16 bit data ~s may be used to couple both f irst storage means 210 and second storage m~ans 220 to graphics contrc: ller 240 .
Data buses of oth~r~ width~ may also be used. Apparatus 200 functions: su~stantially in accordance with apparatus 100, -:
: . .
with a second storage me~ns having been rereived by re~

120. Apparatus 200 is thus configured to operate either in the ~ I)ual Color Space or the ~ n~3~A Single Frame Buffer M*des desc~ibed above.
: ~:~ ' ' :
The pre~ent invention may be embodied in other ~I specif ~ c ~orms w~thout departing from the spirit or e~entia~ attribu~es of the inv~ntion . ~ cordirlgly ~
refer~nc:e s~ould be made to ~he appended claims, rather than he ~or~going sp~cif ic:ation, as indic:ating the ~;cope of ~he inventiorl.

~ .
~ ~ 15

Claims

What is claimed is:

1. An apparatus for processing visual data, comprising:
(a) a first storage means providing first memory locations for storing graphics data in a color lookup table (CLUT) color format;
(b) a second storage means providing second memory locations for storing video data in a sub sampled YUV color format;
(c) means for up sampling the video data to provide up sampled video data and for forming a merged pixel stream from the graphics data and the up sampled video data, wherein said merged pixel stream is formed by means (c) employing chroma keying in which a pixel of the pixel stream represents video data when a corresponding graphics pixel of the graphics data represents a chroma key value; and (d) means for generating an analog signal representative of the merged pixel stream.

2. The apparatus of claim 1, further comprising:
(e) means for serially providing pixels of the graphics data stored in the first memory locations, wherein the first memory locations include dynamic random access memory locations.

3. The apparatus of claim 1, further comprising:
(e) means for serially providing pixels of the video data stored in the second memory locations, wherein the second memory locations include dynamic random access memory locations.

4. The apparatus of claim 1, wherein the analog signal is in an RGB
format.

5. The apparatus of claim 1, further comprising:
(e) means for serially providing pixels of the graphics data stored in the first memory locations; and (f) means for serially providing pixels of the video data stored in the second memory locations; wherein:
the first memory locations, means (e), the second memory locations, and means (f) are included in one or more random access memory devices;
means (c) is included in a graphics controller;
means (d) comprises a digital-to-analog converter; and the analog signal is in an RGB format;

6. The apparatus of claim 5, wherein all pixels of the merged pixel stream are in one color format.

7. The apparatus of claim 1, wherein means (b) comprises means for receiving the second storage means.

8. The apparatus of claim 1, wherein the sub sampled YUV color format is a sub sampled YUV4:1:1 color format.

9. The apparatus of claim 1, wherein the merged pixel stream formed by means (c) comprises 24-bit RGB pixels.

10. The apparatus of claim 1, wherein the graphics data and the video data represent images stored at different spatial resolutions.

11. A method for processing visual data, comprising the steps of:
(a) storing in first memory locations of a first storage means graphics data in a color lookup table (CLUT) color format;
(b) storing in second memory locations of a second storage means video data in a sub sampled YUV color format;
(c) up sampling the video data to provide up sampled video data and forming a merged pixel stream from the graphics data and the up sampled video data, wherein said merged pixel stream is formed by employing chroma keying in which a pixel of the pixel stream represents video data when a corresponding graphics pixel of the graphics data represents a chroma key value; and (d) generating an analog signal representative of the merged pixel stream.

12. The method of claim 11, further comprising the step of:
(e) serially providing pixels of the graphics data stored in the first memory locations, wherein the first memory locations include dynamic random access memory locations.

13. The method of claim 11, further comprising the step of:
(e) serially providing pixels of the video data stored in the second memory locations, wherein the second memory locations include dynamic random access memory locations.

14. The method of claim 11, wherein the analog signal is in an RGB
format.

15. The method of claim 11, further comprising the steps of:
(e) serially providing pixels of the graphics data stored in the first memory locations; and (f) serially providing pixels of the video data stored in the second memory locations; wherein:
the first memory locations, means for performing step (e), the second memory locations, and means for performing step (f) are included in one or more random access memory devices;
step (c) is implemented in a graphics controller;
step (d) comprises digital to analog conversion; and the analog signal is in an RGB format.

16. The method of claim 15, wherein all pixels of the merged pixel stream are in one color format.

17. The method of claim 11, wherein step (b) comprises the step of receiving the second storage means with a means for receiving the second storage means.

18. The method of claim 11, wherein the sub sampled YUV color format is a sub sampled YUV4: 1:1 color format.

19. The method of claim 11, wherein the merged pixel stream formed by step (c) comprises 24-bit RGB pixels.

20. The method of claim 11, wherein the graphics data and the video data represent images stored at different spatial resolutions.