CA2118147C - Method for lowering the phase transformation temperature of a metal silicide - Google Patents
Method for lowering the phase transformation temperature of a metal silicide Download PDFInfo
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- CA2118147C CA2118147C CA002118147A CA2118147A CA2118147C CA 2118147 C CA2118147 C CA 2118147C CA 002118147 A CA002118147 A CA 002118147A CA 2118147 A CA2118147 A CA 2118147A CA 2118147 C CA2118147 C CA 2118147C
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- refractory metal
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- 238000000034 method Methods 0.000 title claims description 76
- 229910052751 metal Inorganic materials 0.000 title abstract description 72
- 239000002184 metal Substances 0.000 title abstract description 72
- 229910021332 silicide Inorganic materials 0.000 title abstract description 50
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title abstract description 47
- 230000009466 transformation Effects 0.000 title abstract description 24
- 239000003870 refractory metal Substances 0.000 claims abstract description 150
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 101
- 239000010703 silicon Substances 0.000 claims abstract description 100
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 99
- 239000010936 titanium Substances 0.000 claims abstract description 54
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 50
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 49
- 229910052750 molybdenum Inorganic materials 0.000 claims abstract description 28
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 238000000151 deposition Methods 0.000 claims abstract description 27
- 238000000137 annealing Methods 0.000 claims abstract description 24
- 238000010438 heat treatment Methods 0.000 claims abstract description 23
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 21
- 229910052715 tantalum Inorganic materials 0.000 claims abstract description 18
- 229910052758 niobium Inorganic materials 0.000 claims abstract description 10
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 61
- 238000001704 evaporation Methods 0.000 claims description 22
- 230000008020 evaporation Effects 0.000 claims description 20
- 239000007943 implant Substances 0.000 claims description 14
- 238000005468 ion implantation Methods 0.000 claims description 11
- 229910045601 alloy Inorganic materials 0.000 claims description 7
- 239000000956 alloy Substances 0.000 claims description 7
- 238000004544 sputter deposition Methods 0.000 claims description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 6
- 239000008188 pellet Substances 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 238000001883 metal evaporation Methods 0.000 claims description 3
- 229910017604 nitric acid Inorganic materials 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 238000005477 sputtering target Methods 0.000 claims description 2
- 229910001069 Ti alloy Inorganic materials 0.000 claims 20
- 239000000758 substrate Substances 0.000 claims 8
- 239000002019 doping agent Substances 0.000 claims 4
- 239000012212 insulator Substances 0.000 claims 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims 2
- 229910052804 chromium Inorganic materials 0.000 claims 2
- 229910052720 vanadium Inorganic materials 0.000 claims 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims 1
- 238000005240 physical vapour deposition Methods 0.000 claims 1
- 229910052707 ruthenium Inorganic materials 0.000 abstract description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 4
- 239000010937 tungsten Substances 0.000 abstract description 4
- 229910017052 cobalt Inorganic materials 0.000 abstract description 3
- 239000010941 cobalt Substances 0.000 abstract description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 abstract description 3
- 239000012071 phase Substances 0.000 description 66
- 238000013459 approach Methods 0.000 description 25
- 229910008479 TiSi2 Inorganic materials 0.000 description 16
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 16
- 230000015572 biosynthetic process Effects 0.000 description 15
- 230000008569 process Effects 0.000 description 9
- 150000002500 ions Chemical class 0.000 description 8
- 210000003127 knee Anatomy 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 6
- 230000008901 benefit Effects 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 238000004151 rapid thermal annealing Methods 0.000 description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 238000005054 agglomeration Methods 0.000 description 4
- 230000002776 aggregation Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000011065 in-situ storage Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 4
- 239000011733 molybdenum Substances 0.000 description 4
- 239000010955 niobium Substances 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 3
- 229910021471 metal-silicon alloy Inorganic materials 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 239000007790 solid phase Substances 0.000 description 3
- 229910004339 Ti-Si Inorganic materials 0.000 description 2
- 229910010978 Ti—Si Inorganic materials 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 230000032798 delamination Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000006911 nucleation Effects 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000000877 morphologic effect Effects 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 238000000879 optical micrograph Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
Classifications
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/42—Silicides
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B1/00—Single-crystal growth directly from the solid state
- C30B1/02—Single-crystal growth directly from the solid state by thermal treatment, e.g. strain annealing
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/04—Dopants, special
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/147—Silicides
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- Metallurgy (AREA)
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- Computer Hardware Design (AREA)
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- Thermal Sciences (AREA)
- Ceramic Engineering (AREA)
- Mechanical Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemical Vapour Deposition (AREA)
- Silicon Compounds (AREA)
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Abstract
The phase transformation temperature of a metal silicide layer formed overlying a silicon layer on a semiconductor wafer is lowered.
First, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal. The precursory metal may be a refractory metal, and is preferably titanium, tungsten, or cobalt. The concentration of the refractory metal at the surface of the silicon layer is preferably less than about 101 atoms/cm3. The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The heating step used to form the silicide is performed at a temperature less than about 700°C, and more preferably between about 600-700°C. Optionally, the wafer is annealed following the step of disposing the refractory metal and prior to the step of depositing the precursory metal layer. Preferably, this annealing step is performed at a wafer temperature of at least about 900°C.
First, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal. The precursory metal may be a refractory metal, and is preferably titanium, tungsten, or cobalt. The concentration of the refractory metal at the surface of the silicon layer is preferably less than about 101 atoms/cm3. The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The heating step used to form the silicide is performed at a temperature less than about 700°C, and more preferably between about 600-700°C. Optionally, the wafer is annealed following the step of disposing the refractory metal and prior to the step of depositing the precursory metal layer. Preferably, this annealing step is performed at a wafer temperature of at least about 900°C.
Description
METHOD FOR LOWERING THE PHASE TRANSFORMATION
TEMPERATURE OF A METAL SILICIDE
FIELD OF THE INVENTION
The present invention relates generally to integrated circuit devices and, more particularly, to a method for forming a metal silicide layer overlying a silicon layer in an integrated circuit device where the phase transformation temperature of the metal silicide has been reduced by the use of a second refractory metal.
DESCRIPTION OF THE PRIOR ART
Titanium silicide has become the most widely-used silicide in the VLSI industry for self-aligned silicide applications because of its combined characteristics of low resistivity, the ability to be self-aligned, and relatively good thermal stability. Although TiSi2 has certain advantages relative to other silicides, the fact that it is a polymorphic material presents additional problems in its use. Specifically, in typical use TiSi2 exists as either an orthorhombic base-centered phase having 12 atoms per unit cell and a resistivity of about 60-90 micro-ohm-cm (known in the industry as the C49 phase), or as a more thermodynamically-favored orthorhombic face-centered phase which has 24 atoms per unit cell and a resistivity of about 12-20 micro-ohm-cm (known as the C54 phase).
When using the generally-accepted processing conditions for forming titanium silicide, the less-desirable, higher-resistivity C49 phase is formed first. In order to obtain the lower-resistivity C54 phase, a second high-temperature annealing step is required. This second step is disadvantageous because it can have detrimental effects on the silicide and other integrated circuit elements, especially at smaller line-widths. For example, the increasing use of dual-doped polysilicon gate structures in some devices has increased their sensitivity to additional heat cycles, as is ._ 21 1 8 1 47 required by the second anneal step. Also, silicon nitride peeling and cracking have been associated with the second annealing step.
The generally accepted set of processing conditions for forming titanium silicide include: (1) pre-cleaning, (2) titanium deposition, (3) silicide formation at a temperature less than about 700°C, (4) selective etching, and (5) a phase transformation anneal at a temperature greater than about 700°C. It is the phase transformation anneal that converts the dominant C49 phase to the C54 phase. The initial formation temperature is kept below 700°C
in order to minimize over-spacer bridging. The second transformation anneal is performed after any un-reacted titanium has been selectively removed and is generally performed at temperatures of 50-200°C above the formation temperature to insure full transformation to the C54 phase for best control of sheet resistance. However, as device line-widths and silicide film thicknesses continue to be scaled down, it becomes ever more desirable to eliminate the need for this second anneal step, as discussed further below.
It is generally accepted that the C49 phase forms first because of a lower surface energy than that of the C54 phase. In other words, the higher surface energy of the C54 phase forms a higher energy barrier to its formation. The second transformation anneal step used in the standard process above provides the additional thermal energy necessary to both overcome the nucleation barrier associated with forming the new surface and growing the crystalline structure of the newly-forming C54 phase. In VLSI
applications, if the phase transformation is inhibited or fails to occur uniformly, a degradation in circuit performance is observed.
In some higher-performance circuits, the RC delay associated with a poor phase transformation is typically about 5-10 percent.
A significant limitation on the C49-to-C54 phase transformation is a phenomenon known as agglomeration. If the thermal energy used to obtain the phase transformation is excessive, then a morphological degradation of the titanium silicide results, which is commonly referred to as agglomeration.
As line-widths and silicide film thicknesses decrease, the thermal energy required to affect the C49-to-C54 phase transformation increases, yet the thermal energy level at which the silicide film starts to agglomerate decreases. Thus, there is an ever-shrinking process window for performing this phase transformation, making process control and uniformity more difficult to achieve.
Thus, there is a need for an improved method for forming the C54 phase of titanium silicide without requiring a second high-temperature annealing step, as in the generally-accepted process above. Eliminating the second annealing step would reduce the problems and limitations resulting from agglomeration of silicide films during the phase transformation anneal.
SUMMARY OF THE INVENTION
This need is satisfied, the limitations of the prior art overcome, and other benefits realized in accordance with the principles of the present invention by a method for forming a metal silicide overlying a silicon layer on a semiconductor wafer.
According to this method, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal (later used to form the metal silicide) is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal.
It should be noted that the term "precursory" is used throughout for purposes of identification and clarity only and does not itself imply any chemical properties of the metal it identifies.
In addition to the precursory metal itself, the precursory 21 18 14~
metal layer may also incorporate silicon, as for example in the known polycide process. When the precursory metal layer incorporates silicon, the final metal silicide is obtained by heating the wafer to a temperature sufficient to obtain the desired solid phase following deposition of the metal-silicon alloy (which in some cases may be stoichiometric). In addition to Si, the precursory metal layer may incorporate other elements from periodic table Groups IIB, IIIB, IVB, VB, and VIB, including B, C, N, O, A1, P , S, Zn, Ga, Ge, As, Se, Cd, In, Sn, Sb, Te, Mg, T1, Pb and Bi.
Preferably, the phase transformation temperature of the metal silicide is lowered by the presence of the refractory metal at the surface of the silicon layer. The precursory metal may be a refractory metal, and is preferably titanium, tungsten, or cobalt.
The precursory metal may also be molybdenum, nickel, platinum, or palladium. Further, the precursory metal generally forms a metal silicide having a metastable solid phase. The refractory metal is preferably a metal that is capable of forming a metal silicide when heated to a temperature greater than about 900°C, and the concentration of the refractory metal at the surface of the silicon layer is preferably less than about 101' atoms/cm3. The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The silicon layer may be monocrystalline or polycrystalline, but is preferably polycrystalline. The heating step used to form the silicide is performed at a temperature less than about 700°C, and more preferably between about 600-700°C.
There are several approaches for disposing the refractory metal that may be used. In general, these methods of disposition place refractory metal atoms on or within a few Angstroms of the surface, for example within about 2 Angstroms. A first preferred approach for disposing the refractory metal is by ion implantation with a dose of about lOlz to 5x1014 atoms/cmz, and more preferably a dose of about 1013 to 1014 atoms/cmz. The preferred implant energy .. 211814 is about 45 to 90 KeV. In another preferred approach, the refractory metal is disposed on the surface of the silicon layer by evaporation of, say, a metal pellet. Also, the refractory metal may be disposed by sputtering or by exposing the surface of the silicon layer to a solution containing ions of the refractory metal. For example, the solution may be a dilute acid solution containing HC1 or nitric acid. Under all of the above disposition approaches except implantation, the thickness of the disposed refractory metal layer on the silicon surface is preferably less than about 2.0 nm, and more preferably about 0.5 to 1.5 nm.
Optionally, the wafer is annealed following the step of disposing the refractory metal and prior to the step of depositing the precursory metal layer. Preferably, this annealing step is performed at a wafer temperature of at least about 900°C, and more preferably between about 900 and 1000°C. In one approach, this annealing is performed for at least about 5 seconds using rapid thermal annealing (RTA). Alternatively, annealing in a furnace for at least about 10 minutes may be used.
In a more preferred approach to the present invention, a titanium silicide layer is formed overlying a silicon layer on a semiconductor wafer. According to this approach, a refractory metal is disposed proximate to the surface of the silicon layer, a titanium layer is deposited overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the titanium silicide layer at least in part from the titanium layer.
Preferably, the titanium silicide layer formed during this heating step substantially exhibits the C54 phase of TiSi2. Preferably, the titanium layer is deposited to a thickness of about 25-57.5 nm, and the TiSi2 layer is formed at a temperature less than about 700°C, and more preferably about 600-700°C. Also, the refractory metal is preferably Mo, Co, or W and is preferably disposed by either ion implantation or metal evaporation. It has been found 211814?
that Mo and Co give the best results, even relative to W. Ion implantation is preferably performed with an implant dose of about 1013 to ld4 atoms/c~n . Preferably, the optional annealing step described above is performed.
In an alternative embodiment according to the present invention, a metal silicide is formed in a layer overlying a silicon layer on a semiconductor wafer by a method comprising the steps of depositing a precursory metal layer overlying the silicon layer, where the precursory metal layer contains a small quantity of a refractory metal, and heating the wafer to a temperature sufficient to form the metal silicide from the precursory metal layer, where the phase transformation temperature of said metal silicide is lowered by the presence of said refractory metal at the surface of said silicon layer. Preferably, the precursory metal and the refractory metal are deposited from the same source, and more preferably the atomic percentage of the refractory metal layer in the source is less than about 1 percent.
In a preferred approach according to the alternative embodiment, a titanium layer is deposited from a source of titanium which also contains a small quantity of a refractory metal. The wafer is then heated to a temperature sufficient to substantially form the C54 phase of titanium silicide. Preferably this temperature is less than about 700°C, and the atomic percentage of the refractory metal is less than about 1 atomic percent of the combined titanium and refractory metal weight.
An advantage of the present invention is that a phase transformation annealing step is eliminated. For example, with respect to titanium silicide the desired C54 phase is substantially formed directly during the titanium silicide formation step. No second phase transformation anneal is required. Also, agglomeration is essentially eliminated because the titanium silicide film is exposed to lower processing temperatures. As other advantages of the present invention, there is improved ability to control the microstructure of the final C54 phase of the silicide film, and the small grain size of the C54 phase grains may be less than the critical dimensions of the devices being fabricated.
The foregoing and other objects, features, and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1-3 are cross-sections illustrating the formation of the C54 phase of titanium silicide according to a preferred approach of the present invention.
FIG. 4 is a graph of the sheet resistance of a titanium silicide layer versus sputtered titanium thickness for several process cases with and without the use of a refractory metal according to the present invention.
FIGS. 5-8 are in-situ scanning resistance graphs illustrating the sheet resistance of titanium silicide layers being formed for several process cases with and without the use of an evaporated or implanted refractory metal according to the present invention.
FIG. 9 is a histogram of the measured resistance of titanium silicide lines with and without a Mo ion implant according to the present invention.
BEST MODE FOR CARRYING OUT THE INVENTION
211814?
In a preferred approach according to the present invention, a titanium silicide layer having the C54 phase as the dominant phase is formed on a silicon layer by a single silicidation heating step.
Because the TiSi2 layer is formed having substantially the C54 phase, a second annealing step, which is required with prior methods, is not needed to transform the Ti5i2 from the C49 to the C54 phase. In this preferred approach a refractory metal is disposed proximate to the surface of the silicon layer, and a titanium layer is deposited over the refractory metal and the silicon surface. The wafer is then heated to a temperature of about 600 to 700°C for a time period sufficient to form the C54 phase of titanium silicide.
More specifically, with reference to FIG. 1, a silicon layer 10, which may be a monocrystalline silicon wafer (100) or polycrystalline silicon, is provided. Silicon layer 10 may be, for example, a polycrystalline N or P-type line or a monocrystalline N
or P-type region. The refractory metal is disposed either on or near a top surface 12 of silicon layer 10, depending in part on the manner in which the metal is disposed. It is believed that the refractory metal acts to lower the surface energy barrier for the formation of the C54 phase of TiSi2, and therefore, that the presence of the refractory metal at or near the surface promotes the formation of the C54 phase. It is believed that a refractory metal-silicon alloy is formed near top surface 12. It is not known with certainty whether this is a metal-silicon complex or a metal-silicon compound. In general, some of the disposed refractory metal should be on or within a few Angstroms of top surface 12. Of course, the exact disposition of the refractory metal atoms will depend upon the manner of disposition. However, for purposes of this application each manner of diposition described herein is considered to dispose refractory metal atoms proximate to the silicon surface.
Referring now to FIG. 2, a refractory metal 14 is shown proximate to the surface of silicon layer 10. First, it should be appreciated that FIG. 2 is for illustrative purposes only and that refractory metal 14 will not necessarily cover all of top surface 12. Second, it should be noted that distribution of refractory metal 14 will vary also depending upon the manner of disposition.
For example, if refractory metal 14 is disposed by ion implantation, then most of the metal will be below top surface 12.
On the other hand, if the metal is disposed by evaporation, then most of the metal will be disposed on top surface 12, rather than underneath it. With both the ion implantation and evaporation approaches, it is believed that it is the concentration of the refractory metal proximate to top surface 12 that lowers the C54 phase surface energy barrier. After refractory metal 14 is disposed, then a titanium layer 16 is deposited over refractory metal 14 by, say, sputtering or evaporation. For example, a thickness of 25 to 57.5 nm is used, although one skilled in the art will recognize that greater and lesser thicknesses may also be used. Top surface 12 is not explicitly shown in FIG. 2 because its position will vary according to the manner of refractory metal disposition used.
In addition to sputtering or evaporation, titanium layer 16 may also be deposited over refractory metal 14 by chemical vapor deposition. Further, when deposited by one of these methods, instead of an essentially titanium layer, a layer containing an alloy of Ti and Si may be deposited. This alloy may be stoichiometric TiSi2, but this is not required, and the Ti-Si alloy may be either rich or lean in its silicon composition. When a Ti-Si alloy is deposited, the method according to the present invention is substantially similar to that described herein. Any required modifications will be recognized by one of skill in the art. Also, as used herein, the deposition of a titanium layer may alternatively refer to the deposition of a titanium-silicon alloy layer.
In FIG. 3, a TiSi2 film 18 has been formed over silicon layer by heating silicon layer 10 to a temperature between about 600 5 and 700°C for a time period sufficient for the C54 phase of TiSi2 to form. This time period is generally about 20 seconds for RTA to about 20 minutes for annealing in a conventional furnace.
According to the method of the present invention, it is believed that the forming TiSiz film does not substantially pass through the 10 C49 phase, but primarily goes directly to the C54 phase due to the lowered surface energy barrier.
An optional annealing step has been found beneficial for further promoting the formation of the C54 phase of TiSi2, especially when forming the silicide at lower temperatures, say below about 650°C. This optional anneal is performed following the disposition of refractory metal 14 and prior to the deposition of Ti layer 16. In general, this anneal is performed at a wafer temperature of at least about 900°C, and more preferably 900-1000°C, for a time period of at least about 5 seconds when using RTA and of generally about 10-30 minutes when using a conventional quartz furnace. A preferred anneal is at a temperature of about 900°C for about 10 minutes in a furnace in a NZ ambient. It is believed that this optional anneal may further promote the formation of the refractory metal-silicon alloy at the surface of the silicon layer, though this is not certain.
In general, it is believed that the refractory metal according to the method of the present invention may be any metal capable of forming a metal silicide when heated in the presence of silicon to a temperature greater than about 900°C. For the purposes of this application, "refractory metal" is defined to include, without limitation, the following preferred metals: Mo, Co, W, Ta, Nb, Ru, or Cr. Mo and Co provide the most significant effect, and W
~ 2118147 provides a somewhat less significant effect than Mo or Co. It is believed that the above metals will in general work with any of the herein disclosed manners of disposition, but ion implantation and evaporation of Mo, Co, and W are preferred approaches.
Discussing now the above silicidation process in greater detail, there are several approaches for disposing the refractory metal that may be used. In general, these methods of disposition place refractory metal atoms on or within a few Angstroms of top surface 12. It is believed that the refractory metal atoms closest to the silicon interface are most active, but other more distant atoms are not excluded from the meaning of proximate as used herein. For example, atoms within about 2 Angstroms (i.e. about 0.2 nm) of the surface may be the most active. A first preferred approach for disposing the refractory metal is by ion implantation with a dose of about 101 to 5x144 atoms/cr~ and even more preferably a dose of about 1013 to 1014 atoms/cr~ . The preferred implant energy for these cases is about 45 to 90 KeV.
One way for implanting refractory metals involves the use of the arc chamber of commercially available ion implant systems.
Because the arc chamber is commonly made from, or in other cases lined with, refractory metals (such a molybdenum, niobium, tantalum, or tungsten), one method of implanting these metals is accomplished by using the arc chamber as the source of the metal to be implanted. The metal species to be implanted is selected by appropriately varying the arc chamber material and by adjusting the magnetic analyzer to select the desired atomic mass unit (AMU) of the metal species based on the known isotopes of the desired species. For example, an appropriate setting is 98 AMU for Mo, or 184 for W. Because W is also a common filament material in the ion source filament of the implant tool, W can be alternatively implanted by adjusting the analyzer magnet to 184 AMU for singly-ionized W, or to 92 AMU for doubly-ionized W. The dose and energy . 2118147 selected for a particular metal species will be limited by the capabilities of the ion implant system and the time devoted to performing the implant.
For the specific case of a Mo implant, a Mo arc chamber is installed into the implant system, a boron triflouride source gas (BF3) is introduced into the arc chamber. It is believed that ionized BF3 acts to volatilize molybdenum from the arc chamber to provide an adequate Mo ion ( 98Mo+) beam current of about 200 mA
with an implant energy of at least about 45 KeV. Because arc chambers sometimes become coated with other materials during use in other conventional applications, it is preferred that a clean or new source chamber be used to obtain the Mo ion beam current.
When implanting Mo atoms under the above conditions (i.e. an energy of 45 KeV), it has been determined that the greatest concentration of Mo atoms occurs at a depth in the silicon layer of about 30 nm, corresponding to a peak Mo concentration of about 1019 atoms/cm3. However, as discussed above, the Mo atom concentration of greatest interest is that at the surface. When using the optional anneal step above, SIMS data has indicated that the concentration of Mo atoms at the surface is about 5x1018 atoms/cm3.
It is expected that a surface concentration of the refractory metal at the silicon interface less than about 101' atoms/cm~ may be desirable.
In another preferred approach, the refractory metal is disposed on the surface of the silicon layer by evaporation of, say, a metal pellet. This may be by either e-beam evaporation or by resistive heating (e.g, placing the pellet in a crucible that is heated by a large electrical current). When using evaporation, it is important that the thickness of the refractory metal not be too great. For example, the thickness of a Mo layer disposed on the silicon layer is preferably less than about 2.0 nm. This is not an absolute maximum thickness, but as the thickness of the Mo layer increases above 2.0 nm, peeling of the silicide film has been observed. More preferably, a Mo thickness of about 0.5-1.5 nm is used. The desired thicknesses for other metals may vary somewhat.
When evaporating such small thicknesses of refractory metal onto the silicon layer, it is sometimes difficult to control the rate of evaporation. As a result, in one evaporation approach a shutter is positioned over the evaporation metal source chamber to contain the refractory metal until ready for disposition on the silicon layer. Then, the shutter is opened and closed fairly rapidly (a so-called "flash" evaporation) to provide a thin refractory metal layer over the silicon layer. Other evaporation approaches could be used that better control the rate of evaporation.
As an alternative to evaporation of the refractory metal, the refractory metal may instead be disposed by sputtering to a thickness on the silicon layer similar to that described for evaporation above. Modifications used with a sputtering approach will be recognized by one skilled in the art.
In addition to the above, the refractory metal may be disposed on the silicon layer by exposing the surface of the silicon layer to a solution containing ions of the refractory metal. In a preferred approach, the solution is aqueous and may contain a dilute acid, such as HC1 or nitric acid.
Although a preferred approach of the present invention has been described above, it is not intended that the practice of the invention be limited only to the formation of titanium silicide films. Rather, the present invention presents a method for other metal silicides that are to be formed on a silicon layer on a semiconductor wafer. According to this method, a refractory metal Z~ 1a~47 is disposed proximate to the surface of the silicon layer, a precursory metal is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal.
It is believed that the phase transformation temperature of the metal silicide is lowered by the presence of the refractory metal at the surface of the silicon layer. For example, because of the small grain size of C54-phase TiSiz films, it is believed that the activation energy for the phase transformation to the C54 phase is lowered. The precursory metal may be a refractory metal, and is preferably titanium (as discussed above), tungsten, or cobalt. The precursory metal may also be molybdenum, nickel, platinum, or palladium. Further, the precursory metal is one that generally forms a metal silicide having more than one solid phase. The refractory metal is preferably a metal that is capable of forming a metal silicide. The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The silicon layer may be monocrystalline or polycrystalline. The heating step used to form the silicide is performed at a temperature less than about 700°C, and more preferably between about 600-700°C. These temperatures are preferred for TiSi2, and may vary some for other metal silicides.
The several approaches for disposing the refractory metal discussed above may in general be used for the general method of the invention. Preferably, the refractory metal atoms are placed on or within a few Angstroms of the surface, and the thickness of these atoms is sufficiently thin to avoid silicide delamination due to stress effects.
As for the TiSi2 approach above, the wafer is optionally annealed following the step of disposing the refractory metal and prior to the step of depositing the precursory metal layer.
Preferably, this annealing step is performed at a wafer temperature of at least about 900°C, and more preferably between about 900 and 1000°C.
FIGS. 4-9 present experimental data for several TiSi2 films formed according to the present invention. FIG. 4 is a graph of the sheet resistance of a titanium silicide layer versus sputtered titanium thickness for several process cases with and without the use of a refractory metal according to the present invention. The data indicated as a standard film was formed without a refractory metal and without a second phase transformation anneal. The TiSiz films corresponding to the data point for W, and the data for Mo were formed by a 600°C anneal for 30 minutes in N2 on (100) single-crystal silicon according to the present invention. An optional 5 second, 1000°C, RTA anneal was used following the implantation of the refractory metal (used for both W and Mo). The optional anneal is necessary when the TiSi2 film is formed at about 600°C, but is not necessary for a formation temperature of about 700°C. The sheet resistance for each film is indicated by the data points in the graph.
FIGS. 5-7 are in-situ scanning resistance graphs illustrating the sheet resistance of titanium silicide layers being formed for several process cases both with and without the use of an evaporated refractory metal according to the present invention.
These measurements were made by continuously placing a four-point probe within a furnace during the formation of the TiSiz films.
The refractory metal in FIGS. 5-7, where used, was disposed by the "flash" evaporation method described above. FIG. 8 is an in-situ scanning resistance graph for TiSiz films where an implanted, rather than evaporate, refractory metal was used. Common conditions for FIGS. 5-8 include the formation of a silicide film from a Ti layer of about 57.5 nm thickness previously deposited over an approximately 300 nm polysilicon layer. Each silicide film 211814' was formed by gradually increasing temperature at about 15°C per minute.
Looking now at FIG. 5, curve 30 shows sheet resistance behavior for a titanium silicide film formed without the use of a refractory metal. Curve 30 exhibits the known and expected alloy effect at about point 32, with curve 30 forming a resistance peak at about 500°C. Above about 500°C, its resistance drops as indicated by arrow 34. As the temperature moves from about 500°C
to about 700°C, the forming TiSiz film is substantially in the C49 phase. At about 700°C curve 30 flattens out into a so-called "knee" at point 36 in which the resistance is substantially constant with increasing temperature. This "knee" results from the failure of the silicide film to convert from the C49 phase to the C54 phase until even higher temperatures are reached. In contrast to curve 30, curve 40 illustrates resistance for a silicide film formed following the disposition of about 0.015 nm of Mo according to the present invention. Behavior is similar, but note that the "knee" observed for curve 30 above is substantially not present for curve 40 (see point 42). It is believed that the absence of this knee indicates that the C54 phase of TiSiz is directly formed to a substantial degree during silicidation without passing through the C49 phase.
In FIG. 6, curve 50 shows sheet resistance behavior for a forming silicide film where about a 0.015 nm Ta layer was disposed by flash evaporation according to the present invention. As for curve 40 in FIG. 5, no significant knee is observed during the formation of the C54 phase of TiSi2. In FIG. 7, curve 60 illustrates sheet resistance versus temperature for a TiSiz film formed using about 0.015 nm of W according to the present invention. Curves 30 and 40 are shown for comparison with curve 60. Again, for curve 60 there is no significant knee and the C54 phase is substantially formed at a temperature less than about 21 1814?
700°C.
FIG. 8 is an in-situ scanning resistance graph illustrating the sheet resistance of a titanium silicide layer formed using an implanted refractory metal according to the present invention.
Curve 70 is a control silicide film formed without a refractory metal, for comparison purposes, and curve 80 is a TiSiz film formed where Mo has been implanted (at a dosage of 1014 atoms/cm2 and an implant energy of 45 KeV) prior to depositing Ti. After implanting Mo, an annealing step was performed at 900°C for 10 minutes also prior to depositing Ti. As for the conventional curve 30 above, curve 70 exhibits a knee at point 72, but curve 80 does not. The absence of a knee for curve 80 indicates that the C54 phase of TiSi2 is substantially formed at temperatures below about 700°C.
FIG. 9 is a histogram of the measured resistance of titanium silicide lines with and without a Mo ion implant according to the present invention.
In addition to the data presented in FIGS. 4-9 above, there is further support that the C49 phase is substantially by-passed in silicidation by the present invention. Optical micrographs of the C54 phase of titanium silicide layers formed according to the present invention have indicated a grain size significantly smaller than in the conventional case without a refractory metal. This supports that the nucleation energy barrier of the C54 phase is significantly reduced by the method of the present invention. This becomes most important in VLSI circuits where the linewidths are less than the grain size of the C54 phase that would be formed if using the conventional approach.
Although it is believed that the method according to the present invention described above is fairly robust, there are some precautions to its use. First, heat cycles above 700°C for BU9-93-016 lg extended periods must be avoided when using the present invention to prevent possible silicide instability problems. Second, if the thickness of the refractory metal layer is too great, then delamination of the silicide may result.
Another advantage of the present invention is that it does not create an amorphous silicon layer at the top surface of the silicon layer. Specifically, when using the ion implantation method to dispose the refractory metal, the optional annealing step removes any amorphous silicon that may be present. The optional anneal is not necessary with the other manners of disposition in order to avoid amorphous silicon. It is desirable to avoid the presence of amorphous silicon because it has been associated with junction leakage failures.
In an alternative embodiment according to the present invention, a metal silicide is formed in a layer overlying a silicon layer on a semiconductor wafer by a method comprising the steps of depositing a precursory metal layer overlying the silicon layer, where the precursory metal layer contains a small quantity of a refractory metal, and heating the wafer to a temperature sufficient to form the metal silicide from the precursory metal layer, where the phase transformation temperature of said metal silicide is lowered by the presence of said refractory metal at the surface of said silicon layer. Preferably, the precursory metal and the refractory metal are deposited from the same source, and more preferably the atomic percentage of the refractory metal layer in the source is less than about 1 percent. The preferred refractory metals discussed above are expected to also be useful with this embodiment.
In a preferred approach according to the alternative embodiment, a titanium layer is deposited from a source of titanium which also contains a small quantity of a refractory metal. The wafer is then heated to a temperature sufficient to substantially form the C54 phase of titanium silicide. Preferably this temperature is less than about 700°C, and the atomic percentage of the refractory metal is less than about one atomic percent of the combined titanium and refractory metal weight. The source of the titanium may be a sputtering target or evaporation pellet.
Although the present invention has been described in detail above, it is not intended to be limited to the specific form set forth herein, but, on the contrary, it is intended to cover such alternatives and equivalents as can reasonably be included within the spirit and scope of the invention as defined by the appended claims.
TEMPERATURE OF A METAL SILICIDE
FIELD OF THE INVENTION
The present invention relates generally to integrated circuit devices and, more particularly, to a method for forming a metal silicide layer overlying a silicon layer in an integrated circuit device where the phase transformation temperature of the metal silicide has been reduced by the use of a second refractory metal.
DESCRIPTION OF THE PRIOR ART
Titanium silicide has become the most widely-used silicide in the VLSI industry for self-aligned silicide applications because of its combined characteristics of low resistivity, the ability to be self-aligned, and relatively good thermal stability. Although TiSi2 has certain advantages relative to other silicides, the fact that it is a polymorphic material presents additional problems in its use. Specifically, in typical use TiSi2 exists as either an orthorhombic base-centered phase having 12 atoms per unit cell and a resistivity of about 60-90 micro-ohm-cm (known in the industry as the C49 phase), or as a more thermodynamically-favored orthorhombic face-centered phase which has 24 atoms per unit cell and a resistivity of about 12-20 micro-ohm-cm (known as the C54 phase).
When using the generally-accepted processing conditions for forming titanium silicide, the less-desirable, higher-resistivity C49 phase is formed first. In order to obtain the lower-resistivity C54 phase, a second high-temperature annealing step is required. This second step is disadvantageous because it can have detrimental effects on the silicide and other integrated circuit elements, especially at smaller line-widths. For example, the increasing use of dual-doped polysilicon gate structures in some devices has increased their sensitivity to additional heat cycles, as is ._ 21 1 8 1 47 required by the second anneal step. Also, silicon nitride peeling and cracking have been associated with the second annealing step.
The generally accepted set of processing conditions for forming titanium silicide include: (1) pre-cleaning, (2) titanium deposition, (3) silicide formation at a temperature less than about 700°C, (4) selective etching, and (5) a phase transformation anneal at a temperature greater than about 700°C. It is the phase transformation anneal that converts the dominant C49 phase to the C54 phase. The initial formation temperature is kept below 700°C
in order to minimize over-spacer bridging. The second transformation anneal is performed after any un-reacted titanium has been selectively removed and is generally performed at temperatures of 50-200°C above the formation temperature to insure full transformation to the C54 phase for best control of sheet resistance. However, as device line-widths and silicide film thicknesses continue to be scaled down, it becomes ever more desirable to eliminate the need for this second anneal step, as discussed further below.
It is generally accepted that the C49 phase forms first because of a lower surface energy than that of the C54 phase. In other words, the higher surface energy of the C54 phase forms a higher energy barrier to its formation. The second transformation anneal step used in the standard process above provides the additional thermal energy necessary to both overcome the nucleation barrier associated with forming the new surface and growing the crystalline structure of the newly-forming C54 phase. In VLSI
applications, if the phase transformation is inhibited or fails to occur uniformly, a degradation in circuit performance is observed.
In some higher-performance circuits, the RC delay associated with a poor phase transformation is typically about 5-10 percent.
A significant limitation on the C49-to-C54 phase transformation is a phenomenon known as agglomeration. If the thermal energy used to obtain the phase transformation is excessive, then a morphological degradation of the titanium silicide results, which is commonly referred to as agglomeration.
As line-widths and silicide film thicknesses decrease, the thermal energy required to affect the C49-to-C54 phase transformation increases, yet the thermal energy level at which the silicide film starts to agglomerate decreases. Thus, there is an ever-shrinking process window for performing this phase transformation, making process control and uniformity more difficult to achieve.
Thus, there is a need for an improved method for forming the C54 phase of titanium silicide without requiring a second high-temperature annealing step, as in the generally-accepted process above. Eliminating the second annealing step would reduce the problems and limitations resulting from agglomeration of silicide films during the phase transformation anneal.
SUMMARY OF THE INVENTION
This need is satisfied, the limitations of the prior art overcome, and other benefits realized in accordance with the principles of the present invention by a method for forming a metal silicide overlying a silicon layer on a semiconductor wafer.
According to this method, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal (later used to form the metal silicide) is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal.
It should be noted that the term "precursory" is used throughout for purposes of identification and clarity only and does not itself imply any chemical properties of the metal it identifies.
In addition to the precursory metal itself, the precursory 21 18 14~
metal layer may also incorporate silicon, as for example in the known polycide process. When the precursory metal layer incorporates silicon, the final metal silicide is obtained by heating the wafer to a temperature sufficient to obtain the desired solid phase following deposition of the metal-silicon alloy (which in some cases may be stoichiometric). In addition to Si, the precursory metal layer may incorporate other elements from periodic table Groups IIB, IIIB, IVB, VB, and VIB, including B, C, N, O, A1, P , S, Zn, Ga, Ge, As, Se, Cd, In, Sn, Sb, Te, Mg, T1, Pb and Bi.
Preferably, the phase transformation temperature of the metal silicide is lowered by the presence of the refractory metal at the surface of the silicon layer. The precursory metal may be a refractory metal, and is preferably titanium, tungsten, or cobalt.
The precursory metal may also be molybdenum, nickel, platinum, or palladium. Further, the precursory metal generally forms a metal silicide having a metastable solid phase. The refractory metal is preferably a metal that is capable of forming a metal silicide when heated to a temperature greater than about 900°C, and the concentration of the refractory metal at the surface of the silicon layer is preferably less than about 101' atoms/cm3. The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The silicon layer may be monocrystalline or polycrystalline, but is preferably polycrystalline. The heating step used to form the silicide is performed at a temperature less than about 700°C, and more preferably between about 600-700°C.
There are several approaches for disposing the refractory metal that may be used. In general, these methods of disposition place refractory metal atoms on or within a few Angstroms of the surface, for example within about 2 Angstroms. A first preferred approach for disposing the refractory metal is by ion implantation with a dose of about lOlz to 5x1014 atoms/cmz, and more preferably a dose of about 1013 to 1014 atoms/cmz. The preferred implant energy .. 211814 is about 45 to 90 KeV. In another preferred approach, the refractory metal is disposed on the surface of the silicon layer by evaporation of, say, a metal pellet. Also, the refractory metal may be disposed by sputtering or by exposing the surface of the silicon layer to a solution containing ions of the refractory metal. For example, the solution may be a dilute acid solution containing HC1 or nitric acid. Under all of the above disposition approaches except implantation, the thickness of the disposed refractory metal layer on the silicon surface is preferably less than about 2.0 nm, and more preferably about 0.5 to 1.5 nm.
Optionally, the wafer is annealed following the step of disposing the refractory metal and prior to the step of depositing the precursory metal layer. Preferably, this annealing step is performed at a wafer temperature of at least about 900°C, and more preferably between about 900 and 1000°C. In one approach, this annealing is performed for at least about 5 seconds using rapid thermal annealing (RTA). Alternatively, annealing in a furnace for at least about 10 minutes may be used.
In a more preferred approach to the present invention, a titanium silicide layer is formed overlying a silicon layer on a semiconductor wafer. According to this approach, a refractory metal is disposed proximate to the surface of the silicon layer, a titanium layer is deposited overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the titanium silicide layer at least in part from the titanium layer.
Preferably, the titanium silicide layer formed during this heating step substantially exhibits the C54 phase of TiSi2. Preferably, the titanium layer is deposited to a thickness of about 25-57.5 nm, and the TiSi2 layer is formed at a temperature less than about 700°C, and more preferably about 600-700°C. Also, the refractory metal is preferably Mo, Co, or W and is preferably disposed by either ion implantation or metal evaporation. It has been found 211814?
that Mo and Co give the best results, even relative to W. Ion implantation is preferably performed with an implant dose of about 1013 to ld4 atoms/c~n . Preferably, the optional annealing step described above is performed.
In an alternative embodiment according to the present invention, a metal silicide is formed in a layer overlying a silicon layer on a semiconductor wafer by a method comprising the steps of depositing a precursory metal layer overlying the silicon layer, where the precursory metal layer contains a small quantity of a refractory metal, and heating the wafer to a temperature sufficient to form the metal silicide from the precursory metal layer, where the phase transformation temperature of said metal silicide is lowered by the presence of said refractory metal at the surface of said silicon layer. Preferably, the precursory metal and the refractory metal are deposited from the same source, and more preferably the atomic percentage of the refractory metal layer in the source is less than about 1 percent.
In a preferred approach according to the alternative embodiment, a titanium layer is deposited from a source of titanium which also contains a small quantity of a refractory metal. The wafer is then heated to a temperature sufficient to substantially form the C54 phase of titanium silicide. Preferably this temperature is less than about 700°C, and the atomic percentage of the refractory metal is less than about 1 atomic percent of the combined titanium and refractory metal weight.
An advantage of the present invention is that a phase transformation annealing step is eliminated. For example, with respect to titanium silicide the desired C54 phase is substantially formed directly during the titanium silicide formation step. No second phase transformation anneal is required. Also, agglomeration is essentially eliminated because the titanium silicide film is exposed to lower processing temperatures. As other advantages of the present invention, there is improved ability to control the microstructure of the final C54 phase of the silicide film, and the small grain size of the C54 phase grains may be less than the critical dimensions of the devices being fabricated.
The foregoing and other objects, features, and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1-3 are cross-sections illustrating the formation of the C54 phase of titanium silicide according to a preferred approach of the present invention.
FIG. 4 is a graph of the sheet resistance of a titanium silicide layer versus sputtered titanium thickness for several process cases with and without the use of a refractory metal according to the present invention.
FIGS. 5-8 are in-situ scanning resistance graphs illustrating the sheet resistance of titanium silicide layers being formed for several process cases with and without the use of an evaporated or implanted refractory metal according to the present invention.
FIG. 9 is a histogram of the measured resistance of titanium silicide lines with and without a Mo ion implant according to the present invention.
BEST MODE FOR CARRYING OUT THE INVENTION
211814?
In a preferred approach according to the present invention, a titanium silicide layer having the C54 phase as the dominant phase is formed on a silicon layer by a single silicidation heating step.
Because the TiSi2 layer is formed having substantially the C54 phase, a second annealing step, which is required with prior methods, is not needed to transform the Ti5i2 from the C49 to the C54 phase. In this preferred approach a refractory metal is disposed proximate to the surface of the silicon layer, and a titanium layer is deposited over the refractory metal and the silicon surface. The wafer is then heated to a temperature of about 600 to 700°C for a time period sufficient to form the C54 phase of titanium silicide.
More specifically, with reference to FIG. 1, a silicon layer 10, which may be a monocrystalline silicon wafer (100) or polycrystalline silicon, is provided. Silicon layer 10 may be, for example, a polycrystalline N or P-type line or a monocrystalline N
or P-type region. The refractory metal is disposed either on or near a top surface 12 of silicon layer 10, depending in part on the manner in which the metal is disposed. It is believed that the refractory metal acts to lower the surface energy barrier for the formation of the C54 phase of TiSi2, and therefore, that the presence of the refractory metal at or near the surface promotes the formation of the C54 phase. It is believed that a refractory metal-silicon alloy is formed near top surface 12. It is not known with certainty whether this is a metal-silicon complex or a metal-silicon compound. In general, some of the disposed refractory metal should be on or within a few Angstroms of top surface 12. Of course, the exact disposition of the refractory metal atoms will depend upon the manner of disposition. However, for purposes of this application each manner of diposition described herein is considered to dispose refractory metal atoms proximate to the silicon surface.
Referring now to FIG. 2, a refractory metal 14 is shown proximate to the surface of silicon layer 10. First, it should be appreciated that FIG. 2 is for illustrative purposes only and that refractory metal 14 will not necessarily cover all of top surface 12. Second, it should be noted that distribution of refractory metal 14 will vary also depending upon the manner of disposition.
For example, if refractory metal 14 is disposed by ion implantation, then most of the metal will be below top surface 12.
On the other hand, if the metal is disposed by evaporation, then most of the metal will be disposed on top surface 12, rather than underneath it. With both the ion implantation and evaporation approaches, it is believed that it is the concentration of the refractory metal proximate to top surface 12 that lowers the C54 phase surface energy barrier. After refractory metal 14 is disposed, then a titanium layer 16 is deposited over refractory metal 14 by, say, sputtering or evaporation. For example, a thickness of 25 to 57.5 nm is used, although one skilled in the art will recognize that greater and lesser thicknesses may also be used. Top surface 12 is not explicitly shown in FIG. 2 because its position will vary according to the manner of refractory metal disposition used.
In addition to sputtering or evaporation, titanium layer 16 may also be deposited over refractory metal 14 by chemical vapor deposition. Further, when deposited by one of these methods, instead of an essentially titanium layer, a layer containing an alloy of Ti and Si may be deposited. This alloy may be stoichiometric TiSi2, but this is not required, and the Ti-Si alloy may be either rich or lean in its silicon composition. When a Ti-Si alloy is deposited, the method according to the present invention is substantially similar to that described herein. Any required modifications will be recognized by one of skill in the art. Also, as used herein, the deposition of a titanium layer may alternatively refer to the deposition of a titanium-silicon alloy layer.
In FIG. 3, a TiSi2 film 18 has been formed over silicon layer by heating silicon layer 10 to a temperature between about 600 5 and 700°C for a time period sufficient for the C54 phase of TiSi2 to form. This time period is generally about 20 seconds for RTA to about 20 minutes for annealing in a conventional furnace.
According to the method of the present invention, it is believed that the forming TiSiz film does not substantially pass through the 10 C49 phase, but primarily goes directly to the C54 phase due to the lowered surface energy barrier.
An optional annealing step has been found beneficial for further promoting the formation of the C54 phase of TiSi2, especially when forming the silicide at lower temperatures, say below about 650°C. This optional anneal is performed following the disposition of refractory metal 14 and prior to the deposition of Ti layer 16. In general, this anneal is performed at a wafer temperature of at least about 900°C, and more preferably 900-1000°C, for a time period of at least about 5 seconds when using RTA and of generally about 10-30 minutes when using a conventional quartz furnace. A preferred anneal is at a temperature of about 900°C for about 10 minutes in a furnace in a NZ ambient. It is believed that this optional anneal may further promote the formation of the refractory metal-silicon alloy at the surface of the silicon layer, though this is not certain.
In general, it is believed that the refractory metal according to the method of the present invention may be any metal capable of forming a metal silicide when heated in the presence of silicon to a temperature greater than about 900°C. For the purposes of this application, "refractory metal" is defined to include, without limitation, the following preferred metals: Mo, Co, W, Ta, Nb, Ru, or Cr. Mo and Co provide the most significant effect, and W
~ 2118147 provides a somewhat less significant effect than Mo or Co. It is believed that the above metals will in general work with any of the herein disclosed manners of disposition, but ion implantation and evaporation of Mo, Co, and W are preferred approaches.
Discussing now the above silicidation process in greater detail, there are several approaches for disposing the refractory metal that may be used. In general, these methods of disposition place refractory metal atoms on or within a few Angstroms of top surface 12. It is believed that the refractory metal atoms closest to the silicon interface are most active, but other more distant atoms are not excluded from the meaning of proximate as used herein. For example, atoms within about 2 Angstroms (i.e. about 0.2 nm) of the surface may be the most active. A first preferred approach for disposing the refractory metal is by ion implantation with a dose of about 101 to 5x144 atoms/cr~ and even more preferably a dose of about 1013 to 1014 atoms/cr~ . The preferred implant energy for these cases is about 45 to 90 KeV.
One way for implanting refractory metals involves the use of the arc chamber of commercially available ion implant systems.
Because the arc chamber is commonly made from, or in other cases lined with, refractory metals (such a molybdenum, niobium, tantalum, or tungsten), one method of implanting these metals is accomplished by using the arc chamber as the source of the metal to be implanted. The metal species to be implanted is selected by appropriately varying the arc chamber material and by adjusting the magnetic analyzer to select the desired atomic mass unit (AMU) of the metal species based on the known isotopes of the desired species. For example, an appropriate setting is 98 AMU for Mo, or 184 for W. Because W is also a common filament material in the ion source filament of the implant tool, W can be alternatively implanted by adjusting the analyzer magnet to 184 AMU for singly-ionized W, or to 92 AMU for doubly-ionized W. The dose and energy . 2118147 selected for a particular metal species will be limited by the capabilities of the ion implant system and the time devoted to performing the implant.
For the specific case of a Mo implant, a Mo arc chamber is installed into the implant system, a boron triflouride source gas (BF3) is introduced into the arc chamber. It is believed that ionized BF3 acts to volatilize molybdenum from the arc chamber to provide an adequate Mo ion ( 98Mo+) beam current of about 200 mA
with an implant energy of at least about 45 KeV. Because arc chambers sometimes become coated with other materials during use in other conventional applications, it is preferred that a clean or new source chamber be used to obtain the Mo ion beam current.
When implanting Mo atoms under the above conditions (i.e. an energy of 45 KeV), it has been determined that the greatest concentration of Mo atoms occurs at a depth in the silicon layer of about 30 nm, corresponding to a peak Mo concentration of about 1019 atoms/cm3. However, as discussed above, the Mo atom concentration of greatest interest is that at the surface. When using the optional anneal step above, SIMS data has indicated that the concentration of Mo atoms at the surface is about 5x1018 atoms/cm3.
It is expected that a surface concentration of the refractory metal at the silicon interface less than about 101' atoms/cm~ may be desirable.
In another preferred approach, the refractory metal is disposed on the surface of the silicon layer by evaporation of, say, a metal pellet. This may be by either e-beam evaporation or by resistive heating (e.g, placing the pellet in a crucible that is heated by a large electrical current). When using evaporation, it is important that the thickness of the refractory metal not be too great. For example, the thickness of a Mo layer disposed on the silicon layer is preferably less than about 2.0 nm. This is not an absolute maximum thickness, but as the thickness of the Mo layer increases above 2.0 nm, peeling of the silicide film has been observed. More preferably, a Mo thickness of about 0.5-1.5 nm is used. The desired thicknesses for other metals may vary somewhat.
When evaporating such small thicknesses of refractory metal onto the silicon layer, it is sometimes difficult to control the rate of evaporation. As a result, in one evaporation approach a shutter is positioned over the evaporation metal source chamber to contain the refractory metal until ready for disposition on the silicon layer. Then, the shutter is opened and closed fairly rapidly (a so-called "flash" evaporation) to provide a thin refractory metal layer over the silicon layer. Other evaporation approaches could be used that better control the rate of evaporation.
As an alternative to evaporation of the refractory metal, the refractory metal may instead be disposed by sputtering to a thickness on the silicon layer similar to that described for evaporation above. Modifications used with a sputtering approach will be recognized by one skilled in the art.
In addition to the above, the refractory metal may be disposed on the silicon layer by exposing the surface of the silicon layer to a solution containing ions of the refractory metal. In a preferred approach, the solution is aqueous and may contain a dilute acid, such as HC1 or nitric acid.
Although a preferred approach of the present invention has been described above, it is not intended that the practice of the invention be limited only to the formation of titanium silicide films. Rather, the present invention presents a method for other metal silicides that are to be formed on a silicon layer on a semiconductor wafer. According to this method, a refractory metal Z~ 1a~47 is disposed proximate to the surface of the silicon layer, a precursory metal is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal.
It is believed that the phase transformation temperature of the metal silicide is lowered by the presence of the refractory metal at the surface of the silicon layer. For example, because of the small grain size of C54-phase TiSiz films, it is believed that the activation energy for the phase transformation to the C54 phase is lowered. The precursory metal may be a refractory metal, and is preferably titanium (as discussed above), tungsten, or cobalt. The precursory metal may also be molybdenum, nickel, platinum, or palladium. Further, the precursory metal is one that generally forms a metal silicide having more than one solid phase. The refractory metal is preferably a metal that is capable of forming a metal silicide. The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The silicon layer may be monocrystalline or polycrystalline. The heating step used to form the silicide is performed at a temperature less than about 700°C, and more preferably between about 600-700°C. These temperatures are preferred for TiSi2, and may vary some for other metal silicides.
The several approaches for disposing the refractory metal discussed above may in general be used for the general method of the invention. Preferably, the refractory metal atoms are placed on or within a few Angstroms of the surface, and the thickness of these atoms is sufficiently thin to avoid silicide delamination due to stress effects.
As for the TiSi2 approach above, the wafer is optionally annealed following the step of disposing the refractory metal and prior to the step of depositing the precursory metal layer.
Preferably, this annealing step is performed at a wafer temperature of at least about 900°C, and more preferably between about 900 and 1000°C.
FIGS. 4-9 present experimental data for several TiSi2 films formed according to the present invention. FIG. 4 is a graph of the sheet resistance of a titanium silicide layer versus sputtered titanium thickness for several process cases with and without the use of a refractory metal according to the present invention. The data indicated as a standard film was formed without a refractory metal and without a second phase transformation anneal. The TiSiz films corresponding to the data point for W, and the data for Mo were formed by a 600°C anneal for 30 minutes in N2 on (100) single-crystal silicon according to the present invention. An optional 5 second, 1000°C, RTA anneal was used following the implantation of the refractory metal (used for both W and Mo). The optional anneal is necessary when the TiSi2 film is formed at about 600°C, but is not necessary for a formation temperature of about 700°C. The sheet resistance for each film is indicated by the data points in the graph.
FIGS. 5-7 are in-situ scanning resistance graphs illustrating the sheet resistance of titanium silicide layers being formed for several process cases both with and without the use of an evaporated refractory metal according to the present invention.
These measurements were made by continuously placing a four-point probe within a furnace during the formation of the TiSiz films.
The refractory metal in FIGS. 5-7, where used, was disposed by the "flash" evaporation method described above. FIG. 8 is an in-situ scanning resistance graph for TiSiz films where an implanted, rather than evaporate, refractory metal was used. Common conditions for FIGS. 5-8 include the formation of a silicide film from a Ti layer of about 57.5 nm thickness previously deposited over an approximately 300 nm polysilicon layer. Each silicide film 211814' was formed by gradually increasing temperature at about 15°C per minute.
Looking now at FIG. 5, curve 30 shows sheet resistance behavior for a titanium silicide film formed without the use of a refractory metal. Curve 30 exhibits the known and expected alloy effect at about point 32, with curve 30 forming a resistance peak at about 500°C. Above about 500°C, its resistance drops as indicated by arrow 34. As the temperature moves from about 500°C
to about 700°C, the forming TiSiz film is substantially in the C49 phase. At about 700°C curve 30 flattens out into a so-called "knee" at point 36 in which the resistance is substantially constant with increasing temperature. This "knee" results from the failure of the silicide film to convert from the C49 phase to the C54 phase until even higher temperatures are reached. In contrast to curve 30, curve 40 illustrates resistance for a silicide film formed following the disposition of about 0.015 nm of Mo according to the present invention. Behavior is similar, but note that the "knee" observed for curve 30 above is substantially not present for curve 40 (see point 42). It is believed that the absence of this knee indicates that the C54 phase of TiSiz is directly formed to a substantial degree during silicidation without passing through the C49 phase.
In FIG. 6, curve 50 shows sheet resistance behavior for a forming silicide film where about a 0.015 nm Ta layer was disposed by flash evaporation according to the present invention. As for curve 40 in FIG. 5, no significant knee is observed during the formation of the C54 phase of TiSi2. In FIG. 7, curve 60 illustrates sheet resistance versus temperature for a TiSiz film formed using about 0.015 nm of W according to the present invention. Curves 30 and 40 are shown for comparison with curve 60. Again, for curve 60 there is no significant knee and the C54 phase is substantially formed at a temperature less than about 21 1814?
700°C.
FIG. 8 is an in-situ scanning resistance graph illustrating the sheet resistance of a titanium silicide layer formed using an implanted refractory metal according to the present invention.
Curve 70 is a control silicide film formed without a refractory metal, for comparison purposes, and curve 80 is a TiSiz film formed where Mo has been implanted (at a dosage of 1014 atoms/cm2 and an implant energy of 45 KeV) prior to depositing Ti. After implanting Mo, an annealing step was performed at 900°C for 10 minutes also prior to depositing Ti. As for the conventional curve 30 above, curve 70 exhibits a knee at point 72, but curve 80 does not. The absence of a knee for curve 80 indicates that the C54 phase of TiSi2 is substantially formed at temperatures below about 700°C.
FIG. 9 is a histogram of the measured resistance of titanium silicide lines with and without a Mo ion implant according to the present invention.
In addition to the data presented in FIGS. 4-9 above, there is further support that the C49 phase is substantially by-passed in silicidation by the present invention. Optical micrographs of the C54 phase of titanium silicide layers formed according to the present invention have indicated a grain size significantly smaller than in the conventional case without a refractory metal. This supports that the nucleation energy barrier of the C54 phase is significantly reduced by the method of the present invention. This becomes most important in VLSI circuits where the linewidths are less than the grain size of the C54 phase that would be formed if using the conventional approach.
Although it is believed that the method according to the present invention described above is fairly robust, there are some precautions to its use. First, heat cycles above 700°C for BU9-93-016 lg extended periods must be avoided when using the present invention to prevent possible silicide instability problems. Second, if the thickness of the refractory metal layer is too great, then delamination of the silicide may result.
Another advantage of the present invention is that it does not create an amorphous silicon layer at the top surface of the silicon layer. Specifically, when using the ion implantation method to dispose the refractory metal, the optional annealing step removes any amorphous silicon that may be present. The optional anneal is not necessary with the other manners of disposition in order to avoid amorphous silicon. It is desirable to avoid the presence of amorphous silicon because it has been associated with junction leakage failures.
In an alternative embodiment according to the present invention, a metal silicide is formed in a layer overlying a silicon layer on a semiconductor wafer by a method comprising the steps of depositing a precursory metal layer overlying the silicon layer, where the precursory metal layer contains a small quantity of a refractory metal, and heating the wafer to a temperature sufficient to form the metal silicide from the precursory metal layer, where the phase transformation temperature of said metal silicide is lowered by the presence of said refractory metal at the surface of said silicon layer. Preferably, the precursory metal and the refractory metal are deposited from the same source, and more preferably the atomic percentage of the refractory metal layer in the source is less than about 1 percent. The preferred refractory metals discussed above are expected to also be useful with this embodiment.
In a preferred approach according to the alternative embodiment, a titanium layer is deposited from a source of titanium which also contains a small quantity of a refractory metal. The wafer is then heated to a temperature sufficient to substantially form the C54 phase of titanium silicide. Preferably this temperature is less than about 700°C, and the atomic percentage of the refractory metal is less than about one atomic percent of the combined titanium and refractory metal weight. The source of the titanium may be a sputtering target or evaporation pellet.
Although the present invention has been described in detail above, it is not intended to be limited to the specific form set forth herein, but, on the contrary, it is intended to cover such alternatives and equivalents as can reasonably be included within the spirit and scope of the invention as defined by the appended claims.
Claims (52)
1. A method for forming a C54 phase titanium silicide layer on a silicon layer on a semiconductor wafer, comprising the steps of:
depositing a titanium layer on said silicon layer from a source of titanium, said titanium layer containing less than 1 atomic % of a refractory metal deposited from the same source as said titanium layer; and heating said wafer to a temperature sufficient to substantially form the C54 phase of said titanium silicide layer from said titanium layer, said temperature being less than about 700°C.
depositing a titanium layer on said silicon layer from a source of titanium, said titanium layer containing less than 1 atomic % of a refractory metal deposited from the same source as said titanium layer; and heating said wafer to a temperature sufficient to substantially form the C54 phase of said titanium silicide layer from said titanium layer, said temperature being less than about 700°C.
2. The method of claim 1 wherein said refractory metal is Mo, Co, W, Ta, Nb, or Cr.
3. The method of claim 1 wherein said source is a sputtering target.
4. The method of claim 1 wherein said source is an evaporation pellet.
5. A method for forming a titanium silicide layer on a silicon layer on a semiconductor wafer, comprising the steps of:
disposing a refractory metal on the surface of said silicon layer by sputtering, said refractory metal occurring in a layer less than 2 nm thick;
depositing a titanium layer over said refractory metal; and heating said wafer to a temperature sufficient to substantially form the C54 phase of said titanium silicide layer from said titanium layer, said temperature being less than about 700°C.
disposing a refractory metal on the surface of said silicon layer by sputtering, said refractory metal occurring in a layer less than 2 nm thick;
depositing a titanium layer over said refractory metal; and heating said wafer to a temperature sufficient to substantially form the C54 phase of said titanium silicide layer from said titanium layer, said temperature being less than about 700°C.
6. The method of claim 5 wherein said refractory metal is Mo, Ta or W.
7. The method of claim 5 further comprising the step of annealing said wafer following said step of disposing a refractory metal and prior to said step of depositing a titanium layer, said annealing being at a wafer temperature between about 900° to 1000°C.
8. A method for forming a titanium silicide layer on a silicon layer on a semiconductor wafer, comprising the steps of:
disposing a refractory metal on the surface of said silicon layer by metal evaporation, said refractory metal occurring in a layer less than 2 nm thick;
depositing a titanium layer over said refractory metal; and heating said wafer to a temperature sufficient to substantially form the C54 phase of said titanium silicide layer from said titanium layer, said temperature being less than about 700°C.
disposing a refractory metal on the surface of said silicon layer by metal evaporation, said refractory metal occurring in a layer less than 2 nm thick;
depositing a titanium layer over said refractory metal; and heating said wafer to a temperature sufficient to substantially form the C54 phase of said titanium silicide layer from said titanium layer, said temperature being less than about 700°C.
9. The method of claim 8 wherein said refractory metal is Mo, Ta or W.
10. The method of claim 8 further comprising the step of annealing said wafer following said step of disposing a refractory metal and prior to said step of depositing a titanium layer, said annealing being at a wafer temperature between about 900° to 1000°C.
11.A method for forming a titanium silicide layer on a silicon layer on a semiconductor wafer, comprising the steps of:
disposing a refractory metal on the surface of said silicon layer by exposing the surface of said silicon layer to a solution containing said refractory metal, said refractory metal occurring in a layer less than 2 nm thick;
depositing a titanium layer over said refractory metal; and heating said wafer to a temperature sufficient to substantially form the C54 phase of said titanium silicide layer from said titanium layer, said temperature being less than about 700°C.
disposing a refractory metal on the surface of said silicon layer by exposing the surface of said silicon layer to a solution containing said refractory metal, said refractory metal occurring in a layer less than 2 nm thick;
depositing a titanium layer over said refractory metal; and heating said wafer to a temperature sufficient to substantially form the C54 phase of said titanium silicide layer from said titanium layer, said temperature being less than about 700°C.
12. The method of claim 11 wherein said refractory metal is Mo, Ta or W.
13. The method of claim 11 further comprising the step of annealing said wafer following said step of disposing a refractory metal and prior to said step of depositing a titanium layer, said annealing being at a wafer temperature between about 900° to 1000°C.
14. The method of claim 11 wherein said solution is aqueous.
15. The method of claim 11 wherein said solution contains dilute hydrochloric or nitric acid.
16. A method for forming a titanium silicide layer on a silicon layer on a semiconductor wafer, comprising the steps of:
disposing a refractory metal proximate to the surface of said silicon layer by ion implantation, with a dose of 10 12 to 5x10 14 atoms/cm2;
depositing a layer comprising titanium and silicon over said refractory metal; and heating said wafer to a temperature sufficient to substantially form the C54 phase of said titanium silicide layer from said layer comprising titanium and silicon, said temperature being less than about 700°C.
disposing a refractory metal proximate to the surface of said silicon layer by ion implantation, with a dose of 10 12 to 5x10 14 atoms/cm2;
depositing a layer comprising titanium and silicon over said refractory metal; and heating said wafer to a temperature sufficient to substantially form the C54 phase of said titanium silicide layer from said layer comprising titanium and silicon, said temperature being less than about 700°C.
17. The method of claim 16 wherein said refractory metal is Mo, Ta or W.
18. A method for forming a titanium silicide layer on a silicon layer on a semiconductor wafer, comprising the steps of:
disposing a refractory metal on the surface of said silicon layer by sputtering, said refractory metal occurring in a layer less than 2 nm thick;
depositing a layer comprising titanium and silicon over said refractory metal; and heating said wafer to a temperature sufficient to substantially form the C54 phase of said titanium silicide layer from said layer comprising titanium and silicon, said temperature being less than about 700°C.
disposing a refractory metal on the surface of said silicon layer by sputtering, said refractory metal occurring in a layer less than 2 nm thick;
depositing a layer comprising titanium and silicon over said refractory metal; and heating said wafer to a temperature sufficient to substantially form the C54 phase of said titanium silicide layer from said layer comprising titanium and silicon, said temperature being less than about 700°C.
19. The method of claim 18 wherein said refractory metal is Mo, Ta or W.
20. A method for forming a titanium silicide layer on a silicon layer on a semiconductor wafer, comprising the steps of:
disposing a refractory metal on the surface of said silicon layer by metal evaporation, said refractory metal occurring in a layer less than 2 nm thick;
depositing a layer comprising titanium and silicon over said refractory metal; and heating said wafer to a temperature sufficient to substantially form the C54 phase of said titanium silicide layer from said layer comprising titanium and silicon, said temperature being less than about 700°C.
disposing a refractory metal on the surface of said silicon layer by metal evaporation, said refractory metal occurring in a layer less than 2 nm thick;
depositing a layer comprising titanium and silicon over said refractory metal; and heating said wafer to a temperature sufficient to substantially form the C54 phase of said titanium silicide layer from said layer comprising titanium and silicon, said temperature being less than about 700°C.
21. The method of claim 20 wherein said refractory metal is Mo, Ta or W.
22. A method for forming a titanium silicide layer on a silicon layer on a semiconductor wafer, comprising the steps of:
disposing a refractory metal on the surface of said silicon layer by exposing the surface of said silicon layer to a solution containing said refractory metal, said refractory metal occurring in a layer less than 2 nm thick;
depositing a layer comprising titanium and silicon over said refractory metal; and heating said wafer to a temperature sufficient to substantially form the C54 phase of said titanium silicide layer from said layer comprising titanium and silicon, said temperature being less than about 700°C.
disposing a refractory metal on the surface of said silicon layer by exposing the surface of said silicon layer to a solution containing said refractory metal, said refractory metal occurring in a layer less than 2 nm thick;
depositing a layer comprising titanium and silicon over said refractory metal; and heating said wafer to a temperature sufficient to substantially form the C54 phase of said titanium silicide layer from said layer comprising titanium and silicon, said temperature being less than about 700°C.
23. The method of claim 22 wherein said refractory metal is Mo, Ta or W.
24. A method for forming a C54 phase titanium silicide layer overlying a silicon layer on a semiconductor wafer, comprising the steps of:
disposing a refractory metal proximate to the surface of said silicon layer by ion implantation with a dose of 10 12 to 5x10 14 atoms/cm2;
depositing a titanium layer overlying said silicon layer; and heating said wafer to a temperature sufficient to form said C54 phase titanium silicide layer from said titanium layer.
disposing a refractory metal proximate to the surface of said silicon layer by ion implantation with a dose of 10 12 to 5x10 14 atoms/cm2;
depositing a titanium layer overlying said silicon layer; and heating said wafer to a temperature sufficient to form said C54 phase titanium silicide layer from said titanium layer.
25. The method of claim 24 wherein the C54 phase of said titanium silicide layer is formed at a wafer temperature of less than about 700°C.
26. The method of claim 24 wherein said titanium layer is deposited to a thickness of between about 25 to 57.5 nm.
27. The method of claim 24 wherein said refractory metal is Mo, W, Ta, Nb, or Cr.
28. The method of claim 27 wherein said refractory metal is Mo, Ta, or W.
29. The method of claim 28 wherein said step of disposing said refractory metal is performed by ion implantation with an implant dose of about 10 13 to 10 14 atoms/cm2.
30. The method of claim 29 further comprising the step of annealing said wafer following said step of disposing a refractory metal and prior to said step of depositing a titanium layer, said annealing being at a wafer temperature between about 900° to 1000°C.
31. The method of claim 24 Wherein said refractory metal is Mo.
32. A method of forming a titanium silicide layer on a silicon substrate of a semiconductor device, comprising:
disposing a titanium alloy layer over the silicon substrate wherein said titanium alloy comprises from 1 to 20 atomic percent refractory metal; and heating said titanium alloy to a temperature sufficient to substantially form C54 phase titanium silicide.
disposing a titanium alloy layer over the silicon substrate wherein said titanium alloy comprises from 1 to 20 atomic percent refractory metal; and heating said titanium alloy to a temperature sufficient to substantially form C54 phase titanium silicide.
33. The method of claim 32 wherein said temperature is less than about 700°C.
34. The method of claim 32 wherein said substrate is heated to a temperature sufficient to completely transform said titanium alloy layer to C54 phase titanium silicide.
35. The method of claim 32 wherein said refractory metal comprises one or more elements of the group consisting of Ta, Nb, W, V and Cr.
36. The method of claim 33 wherein said titanium alloy comprises from 1 to 15 atomic percent refractory metal.
37. The method of claim 36 wherein said refractory metal comprises a refractory metal selected from the group consisting of Ta and Nb.
38. The method of claim 33 wherein said titanium alloy comprises titanium, silicon and a refractory metal.
39. The method of claim 32 wherein said titanium alloy layer is disposed 10 to 60 nm thick over said silicon substrate.
40. The method of claim 32 wherein said silicon substrate is selected from the group consisting of monocrystalline silicon, polycrystalline silicon, amorphous silicon, and a silicon germanium alloy.
41. The method of claim 32 wherein said silicon substrate is selected from the group of silicon on insulator containing N-type dopant and silicon on insulator containing P-type dopant.
42. The method of claim 32 wherein said titanium alloy is deposited over said silicon substrate by physical vapor deposition.
43. The method of claim 32 wherein said titanium alloy is deposited over said silicon substrate by chemical vapor deposition.
44. The method of claim 32 wherein said titanium alloy comprises 1 to about 5 atomic percent Mo.
45. A method of forming a titanium silicide layer in a semiconductor device, comprising:
depositing a 10 to 200 nm titanium alloy layer over a semiconductor device, wherein said titanium alloy comprises from 1 to 15 atomic percent refractory metal and said semiconductor device incorporates a plurality of electronic components having exposed silicon surfaces;
heating said titanium alloy layer to a temperature sufficient to substantially form C54 phase titanium silicide in the titanium alloy layer overlying said silicon surfaces, said temperature being less than about 700°C; and etching unreacted portions of said titanium alloy layer.
depositing a 10 to 200 nm titanium alloy layer over a semiconductor device, wherein said titanium alloy comprises from 1 to 15 atomic percent refractory metal and said semiconductor device incorporates a plurality of electronic components having exposed silicon surfaces;
heating said titanium alloy layer to a temperature sufficient to substantially form C54 phase titanium silicide in the titanium alloy layer overlying said silicon surfaces, said temperature being less than about 700°C; and etching unreacted portions of said titanium alloy layer.
46. A method of forming a titanium silicide layer in a semiconductor device, comprising:
depositing a 10 to 200 nm titanium alloy layer over a semiconductor device, wherein said titanium alloy comprises from 1 to 15 atomic percent refractory metal and said semiconductor device incorporates a plurality of electronic components having exposed silicon surfaces;
heating said titanium alloy layer to a temperature sufficient to form titanium silicide in the titanium alloy layer overlying said silicon surfaces;
etching unreacted portions of said titanium alloy layer; and heating said titanium silicide to a temperature sufficient to substantially form C54 phase titanium silicide, said temperature being less than about 700°C.
depositing a 10 to 200 nm titanium alloy layer over a semiconductor device, wherein said titanium alloy comprises from 1 to 15 atomic percent refractory metal and said semiconductor device incorporates a plurality of electronic components having exposed silicon surfaces;
heating said titanium alloy layer to a temperature sufficient to form titanium silicide in the titanium alloy layer overlying said silicon surfaces;
etching unreacted portions of said titanium alloy layer; and heating said titanium silicide to a temperature sufficient to substantially form C54 phase titanium silicide, said temperature being less than about 700°C.
47. A semiconductor device having a titanium silicide layer comprising:
a silicon layer; and a layer of titanium silicide over said silicon layer wherein said layer of titanium silicide comprises substantially C54 phase titanium silicide and from 1 to 20 atomic percent refractory metal.
a silicon layer; and a layer of titanium silicide over said silicon layer wherein said layer of titanium silicide comprises substantially C54 phase titanium silicide and from 1 to 20 atomic percent refractory metal.
48. The semiconductor device of claim 47 wherein said titanium silicide layer has a thickness between 10 and 20 nm.
49. The semiconductor device of claim 47 or claim 48 wherein said silicon layer is selected from the group of monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium alloy, silicon on insulator having N-type dopant and silicon on insulator having P-type dopant.
S0. The semiconductor device of claim 47 or claim 48 wherein said refractory metal is selected from the group of one or more of the following Ta, Nb, W, V or Cr.
51. The semiconductor device of claim 47 or claim 48 wherein said titanium silicide layer comprises from 1 to 15 atomic percent refractory metal.
52. The semiconductor device of claim 47 or claim 48 wherein said titanium silicide layer comprises from 1 to 5 atomic percent Mo.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/145,921 US5510295A (en) | 1993-10-29 | 1993-10-29 | Method for lowering the phase transformation temperature of a metal silicide |
| US145,921 | 1993-10-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2118147A1 CA2118147A1 (en) | 1995-04-30 |
| CA2118147C true CA2118147C (en) | 2000-05-16 |
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| CA002118147A Expired - Fee Related CA2118147C (en) | 1993-10-29 | 1994-10-14 | Method for lowering the phase transformation temperature of a metal silicide |
Country Status (10)
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| US (1) | US5510295A (en) |
| EP (1) | EP0651076B1 (en) |
| JP (1) | JP2673103B2 (en) |
| KR (1) | KR0155587B1 (en) |
| AT (1) | ATE183251T1 (en) |
| BR (1) | BR9404247A (en) |
| CA (1) | CA2118147C (en) |
| DE (1) | DE69420004T2 (en) |
| ES (1) | ES2136148T3 (en) |
| TW (1) | TW262573B (en) |
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| JPS586172A (en) * | 1981-07-03 | 1983-01-13 | Toshiba Corp | Semiconductor device |
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| JPS63276244A (en) * | 1987-05-08 | 1988-11-14 | Nec Corp | Manufacture of semiconductor device |
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-
1993
- 1993-10-29 US US08/145,921 patent/US5510295A/en not_active Expired - Lifetime
-
1994
- 1994-10-06 ES ES94115744T patent/ES2136148T3/en not_active Expired - Lifetime
- 1994-10-06 EP EP94115744A patent/EP0651076B1/en not_active Expired - Lifetime
- 1994-10-06 AT AT94115744T patent/ATE183251T1/en not_active IP Right Cessation
- 1994-10-06 DE DE69420004T patent/DE69420004T2/en not_active Expired - Lifetime
- 1994-10-14 CA CA002118147A patent/CA2118147C/en not_active Expired - Fee Related
- 1994-10-19 KR KR1019940026698A patent/KR0155587B1/en not_active IP Right Cessation
- 1994-10-21 JP JP6256787A patent/JP2673103B2/en not_active Expired - Lifetime
- 1994-10-26 BR BR9404247A patent/BR9404247A/en not_active IP Right Cessation
-
1995
- 1995-01-26 TW TW084100702A patent/TW262573B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| ES2136148T3 (en) | 1999-11-16 |
| BR9404247A (en) | 1995-06-20 |
| KR0155587B1 (en) | 1998-11-16 |
| DE69420004T2 (en) | 2000-03-30 |
| CA2118147A1 (en) | 1995-04-30 |
| KR950011644A (en) | 1995-05-15 |
| TW262573B (en) | 1995-11-11 |
| JPH07169711A (en) | 1995-07-04 |
| JP2673103B2 (en) | 1997-11-05 |
| EP0651076A1 (en) | 1995-05-03 |
| US5510295A (en) | 1996-04-23 |
| ATE183251T1 (en) | 1999-08-15 |
| DE69420004D1 (en) | 1999-09-16 |
| EP0651076B1 (en) | 1999-08-11 |
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