CA2121960A1 - Method and apparatus for providing electrical access to devices in a multi-chip module - Google Patents
Method and apparatus for providing electrical access to devices in a multi-chip moduleInfo
- Publication number
- CA2121960A1 CA2121960A1 CA002121960A CA2121960A CA2121960A1 CA 2121960 A1 CA2121960 A1 CA 2121960A1 CA 002121960 A CA002121960 A CA 002121960A CA 2121960 A CA2121960 A CA 2121960A CA 2121960 A1 CA2121960 A1 CA 2121960A1
- Authority
- CA
- Canada
- Prior art keywords
- devices
- chip module
- bond pads
- package body
- leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49004—Electrical device making including measuring or testing of device or component part
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49121—Beam lead frame or beam lead device
Abstract
METHOD AND APPARATUS FOR PROVIDING ELECTRICAL
ACCESS TO DEVICES IN A MULTI-CHIP MODULE
ABSTRACT OF THE DISCLOSURE
Multi-chip module (MCM) (10) includes package body (12) having cavity (20) for accepting a plurality of devices and substrates and seal ring (26) to ensure the integrity of the package. Lead frame (18) having a plurality of individual leads (28) is coupled to the package body (12). Plurality of test points (38) or test pins (30) are located on the external surface of package body (12). A plurality of bond pads are located in cavity (20), including a first set or tier and a second set or tier of bond pads for electrically coupling the devices and substrates in the cavity (20) external to package body (12). The first set or tier of bond pads provides electrical connection between the individual devices in MCM (10) to plurality of test points (38) or test pins (30), and the second set or tier of bond pads provides electrical connection between the individual devices in MCM (10) and plurality of individual leads (28).
ACCESS TO DEVICES IN A MULTI-CHIP MODULE
ABSTRACT OF THE DISCLOSURE
Multi-chip module (MCM) (10) includes package body (12) having cavity (20) for accepting a plurality of devices and substrates and seal ring (26) to ensure the integrity of the package. Lead frame (18) having a plurality of individual leads (28) is coupled to the package body (12). Plurality of test points (38) or test pins (30) are located on the external surface of package body (12). A plurality of bond pads are located in cavity (20), including a first set or tier and a second set or tier of bond pads for electrically coupling the devices and substrates in the cavity (20) external to package body (12). The first set or tier of bond pads provides electrical connection between the individual devices in MCM (10) to plurality of test points (38) or test pins (30), and the second set or tier of bond pads provides electrical connection between the individual devices in MCM (10) and plurality of individual leads (28).
Description
.-., ;. .
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to the field of electronic devices, and more particularly, to providing electrical access to devices in a multi-chip module ~MCM) . Even more specifically the present invention -relates to a method and system for providing electrical :~
access to a multi-chip module that includes test points or test pins that can be easily accessed external to the ~:
MCM packages without increasing the lead count or package . ....
size of the MCM package. .;..... :::
.:
~ .
,., ~ .
' BACKGROUND OF THE INVENTION
As the complexity and density of semiconductor devices increases, the need for new packaging techniques has also arisen. A multi-chip module (MCM) containing multiple devices in a single package is one packaging approach. In an MCM, multiple semiconductor and passive devices are placed on substrate(s) in an MCM package.
Sealing the MCM protects the devices within the MCM.
This technique achieves a higher degree of device density than separately packaged semiconductor devices mounted on ~-a printed circuit board. The higher density of MCM's translates to faster data processing times within the MCM. Additionally, locating all of the devices within a single MCM eliminates the need for driver circuits that would otherwise be required between the various devices.
Using an MCM in turn reduces the chip count and power consumption required versus using individually pacXaged devices. The reduced chip count of an MCM also results in an increase in reliability of a system using MCMs over using discrete devices mounted to a printed circuit board.
While MCMs solve a number of design problems, they also give rise to a new set of problems. In particular, there are concerns with the testability and access to the individual devices in an MCM. Typically, only a portion of the inputs and outputs of the individual devices in an MCM have a direct connection to the leads of the MCM.
Therefore, once an MCM is populated with various semiconductor and passive devices, testing the individual devices within the MCM is difficult. The small size of the individual devices in the MCM, coupled with the fact that not all of the inputs and outputs of the individual devices in an MCM can be connected to the input/output ;~
(I/O) pins of the MCM, denies access to the individual devices within the MCM. Thereby, making troubleshooting ~
a malfunctioning MCM very difficult. In particular, -' ' . .
` -~ 2121960 determ;ning the inoperable device(s) in an MCM can be very difficult.
Past approaches to solve this problem include a rigid incoming inspection system to ensure placing only good devices in the MCM. Unfortunately, a full functional test of a semiconductor die is often not possible. To fully exercise semiconductor die requires testing the die over the full temperature range of its application. Additionally, achieving a good electrical contact to the bond pads of a die by test probe is difficult. This prevents the necessary testing at incoming inspection, and particularly denies testing at the full speed and over the full temperature range of the individual devices in their application in the MCM.
Once an individual device slips through incoming inspection and is placed in the MCM, the time to isolate a die, if possible at all, and the time necessary to remove and replace a bad die is very expensive and time consuming. Troubleshooting an unsealed malfunctioning MCM includes testing with electrical probes. In this approach, a test probe is used to electrically access a suspected bad device in the MCM. Disadvantages of this method include the small size of the individual devices in the MCM, the relative size of the probe in relation to the bond pads of the individual devices, the density of the devices in the MCM, the likelihood of causing damage with a misplaced probe, and the inability to fully exercise an individual device with electrical test probes. For example, to full~ test a microprocessor in an MCM requires sufficient number of test probes for both data and address bus lines in the microprocessor.
For modern microprocessors the number of probes that would be required will not physically fit into the MCM
cavity. Additionally, the inability to fully test individual devices mounted within the MCM results in a reiterative process of removing suspected devices and ` 2121960 ., retesting the MCM until all faults are removed. A trial and error remove and replace methodology'for the individual devices in a malfunctioning MCM leads to unnecessary removal of good parts and possible damage, if not destruction, to the MCM in total. This proces~ is very time consuming and expensive without providing acceptable results. Sealing the MCM with its lid denies even probe access to the individual devices in the MCM.
It is an object of the present invention, therefore to provide an improved method and apparatus for providing electrical access to the individual devices in an MCM
without increasing the lead count or package size of the MCM package. A technical advantage of the present invention is that the MCM package includes test points and/or test pins which can be easily accessed externally to the package of the MCM by either a test probe or a test socket. The test pins and test points work in combination with the leads of the MCM package to provide greater electrical access to the individual devices within the MCM.
It is a further object of the present invention to provide an apparatus and method using the improved NCM
package to allow for better troubleshooting of MCMs both before and after they are sealed, and allowing for software emulation on and programming or reprogramming of devices in the MCM.
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` 2121960 BRIEF DESCRIPTION OF THE DRAWINGS
Other objects and advantages of the present invention will be apparent from the reading of the specification and appended claims in conjunction with drawings, wherein:
FIGURE 1 provides a perspective view looking into the cavity of the multi-chip module package; - :
FIGURE 2 depicts the detail of the area as identified in FIGURE 1;
FIGURE 3 depicts a cross-sectional view of multi-chip module package as identified in FIGURE 1; and FIGUREs 4a and 4b depict perspective views of circuit implementations of the preferred embodiments.
` ~`` 2121960 DETAILED DESCRIPTION OF THE INVENTION
In FIGURE 1, is shown a simplified view looking down into multi-chip module (MCM) 10. MCM 10 includes package body 12 with top surface 14, bottom surface 16, and lead frame 18. Package body 12 includes cavity 20, two sets of bond pads, including test pin bond pad set 22 and package input and output (I/O) bond pad set 24. Package body 12 also includes seal ring 26, and individual leads 28 in lead frame 18. Test pins 30 may be flush with or protrude from top surface 14. Alternatively, test pins 30 may protrude from bottom surface 16 in the event that cavity 20 is mounted from the upward side.
FIGURE 2 depicts one possible top surface 14 or bottom surface 16 (bottom if package is mount cavity up) embodiment for the sets of bond pads. The sets of bond pads may be arranged where test pin bond pad layer 22 is located separately from package I/O bond pad layer 24.
Test pin bond pad set 22 includes individual bond pads 32, and package I/O bond pad set 24 includes individual bond pads 34. This arrangement can be reversed without affecting the inventive concept of the present invention.
Additionally, the sets of bond pads may all be located on ~--the same level.
FIGURE 3 depicts a cross-sectional view of MCM 10 showing the orientation of individual leads 28, package body 12, package I/O bond bad layer 24, test pin bond pad layer 22, and top 14 and bottom 16 surfaces of MCM 10. ~ -~
Individual bond pads 34 for package I/O bond pad set 24 are electrically coupled to leads 28 of MCM 10.
Individual bond pads 32 for test pin bond pad set 22 are electrically coupled to test pins 30 and test points 38.
Referring again to FIGURE I, individual devices (not shown) of MCM 10 may be electrically connected by appropriate bond wires to individual bond pads 32 of test pin bond pad set 22 or individual bond pads 34 of I/O
bond pad set 24 as is desired to provide electrical ' ' `~ 2121~60 access to the devices in MCM l0. When MCM l0 is sealed, a lid is placed over cavity 20 and a seal is made with seal ring 26.
Once the individual devices are placed in MCM l0 and bonded to the appropriate bond pads, MCN l0 can be tested at the module level through individual leads 28 of MCM
l0. If MCM l0 is found to be non-functional, knowing how individual devices are connected to leads 28 and test pins 30 of MCM l0 allows the individual devices in MCM l0 to be tested. By appropriately connecting to individual leads 28 and test pins 30 of MCM l0, the individual devices are isolated allowing for determination of whether they are the cause of the non-functionality of MCM l0. Testing individual devices in MCM lO by this method is possible prior to or after sealing MCM l0. By providing access to individual devices in MCM l0, isolation of malfunctioning devices within MCM l0 is possible without using the time-consuming and often damaging process of test probing individual devices.
Additionally, once MCM l0 is sealed, whereas access to -~
individual devices in MCM l0 by probe is lost, test pins 30 in combination with package leads 28 provide the necessary electrical access to the individual devices in -MCM l0.
Additionally, the access methodology for MCM's depicted in these figures also provides for greater access for purposes other than troubleshooting once MCM
l0 is sealed. For example, if MCM l0 contains a programmable device, by appropriately connecting the programming inpu1:s of the programmable device to test pins 30 and leads 28 of MCM l0, it will be possible to program and/or reprogram the programmable device after MCM l0 is sealed. Also, in applications where MCM l0 contains a microprocessor, it may be desirable to test software to be run on the microprocessor. By using test pins 30 and leads 28 of MCM l0, a software designer can 2~21960 access the microprocessor in MCM 10 for software emulation.
Referring to FIGURE 4a, when sealed MCM 10 is mounted to printed circuit board 36, cavity 20 side of MCM 10 is mounted face down onto the surface of printed circuit board 36. This results with the lid 40 as bottom surface 16 closest to printed circuit board 36 and top surface 14 the visible surface when looking down on the MCM 10. If, on the other hand, cavity 20 is mounted face-up, than the emulation and in-circuit test pads are placed on the bottom of the package.
Test access, software emulation, and reprogramming -of programmable devices in MCM 10 remain available. By using appropriate test pins 30 and package leadi 28 individual devices can be accessed, even after MCM 10 is mounted to printed circuit board 36. Test pins 30 may be embodied in pin grid array (PGA) type pins as depicted in ;~
FIGUR~ 4a. Test pins 30 are easily accessed by a clip or - -other socket mechanism. In an alternate embodiment shown in FIGURE 4b, test pins 30 are test points 38 which are -~
either flush with or slightly extending from package body 12 top surface 14.
For example, FIGUREs 4a and 4b depict two -embodiments of the present invention and demonstrate some of their technical advantages. Because test points 38 or -test pins 30 have been included in MCM 10 package body 12, it is possible to troubleshoot, perform software -emulation upon, or reprogram individual devices in MCM 10 even after it has béen mounted onto printed circuit board ~-~
36. Access to individual devices in MCM 10 is accomplished without increasing the size of package body 12 or the number of leads 28.
The package material for MCM package body 12 can be ceramic, plastic, laminate, or metal. Additionally, test points 38 or test pins 30 can be located throughout the :
.
.` g body of MCM pacXage body 12, and do not have to be located along a peripheral ring of package body 12.
Other embodiments of the present invention that may not have been discussed here in detail can be easily identified.
' .~.
.
OPERATION
The basic operation of the preferred embodiment is very straightforward once conceived and comprises, for example, placing individual devices within the cavity 20 of MCM 10 package body 12. By appropriately electrically connecting individual devices within cavity 20 by bond wires to the bond pads of test pin bond pad layer 22 or package I/O bond pad layer 24 the present embodiment provides the desired functionality at leads 28 of MCM 10 and the desired access to individual devices within MCM
10 at test points 38 or test pins 30. The improved - ~-access is available before MCM 10 is sealed, after sealing, and even after the placing MCM 10 on printed circuit board 36. This allows easier troubleshooting of MCM 10, software test emulation, and programming changes to the devices in MCM 10 even after sealing MCM 10.
In summary, we have illustrated one embodiment of the inventive concept of the multi-chip module package with additional test points. The multi-chip module package includes a package body having a cavity for accepting a plurality of micro-electronic devices and substrates and a seal ring to ensure the integrity of the package. A lead frame having a plurality of leads is coupled to the package body and a plurality of test points are located on the external surface of the package body. Alternatively, package input and output may be an integral part of the package. This would not require use of the leadframe. A plurality of bond pads are located in the cavity of the package including a first set or tier and second set or tier of bond pads for electrically coupling the devices and substrates in the cavity external to the package body. The first set or tier of bond pads are electrically coupled to the plurality of ; ~
test points and the second set or tier of bond pads are -electrically coupled to the plurality of leads.
` `- 2121960 A~ a result of the above, although the invention has been described with reference to the above embodiments, its description is not meant to be construed in a limiting sense. Various modifications of the disclosed preferred embodiment, as well as the alternative embodiments of the invention may make further embodiments apparent to persons skilled in the art upon reference to the above description. It is, therefore, contemplated that the appended claims will cover such modifications that will fall within the true scope of the invention.
,
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to the field of electronic devices, and more particularly, to providing electrical access to devices in a multi-chip module ~MCM) . Even more specifically the present invention -relates to a method and system for providing electrical :~
access to a multi-chip module that includes test points or test pins that can be easily accessed external to the ~:
MCM packages without increasing the lead count or package . ....
size of the MCM package. .;..... :::
.:
~ .
,., ~ .
' BACKGROUND OF THE INVENTION
As the complexity and density of semiconductor devices increases, the need for new packaging techniques has also arisen. A multi-chip module (MCM) containing multiple devices in a single package is one packaging approach. In an MCM, multiple semiconductor and passive devices are placed on substrate(s) in an MCM package.
Sealing the MCM protects the devices within the MCM.
This technique achieves a higher degree of device density than separately packaged semiconductor devices mounted on ~-a printed circuit board. The higher density of MCM's translates to faster data processing times within the MCM. Additionally, locating all of the devices within a single MCM eliminates the need for driver circuits that would otherwise be required between the various devices.
Using an MCM in turn reduces the chip count and power consumption required versus using individually pacXaged devices. The reduced chip count of an MCM also results in an increase in reliability of a system using MCMs over using discrete devices mounted to a printed circuit board.
While MCMs solve a number of design problems, they also give rise to a new set of problems. In particular, there are concerns with the testability and access to the individual devices in an MCM. Typically, only a portion of the inputs and outputs of the individual devices in an MCM have a direct connection to the leads of the MCM.
Therefore, once an MCM is populated with various semiconductor and passive devices, testing the individual devices within the MCM is difficult. The small size of the individual devices in the MCM, coupled with the fact that not all of the inputs and outputs of the individual devices in an MCM can be connected to the input/output ;~
(I/O) pins of the MCM, denies access to the individual devices within the MCM. Thereby, making troubleshooting ~
a malfunctioning MCM very difficult. In particular, -' ' . .
` -~ 2121960 determ;ning the inoperable device(s) in an MCM can be very difficult.
Past approaches to solve this problem include a rigid incoming inspection system to ensure placing only good devices in the MCM. Unfortunately, a full functional test of a semiconductor die is often not possible. To fully exercise semiconductor die requires testing the die over the full temperature range of its application. Additionally, achieving a good electrical contact to the bond pads of a die by test probe is difficult. This prevents the necessary testing at incoming inspection, and particularly denies testing at the full speed and over the full temperature range of the individual devices in their application in the MCM.
Once an individual device slips through incoming inspection and is placed in the MCM, the time to isolate a die, if possible at all, and the time necessary to remove and replace a bad die is very expensive and time consuming. Troubleshooting an unsealed malfunctioning MCM includes testing with electrical probes. In this approach, a test probe is used to electrically access a suspected bad device in the MCM. Disadvantages of this method include the small size of the individual devices in the MCM, the relative size of the probe in relation to the bond pads of the individual devices, the density of the devices in the MCM, the likelihood of causing damage with a misplaced probe, and the inability to fully exercise an individual device with electrical test probes. For example, to full~ test a microprocessor in an MCM requires sufficient number of test probes for both data and address bus lines in the microprocessor.
For modern microprocessors the number of probes that would be required will not physically fit into the MCM
cavity. Additionally, the inability to fully test individual devices mounted within the MCM results in a reiterative process of removing suspected devices and ` 2121960 ., retesting the MCM until all faults are removed. A trial and error remove and replace methodology'for the individual devices in a malfunctioning MCM leads to unnecessary removal of good parts and possible damage, if not destruction, to the MCM in total. This proces~ is very time consuming and expensive without providing acceptable results. Sealing the MCM with its lid denies even probe access to the individual devices in the MCM.
It is an object of the present invention, therefore to provide an improved method and apparatus for providing electrical access to the individual devices in an MCM
without increasing the lead count or package size of the MCM package. A technical advantage of the present invention is that the MCM package includes test points and/or test pins which can be easily accessed externally to the package of the MCM by either a test probe or a test socket. The test pins and test points work in combination with the leads of the MCM package to provide greater electrical access to the individual devices within the MCM.
It is a further object of the present invention to provide an apparatus and method using the improved NCM
package to allow for better troubleshooting of MCMs both before and after they are sealed, and allowing for software emulation on and programming or reprogramming of devices in the MCM.
. ' : .: , : ' .
~'" ~' ' ,, ,. ~
. , ' .
'-~: . ' :
.. ..
'':'''~'' ~-':
. ~
,~
` 2121960 BRIEF DESCRIPTION OF THE DRAWINGS
Other objects and advantages of the present invention will be apparent from the reading of the specification and appended claims in conjunction with drawings, wherein:
FIGURE 1 provides a perspective view looking into the cavity of the multi-chip module package; - :
FIGURE 2 depicts the detail of the area as identified in FIGURE 1;
FIGURE 3 depicts a cross-sectional view of multi-chip module package as identified in FIGURE 1; and FIGUREs 4a and 4b depict perspective views of circuit implementations of the preferred embodiments.
` ~`` 2121960 DETAILED DESCRIPTION OF THE INVENTION
In FIGURE 1, is shown a simplified view looking down into multi-chip module (MCM) 10. MCM 10 includes package body 12 with top surface 14, bottom surface 16, and lead frame 18. Package body 12 includes cavity 20, two sets of bond pads, including test pin bond pad set 22 and package input and output (I/O) bond pad set 24. Package body 12 also includes seal ring 26, and individual leads 28 in lead frame 18. Test pins 30 may be flush with or protrude from top surface 14. Alternatively, test pins 30 may protrude from bottom surface 16 in the event that cavity 20 is mounted from the upward side.
FIGURE 2 depicts one possible top surface 14 or bottom surface 16 (bottom if package is mount cavity up) embodiment for the sets of bond pads. The sets of bond pads may be arranged where test pin bond pad layer 22 is located separately from package I/O bond pad layer 24.
Test pin bond pad set 22 includes individual bond pads 32, and package I/O bond pad set 24 includes individual bond pads 34. This arrangement can be reversed without affecting the inventive concept of the present invention.
Additionally, the sets of bond pads may all be located on ~--the same level.
FIGURE 3 depicts a cross-sectional view of MCM 10 showing the orientation of individual leads 28, package body 12, package I/O bond bad layer 24, test pin bond pad layer 22, and top 14 and bottom 16 surfaces of MCM 10. ~ -~
Individual bond pads 34 for package I/O bond pad set 24 are electrically coupled to leads 28 of MCM 10.
Individual bond pads 32 for test pin bond pad set 22 are electrically coupled to test pins 30 and test points 38.
Referring again to FIGURE I, individual devices (not shown) of MCM 10 may be electrically connected by appropriate bond wires to individual bond pads 32 of test pin bond pad set 22 or individual bond pads 34 of I/O
bond pad set 24 as is desired to provide electrical ' ' `~ 2121~60 access to the devices in MCM l0. When MCM l0 is sealed, a lid is placed over cavity 20 and a seal is made with seal ring 26.
Once the individual devices are placed in MCM l0 and bonded to the appropriate bond pads, MCN l0 can be tested at the module level through individual leads 28 of MCM
l0. If MCM l0 is found to be non-functional, knowing how individual devices are connected to leads 28 and test pins 30 of MCM l0 allows the individual devices in MCM l0 to be tested. By appropriately connecting to individual leads 28 and test pins 30 of MCM l0, the individual devices are isolated allowing for determination of whether they are the cause of the non-functionality of MCM l0. Testing individual devices in MCM lO by this method is possible prior to or after sealing MCM l0. By providing access to individual devices in MCM l0, isolation of malfunctioning devices within MCM l0 is possible without using the time-consuming and often damaging process of test probing individual devices.
Additionally, once MCM l0 is sealed, whereas access to -~
individual devices in MCM l0 by probe is lost, test pins 30 in combination with package leads 28 provide the necessary electrical access to the individual devices in -MCM l0.
Additionally, the access methodology for MCM's depicted in these figures also provides for greater access for purposes other than troubleshooting once MCM
l0 is sealed. For example, if MCM l0 contains a programmable device, by appropriately connecting the programming inpu1:s of the programmable device to test pins 30 and leads 28 of MCM l0, it will be possible to program and/or reprogram the programmable device after MCM l0 is sealed. Also, in applications where MCM l0 contains a microprocessor, it may be desirable to test software to be run on the microprocessor. By using test pins 30 and leads 28 of MCM l0, a software designer can 2~21960 access the microprocessor in MCM 10 for software emulation.
Referring to FIGURE 4a, when sealed MCM 10 is mounted to printed circuit board 36, cavity 20 side of MCM 10 is mounted face down onto the surface of printed circuit board 36. This results with the lid 40 as bottom surface 16 closest to printed circuit board 36 and top surface 14 the visible surface when looking down on the MCM 10. If, on the other hand, cavity 20 is mounted face-up, than the emulation and in-circuit test pads are placed on the bottom of the package.
Test access, software emulation, and reprogramming -of programmable devices in MCM 10 remain available. By using appropriate test pins 30 and package leadi 28 individual devices can be accessed, even after MCM 10 is mounted to printed circuit board 36. Test pins 30 may be embodied in pin grid array (PGA) type pins as depicted in ;~
FIGUR~ 4a. Test pins 30 are easily accessed by a clip or - -other socket mechanism. In an alternate embodiment shown in FIGURE 4b, test pins 30 are test points 38 which are -~
either flush with or slightly extending from package body 12 top surface 14.
For example, FIGUREs 4a and 4b depict two -embodiments of the present invention and demonstrate some of their technical advantages. Because test points 38 or -test pins 30 have been included in MCM 10 package body 12, it is possible to troubleshoot, perform software -emulation upon, or reprogram individual devices in MCM 10 even after it has béen mounted onto printed circuit board ~-~
36. Access to individual devices in MCM 10 is accomplished without increasing the size of package body 12 or the number of leads 28.
The package material for MCM package body 12 can be ceramic, plastic, laminate, or metal. Additionally, test points 38 or test pins 30 can be located throughout the :
.
.` g body of MCM pacXage body 12, and do not have to be located along a peripheral ring of package body 12.
Other embodiments of the present invention that may not have been discussed here in detail can be easily identified.
' .~.
.
OPERATION
The basic operation of the preferred embodiment is very straightforward once conceived and comprises, for example, placing individual devices within the cavity 20 of MCM 10 package body 12. By appropriately electrically connecting individual devices within cavity 20 by bond wires to the bond pads of test pin bond pad layer 22 or package I/O bond pad layer 24 the present embodiment provides the desired functionality at leads 28 of MCM 10 and the desired access to individual devices within MCM
10 at test points 38 or test pins 30. The improved - ~-access is available before MCM 10 is sealed, after sealing, and even after the placing MCM 10 on printed circuit board 36. This allows easier troubleshooting of MCM 10, software test emulation, and programming changes to the devices in MCM 10 even after sealing MCM 10.
In summary, we have illustrated one embodiment of the inventive concept of the multi-chip module package with additional test points. The multi-chip module package includes a package body having a cavity for accepting a plurality of micro-electronic devices and substrates and a seal ring to ensure the integrity of the package. A lead frame having a plurality of leads is coupled to the package body and a plurality of test points are located on the external surface of the package body. Alternatively, package input and output may be an integral part of the package. This would not require use of the leadframe. A plurality of bond pads are located in the cavity of the package including a first set or tier and second set or tier of bond pads for electrically coupling the devices and substrates in the cavity external to the package body. The first set or tier of bond pads are electrically coupled to the plurality of ; ~
test points and the second set or tier of bond pads are -electrically coupled to the plurality of leads.
` `- 2121960 A~ a result of the above, although the invention has been described with reference to the above embodiments, its description is not meant to be construed in a limiting sense. Various modifications of the disclosed preferred embodiment, as well as the alternative embodiments of the invention may make further embodiments apparent to persons skilled in the art upon reference to the above description. It is, therefore, contemplated that the appended claims will cover such modifications that will fall within the true scope of the invention.
,
Claims (9)
1. A multi-chip module package for providing electrical access to the individual devices in the multi-chip module without increasing the lead count or package size of the multi-chip module package, the multi-chip module package comprising:
a package body having a cavity for accepting a plurality of devices and substrates;
a plurality of test points located on the external surface of said package body; and a plurality of bond pads in said cavity, including a first set and a second set of bond pads, for electrically coupling the devices and substrates in said cavity external to said package body, said first set of bond pads being electrically coupled to said plurality of test points, and said second set of bond pads being electrically coupled to said plurality of leads.
a package body having a cavity for accepting a plurality of devices and substrates;
a plurality of test points located on the external surface of said package body; and a plurality of bond pads in said cavity, including a first set and a second set of bond pads, for electrically coupling the devices and substrates in said cavity external to said package body, said first set of bond pads being electrically coupled to said plurality of test points, and said second set of bond pads being electrically coupled to said plurality of leads.
2. A method for providing electrical access to the individual devices in a multi-chip module package without increasing the lead count or package size of the multi-chip module package, comprising the steps of:
locating a plurality of devices and substrates in a package body having a cavity;
coupling a lead-frame having a plurality of leads to the package body;
providing a plurality of test points located on the external surface of the package body;
providing a plurality of bond pads in said cavity, including a first set and a second set of bond pads, for electrically coupling the devices and substrates in the cavity external to the package body; and electrically coupling the first set of bond pads to the plurality of test points and the second set of bond pads to the plurality of leads.
locating a plurality of devices and substrates in a package body having a cavity;
coupling a lead-frame having a plurality of leads to the package body;
providing a plurality of test points located on the external surface of the package body;
providing a plurality of bond pads in said cavity, including a first set and a second set of bond pads, for electrically coupling the devices and substrates in the cavity external to the package body; and electrically coupling the first set of bond pads to the plurality of test points and the second set of bond pads to the plurality of leads.
3. A printed circuit board assembly having a multi-chip module package for providing electrical access to the individual devices in the multi-chip module without increasing the lead count or package size of the multi-chip module package, the multi-chip module package comprising:
a printed circuit board for associating with at least one multi-chip module;
a package body having a cavity for accepting a plurality of devices and substrates;
a lead-frame having a plurality of leads coupled to said package body;
a plurality of test pins located on the external surface of said package body; and a plurality of bond pads in said cavity, including a first set and a second set of bond pads, for electrically coupling the devices and substrates in said cavity external to said package body, said first set of bond pads are electrically coupled to said plurality of test pins, and said second set of bond pads are electrically coupled to said plurality of leads.
a printed circuit board for associating with at least one multi-chip module;
a package body having a cavity for accepting a plurality of devices and substrates;
a lead-frame having a plurality of leads coupled to said package body;
a plurality of test pins located on the external surface of said package body; and a plurality of bond pads in said cavity, including a first set and a second set of bond pads, for electrically coupling the devices and substrates in said cavity external to said package body, said first set of bond pads are electrically coupled to said plurality of test pins, and said second set of bond pads are electrically coupled to said plurality of leads.
4. A method for providing electrical access to the individual electronic devices in a multi-chip module package of a printed circuit board without increasing the lead count or package size of the multi-chip module package, comprising the steps of:
locating a multi-chip module on a printed circuit board;
locating a plurality of devices and substrates in a package body of said multi-chip module, said package body having a cavity;
coupling a lead-frame having a plurality of leads to the package body;
providing a plurality of test pins located on the external surface of the package body;
providing a plurality of bond pads in said cavity, including a first set and a second set of bond pads, for electrically coupling the devices and substrates in the cavity external to the package body; and electrically coupling the first set of bond pads to the plurality of test pins and the second set of bond pads to the plurality of leads.
locating a multi-chip module on a printed circuit board;
locating a plurality of devices and substrates in a package body of said multi-chip module, said package body having a cavity;
coupling a lead-frame having a plurality of leads to the package body;
providing a plurality of test pins located on the external surface of the package body;
providing a plurality of bond pads in said cavity, including a first set and a second set of bond pads, for electrically coupling the devices and substrates in the cavity external to the package body; and electrically coupling the first set of bond pads to the plurality of test pins and the second set of bond pads to the plurality of leads.
5. A multi-chip module formed to contain a plurality of devices and substrates, comprising:
package body formed to accept a plurality of devices and substrates;
a lead-frame having a plurality of leads formed to associate with said package body;
test means associated with the external surface of said package body; and a first and a second electrically coupling means for electrically coupling said devices and substrates external to said package body, said first set of bond pads being electrically coupled to said test means, and said second set or tier of bond pads being electrically coupled to said plurality of leads.
package body formed to accept a plurality of devices and substrates;
a lead-frame having a plurality of leads formed to associate with said package body;
test means associated with the external surface of said package body; and a first and a second electrically coupling means for electrically coupling said devices and substrates external to said package body, said first set of bond pads being electrically coupled to said test means, and said second set or tier of bond pads being electrically coupled to said plurality of leads.
6. A method electrically accessing individual devices within a multi-chip module, comprising the steps of:
forming a plurality of devices into a multi-chip module package body;
coupling a plurality of leads to said multi-chip module package body;
forming a plurality of test pins on an external surface of said multi-chip module package body;
forming a plurality of bond pads in said multi-chip module, including a first set and a second set of bond pads, to electrically couple said devices external to the module package body;
electrically coupling said devices to said plurality of bond pads; and electrically coupling said first set of bond pads to said plurality of test pins and said second set of bond pads to said plurality of leads.
forming a plurality of devices into a multi-chip module package body;
coupling a plurality of leads to said multi-chip module package body;
forming a plurality of test pins on an external surface of said multi-chip module package body;
forming a plurality of bond pads in said multi-chip module, including a first set and a second set of bond pads, to electrically couple said devices external to the module package body;
electrically coupling said devices to said plurality of bond pads; and electrically coupling said first set of bond pads to said plurality of test pins and said second set of bond pads to said plurality of leads.
7. A multi-chip module including a plurality of devices and substrates comprising in combination:
substrate including a plurality of interconnected and distinguishable circuits;
a plurality of leads for connection to external circuitry comprising a part of said substrate and originating from the periphery thereof; and a plurality of electrical terminations situated apart from said plurality of leads.
substrate including a plurality of interconnected and distinguishable circuits;
a plurality of leads for connection to external circuitry comprising a part of said substrate and originating from the periphery thereof; and a plurality of electrical terminations situated apart from said plurality of leads.
8. A method of forming a multi-chip module including a plurality of devices and substrates, comprising the steps of:
forming a substrate including a plurality of interconnected and distinguishable circuits;
forming a plurality of leads for connection to external circuitry, said leads comprising a part of said substrate and originating from the periphery thereof; and placing a plurality of electrical terminations in said multi-chip module apart from said plurality of leads.
forming a substrate including a plurality of interconnected and distinguishable circuits;
forming a plurality of leads for connection to external circuitry, said leads comprising a part of said substrate and originating from the periphery thereof; and placing a plurality of electrical terminations in said multi-chip module apart from said plurality of leads.
9. A method for testing a plurality of devices in a multi-chip module, the method comprising the steps of:
connecting external circuitry to a plurality of leads, said plurality of leads comprising a part of the multi-chip module and originating from the periphery thereof; and connecting an external test circuit to a plurality of electrical terminations, said electrical terminations being situated apart from said plurality of leads.
connecting external circuitry to a plurality of leads, said plurality of leads comprising a part of the multi-chip module and originating from the periphery thereof; and connecting an external test circuit to a plurality of electrical terminations, said electrical terminations being situated apart from said plurality of leads.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/058,553 US5396032A (en) | 1993-05-04 | 1993-05-04 | Method and apparatus for providing electrical access to devices in a multi-chip module |
| US08/058,553 | 1993-05-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2121960A1 true CA2121960A1 (en) | 1994-11-05 |
Family
ID=22017530
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002121960A Abandoned CA2121960A1 (en) | 1993-05-04 | 1994-04-22 | Method and apparatus for providing electrical access to devices in a multi-chip module |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US5396032A (en) |
| CA (1) | CA2121960A1 (en) |
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| US5608337A (en) * | 1995-06-07 | 1997-03-04 | Altera Corporation | Method and apparatus of testing an integrated circuit device |
| US5608359A (en) * | 1995-10-10 | 1997-03-04 | Motorola, Inc. | Function-differentiated temperature compensated crystal oscillator and method of producing the same |
| US5766978A (en) * | 1996-01-26 | 1998-06-16 | Hewlett-Packard Company | Process for testing an integrated circuit package using an integrated circuit package retainer |
| US5796171A (en) * | 1996-06-07 | 1998-08-18 | Lsi Logic Corporation | Progressive staggered bonding pads |
| US6329594B1 (en) | 1998-01-16 | 2001-12-11 | Bae Systems Information And Electronic Systems Integration, Inc. | Integrated circuit package |
| US6026221A (en) * | 1998-02-18 | 2000-02-15 | International Business Machines Corporation | Prototyping multichip module |
| US6464513B1 (en) * | 2000-01-05 | 2002-10-15 | Micron Technology, Inc. | Adapter for non-permanently connecting integrated circuit devices to multi-chip modules and method of using same |
| US6407566B1 (en) | 2000-04-06 | 2002-06-18 | Micron Technology, Inc. | Test module for multi-chip module simulation testing of integrated circuit packages |
| US20020011909A1 (en) * | 2000-07-31 | 2002-01-31 | Delta Electronics, Inc. | Method for packing electronic device by interconnecting frame body and frame leads with insulating block and its packing structure |
| US7045889B2 (en) * | 2001-08-21 | 2006-05-16 | Micron Technology, Inc. | Device for establishing non-permanent electrical connection between an integrated circuit device lead element and a substrate |
| US7049693B2 (en) * | 2001-08-29 | 2006-05-23 | Micron Technology, Inc. | Electrical contact array for substrate assemblies |
| US8680670B2 (en) | 2010-10-22 | 2014-03-25 | International Business Machines Corporation | Multi-chip module system with removable socketed modules |
| CN106340469B (en) * | 2016-11-16 | 2023-06-23 | 长电科技（滁州）有限公司 | Test groove-adjustable transistor package test seat and operation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4167647A (en) * | 1974-10-02 | 1979-09-11 | Santa Barbara Research Center | Hybrid microelectronic circuit package |
| US4082394A (en) * | 1977-01-03 | 1978-04-04 | International Business Machines Corporation | Metallized ceramic and printed circuit module |
| US4180161A (en) * | 1977-02-14 | 1979-12-25 | Motorola, Inc. | Carrier structure integral with an electronic package and method of construction |
| US4331831A (en) * | 1980-11-28 | 1982-05-25 | Bell Telephone Laboratories, Incorporated | Package for semiconductor integrated circuits |
| US4711024A (en) * | 1981-10-30 | 1987-12-08 | Honeywell Information Systems Inc. | Method for making testable electronic assemblies |
| DE3234745C2 (en) * | 1982-09-20 | 1986-03-06 | Siemens AG, 1000 Berlin und 8000 München | Method of handling film-mounted integrated circuits and apparatus for carrying out the same |
| US4920454A (en) * | 1983-09-15 | 1990-04-24 | Mosaic Systems, Inc. | Wafer scale package system and header and method of manufacture thereof |
| US4727410A (en) * | 1983-11-23 | 1988-02-23 | Cabot Technical Ceramics, Inc. | High density integrated circuit package |
| US4701781A (en) * | 1984-07-05 | 1987-10-20 | National Semiconductor Corporation | Pre-testable semiconductor die package |
| US4801561A (en) * | 1984-07-05 | 1989-01-31 | National Semiconductor Corporation | Method for making a pre-testable semiconductor die package |
| US4772936A (en) * | 1984-09-24 | 1988-09-20 | United Technologies Corporation | Pretestable double-sided tab design |
| US4866508A (en) * | 1986-09-26 | 1989-09-12 | General Electric Company | Integrated circuit packaging configuration for rapid customized design and unique test capability |
| US5103557A (en) * | 1988-05-16 | 1992-04-14 | Leedy Glenn J | Making and testing an integrated circuit using high density probe points |
| US5008614A (en) * | 1988-10-11 | 1991-04-16 | Hewlett-Packard Company | TAB frame and process of testing same |
| GB9018764D0 (en) * | 1990-08-28 | 1990-10-10 | Lsi Logic Europ | Packaging of electronic devices |
| US5138115A (en) * | 1990-10-12 | 1992-08-11 | Atmel Corporation | Carrierles surface mounted integrated circuit die |
| US5241133A (en) * | 1990-12-21 | 1993-08-31 | Motorola, Inc. | Leadless pad array chip carrier |
| US5221812A (en) * | 1991-06-28 | 1993-06-22 | Vlsi Technology, Inc. | System for protecting leads to a semiconductor chip package during testing, burn-in and handling |
| US5210485A (en) * | 1991-07-26 | 1993-05-11 | International Business Machines Corporation | Probe for wafer burn-in test system |
-
1993
- 1993-05-04 US US08/058,553 patent/US5396032A/en not_active Expired - Lifetime
-
1994
- 1994-04-22 CA CA002121960A patent/CA2121960A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| US5396032A (en) | 1995-03-07 |
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