CA2123923A1 - Pcmcia interface using shared memory - Google Patents
Pcmcia interface using shared memoryInfo
- Publication number
- CA2123923A1 CA2123923A1 CA002123923A CA2123923A CA2123923A1 CA 2123923 A1 CA2123923 A1 CA 2123923A1 CA 002123923 A CA002123923 A CA 002123923A CA 2123923 A CA2123923 A CA 2123923A CA 2123923 A1 CA2123923 A1 CA 2123923A1
- Authority
- CA
- Canada
- Prior art keywords
- pcmcia
- memory
- peripheral
- host computer
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4403—Processor initialisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
Abstract
PCMCIA Interface Using Shared Memory Abstract A "Personal Computer Memory Card International Association"
(PCMCIA) peripheral, e.g., a modem, incorporates a shared memory interface to a personal computer. This shared memory interface provides the capability to easily program the PCMCIA peripheral either in the factory or in the field. In addition, the shared memory interface removes the requirement of having a resident "boot-up"
code in the PCMCIA peripheral. Finally, the shared memory interface provides the capability to transfer user data from the personal computer, i.e., data terminal, to the PCMCIA modem at a higher data transfer rate than is currently available via the modem's universal asynchronous receive/transmit (UART) integrated circuit.
(PCMCIA) peripheral, e.g., a modem, incorporates a shared memory interface to a personal computer. This shared memory interface provides the capability to easily program the PCMCIA peripheral either in the factory or in the field. In addition, the shared memory interface removes the requirement of having a resident "boot-up"
code in the PCMCIA peripheral. Finally, the shared memory interface provides the capability to transfer user data from the personal computer, i.e., data terminal, to the PCMCIA modem at a higher data transfer rate than is currently available via the modem's universal asynchronous receive/transmit (UART) integrated circuit.
Description
SENT BY: 5-16-94; 3:01F'M; Ml` IF'-L~W~ 613 237 00~5;~ 4/23 PCMCL~ ~terface Using Shared ~qemory Bac~round oî the ~nventiun The present invention relates to data cornmunications equipmenl and.
more par~icularly, to a modem having a "Personal Computer Memory Card S InterrlRtional Association" inlcrface.
The "Personal Computer ~erno~ Card Intorr~ional Association"
(PCMCLA) int~rface defines the physical s1~e nnd thc electrical interconnection for a class of computer peliphera~s, i.e., PCMCIA penpheraLs. Generdlly, the size of aPCMCIA peripheral is approxirnately that of a "credi~ card." Each c~dit card size 10 PCM(~IA peripheral electrically intercormects ~ia a PCMC1A electrical connector to a "host computer," which is typically a "no~ebook" sizc personal computer (PC).
PCMCIA pe~ipheraLs like ITlemory, moderns, fax, hard disks. etc., arc cu~n~ly available.
Like their more conventional cousins, a PCMCIA modem is a comple:c lS piece of equipment that c~rnprises specialized r~ucroproccssor circuitry. Forexample, a PCMCIA modem typically includes a general-purpose microprocessor (CPU), memory, a teleph-~ne line interface lo the F'ublic Switched Telephone Network (PSTN), and a high-speed digital signal processor for proccssing ~he respective communications signal in bo~h Ihe transmit and r~ceive directions. The 20 functionality of the PCMC1A modern is provided by the CPU's execurion of a computer ~rogra~, i.e., the "operating prograrn," ~hat resides in the PCMCIA
modern's merr~ry~ This memory is usua]ly "flash memory," which is a non-volatilememory tha~ is field-progr~unmable by the modern's CPU.
An advantdge Qf the flash rl emory is that it a~lows field qpgradcs of the 2~ rf~odem's operating program for eitber pro~riding new fea1ures or "bug" fixes. In order to per~orm a field upgrade a part of the flash memory is reserved for a "boot block" computer prograr~L This part of the flash mem~ is write-protected so that i~
retains its data, i.e., the boot block, even ~4hen the rest of rhe flash memory is erased and reprogramrned. The boot block includes computer software fw booti~g-up the 30 modem, e.g., after application of power, and for loading the remainder of Ihe flash memory with the operaring prograrn.
A field Upgrd~le of the modem's flash nnemory is p~onTIed over one of the serial data pGrts, either the data communications port or the data terminal port.
First, the modem's CPU receives a cotr~mand to reload the operating program from a 35 "hos~" coupled to one of the seri~ ports. Then the modem's (~PU execu~es thatportion of the boot block associated with Inading the flash memory. This part of Lhe M::IY 16 ' 94 14 :57 PI~GE . 004 ,~
SENT sY 5-16-9~: 3:02P,U: MT l~-UW~ 613 237 0045;~ 5/23 21~3923 ! ~ , , - 2 -software first erases thc remaining portion of the flash mery and then reccives the new operating program via one of the serial ports and writes the new operating program to the flasb memor,v.
An altema~ive approach that does not requ~ a non-wlilable boot block 5 in the ~ash memory i5 provided by AT~T Paradyne's 3~no mo~em, which complises an independent "upper ban~" and "lower banlc" of flash momory. The modem's C*U can boot from either bank. The modcm's CPU b~gins operation by execu~ing the comput~r prograrn stored in one of the flash memory banks, i.e., Ihe ac~ive bank of fiash memoly. This computer Faogram includes the boot code and the ln operating program. When the modem's CPU receives a command from the hos~ to change thc operating progrsm via one of the serial ports, the modem's CPU executes a do~vnload program conrained in the activc bank of flash memory. This download software first erases the non-nctive bank of flash memoly and ~hen copies Ihe received d~ta ~om one o~ the serial data por~s into the non-ac~ive bank. This 15 received data is the new computer ~rograrn, which conta~ns new boot code a~d the new operating program. At the conclusion of this download mode, ~he modem's CPU toggles a non-volatile s vitch so that i~ will boot after a reset from Ihe newly updated bank of flash memary, i.e., it switches which bank of flash memory is the active bank. This approach is disclosed in the co-pending, coaunonly assigned 20 Unit~d States Patem application ~f Hechl et al. entitled "Apparatus and Method for Downloading ProErams," serial No. ~7188025~, filed on May 8, 1992.
As described abovc, Qlthough a flash memory upgrade for a PCMCIA
rnodcm vi~ one of the sc~rial por~s is an advantRgeous approach, there are several limitattons. One is that during manufacture the boot block must be programrned into 2.5 the Qash rnemory prior to soldering the flash memo~ onto Ihe printed circuil board.
This adds COSl tO the manufactu~ng process of the PCMCIA modetL In addition, if the boo~ block is somehow e~ased or colrupted and power to the PCMCIA modem is lost, there is no recovery mechanisrn other than remoYing and replacing the flash memory. F~hermore, the size of the boot block is fixed (typically 16~C bytes)7 30 vhich presents ConstrainLc on the functionality of the boot bloclc. In addition, Ihe boot block sin~larly cons~ains the size of the PCMCIA mode~ opera~ing prog~arn since a por~ion of the flash mernory is dedicated to the boot bloc~ Finally, the speed Or any field upgrade is limited because Qf the use of a serial data por~.
1`1~1Y 16 ' 94 14: 58 Pl:iGE . za5 SENT BY: 5-16-94 ; 3:02~1\1; MT IP-L~W~ 613 237 OOg5;# 6~23 -Surnm~t-y of th~ lnvention This invention eliminates all of thc abo~e-mentioned limitations by psoviding a method and apparatus for loading a llash memory afu~r it is a part of a complercd PCMCIA modern assembly. In accordancc with the principles of the 5 inventi~n, a PG~CIA peripheral incorporates a shared rnemory interface to a host computer via the PCMCL~ connector. This shared n~cmory provides the capability to easily load or ch~nge the computer prograrn of the PCMCIA peripheral from thehost computer without requiring either the a priori prescnce of a dedical~i bootblock in the flash tnernory or the usc of a serial data port.
1n In an ernbodiment of the invention, a PC~ rnodcm includes a CP~, mcmory, and a shared r~emory that is coupled to a personal computer (PC) via thePCMCIA conneclor. During r~mal operation, Lhe CPIJ accesses and executes any computcr program stored in the tnemory A field upgrade or ini~ial factory lo~d is p~rformed in the following rnanner. first, the PC applies a r~,set to the PCMCIAl!i modem. During ~his reset, the PC stores a control prograT~ in the shared memory.
After storing the conlrol program, thc PC aiters the memQry map Qf the PCMCIA
modem so that after the reset thc CPU executes the control program stored in thesha~i memory. T11is control program further provi~es the abiii~y to the PCMCIA
modem to ~ransfer a new computer program via the shared memory lo the mernory 20 of Ihe PCMCIA modem, i.e., thc control program is the boot bk~clc sofnvare. After transferring the new cornpuler prog}am, the PC a~ain initiatcs a resct of the PCMC:IA tnodem tha~ returns the memory map of the PCMCIA modem to no~mal ~uch that aft~ thc reSet the CPU executes the new computer program slored in thePCMCIA n~odem's mernory.
In accordance ~ith a feature of ~he invention, n~ither the field upgrade nor the initial program load in ~be factory rcquire any boot block soft~are to oe resident in the PCMCIA card.
Anothcr feature of the invention uses the shared mcmory interface to transfer user data from the personal computer, i.o., data telrninal, to the PCMCLA
30 modem. This results in a higb.cr data transfer rate than is currently avail ble via the on-board uni-rersal asynchronous receive/transmit (UART) in~egrated circuit thatcouples the r~m to any terrninal equipment.
Brief Description of the DrawinR
l;IG. I is a block dhgram of a portion of a PCM('~ modem embodying 3S the principles of the tnvention;
~ 1Y 16 ' 94 14: 56 P~GE . 006 SENT BY: 5-16-99: 3:02PM: MT I~ W~ 613 237 0045:~ 7/23 FIG. 2 is a table irnplelnent~i by chip enable rou1irlg logic lS0 of FIG.
FIG. 3 illustr~tes a PCMCIA peripheral map for host computer 200 of FIG. l;
S FIG. 4 is a flow dia~ram of a m~thod embodying the principles of the invention; arld E;IG. S is a flow diagram of a memory arbi~ration method pçrfon.ned by CPU 170 of PIG. 1.
Detniled Description FIG. 1 shows a portion of a PClUCIA rnodem that embodies the inventive concepts af this invention. ~s shown, host computer 200 includes PCMCIA slot 2~0 for receiving PCM(:~IA modem 100, host CPU 270. and reraov~blc storage unit 21~ for rec~iving floppy disk 216. PCMCIA modem 100 includes CPU 170, program memory 160, sharcd memory 130, chip enable routing logic 15n, control logic 140, and PCMCIA connector 120. CPU 17() is a microprocessor-based central processing unit which operates on, or executes, program data stored in program memory 160 ~r shsred mernory 130 (discussed below) via contr~l processor bus 175, which providcs control, addre~s and data sigll815 (not shown). PCMICIA modem 100 is physical1y and electrically coupled tl~
host computer 200 Yitl PCMCIA interface 10. The latter includes PCMC~A
cormector 120 af PCMCIA modem 100 and PCMCIA slot 220 of host computer 200.
For the pu~poses of this example, program memory 160 is a flash memory. Tbe pro~ram data storcd in pro~am mcrnory 160 is he~inafter ~eferred ~o as the operating computer program. l~Is operating computer program provides the modem 25 functionality f~r hansn~itting and re~iving da~a via a cornmunications facility (not shown).
It is ~ssurned that CPU 170 includes appropnate addrcss decode and chip enable logic. Two chip enable signals, CEl and C~2. ar~ provided by CPIJ 170 on lines 171 and 1?2, respectively. These chip enable signals are used to select~1) eilher prograrn memory 160 or shared memory 130. Normally, these chip enablesignals would bc coupled dircctly ~o lhcs~, memory deYices. Howe~er, in accn~Lance with Ihe principles of the invention, CEl and CE2 are applied tO chip enable routing logic lS0, which ,~rovides chip onablc signa~s to program memory 160 and shared memory 130 as a function of the rnode of operation of PCMClA modem 100. This 35 is sho~n in FIG. 2. For the purposes of this example it ie acsumed that there are two modes of operation: a "nonnal rnode" and a "download mode." During a nonnal M~Y 16 ' 94 14: 58 P~GE . 007 SENT BY: 5-16-9~: 3:03~M: MT l~-L~W~ 613 237 0045:# 8~23 mode, chip enable routing logic lS0 providos CEI to program memory lfi0, via linc 151; and provides CE2 to sha~cd memory 120, via line 152.
Af`tcr a CPU reset signal is applied ~o CPU 170 ~ria line 144, CPU 170 applies CEI to chip enable routing logic 150. As is known in the art, afte~
S application of a resel signal, a rnicro-processor starts execution a~ a known s~arting addrcss location. For the purposes of this example, it is assumcd that this ~ fined location is ma~ped to an ad~ss range associa~ed wi~h CEI. The CPU rese~ signal on Une 144 is provided by control logic l40 either as a result of RESET signal (not shown) defined in the PCMCIA interface being asserted, e.g., durirlg a power-up l0 condition; or as a result of a memory access by hosl CPU 270 (di~cussed below). In the normal rTlode of ~eration, as shown in FIG. 2, OEl is routed to program memory 160 so that CPU 170 execu~cs the opera~ng compuler program~ In this nor~n~l mode, CPU 170 accesses shared nlemory 130 by providing CE on linc 152 via chip enable routing logic 150.
Shared mcmory 130 is also known as a "dual por~ ram" and has two sels of addrcss, data, and control lines. One set is used to inlerface to PCMCTA bus 121 and tho other ser is used to intefface to control processor bus 175. In Accordancc with the principles of Ihe invendon, sh~ed ~erncry 130 is puI to different use depending on the mode of operation. As shown in ~IG. I, dunng tne nonnal modo 20 of operation, shared memory 130 comprises PCMCIA attribute rep,ion 135, whichincludes the software definable Card Infonn~tion Stn~cture, Pin Rep]acement Register, Configura~ion Option Regis~er, Card Configulation and Status Register in acc~lance with the PCMCIA interface standard. However, duIing th~ download mode of oporation (discussed below), shared rnemory 130 includes region 136, ~5 which is ~ buffcr that storcs d~ta received from host CPU 270 of host c~mputer 200;
and region 137, which stores a control program provided by hosr CPU 270 and subsequently sxecuted by CPU l70.
In ~ccordance wi~h the principles of the inveDdon, the other mode of operadon--the download mode--directs CPU 170 to begin execution of progr~n 3Q da~ from shared mernory 130 after tho applica~ion of a CPU reset signal on line 144.
In particular, in thc download mode of opera~ion, chi,~ enable routing logic 150swi~chcs thc CEI signal from lead I51 to lead 152, and conversely, switches the CE2 signal from lcad 152 ~o lead 151. As a rosult, CPU 170 now exe~utes instrucdons s~ored in sh~rcd memory 130 after exiting from a reset condition.
i1i:1Y 16 ' 94 1 4: 59 PFIGE . 008 , SENT BY: 5-16-94; 3:03~M; MT l~-UW~ 613 237 00~5;# 9/23 ~ .1 ?.~
Whether or no~ the down]oad mode of operation is en~ered by P~SCIA
modem 100 is under the control of host CPU 270. lt should be noted that under the PCIvlCIA standard, pornons, or all, of PCMCIA modem 100 is rnapped ~nto a part of the PC)~ClA peripheral space of host C~PU 270. An illustrative PCMCIA peripheralmap of PCMCIA 100 as viewed by host CPU 270 i~ shown in FIG. 3. An illustrative rnethod for usc in host CPU 270 for switching PCMC~A modem ]00 to the do~nload mode is shown in ~G. 4. Hos~ CPU 270 affec~s a reset of CPU 170 in step 405 by asser~in~ the REST signal of the PChlClA interface, or by writing aparacular data value ~o a particular memory location on PCMCIA modem 100 that is10 associat~d with resetting PCr~CIA modem ]00, i.e., a "reset location" as shown in ~IG. 3. In this example, ~his rescl location is within the shared memory region and during non~nal opc~rstion is associated with the Configuradon Opdon Register, wbich i~ a part of PCMCIA attnbute reg~on 13S as defined by Ihe PCMCL~ standard. Onc of thc defined dats bi~s of the Configuration Option Register is the "SRESET" bit.
15 CPU 270 affects a reset of PCMCIA moden~ 100 by serting the nSRESEr" bit, which is d7, equal to a logical one, Control lo~ic 140 of P~MCIA mods~m 100 detects this memory writo to the resc~ location aDd in response ~hereto generale~ a CPU rese~ ~gnal on line 144 ~o CPU 170.
While the CPU rcset signal is ac~e CPU 170 is inaClive, i.e., performs 20 no rnemory accesses. Host CPU 270 then wntes a con~rol program to shared memol~y region 137 in step 410. After stcp 410, hosl CPU 270 s~vitches the mode nf operarion of PCMClA modem 100 by accessing in a particular wuy a respective predefined memory location associatcd with Ihe download mo~o in step 415. In tbis exarnp1e, host CIPU 270 perfonns three consecutive w~itcs of a prodef~ncd data value 2~ ~o the do~,vnload mode location. Cont~ol logic 140 of PCMCJA modem 100 detects th~sc ~onsç~utive rne~nory accesses and compares the data vallles being wriuen by CPU 270 to the predefined data value. If ~he data values being wrilten cqual thepredefined data value, con~l logic 140 applies a control signal on line 142 to chip enable routing logic 150. The latter allers the routin~ of the ubove-mentioncd chip 30 enable signals as shown in FIG. 2 for thc download mo~. It is assumed that sleps 41n and 415 occur while thc abov~-mentioned reset si~nal on line 144 is still active.
In oth words, it is assumed that control logic 140 generdtes a CPU reset signal oF
sufficient wtdth to provid~ the t~rne for host CPU 270 to perfor~n steps 410 aud 415.
~f hos~ CPU 270 does not switch the mode of operation within the period of tir~e35 whon the CPU resel signal is active, control logic 140 blocks any subsequ~n~
attempts to sv.~itch modes and PCMCIA modern l(~ simply con~inues to rernain in PfiGE . 009 1`1~1Y I 6 ' 94 1 4: 59 SE~IT BY: 5-16-94; 3:03~M: MT lP-LAW~ 613 237 0045:#10/23 2~23923 the normal modc. In other words, control logic 140 provides a "lockoul mechanism"
that pre~ents inadverten~ switching of chip enables. This lockoor mechanism forces PC~I~L4. mode~n 100 to defau~t to thc nonnal mode af~er a CPU reset signal is applied unless host CPU 270 acccsses in ~he pr~scribed menner the download n~ie S location. Alternad~ely, to avoid this tirnc constr~unt on host CPU 270, ~he latter can ma~e use of thc SRESEr bit for ~urning on and of f the CPU reset signal.
In the d~wnload rnode and after removal of the CPU rese~ signal, (~PU
170 cxccutes the contTol program in shared rnemory 130. Host ~PU 270 then transfers data to shared rnemory region 136 in step 420. This data represenlS
~0 portions of the new cornputer prograra to be plnced into prog~n memory 160. lhc control program, when executed by CPU 170, transfers the data placed in sharcd memory region 136 by host C~PU 2.70 to program memory 160--thus cha~ging the operating computer pro~ram execu~ed by CPU 170 during the norrnal m~de of operation. rt should be noted ~hat no boot block soft vare is required to be residenl in lS the PCMaA peripheral othor than the temporary control program provided by hnst CPU 270 in order to accomplish this download, irrespective of wh ~her this download is a pan of a field upgrade a~ the initial program load in a factoIy. k is ~ssumcd that the control progrem ex~cuted by CPU ~70 includes a "hand-shakin~"
procedure for coonlina~ing the transr~r of data blocks from host CPU 270 to program ~emoty 160. Far example, after the data in shared mernory region 136 is ~rritten by CPU 170 to a portion of pro~arn memory 160, CPU 170 writes to a predefined "flag" location of shered mcmcry 130. This fla~ when read by host CPU 270, indicates to host CPU 270 to write the next p~i~n of the operating computer program to shared memory region 136.
Aftcr host (:PU 270 has finished downloading the new operating computer prograrn to PCMCLA 00d~m lO0, host CPU 270 again resets PCMCIA
modem 100 in step 425. With the applicatinn of the CPU reset signal, control logic 140 swi~ches PCMUA modem 100 back to the norrrlal mode as part of the lock-out rncchanism described above. As a result, control logic ~40 alters the routing of the 30 above^mentioned chip enable signals as shown in FIG. 2 for ~he norrnal mode. In the norrn~ ode and sfter r~moval af the CPU rc.cet signal, CPU 170 executes Ihe new operating computer program now s~ored in pro~m memoly 160.
As can be seen from the nbo~re description, when transferring data from the buffer locatcd within shared memo~y region 136 to program memory 1~0, both 35 CPl~ 170 and host CPU 270 are accessing shared memory 130. For exarnple, at the ssme tim~ CPU 170 is reading program dsta from shared memory region 137--host ~ 1Y 16 '94 1~:59 Pl:IGE.~3~Z
SE~T BY: 5~16-94; 3:0~N: MT l~-LAW~ 613 237 0045;#11/23 CPV may be atrernpdtlg to write dala to ~he buffer locdted within shared rriemory region 136. As a result, a memory ContenLion scherne is required to arbitrate bet~,veen C~U 170 and host CPU 270 when they atTempt to access shared m~
] 30 simul~aneously In this exarnple, the mernory contention schcme is implemented by a cornbination of hardv~are, represented by control k~gic 140, a softwsre prolocol. and the P~ICIA defined WArr si~nal on line 142. Altbough shown as ~ separate signal for convenience, it should be realized that uhe WAlT signal on liDe 142 is a subset of PCMClA bus 121.
Control logic 140 monitors PCMCT~ bu~ 121 to detect any shared n~emory accesses by host CPU 270. When hos~ CPII 270 be~ins a shared memory access tn PCMCIA modem 100, control logic 140 activates the host accoss .signal on line 141, l,vhich i5 received by CPU 170. ln addition, CPU 170 provides a wait enable signal on line 173, which is received by control unit 140. rf Ihe wait enab]e 1~ ~signal is active, control unit 140 enables the generation of the WArr signal on line 142 in response to any subsequent shared memory access by host CPU 2?0. As is l~nown in the art, when the PCMCLA WAIT signal on line 142 is active, bosl CPU
270 inserts wait sta~es in the currerlt memory access. Convcrsely, if the wait enab]e signal is inactivc, control unit 140 disables the generation of this WAlT signal so 20 that no addilionsl wait s~atcs are inse~ed into a shared mem~y access of host CP~J
270. It should be noted that the PCMCIA specificstion requires th~t accosses by host computer 270 via PC~MCIA connector 120 be complcted u,ith no more than a l2 microsccond delay.
FJG. S shows a flow diagranl for a method used by CPU 170 for 25 irnplementing a soft vare protocol to contro1 the generation of the wai~ ensb1e signal on lino 173. Whenever (~PU 170 ~ccesses sharcd mernory, CPU 170 firsl activates ~he wait enable signal on line 173 in step 505. CPI.7 170 then reads, or samples, ~he host acce6s si~nal on line 141 in step 51(1. rhis allows (~IJ 170 to checl~ if hclst CPU 270 has already beglln an access to shared memory. ~f Ihe host ~ccess signal is 30 acive, thcn the wait enablc signal on lille 173 is disabled and CPV 170 itself waits for a predcterrnined peri~7d of timc, T, in step 515 befo~ returning to s~p 505. Thc latter step is important bccause host CPU 270 may ignore ~he WATT signal on line141 if it was enabled after the wait recognition window of hosl CPU 270. This may uccur bcc~usc of the asynchronous relationship of any sh ned mernory accesses by35 ~he two processors. However, if dle host access signlll is ir~ , CPU 170 accesses sharcd mcrLory in step 520 and then disablcs the wai~ enable signal on line 173 in PRGE . 01 !
1~1RY 16 '94 15:00 SENT BY: 5-16-94: 3:04~M ~ UW~ 613 237 00~5;~12'23 2~23~23 step 530.
As described above and in accordance with the princip1es of the invention, host CPU 270 is able to change the operatin~ compulcr program stored in PCMCIA modem lOO and thereby provide an easy rneans to update or charlge the S funcsionality of PCMCTA modem 100. As shown in E~IG. 1, the program data execul~d by PCMC~ modern lOO can be provid~d to hosl CPU 270 via floppy disk 2l6. Indecd, any type of progrdlDs for PCM(~L~ modem lOO can be easily provided.For example, 90ppy dislc 216 can supply a dia~nostic testing pro~ram. which ~hendownloaded by hoss CPU 270 allows PCMCIA modem lOO ~o perform a series of 10 diagnostic tesss.
In addision. Ihe use of shared mem~ry 130 in PCMCIA modem lOO also provides other improvements ~o systern opcra~ion. For example, since ~he PCMCIA
peripheral is B modem, hos~ compu~r 200 is a data terminal. As is known in the art, hosr CPU 270 sransfers data for tsansrnission over a data cornmLnications chflnnel 15 (not shown) by wriring data in psrallel to a UART (not shown) of PC~ICI~ modem 100. This UART then conYcrts ~he data to a serial form tn sirnulate Ihe serial data transmission from the data tennin~l. Consequently, the PCMCIA modem again converts thc serial data strearn from its UART back ~o a pa~allel forrn agflin.
Unfonunate~y, ~his prl~cess t~nds ~o limi~ Ihe speed oî any dnsa tr~nsfcr. However, in 20 accordance with the in~ention, sha~ed memory 130 can be used to transfer user data betweèn the data terminal and the modem at a a higher data transfer rate. lhis is accornplishod by dedicating a portion of sha~d memory ~?sO as a buffer for dir~c~ly transf~rin~ dasa from host c~rnputer 200 to PCMCL~ rnodom lOO.
In addition, in th~ prior an, the PCMCI~ a~ribu~ s :ructure is typically 25 p~e-defincd and non-changeable, e.g., a read-only memory (ROM) is used to provide the PCMUA a~tribute structure. However, the use of shared memory 130 allows for a software definable PCMCIA card infom~ation structure ~hat can be dyn~rrucally altercd by CPU 170.
The forcgoing merely illust~ates the principles of the invention and il 30 will thus be appreciated thst tho~se sldll~d in ~he art will be able to devise numerous ~l~ernative a~angements which, although not explicitly described herein, embody the principles of the invention and are within its spirit and scope.
For example, slthough the i~ventive conccpt was desctibed in ~erms of utilizing flash rnemory, any non-vola~ile programmable RAM can be us~ In fact, 35 even volatile RA~I can ~e used as long às the PCMCIA peripheraI is pr~perly initialized by the host corDputer on power-up of the system.
t~1RY 16 '94 15:00 PRGE.012
more par~icularly, to a modem having a "Personal Computer Memory Card S InterrlRtional Association" inlcrface.
The "Personal Computer ~erno~ Card Intorr~ional Association"
(PCMCLA) int~rface defines the physical s1~e nnd thc electrical interconnection for a class of computer peliphera~s, i.e., PCMCIA penpheraLs. Generdlly, the size of aPCMCIA peripheral is approxirnately that of a "credi~ card." Each c~dit card size 10 PCM(~IA peripheral electrically intercormects ~ia a PCMC1A electrical connector to a "host computer," which is typically a "no~ebook" sizc personal computer (PC).
PCMCIA pe~ipheraLs like ITlemory, moderns, fax, hard disks. etc., arc cu~n~ly available.
Like their more conventional cousins, a PCMCIA modem is a comple:c lS piece of equipment that c~rnprises specialized r~ucroproccssor circuitry. Forexample, a PCMCIA modem typically includes a general-purpose microprocessor (CPU), memory, a teleph-~ne line interface lo the F'ublic Switched Telephone Network (PSTN), and a high-speed digital signal processor for proccssing ~he respective communications signal in bo~h Ihe transmit and r~ceive directions. The 20 functionality of the PCMC1A modern is provided by the CPU's execurion of a computer ~rogra~, i.e., the "operating prograrn," ~hat resides in the PCMCIA
modern's merr~ry~ This memory is usua]ly "flash memory," which is a non-volatilememory tha~ is field-progr~unmable by the modern's CPU.
An advantdge Qf the flash rl emory is that it a~lows field qpgradcs of the 2~ rf~odem's operating program for eitber pro~riding new fea1ures or "bug" fixes. In order to per~orm a field upgrade a part of the flash memory is reserved for a "boot block" computer prograr~L This part of the flash mem~ is write-protected so that i~
retains its data, i.e., the boot block, even ~4hen the rest of rhe flash memory is erased and reprogramrned. The boot block includes computer software fw booti~g-up the 30 modem, e.g., after application of power, and for loading the remainder of Ihe flash memory with the operaring prograrn.
A field Upgrd~le of the modem's flash nnemory is p~onTIed over one of the serial data pGrts, either the data communications port or the data terminal port.
First, the modem's CPU receives a cotr~mand to reload the operating program from a 35 "hos~" coupled to one of the seri~ ports. Then the modem's (~PU execu~es thatportion of the boot block associated with Inading the flash memory. This part of Lhe M::IY 16 ' 94 14 :57 PI~GE . 004 ,~
SENT sY 5-16-9~: 3:02P,U: MT l~-UW~ 613 237 0045;~ 5/23 21~3923 ! ~ , , - 2 -software first erases thc remaining portion of the flash mery and then reccives the new operating program via one of the serial ports and writes the new operating program to the flasb memor,v.
An altema~ive approach that does not requ~ a non-wlilable boot block 5 in the ~ash memory i5 provided by AT~T Paradyne's 3~no mo~em, which complises an independent "upper ban~" and "lower banlc" of flash momory. The modem's C*U can boot from either bank. The modcm's CPU b~gins operation by execu~ing the comput~r prograrn stored in one of the flash memory banks, i.e., Ihe ac~ive bank of fiash memoly. This computer Faogram includes the boot code and the ln operating program. When the modem's CPU receives a command from the hos~ to change thc operating progrsm via one of the serial ports, the modem's CPU executes a do~vnload program conrained in the activc bank of flash memory. This download software first erases the non-nctive bank of flash memoly and ~hen copies Ihe received d~ta ~om one o~ the serial data por~s into the non-ac~ive bank. This 15 received data is the new computer ~rograrn, which conta~ns new boot code a~d the new operating program. At the conclusion of this download mode, ~he modem's CPU toggles a non-volatile s vitch so that i~ will boot after a reset from Ihe newly updated bank of flash memary, i.e., it switches which bank of flash memory is the active bank. This approach is disclosed in the co-pending, coaunonly assigned 20 Unit~d States Patem application ~f Hechl et al. entitled "Apparatus and Method for Downloading ProErams," serial No. ~7188025~, filed on May 8, 1992.
As described abovc, Qlthough a flash memory upgrade for a PCMCIA
rnodcm vi~ one of the sc~rial por~s is an advantRgeous approach, there are several limitattons. One is that during manufacture the boot block must be programrned into 2.5 the Qash rnemory prior to soldering the flash memo~ onto Ihe printed circuil board.
This adds COSl tO the manufactu~ng process of the PCMCIA modetL In addition, if the boo~ block is somehow e~ased or colrupted and power to the PCMCIA modem is lost, there is no recovery mechanisrn other than remoYing and replacing the flash memory. F~hermore, the size of the boot block is fixed (typically 16~C bytes)7 30 vhich presents ConstrainLc on the functionality of the boot bloclc. In addition, Ihe boot block sin~larly cons~ains the size of the PCMCIA mode~ opera~ing prog~arn since a por~ion of the flash mernory is dedicated to the boot bloc~ Finally, the speed Or any field upgrade is limited because Qf the use of a serial data por~.
1`1~1Y 16 ' 94 14: 58 Pl:iGE . za5 SENT BY: 5-16-94 ; 3:02~1\1; MT IP-L~W~ 613 237 OOg5;# 6~23 -Surnm~t-y of th~ lnvention This invention eliminates all of thc abo~e-mentioned limitations by psoviding a method and apparatus for loading a llash memory afu~r it is a part of a complercd PCMCIA modern assembly. In accordancc with the principles of the 5 inventi~n, a PG~CIA peripheral incorporates a shared rnemory interface to a host computer via the PCMCL~ connector. This shared n~cmory provides the capability to easily load or ch~nge the computer prograrn of the PCMCIA peripheral from thehost computer without requiring either the a priori prescnce of a dedical~i bootblock in the flash tnernory or the usc of a serial data port.
1n In an ernbodiment of the invention, a PC~ rnodcm includes a CP~, mcmory, and a shared r~emory that is coupled to a personal computer (PC) via thePCMCIA conneclor. During r~mal operation, Lhe CPIJ accesses and executes any computcr program stored in the tnemory A field upgrade or ini~ial factory lo~d is p~rformed in the following rnanner. first, the PC applies a r~,set to the PCMCIAl!i modem. During ~his reset, the PC stores a control prograT~ in the shared memory.
After storing the conlrol program, thc PC aiters the memQry map Qf the PCMCIA
modem so that after the reset thc CPU executes the control program stored in thesha~i memory. T11is control program further provi~es the abiii~y to the PCMCIA
modem to ~ransfer a new computer program via the shared memory lo the mernory 20 of Ihe PCMCIA modem, i.e., thc control program is the boot bk~clc sofnvare. After transferring the new cornpuler prog}am, the PC a~ain initiatcs a resct of the PCMC:IA tnodem tha~ returns the memory map of the PCMCIA modem to no~mal ~uch that aft~ thc reSet the CPU executes the new computer program slored in thePCMCIA n~odem's mernory.
In accordance ~ith a feature of ~he invention, n~ither the field upgrade nor the initial program load in ~be factory rcquire any boot block soft~are to oe resident in the PCMCIA card.
Anothcr feature of the invention uses the shared mcmory interface to transfer user data from the personal computer, i.o., data telrninal, to the PCMCLA
30 modem. This results in a higb.cr data transfer rate than is currently avail ble via the on-board uni-rersal asynchronous receive/transmit (UART) in~egrated circuit thatcouples the r~m to any terrninal equipment.
Brief Description of the DrawinR
l;IG. I is a block dhgram of a portion of a PCM('~ modem embodying 3S the principles of the tnvention;
~ 1Y 16 ' 94 14: 56 P~GE . 006 SENT BY: 5-16-99: 3:02PM: MT I~ W~ 613 237 0045:~ 7/23 FIG. 2 is a table irnplelnent~i by chip enable rou1irlg logic lS0 of FIG.
FIG. 3 illustr~tes a PCMCIA peripheral map for host computer 200 of FIG. l;
S FIG. 4 is a flow dia~ram of a m~thod embodying the principles of the invention; arld E;IG. S is a flow diagram of a memory arbi~ration method pçrfon.ned by CPU 170 of PIG. 1.
Detniled Description FIG. 1 shows a portion of a PClUCIA rnodem that embodies the inventive concepts af this invention. ~s shown, host computer 200 includes PCMCIA slot 2~0 for receiving PCM(:~IA modem 100, host CPU 270. and reraov~blc storage unit 21~ for rec~iving floppy disk 216. PCMCIA modem 100 includes CPU 170, program memory 160, sharcd memory 130, chip enable routing logic 15n, control logic 140, and PCMCIA connector 120. CPU 17() is a microprocessor-based central processing unit which operates on, or executes, program data stored in program memory 160 ~r shsred mernory 130 (discussed below) via contr~l processor bus 175, which providcs control, addre~s and data sigll815 (not shown). PCMICIA modem 100 is physical1y and electrically coupled tl~
host computer 200 Yitl PCMCIA interface 10. The latter includes PCMC~A
cormector 120 af PCMCIA modem 100 and PCMCIA slot 220 of host computer 200.
For the pu~poses of this example, program memory 160 is a flash memory. Tbe pro~ram data storcd in pro~am mcrnory 160 is he~inafter ~eferred ~o as the operating computer program. l~Is operating computer program provides the modem 25 functionality f~r hansn~itting and re~iving da~a via a cornmunications facility (not shown).
It is ~ssurned that CPU 170 includes appropnate addrcss decode and chip enable logic. Two chip enable signals, CEl and C~2. ar~ provided by CPIJ 170 on lines 171 and 1?2, respectively. These chip enable signals are used to select~1) eilher prograrn memory 160 or shared memory 130. Normally, these chip enablesignals would bc coupled dircctly ~o lhcs~, memory deYices. Howe~er, in accn~Lance with Ihe principles of the invention, CEl and CE2 are applied tO chip enable routing logic lS0, which ,~rovides chip onablc signa~s to program memory 160 and shared memory 130 as a function of the rnode of operation of PCMClA modem 100. This 35 is sho~n in FIG. 2. For the purposes of this example it ie acsumed that there are two modes of operation: a "nonnal rnode" and a "download mode." During a nonnal M~Y 16 ' 94 14: 58 P~GE . 007 SENT BY: 5-16-9~: 3:03~M: MT l~-L~W~ 613 237 0045:# 8~23 mode, chip enable routing logic lS0 providos CEI to program memory lfi0, via linc 151; and provides CE2 to sha~cd memory 120, via line 152.
Af`tcr a CPU reset signal is applied ~o CPU 170 ~ria line 144, CPU 170 applies CEI to chip enable routing logic 150. As is known in the art, afte~
S application of a resel signal, a rnicro-processor starts execution a~ a known s~arting addrcss location. For the purposes of this example, it is assumcd that this ~ fined location is ma~ped to an ad~ss range associa~ed wi~h CEI. The CPU rese~ signal on Une 144 is provided by control logic l40 either as a result of RESET signal (not shown) defined in the PCMCIA interface being asserted, e.g., durirlg a power-up l0 condition; or as a result of a memory access by hosl CPU 270 (di~cussed below). In the normal rTlode of ~eration, as shown in FIG. 2, OEl is routed to program memory 160 so that CPU 170 execu~cs the opera~ng compuler program~ In this nor~n~l mode, CPU 170 accesses shared nlemory 130 by providing CE on linc 152 via chip enable routing logic 150.
Shared mcmory 130 is also known as a "dual por~ ram" and has two sels of addrcss, data, and control lines. One set is used to inlerface to PCMCTA bus 121 and tho other ser is used to intefface to control processor bus 175. In Accordancc with the principles of Ihe invendon, sh~ed ~erncry 130 is puI to different use depending on the mode of operation. As shown in ~IG. I, dunng tne nonnal modo 20 of operation, shared memory 130 comprises PCMCIA attribute rep,ion 135, whichincludes the software definable Card Infonn~tion Stn~cture, Pin Rep]acement Register, Configura~ion Option Regis~er, Card Configulation and Status Register in acc~lance with the PCMCIA interface standard. However, duIing th~ download mode of oporation (discussed below), shared rnemory 130 includes region 136, ~5 which is ~ buffcr that storcs d~ta received from host CPU 270 of host c~mputer 200;
and region 137, which stores a control program provided by hosr CPU 270 and subsequently sxecuted by CPU l70.
In ~ccordance wi~h the principles of the inveDdon, the other mode of operadon--the download mode--directs CPU 170 to begin execution of progr~n 3Q da~ from shared mernory 130 after tho applica~ion of a CPU reset signal on line 144.
In particular, in thc download mode of opera~ion, chi,~ enable routing logic 150swi~chcs thc CEI signal from lead I51 to lead 152, and conversely, switches the CE2 signal from lcad 152 ~o lead 151. As a rosult, CPU 170 now exe~utes instrucdons s~ored in sh~rcd memory 130 after exiting from a reset condition.
i1i:1Y 16 ' 94 1 4: 59 PFIGE . 008 , SENT BY: 5-16-94; 3:03~M; MT l~-UW~ 613 237 00~5;# 9/23 ~ .1 ?.~
Whether or no~ the down]oad mode of operation is en~ered by P~SCIA
modem 100 is under the control of host CPU 270. lt should be noted that under the PCIvlCIA standard, pornons, or all, of PCMCIA modem 100 is rnapped ~nto a part of the PC)~ClA peripheral space of host C~PU 270. An illustrative PCMCIA peripheralmap of PCMCIA 100 as viewed by host CPU 270 i~ shown in FIG. 3. An illustrative rnethod for usc in host CPU 270 for switching PCMC~A modem ]00 to the do~nload mode is shown in ~G. 4. Hos~ CPU 270 affec~s a reset of CPU 170 in step 405 by asser~in~ the REST signal of the PChlClA interface, or by writing aparacular data value ~o a particular memory location on PCMCIA modem 100 that is10 associat~d with resetting PCr~CIA modem ]00, i.e., a "reset location" as shown in ~IG. 3. In this example, ~his rescl location is within the shared memory region and during non~nal opc~rstion is associated with the Configuradon Opdon Register, wbich i~ a part of PCMCIA attnbute reg~on 13S as defined by Ihe PCMCL~ standard. Onc of thc defined dats bi~s of the Configuration Option Register is the "SRESET" bit.
15 CPU 270 affects a reset of PCMCIA moden~ 100 by serting the nSRESEr" bit, which is d7, equal to a logical one, Control lo~ic 140 of P~MCIA mods~m 100 detects this memory writo to the resc~ location aDd in response ~hereto generale~ a CPU rese~ ~gnal on line 144 ~o CPU 170.
While the CPU rcset signal is ac~e CPU 170 is inaClive, i.e., performs 20 no rnemory accesses. Host CPU 270 then wntes a con~rol program to shared memol~y region 137 in step 410. After stcp 410, hosl CPU 270 s~vitches the mode nf operarion of PCMClA modem 100 by accessing in a particular wuy a respective predefined memory location associatcd with Ihe download mo~o in step 415. In tbis exarnp1e, host CIPU 270 perfonns three consecutive w~itcs of a prodef~ncd data value 2~ ~o the do~,vnload mode location. Cont~ol logic 140 of PCMCJA modem 100 detects th~sc ~onsç~utive rne~nory accesses and compares the data vallles being wriuen by CPU 270 to the predefined data value. If ~he data values being wrilten cqual thepredefined data value, con~l logic 140 applies a control signal on line 142 to chip enable routing logic 150. The latter allers the routin~ of the ubove-mentioncd chip 30 enable signals as shown in FIG. 2 for thc download mo~. It is assumed that sleps 41n and 415 occur while thc abov~-mentioned reset si~nal on line 144 is still active.
In oth words, it is assumed that control logic 140 generdtes a CPU reset signal oF
sufficient wtdth to provid~ the t~rne for host CPU 270 to perfor~n steps 410 aud 415.
~f hos~ CPU 270 does not switch the mode of operation within the period of tir~e35 whon the CPU resel signal is active, control logic 140 blocks any subsequ~n~
attempts to sv.~itch modes and PCMCIA modern l(~ simply con~inues to rernain in PfiGE . 009 1`1~1Y I 6 ' 94 1 4: 59 SE~IT BY: 5-16-94; 3:03~M: MT lP-LAW~ 613 237 0045:#10/23 2~23923 the normal modc. In other words, control logic 140 provides a "lockoul mechanism"
that pre~ents inadverten~ switching of chip enables. This lockoor mechanism forces PC~I~L4. mode~n 100 to defau~t to thc nonnal mode af~er a CPU reset signal is applied unless host CPU 270 acccsses in ~he pr~scribed menner the download n~ie S location. Alternad~ely, to avoid this tirnc constr~unt on host CPU 270, ~he latter can ma~e use of thc SRESEr bit for ~urning on and of f the CPU reset signal.
In the d~wnload rnode and after removal of the CPU rese~ signal, (~PU
170 cxccutes the contTol program in shared rnemory 130. Host ~PU 270 then transfers data to shared rnemory region 136 in step 420. This data represenlS
~0 portions of the new cornputer prograra to be plnced into prog~n memory 160. lhc control program, when executed by CPU 170, transfers the data placed in sharcd memory region 136 by host C~PU 2.70 to program memory 160--thus cha~ging the operating computer pro~ram execu~ed by CPU 170 during the norrnal m~de of operation. rt should be noted ~hat no boot block soft vare is required to be residenl in lS the PCMaA peripheral othor than the temporary control program provided by hnst CPU 270 in order to accomplish this download, irrespective of wh ~her this download is a pan of a field upgrade a~ the initial program load in a factoIy. k is ~ssumcd that the control progrem ex~cuted by CPU ~70 includes a "hand-shakin~"
procedure for coonlina~ing the transr~r of data blocks from host CPU 270 to program ~emoty 160. Far example, after the data in shared mernory region 136 is ~rritten by CPU 170 to a portion of pro~arn memory 160, CPU 170 writes to a predefined "flag" location of shered mcmcry 130. This fla~ when read by host CPU 270, indicates to host CPU 270 to write the next p~i~n of the operating computer program to shared memory region 136.
Aftcr host (:PU 270 has finished downloading the new operating computer prograrn to PCMCLA 00d~m lO0, host CPU 270 again resets PCMCIA
modem 100 in step 425. With the applicatinn of the CPU reset signal, control logic 140 swi~ches PCMUA modem 100 back to the norrrlal mode as part of the lock-out rncchanism described above. As a result, control logic ~40 alters the routing of the 30 above^mentioned chip enable signals as shown in FIG. 2 for ~he norrnal mode. In the norrn~ ode and sfter r~moval af the CPU rc.cet signal, CPU 170 executes Ihe new operating computer program now s~ored in pro~m memoly 160.
As can be seen from the nbo~re description, when transferring data from the buffer locatcd within shared memo~y region 136 to program memory 1~0, both 35 CPl~ 170 and host CPU 270 are accessing shared memory 130. For exarnple, at the ssme tim~ CPU 170 is reading program dsta from shared memory region 137--host ~ 1Y 16 '94 1~:59 Pl:IGE.~3~Z
SE~T BY: 5~16-94; 3:0~N: MT l~-LAW~ 613 237 0045;#11/23 CPV may be atrernpdtlg to write dala to ~he buffer locdted within shared rriemory region 136. As a result, a memory ContenLion scherne is required to arbitrate bet~,veen C~U 170 and host CPU 270 when they atTempt to access shared m~
] 30 simul~aneously In this exarnple, the mernory contention schcme is implemented by a cornbination of hardv~are, represented by control k~gic 140, a softwsre prolocol. and the P~ICIA defined WArr si~nal on line 142. Altbough shown as ~ separate signal for convenience, it should be realized that uhe WAlT signal on liDe 142 is a subset of PCMClA bus 121.
Control logic 140 monitors PCMCT~ bu~ 121 to detect any shared n~emory accesses by host CPU 270. When hos~ CPII 270 be~ins a shared memory access tn PCMCIA modem 100, control logic 140 activates the host accoss .signal on line 141, l,vhich i5 received by CPU 170. ln addition, CPU 170 provides a wait enable signal on line 173, which is received by control unit 140. rf Ihe wait enab]e 1~ ~signal is active, control unit 140 enables the generation of the WArr signal on line 142 in response to any subsequent shared memory access by host CPU 2?0. As is l~nown in the art, when the PCMCLA WAIT signal on line 142 is active, bosl CPU
270 inserts wait sta~es in the currerlt memory access. Convcrsely, if the wait enab]e signal is inactivc, control unit 140 disables the generation of this WAlT signal so 20 that no addilionsl wait s~atcs are inse~ed into a shared mem~y access of host CP~J
270. It should be noted that the PCMCIA specificstion requires th~t accosses by host computer 270 via PC~MCIA connector 120 be complcted u,ith no more than a l2 microsccond delay.
FJG. S shows a flow diagranl for a method used by CPU 170 for 25 irnplementing a soft vare protocol to contro1 the generation of the wai~ ensb1e signal on lino 173. Whenever (~PU 170 ~ccesses sharcd mernory, CPU 170 firsl activates ~he wait enable signal on line 173 in step 505. CPI.7 170 then reads, or samples, ~he host acce6s si~nal on line 141 in step 51(1. rhis allows (~IJ 170 to checl~ if hclst CPU 270 has already beglln an access to shared memory. ~f Ihe host ~ccess signal is 30 acive, thcn the wait enablc signal on lille 173 is disabled and CPV 170 itself waits for a predcterrnined peri~7d of timc, T, in step 515 befo~ returning to s~p 505. Thc latter step is important bccause host CPU 270 may ignore ~he WATT signal on line141 if it was enabled after the wait recognition window of hosl CPU 270. This may uccur bcc~usc of the asynchronous relationship of any sh ned mernory accesses by35 ~he two processors. However, if dle host access signlll is ir~ , CPU 170 accesses sharcd mcrLory in step 520 and then disablcs the wai~ enable signal on line 173 in PRGE . 01 !
1~1RY 16 '94 15:00 SENT BY: 5-16-94: 3:04~M ~ UW~ 613 237 00~5;~12'23 2~23~23 step 530.
As described above and in accordance with the princip1es of the invention, host CPU 270 is able to change the operatin~ compulcr program stored in PCMCIA modem lOO and thereby provide an easy rneans to update or charlge the S funcsionality of PCMCTA modem 100. As shown in E~IG. 1, the program data execul~d by PCMC~ modern lOO can be provid~d to hosl CPU 270 via floppy disk 2l6. Indecd, any type of progrdlDs for PCM(~L~ modem lOO can be easily provided.For example, 90ppy dislc 216 can supply a dia~nostic testing pro~ram. which ~hendownloaded by hoss CPU 270 allows PCMCIA modem lOO ~o perform a series of 10 diagnostic tesss.
In addision. Ihe use of shared mem~ry 130 in PCMCIA modem lOO also provides other improvements ~o systern opcra~ion. For example, since ~he PCMCIA
peripheral is B modem, hos~ compu~r 200 is a data terminal. As is known in the art, hosr CPU 270 sransfers data for tsansrnission over a data cornmLnications chflnnel 15 (not shown) by wriring data in psrallel to a UART (not shown) of PC~ICI~ modem 100. This UART then conYcrts ~he data to a serial form tn sirnulate Ihe serial data transmission from the data tennin~l. Consequently, the PCMCIA modem again converts thc serial data strearn from its UART back ~o a pa~allel forrn agflin.
Unfonunate~y, ~his prl~cess t~nds ~o limi~ Ihe speed oî any dnsa tr~nsfcr. However, in 20 accordance with the in~ention, sha~ed memory 130 can be used to transfer user data betweèn the data terminal and the modem at a a higher data transfer rate. lhis is accornplishod by dedicating a portion of sha~d memory ~?sO as a buffer for dir~c~ly transf~rin~ dasa from host c~rnputer 200 to PCMCL~ rnodom lOO.
In addition, in th~ prior an, the PCMCI~ a~ribu~ s :ructure is typically 25 p~e-defincd and non-changeable, e.g., a read-only memory (ROM) is used to provide the PCMUA a~tribute structure. However, the use of shared memory 130 allows for a software definable PCMCIA card infom~ation structure ~hat can be dyn~rrucally altercd by CPU 170.
The forcgoing merely illust~ates the principles of the invention and il 30 will thus be appreciated thst tho~se sldll~d in ~he art will be able to devise numerous ~l~ernative a~angements which, although not explicitly described herein, embody the principles of the invention and are within its spirit and scope.
For example, slthough the i~ventive conccpt was desctibed in ~erms of utilizing flash rnemory, any non-vola~ile programmable RAM can be us~ In fact, 35 even volatile RA~I can ~e used as long às the PCMCIA peripheraI is pr~perly initialized by the host corDputer on power-up of the system.
t~1RY 16 '94 15:00 PRGE.012
Claims (9)
1. A PCMCIA peripheral coupled to a host computer by a PCMCIA
connector, the PCMCIA peripheral comprising:
memory means for receiving a number of instructions provided by the host computer via the PCMCIA connector; and processor means; and control means responsive to the host computer for generating at least one control signal to reset the processor means, and for controlling the processor means in such a way that the processor means accesses the memory means to execute the number of instructions.
connector, the PCMCIA peripheral comprising:
memory means for receiving a number of instructions provided by the host computer via the PCMCIA connector; and processor means; and control means responsive to the host computer for generating at least one control signal to reset the processor means, and for controlling the processor means in such a way that the processor means accesses the memory means to execute the number of instructions.
2. The apparatus of claim 1 wherein the control means includes:
control logic means responsive lo the host computer for generating the at least one control signal and for providing an address control signal; and address switching means responsive to the address control signal for causing the processor means to access the memory means to execute the number of instructions.
control logic means responsive lo the host computer for generating the at least one control signal and for providing an address control signal; and address switching means responsive to the address control signal for causing the processor means to access the memory means to execute the number of instructions.
3. Apparatus comprising:
a PCMCIA connector;
processor means responsive to a reset signal for providing a starting address for accessing a memory location to execute at least one instruction stored therein;
first memory means;
second memory means; and control means responsive to at least one control signal received from the PCMCIA connector for a:) providing the reset signal to the processor means, and b) switching between a first and second mode of operation;
where in the first mode of operation, the control means alters the starting address provided by the processor means in such a way that the memory location is located within the first memory means, and in the second mode of operation, the control means alters the starting address provided by the processor means in such a that the memory location is located within the second memory means.
a PCMCIA connector;
processor means responsive to a reset signal for providing a starting address for accessing a memory location to execute at least one instruction stored therein;
first memory means;
second memory means; and control means responsive to at least one control signal received from the PCMCIA connector for a:) providing the reset signal to the processor means, and b) switching between a first and second mode of operation;
where in the first mode of operation, the control means alters the starting address provided by the processor means in such a way that the memory location is located within the first memory means, and in the second mode of operation, the control means alters the starting address provided by the processor means in such a that the memory location is located within the second memory means.
4. The apparatus of claim 3 wherein the second memory means is shared memory between the processor means and a host computer coupled to the shared memory by the PCMCIA connector.
5. The apparatus of claim 4 wherein the at least one control signal is at least one memory access by the host computer to the second memory means via the PCMCIA connector.
6. A method for use is a PCMCIA peripheral for modifying a computer program executed by the PCMCIA peripheral comprising the steps of:
coupling to a host computer via a PCMCIA connector;
receiving a reset signal from the host computer via the PCMCIA
connector;
receiving data from the host computer via the PCMCIA connector for storage in a memory device of the PCMCIA peripheral, where the data represents aplurality of instructions;
generating a control signal in response to a memory access from the host computer via the PCMCIA connector; and responsive to the control signal, accessing the memory device to retrieve the data in such a way that a central processing unit of the PCMCIA peripheral executes the plurality of instructions;
where the memory device is shared between the central processing unit of the PCMCIA peripheral and the host computer.
coupling to a host computer via a PCMCIA connector;
receiving a reset signal from the host computer via the PCMCIA
connector;
receiving data from the host computer via the PCMCIA connector for storage in a memory device of the PCMCIA peripheral, where the data represents aplurality of instructions;
generating a control signal in response to a memory access from the host computer via the PCMCIA connector; and responsive to the control signal, accessing the memory device to retrieve the data in such a way that a central processing unit of the PCMCIA peripheral executes the plurality of instructions;
where the memory device is shared between the central processing unit of the PCMCIA peripheral and the host computer.
7. The method of claim 10 wherein the generating stop occurs while the reset signal is still active.
8. The method of claim 10 wherein the reset signal is a memory access by the host computer to a predefined memory location in the PCMCIA peripheral.
9. A method for accessing a PCMCIA peripheral comprising the steps of:
coupling the the PCMCIA peripheral via a PCMCIA connector;
providing a reset signal to the PCMCIA peripheral via the PCMCIA
connector;
moving data via the PCMCIA connector to a storage location located within the PCMCIA peripheral, the data representing a plurality of instructions; and accessing a memory location of the PCMCIA peripheral via the PCMCIA connector to cause a central processing unit of the PCMCIA peripheral to access the storage location in such a way that the central processing unit executes the plurality of instructions.
coupling the the PCMCIA peripheral via a PCMCIA connector;
providing a reset signal to the PCMCIA peripheral via the PCMCIA
connector;
moving data via the PCMCIA connector to a storage location located within the PCMCIA peripheral, the data representing a plurality of instructions; and accessing a memory location of the PCMCIA peripheral via the PCMCIA connector to cause a central processing unit of the PCMCIA peripheral to access the storage location in such a way that the central processing unit executes the plurality of instructions.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US064,304 | 1993-05-20 | ||
| US08/064,304 US5537654A (en) | 1993-05-20 | 1993-05-20 | System for PCMCIA peripheral to execute instructions from shared memory where the system reset signal causes switching between modes of operation by alerting the starting address |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2123923A1 true CA2123923A1 (en) | 1994-11-21 |
Family
ID=22055011
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002123923A Abandoned CA2123923A1 (en) | 1993-05-20 | 1994-05-19 | Pcmcia interface using shared memory |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5537654A (en) |
| EP (1) | EP0628908A1 (en) |
| JP (2) | JPH06348638A (en) |
| CA (1) | CA2123923A1 (en) |
Families Citing this family (45)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0728772A (en) * | 1993-06-25 | 1995-01-31 | Hitachi Ltd | Microcomputer |
| US6163793A (en) * | 1994-08-05 | 2000-12-19 | Intel Corporation | Method and apparatus for using a driver program executing on a host processor to control the execution of code on an auxiliary processor |
| US5848247A (en) | 1994-09-13 | 1998-12-08 | Hitachi, Ltd. | Microprocessor having PC card interface |
| US5802558A (en) * | 1994-09-30 | 1998-09-01 | Intel Corporation | Method and apparatus for upgrading reprogrammable memory contents in a PCMCIA card |
| US5664198A (en) * | 1994-10-26 | 1997-09-02 | Intel Corporation | High speed access to PC card memory using interrupts |
| DE19503312A1 (en) * | 1995-02-02 | 1996-08-08 | Sel Alcatel Ag | Method and circuit arrangement for loading computers with a computer start program |
| WO1996038784A1 (en) * | 1995-06-02 | 1996-12-05 | Systemsoft Corporation | Digital data processing method and apparatus for peripheral device control |
| US5892972A (en) * | 1995-06-07 | 1999-04-06 | Cirrus Logic, Inc. | Method of constructing a plug and play compatible bus card which allows for mass production of the bus card |
| WO1997006490A1 (en) * | 1995-08-09 | 1997-02-20 | Cirrus Logic, Inc. | Parasitic personal computer interface |
| FR2738367B1 (en) * | 1995-09-05 | 1997-10-17 | Scm Microsystems | METHOD AND APPARATUS FOR FAST DOWNLOADING OF FUNCTIONS IN A VOLATILE MEMORY |
| US5790849A (en) * | 1995-12-22 | 1998-08-04 | Intel Corporation | Method and apparatus to permit the boot of a shared memory buffer architecture employing an arbitrary operating system |
| JPH09247283A (en) * | 1996-03-05 | 1997-09-19 | Mitsubishi Electric Corp | Modem device and communication system |
| KR0174484B1 (en) * | 1996-03-13 | 1999-04-01 | 김광호 | Reset device for modem with fast mode switching function |
| DE69610297T2 (en) * | 1996-07-05 | 2001-01-18 | Hewlett Packard Co | Control device behavior when physical means are removed |
| US5898869A (en) * | 1996-09-20 | 1999-04-27 | The Foxboro Company | Method and system for PCMCIA card boot from dual-ported memory |
| US6275911B1 (en) * | 1996-09-20 | 2001-08-14 | Denso Corporation | Memory writing device for an electronic device |
| US6148347A (en) * | 1996-11-20 | 2000-11-14 | Cisco Technology, Inc. | Mode selectable memory controller for PCMCIA standard memory cards and non-standard memory cards |
| KR100247951B1 (en) * | 1997-04-11 | 2000-03-15 | 윤종용 | Program modification method of PDA |
| US6789212B1 (en) | 1997-04-24 | 2004-09-07 | Edwin E. Klingman | Basic cell for N-dimensional self-healing arrays |
| US6219736B1 (en) | 1997-04-24 | 2001-04-17 | Edwin E. Klingman | Universal serial bus (USB) RAM architecture for use with microcomputers via an interface optimized for integrated services device network (ISDN) |
| US5860021A (en) * | 1997-04-24 | 1999-01-12 | Klingman; Edwin E. | Single chip microcontroller having down-loadable memory organization supporting "shadow" personality, optimized for bi-directional data transfers over a communication channel |
| GB9713094D0 (en) * | 1997-06-21 | 1997-08-27 | Philips Electronics Nv | Optical disc drive |
| US5978862A (en) * | 1997-08-08 | 1999-11-02 | Toshiba America Information Systems, Inc. | PCMCIA card dynamically configured in first mode to program FPGA controlling application specific circuit and in second mode to operate as an I/O device |
| US6459942B1 (en) * | 1997-09-30 | 2002-10-01 | Compaq Information Technologies Group, L.P. | Acoustic coupling compensation for a speakerphone of a system |
| FI112301B (en) | 1997-12-01 | 2003-11-14 | Nokia Corp | Extension short |
| GB2339044B (en) * | 1998-03-02 | 2003-06-04 | Lexar Media Inc | Flash memory card with enhanced operating mode detection and user-friendly interfacing system |
| US6078973A (en) * | 1998-03-31 | 2000-06-20 | Micron Electronics, Inc. | System controller interfacing a main memory and a modem and transferring data directly between dedicated region of the memory and the modem I/O circuitry |
| US6134609A (en) * | 1998-03-31 | 2000-10-17 | Micron Electronics, Inc. | Method for using computer system memory as a modem data buffer by transferring modem I/O data directly to system controller and transferring corresponding system controller data directly to main memory |
| US7043568B1 (en) | 1998-11-12 | 2006-05-09 | Klingman Edwin E | Configuration selection for USB device controller |
| SE9900887L (en) * | 1999-03-12 | 2000-09-13 | Business Security | encryption device |
| TW452727B (en) * | 1999-03-29 | 2001-09-01 | Winbond Electronics Corp | Micro-computer system and method for using reset to set different working modes |
| US6438737B1 (en) | 2000-02-15 | 2002-08-20 | Intel Corporation | Reconfigurable logic for a computer |
| KR20010096764A (en) * | 2000-04-14 | 2001-11-08 | 찬 주 박 | Shopping cart having bar code scanner |
| US6745268B1 (en) * | 2000-08-11 | 2004-06-01 | Micron Technology, Lnc. | Capacitive multidrop bus compensation |
| US6886049B2 (en) * | 2001-01-16 | 2005-04-26 | Sierra Wireless, Inc. | Multi-function interface for connectivity between a communication device and a host |
| CN1122281C (en) * | 2001-06-30 | 2003-09-24 | 深圳市朗科科技有限公司 | Multifunctional semiconductor storage device |
| US6918062B2 (en) * | 2001-09-28 | 2005-07-12 | Intel Corporation | System and method to implement a cost-effective remote system management mechanism using a serial communication controller and interrupts |
| US7502817B2 (en) * | 2001-10-26 | 2009-03-10 | Qualcomm Incorporated | Method and apparatus for partitioning memory in a telecommunication device |
| US6792478B2 (en) | 2002-03-29 | 2004-09-14 | Intel Corporation | System and method to configure input/output (IO) devices to use selected pairs of port addresses |
| US6898651B2 (en) * | 2002-05-10 | 2005-05-24 | Intel Corporation | Method, apparatus, and system for generating serial interrupt requests (IRQ) with power savings |
| GB2394323B (en) * | 2002-10-14 | 2004-09-22 | Elan Digital Systems Ltd | High-throughput uart interfaces |
| WO2006054241A2 (en) * | 2004-11-19 | 2006-05-26 | Koninklijke Philips Electronics, N.V. | Avoiding tv menu negotiation to preset configuration options |
| US20060146842A1 (en) * | 2005-01-05 | 2006-07-06 | Silicon Laboratories Inc. | Programmable transmit wave shaping for 10 BASE-T ethernet controller |
| CN102236571B (en) * | 2011-07-27 | 2013-10-09 | 华为终端有限公司 | Data card upgrading method, personal computer and data card |
| CN109976488B (en) * | 2019-03-15 | 2023-04-14 | 西北工业大学 | Unmanned aerial vehicle machine carries computer software automatic re-setting circuit with programming function |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4156907A (en) * | 1977-03-02 | 1979-05-29 | Burroughs Corporation | Data communications subsystem |
| US4459662A (en) * | 1980-09-29 | 1984-07-10 | Texas Instruments Incorporated | Microcomputer having ROM mass memory for downloading main RAM memory with microcomputer instructions |
| US4519032A (en) * | 1982-06-09 | 1985-05-21 | At&T Bell Laboratories | Memory management arrangement for microprocessor systems |
| US4611202A (en) * | 1983-10-18 | 1986-09-09 | Digital Equipment Corporation | Split screen smooth scrolling arrangement |
| US4825358A (en) * | 1985-04-10 | 1989-04-25 | Microsoft Corporation | Method and operating system for executing programs in a multi-mode microprocessor |
| JPS6225353A (en) * | 1985-07-26 | 1987-02-03 | Hitachi Ltd | Microprogram loading system |
| DE3639571A1 (en) * | 1986-11-20 | 1988-06-01 | Standard Elektrik Lorenz Ag | METHOD AND CIRCUIT ARRANGEMENT FOR CHARGING A SECONDARY COMPUTER |
| US4809269A (en) * | 1987-04-02 | 1989-02-28 | Advanced Micro Devices, Inc. | Dual-port timing controller |
| US5195130A (en) * | 1988-05-05 | 1993-03-16 | Transaction Technology, Inc. | Computer and telephone apparatus with user friendly computer interface and enhanced integrity features |
| US5353432A (en) * | 1988-09-09 | 1994-10-04 | Compaq Computer Corporation | Interactive method for configuration of computer system and circuit boards with user specification of system resources and computer resolution of resource conflicts |
| EP0464433A3 (en) * | 1990-06-29 | 1994-05-18 | Nat Semiconductor Corp | Microcontroller device having remotely programmable eprom & method of programming |
| US5321828A (en) * | 1991-06-07 | 1994-06-14 | Step Engineering | High speed microcomputer in-circuit emulator |
| US5473775A (en) * | 1991-10-11 | 1995-12-05 | Kabushiki Kaisha Toshiba | Personal computer using flash memory as BIOS-ROM |
| US5319751A (en) * | 1991-12-27 | 1994-06-07 | Intel Corporation | Device driver configuration in a computer system |
-
1993
- 1993-05-20 US US08/064,304 patent/US5537654A/en not_active Expired - Fee Related
-
1994
- 1994-05-18 EP EP94303539A patent/EP0628908A1/en not_active Withdrawn
- 1994-05-19 CA CA002123923A patent/CA2123923A1/en not_active Abandoned
- 1994-05-19 JP JP6128004A patent/JPH06348638A/en active Pending
- 1994-05-24 JP JP11000194A patent/JPH0789441A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0789441A (en) | 1995-04-04 |
| US5537654A (en) | 1996-07-16 |
| JPH06348638A (en) | 1994-12-22 |
| EP0628908A1 (en) | 1994-12-14 |
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Legal Events
| Date | Code | Title | Description |
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| EEER | Examination request | ||
| FZDE | Dead |