CA2124464C - Motion video encoding/decoding method, apparatus and storage medium therefor - Google Patents

Abstract

Direct current component coefficients resulting from an orthogonal transformation of a video signal are encoded with a precision, expressed in terms of quantization bits, which may be varied at each video sequence, group of pictures, picture, slice, macroblock or block portion of the video signal in accordance with a required picture quality. The encoded coefficients may be decoded in accordance with the precision used during encoding.

Description

1~~ 94/~8427 ~f ~ y~ ~~ ~ PCT/JP93/01381 y DESCRIPTION
MOTION ~/IDEO ENCODING/DECODING METHOD, APPARATUS AND STORAGE MEDIUM THEREFOR
TECHNICAL FIELD
The present invention relates to video signal encoding and decoding; and, more partiGUlarly, is directed to high precision encodi ng and decodi ng of orthogonal l y transformed coeffi ci ants with efficient compression:
BACKGROUND ART ' Recently, orthogonal transformation techniques have been used to encode a video signal. One such orthogonal transformation is a discrete cosine transformation (DCT). In a two-dimensional DCT; pictures or images represented in the video signal ark dividbd into blocks having a predetermined pixel count; and then each bl~ck is orthogonally transformed into a block of c~efficients.
~°ig. '1 shows a two-dimensional block of DCT cbefficients corresponding to bra image block of g pixels x ~ lines. The coefficient F(0,0) c~rresponds to a direct-c~rrrent component representing an average luminance value of the two-dimensional blocky Row coefficients such as F(1,0), F(2,0) ... F(6,0), F(?,0), w~ ~~~oga2~ p~.-ria~~ioi3si ,~....~;
,l~~~c~t~3v~ 2 t, and similarly .F(1,1), F(2,1) ... F(6,1), F(7,1), represent high-frequency components in the vertical direction of the two-dimensional block. Column coefficients such as F(0,1), F(0,2) ... F(0,6), F(0;7), and similarly F(1,1), F(1,2) ...
F(1,6), F(1,7), represent high-frequency components in the ' horizontal direction of the two-dimensional block.
The DCT encoding 'technique utilizes the two-dimensional correlation within an image 'to concentrate encoded signal power around a specific frequency component. The amount of information needed to represent the image can be compressed si gnif l cantl y l f only coefficients distributed in this concentration are encoded.
For example; in the case. of a flat picture, its blocks exhibit good autocorrelation; that is; amplitude levels of the pixels in the block areaimost equal to each other. Therefare, DCT coefficients cdrrespondi~g to the low-frequency components in the' block; such as F(0;0); F(1,0), F(0,'1), F(1,1), have large values. whi 1a most of the tither coefficients have very low or zero values. Accordingly, Huffman enc~ding, which compacts series of contiguous identical coeffiicients; significantly compresses the am~unt...o~f 'information needed to represent: the image.
A standard for encoding video signals with motion, popularly known as MPEG1, has been' defined by ISO-IECrJTCI/SC2/WG11. In the:MPEG1 technique; a picture is either an "intra picture", meaning that it is encoded as a standalone picture, or an "inter picture", meaning that it is predictively encoded relative to at Vt~~ 94/086127 _ ~ ~ ~ ~ ~ _ FCT/JP93/g1381 '~i least one other picture.
The structure used for representing a video signal in MPEG1 format will now be explained with reference to Fig. 2.
As shown in Fig. 2, a block layer comprises luminance and chrominance blocks having 8 lines x 8 pixels.
A macroblock layer comprises the luminance and chrominance blocks grouped into macroblocks (MB), that is, four luminance blocks Y0, Y'1, Y2, Y3, and two chrominance blocks Cb and Cr; at the same spatial position of a picture as the luminance blocks.
The six blocks in each macroblock are transmitted in the following sequence: YO, Y1 ; Y2, Y3, Cb, Cr: Decisions as to what p red 1 ct 1 oe~ data 1 s to be- used and whethe r o r not a p red 1 ct 1 on error is to be transmitted are made for each of these block wits:
A dice c~mprises a single macroblock or a plurality of macroblocks appearing in'the scanning direction of the picture.
At the '~e~d of a slice; differential values of direct-current component coefficients and motion vectors in the picture are reset. The first macr~bl~ck includes data indicating a position in he picture so as to allow for recovery in the event of an error: Accordingly; a slice can have any arbitrary length and start position which can be changed if an error occurs during transmission.
picture layer comprises frames or fields of an image. A
picture includes at least one slice. Each picture is an I (intra W~ 94!08427 ~., ~ ,~~, ,~, ~~ ~~ ~~~ PC'TlfP93lOI381 ", ~ LT.

field), P (predictive), B (bidirectional) or D picture, depending on the technique used to encode it. An I picture is encoded reiative to itself, that is, without motion compensation relative .
to a previously encoded picture. A P picture is encoded with forward-prediction relative to a p.reviously.~-encoded I or P
picture which temporally precedes the P picture being encoded.
A B picture is encoded with bidirectional-prediction relative to two previously encoded I or P pictures, which temporally precede and succeed the B Picture.
A group of pictures (GOP) layer includes at least one I
picture, and may also have at least one non-T picture.
A video sdquence layer includes at least one GOP.
The MPEG1 standard defines different techniques for encoding the direct-current (DC) and alternating-current (AC) component coefficients of a tw~-dimensional DCT coefficient block.
Representative MPEG1 techniques for encoding and decoding two-dimensional DCT DC component, coefficients in an intra picture encoding process wild no~v be described.
Fig. ~A shows 'an encoding apparatus compr-osing. a DCT ci rcuit ~.'~w qd~ntizer 3, a differentiator 4 and a variable length coding .
(Vi~C) ca rcuit 5. ~n input picture 1 is suppl ied to a DCT ci rcuit 2'a,s bl0~ks of 8 pixels x 8 lines. The DCT circuit 2 is adapted to orthogonally transform each block of 8 pixels x 8 lines into a Mock of DCT coefficients (e!) which is applied to a quantizer 3 that linearly quantizes the DC component coefficient of each W~ 94/08427 PClI.'JP93101381 ~s s f .~ ~ ,-:
F ~ . "n ~ . v h.1 ~~.A~Q V
block using a predetermined quantization step width having, in the case of MPEGi, a value of ~ to produce quantized DC component coefficients (e2). In the linear-quantizati on process, fractions of 0.5 and over are rounded up, while fractions less than 0.5 are disregarded. ,'_-The quantized DC component coefficients (e2) are supplied to a differentiator :4 which is adapted to differentiate blocks adjacent to each other, using different techniques for a luminance (Y) block and corresponding two chrominance (Cb and Cr) blacks, to produce differentiated coefficients (e3).
Ei~. 4A shows a block diagram of the differentiator 4. An input applied to a delay and a subtractor. The subtractor subtracts the delayed input from the current input and outputs the r~sult as a different'ated signal.
Fig: SA shows' a differentiation technique for luminance blocks: A DC component coefficient of a luminance block is diffe~~entiated fr~m direct-current component coefficients of right, left, upper and 'lower adjacent blocks in a zigzag order ans9 'the differentiated result r replaces the DC component co~fficiant in the respective luminance coefficient blocks.
Figs SB shows a differehtiation technique for chrominance blockse DC component coefficients of right and left blocks adjacent to each other ire differentiated and the result replaces the original DC component coefficient in the respective chrominance coefficient blocks.

i~V~ l4/tl84B7 '~ ~ ~ ~ ~ PGT/JP93/013$1 s Since a first block, that is, a first block of an I picture or a first block of a slice, cannot be differentiated, a p redete rmi ned numbs r l s used as an l ni ti al val ue l n the de 1 ay .
element of the differentiator 4. In the case of the MPEG1 standard, a val ue of 128 l s used as the l ni ti al.._..val ue .
The differentiated coefficients (e3) are applied to a VLC
c l rcui t 5 of Fi g : 3A whi ch f uncti ons to encode the coeff l c l ents using a variable length code to produce an encoded video signal ts), The VLC circuit 5 uses the differential DC component coefficient value to obtain a corresponding size value, that is, number of bits that will be used to encode the differential DC
component coefficient, from a table shown as Fig. 6A. For example, a differential DC c~mponent coefficient (e3) with a value of +5 corresponds to a size of 3 bits.
Next, the VLC-circuit 5 encodes the size value using; for luminance blocks, a table shown. as Fig. 68, and for chrominance blocks; a able shown as Fig. 6C. Continuing with the exempla, a size of 3 bits is encoded as 1~1, for a luminance block, or >>0, for a chromin~nce:.:b~obk. . , Then, the VAC c;ircuit 5. encodes the differential DC
component coeff l ci ent usi ng a f l xed-~1 ength- code f rom the tabl a shown l n Fi g . 6A. The f l xed 1 ength code has a unique code val ue for each unencoded value. In the examp'1a, a differential DC
component coefficient (e3) with a value o. +5 corresponds to a ,. .. :.. ..
.~

W~ ~41Q8427 PGT/.DP93/01381 fixed-length encoded value of 101.
Finally, the encoded differential DC component coefficient value is the result of concatenating the variable-length code representing the number of bits that are used to represent the differential DC component coefficient and the,f_ixed-length code representing the differential DC component coefficient. In the example, for a luminance block, the encoded differential DC
component coefficient value is 101101; and for a chrominance block, the encoded value is 110101.
Fig. 3B shows'-a decoding apparatus comprising a variable length decoding circuit 8; an inverse differentiator 9, an inverse quantizer 10 and an inverse DCT circuit 11. These elements operate in a complementary manner to the corresponding elements sh~wn in Fig. 2A. Fig. 4D shows a block diagram of the inverse differ~ntiator g:
A pr~bTem with the encoding tables defined in the MPEG1 standard is that they do not necessarily cover all coefficient values:
To. be more specifica~ io the ~ne-dimensiohal DCT processing, an- output resulting from the DCT processing 'is about 2.~2 times the value prior to 'the processing. In an intra pict~rre encoding process using the MPEG1 technique, a pixel value of an input pic~Cure is in the range 0 to 25~ or a number comprising 8 bits.
Accordingly the Bisect-current component coefficient ~of a two-dimensional DCT transformation coefi=icient is in the range VV~ 94/g8427 PCT/3P93!~1381 0 to 2047 or a number comprising ~1 bits. The range 0 to 2047 is approximately 8 ~= 2~2 ~ 2~2) times the range 0 to 255.
In the MPEG1 technique, a value with this 11-lit precision ~
always undergoes a linear quantization process for transformation i nto an 8-bi t numbs r i n the range 0 to 255 , thus reduc i ng i is precision to. S bits, and is then differentiated. Accordingly, the table shown as Fig. 6A provides numbers in the range -255 to +255. That is, a fixed encoding precision of 8 bits for DCT DC
component coefficients reduces the quality of a high grade picture encoded with the MPEG1 technique.
Fir an input picture having an eight-bit precision, simply enhancing the encoding precision of the DGT DC component c~e~ficients from the conventional eight bits to a higher precision such as elevdn bits results in inefficient encoding in some cases. To be more specific, if an encoding technique with a precision of, for example, eleven bits, is applied to a poor-gradation picture-quality requirement which can be satisfied adqquate7y using an eigi~t-bit precision, unnecessary codes are i nev i ~ab'I y output .
Thus known encoding techniques for a highquality video signal either degrade the pictuc~e or result in inefficient compression of the encoded picture.
DISCLOSURE OF INVENTION
Therefore, an object of the present invention is to provide Vl~fl 94J08427 PGT/JP93/01381 a method and apparatus far encoding and decoding a video signal which avoids the aforementioned disadvantages of the prior art.
Another object of the present invention is to encode the direct current component coefficients representing a video signal wi th' a large r numbs r of bi is than the numbs r , 'af bi is used to represent each pixel in the video signal.
Still another object of the present invention is to adapt the encoding and deeding precision of the DC component coefficients mf a picture to a required quality.
Yet anot6~er object of the present invention is to variable length encode and decode tire DC component coefficients of a picture using tables each having a length that depends on the required encoding and decoding precision, respectively.
In accordance with an aspect of the present invention, an encoding method for a video signal comprises the steps of receiving a picture quality signal and selecting an encoding precision in accordance wi h the picture quality signal. 'the video signal is ~ orthogor~ally transformed to produce di rect current, comp~nent coefficients; and the direct current component coefficients are quantized using the selected encoding precision.
'the picture quality ,signal corresponds to a video sequence, group of pictures; !picture; slice; macrob7ock or block portion ~,f the vi deo s i final .
The quantized direct current component coefficients are variable length encoded using variable length coding tables which WO 94/0842? PCT/JP93/~1381 sa ~ A
~
.;.
~, ~ ~ 1o ~~

each have a 1 engththat i s a functi on of the sel acted encodi ng precision. Thus, the ranges of the tables can be dynamically adapted the enco ding precision requi red the portion of the .
to for video signal being encoded.
In accordance with another aspect of the present invention, a decoding method for an encoded video signal comprises the steps of receiving a picture quality signal and selecting a decoding precision in accordance with the picture quality signal. Encoded direct current component coefficients are extracted from the encoded video signal and aye inverse quantized using the selected decoding precision The picture quality signal corresponds to a video sequence, group of piGtu~es, picture, slice, macroblock or block portion of the encoded video signal.
The encoded direct current componeni; coefficients are vari ab1 a l ength decoded usi ng va~i abl a 1 ength codi ng tabl es whi ch each have a 1~ngth that is a f unction of the selected encoding pwecision:
Since: he picture quality signal can be placed in the encoded video signal, the encoding and decoding precision used.
for direct current component coefficients can be changed together:
The above, and other objects, features and advantages of the present invention will be apparent in the following detailed descr=iption of the preferred embodiments of the present invention W~ 94/138427 PCf/JF93/01381 S~ R t7 _. _, _ ::

when read i n con juncti on wi th the accompanyi ng drawi ngs i n whi ch corresponding parts are identified by the same reference numeral .
BRIEF DESCRIPTION OF DRAWINGS
Fig. 1 is a diagram used for explainir~'g_.. properties of two-dimensional DCT coefficients.
Fig. 2 is a diagram used in explaining the conceptual encoding levels according to the MPEG standard.
y Figs. 3A and 3B are block diagrams used in explaining video encoding and decoding processes, respectively.
Figs. 4A and 48 are block diagrams showing a differentiator and an inverse-cliff erentiator; respectively.
Figs. 5A and 5B are diagrams showing the order in which differentiatic~nand inverse-differentiation, respectively, occur.
Figs. ~A-6C ire tables used in encoding and decoding DC
component coefficients:.
Fi,g: 7 is'a diagram used in explaining encoding according to the present invention:
F~eg. 8 is a source' program which may be used 'in a variable iength'encoder according to the present invention.
Figs. 9A-9C are tables used in encoding and decoding DC
e:ompnnent coefficients according to the p~'esent invention.
Figs. 10A and 10B are charts illustrating a picture header which includes an intra dc_precision code field.
Fig. 11 is a diagram used in explaining. decoding according ~W~ 94/03427 PG'fIJ P93/01331 '~ {~x to the pres~~t'"'invention.
Fig. 12 is a source program which may be used in a variable length decoder according to the present invention.
Fig. 13 is a block diagram showing an embodiment of a motion video picture encoding apparatus in accordance, with the present invention.
Fig. i4 is a block diagram of a quantizer 115 shown in Fig.
i3.
Fig: 15 is a detailed block diagram of an inverse quantizer 118 shown in Fig. 13.
Fig. 16 is a detailed block diagram of a DC coefficient differentiator 125 shown in Fig. 13.
Fig. 17 is a detailed block diagram of a YLC encoder 126 shown in Fig. 13.
Fig. 18 is a block diagram showing an embodiment of a motion video picture decoding apparatus in accordance with the present invention.
F:ig. 13 is adetailed block diagram of a VLC decoder 152 S hown ~i n , F i g . 18 .
Fig: 20 is a detailed block diagram of a DC coefficient ira~rerse differentiator 753 shown in Fig. 18.
Figs: 21A and 21B are: tables which may be used in encoding and decoding DC component c~efficients according to the present invention.
Fig. 22 is a diagram used for explaining a technique of ~V~ 514Ig~42? FCT/J~~/aI3~1 ~i ~~ '-~ ~~ ~
manufacturing an optical disk for storing data encoded according to the present invention.
Fig. 23 is a diagram used for explaining a software generation portion of the manufacturing technique shown in Fig.
2 2 . '..__ REST MODE FOR CARRYING OUT THE INVENTION
~fith an encoder according the present invention, it is possible to adaptively modify the technique for encoding direct-current component coefficients as a function of the required picture quality. That is, the number of quantization bits used f or encoding DCT DC component coefficients can be increased with an increase in required picture quality.
It is also possible to adapt the length of the variable leh~th c~de tables for the direct-current component coefficients in accordance with a change in the precision needed f or DCT DC
component coefficients during encoding, that is, to increase the l ength of the tabl es bei ng used or to decrease the l ength of the cables being used.. Accordingly, the encoding process can be d~~'ried ~ut with a high degree of efficiency.
In addition, with a decoder according to the present invention, it is possible to adaptively modif y the technique f or decoding incoming DCT DC component coefficients.
Furthermore, using the extended variable-length code table for the direct-current component coefficients in accordance with WO 94/08427 A ~ ~' r' PCT/.IP~3/01381 .:...
i4 the precision, in quantization bits, needed for the DC component coefficients enables decoding'of these coefficients with a high degree of efficiency. .
Before the encoding commences, a raw picture to be encoded is evaluated based on the required picture'..__quality. the properties to be evaluated include the quality of the raw picture and the degree of movement of the motion video picture. based on the evaluation data and the required picture quality, the required precision for orthogonally transformed (DCT) DC
component coefficients is then determined. Each sequence, GOP, picture, slice, macroblock or block may be evaluated to adaptively determine the required precision of the DC
Coefficitints:
For example, if the evaluation data indicates that the raw picture does not have good quality, a precision of eight bits for the DC component coefficients will be adequate. For a motion video pidture with fast movement, a precision of eight bits f or the DC coefficients will also be adequate since human vision has low luminance discriminating power.
In another example, in the case of DCT 'DC component coef f i c i en~ts wi th a val ue i n the range D to 2~47 , i t i s necessary to specif y a transmission precision of eleven bits for the coefficients in order to implement lossless coding desired f or the demanded picture quality. The range 0 to 2047 is a maximum range of an output f rom a DCT modul a of an MPEG system for an W~ 94!08427 ~ ~ ~ '~ ~~~ P(.T/3P93/t11381 input picture signal having a:precision of eight bits.
To initially specify the precision of the coefficients or to modif y the precision in the course of processing, it is necessary to set a f l ag and then transmi t i nformati on on the precision of the coefficients in use. , -~-Encoding and decoding of DCT direct current component coefficients for a video signal generally according to the MPEG1 standard shown in Fig. 2, with a precision which may be varied f or portions of the video signal, are described below. The present invention may also be applied to encoding and decoding of video signals in formats other than the MPEG1 format.
The following description is for a video signal having pixels represented wi h a precision of eight bits, and it will be appreciated that the present invention may also be applied to a video signal haring pixels represented with a precision of more or less than eight bits-:
~efecring row to th~ d~-awin~gs, and in particular to Fig. 7, there is illustrated an encoding apparatus according to the present invention:~The apparatus illustrated in Fig. T includes an~.Znput terminal gyp' ~ DCT circuit 61, a quantizer 62, a di'fferent~iator 63, a VLC encoder ~4, s quantization step width circuit 6~, an initial value circuit 66; and a PLC table circuit 67.
A signal CTL, representing a required precision expressed in terms of quantization bits for DC component coefficients from ~~ 941~i~4Z7 ~~/J~'93/01~81 w<?, an orthogonal transformation such as a DCT, is supplied to a terminal 60. The signal CTS may be supplied for each sequence, OOF, picture, slice, macroblock or block.
The required precis5on represented by the signal CTL is determined by quantities per unit time such as,t~he transmission speed or transmission capacity of a transmission line and a recording density of a recording medium. Optionally, the signal CTL can be determined in view of the quality of the decoder and the quality of the picture to be encoded.
In this embodiment shown in Fig. 7, the signal CTL specifies ode df four different bit counts expressing a precision of eight to eleven bits. Ira the case of an eight-bit precision, levels in thd range 0 to 2~6 can be expressed. For nine-bit precision, levels ~n the range O to 511 can be represented. Similarly, ten-bit end eleven-bit previsions can be used for expressing levels in the ranges 0 to 1023 and 0 to 2047 respectively.
A OCT dircuit 61 is adapted~to orthogonally transform blocks of pixels representing a picture into 6 X 8 blocks DCT
cobfficients, and to supply the DCT coefficients to a quantizer 62 v~: whi'ch functions o l i pearl y quanti ze the DC component coefficients, that is,~to divide the coefficients by a variable . quantization step width; to produce quantized coefficients.
A quantization step width circuit 65 functions to provide the variable quantization step width to the quantizer 62 in accordance with the precision of the direct-current component W~ 94!08429 PGT/JP93l01381 n, , ~ .,1_ ; 7 .
y~7%.. ,. _. _e.
coefficients specified by the signal CTL. The quantization step width has a value of 8, 4, 2 or 7 for a specified precision of 8, 9, 10, or 11 bits, respectively. Thus, when eleven-bit precision is required, the value of the DCT DC component coefficient is not quantized. , _._ A differentiation circuit 63 is adapted to receive the quantized coefficients and to differentiate the DC component coefficients to pr~duce d,ifferentiatdd DC component coefficients.
The differentiation process' is carried out independently for the four luminance (Y) blocks and two chrominance (Cb and Cr) blocks in a maGroblock, as generally shown in Figs. 5A and 5B, respectively.
An initial value ci rcuit 66 functions to reset the initial value used in differentiating a block for the first block in each slice and for a block completing the first intra picture encoding process following a block completing an inter picture encoding process. The setting' of they initial value depends on the coefficient precision pacified by he signal CTL. To be mare specific, the initial value is 128, 256, X12 or 1024 for specified 'coefficient precision of 8, 9, 10 or ~ll bits respecti ve l y : The i ni t-i al val ues each date rmi ne' the cents r val ue of a dynami c range ~ If a bri ght or' dark val ue can be speci f i ed in'accordance with the scene, the picture quality of the first block will be improved.
A VLC encoder 64 is adapted to receive the differentiated V6~O 9~4IOg427 Pt.'T/JP93/013~1 ' 18 DC component coefficients and to encode them to produce encoded coefficients in accordance with the precision or the number of quantization bits specified by the signal CTL. Each encoded coefficient is a concatenation of a variable-length cods representing the number of bits used to~..... represent the differentiated coefficient and a fixed-length code representing a differentiated coefficient.
Fig. 8 shows a C Tanguage source code listing of an program which may be used by the VLC encoder 64.
The VLC encoder 64 uses the differential DC component coefficient value to obtain a corresponding size value, that is, number of bits that will be used to encode the differential DC
component coefficient, from a table shown as Fig. 9A.
Next, the VLC encoder 64 encodes the size value using, for luminance blocks, a table shown as Fig. 9D, and for chrominance blocks,; a table shown as' Fig. 9C:
Then, the VLC encoder 64 encodes the differential DC
component GOefficient using a fixed-length code from the table shown in Fig. 9A. The fixed length code has a unique code value for each unencoded value.
Finally, the encoded differential DC component coefficient value is the result of concatenating the variable-length code representing the number of bits that are used to represent the differential DC component coefficient and the fixed-length. code representing the differential DC component coefficient.

WO 94/08427 ~ Pf.°TlJP93i01381 The tables in Figs. 9A-9C correspond to the tables in Figs.
6A--6C extended to include 9, 10 and 17 bit encoding for additional precision. The code tables in Figs. 9A-9C are shown as having fixed contents. Alternatively, the code tables which are modified in accordance with results ~.._of statistical observation of input signals can be used.
A VLC tabl a c i ~GUi t' 67 i s adapted to store the tabl es shown in Figs. 9A-gC and to provide data to the VLC encoder 64. The circuit 67 may be realized as read only memory (ROM). The ROM
contents a tie read ~ut f rom he ROM memo ry by a CPU , not s hown f o r ease of illus ration.
The encoded diffee~ential DCT DC component coefficients produced by the VLC e~cader 64 are then combined with AC
component coefficients into a bit stream to which an error correcting code i added. The'ec~or correction enco~Ded bit stream may be stored on' a recording medium or transmitted through a transmission lire. At that time, the signal GTL can be appended to each associated eq~rence, GOP, picture; slice, macroblock or block as an identif'icatiow signal.
Figs. 10A and 1GB show a ypica'~-description of the header of a p-icture layer. The header includes a two-bit identification signal intro dc_precisi~n, corresponding to the signal CTL, used for selecting one of four extended encoding precision values.
A decodi ng apparatus accordi ng to the present i nventi on. wi 11 naw,be described with reference to Fig. 11.

~~ ~4,Q~2~ PGT/JP93/01381 i ~ '1Y 7 ] ~~ . ,.
- .c~r . ri. w:~ . . 'w~ ~ z 2 0 The apparatus i 1 7 ust rated i n F i g , i 1 i ncl udes a VLC decode r 81, an inverse differentiatar~ 82, an inverse quantizer 83, an inverse DCT circuit 84, a VLC table circuit 85, an initial value circuit 86, a quantization step width circuit 87, a block identifier 88 and an input terminal 89. ,._ The bit stream produced by the encoding apparatus described earlier is supplied to the decoding apparatus through a transmission line ar from a recording medium such as an optical disk.
A signal CTL is supplied to an input terminal 89 through a demodulatian circuit-which is not shown in Fig. 11. As described earl ier, the signal CTL represents, the requi red precision of 8, 9;-1~ or 11 quantized bits for each DC component coefficient resulting from an orthogonal transformation such as the DCT for each video sequence, GOP, picture, slice, macroblock or block portion of a video signal:
Additionally, the decoding apparatus according to the present invention can locally generate a signal CTL. ~n such case, it is necessary to synchronize the'signal CTL generated by the. decoding. apparatus with the signal CTL set in the encoding apparatus:
For example, if a disk is used as a recording medium and a uniform precision is set for the anti re disk, it is possible for a disk playback apparatus, which has a demodulation unit designed f or high-quality pictures, that is, which aiiows specification w~ ~a/osaZ~
PCT/,1~3/OI387 of a precision of 8 to 1l quantized bits per DC component coefficient, to play back motion video pictures with a uniform picture quality. 0~ the other hand, a disk playback apparatus with a demodulation unit designed for only an eight-bit precision cannot play back high-quality pictures having a..~recision of 9, t0 or 11 bits from a disk. However, it is possible to present the so-called picture-quality adjusted to such a disk playback aPParatus.
Similarly; the demodulation unit may provide for all selectable precisions; ~r mad allow for a predetermined precision suitable for a specific type or a specific model of disk playback apps ~-atus .
With the signal CTL, a variable-lehgth code representing a number of biis in a following fixed length cods and the fixed-length cade representing a DG component coefficient are supplied to a VLC deGOder 81 through, among other components, a demodulation circuit which is~not shown. The VLC decoder 8i functions to decode these variable-length and fixed-length codes usi ng an al go~-i thm whi ch may imps emented as a C l anguage compute r program shown in Fig. 12 to produce differentiated DC component coefficients.
A'VLC table ci rcuit 85 is adapted to store the tables shown ih Figs. 9A-9C, and to provide stored data to the VLC decoder 81.
An inverse differentiator 82 serves to receive. the differentiated DC component coefficients and to apply an W~ 94/08427 PCT/JP93/01381 inverse-differentiation process among adjacent blocks to recover quantized DC component coefficients. Each inverse-differentiation process is carried out independently for the four luminance (Y) blocks and two chrominance (Cb and Cr) blocks in order to recover the quantized DC component coefficients. In a ' complementary manner to differentiation explained with reference to Figs. 5A and 5B, a differentiated DC component coefficient of a luminance block undergoes inverse differentiation in a zigzag order from upper left to upper right to lower left to lower right blocks in a m~crobldck. The differentiated OC component coefficients in these blocks are then respectively replaced with the recovered DC component coefficients. For the chrominance blocks;' differentiated DC component coefficients of right and left blocks ad3acent to each other undergo inverse differentiation to produce recovered DC component coefficients which repl-ace the differentiated DC component coefficients in the respective blocks.
An initial value circuit 86 functions to reset an initial value. in these inverse' differentiation processes;. in the fi rst block of a: slice or' a block completing the fi rst .intra picture encoding process following a block completing an inter picture encoding process. The initial value varies, depending upon the specified coefficient precision. To be more specific, the initial value is 128; ' 256, 512 or 1024 for a specified coefficient precision of 8; 9, 10 or 11 bits respectively.

9~V0 ~~108427 PC'f/J~93/01~81 ~ .~ c ~
..- ~a.~ ~c'~ ~fi ' 23 An inverse quantizer 83 is adapted to receive the recovered quantized OC component coefficients and to apply an inverse-linear-quantization process thereto using a variable quantization step width. Specifically, the inverse quantizer 83 multiplies each quantiaed DC component coif-ficient by the quantization. step width to produce a DC component coefficient.
A quantization step, width circuit 87 is adapted to supply the variable quantization s ep width to the inverse quantizer 83 in accordance with=the signal CTL. More specifically, the value of the quantization step .width is 8, 4, 2 or t for a specified precision of 8; 9, 10 or 11 bits respectively.
An inverse DCT circuit 84 functions to receive the DC
component coefficients and to use it as the coefficient F(0,0) shown i n F i g . 1 . The AC component coeff i c i ents a re suppl i ed f rom other inverse DCT circuits; not shown; o form the 8 X 8 matrix shown in dig: 1. The inverse DCT circuit 84 functions to apply a two-dimensional inverse DCT process'to the matrix to restore the original luminance or chrominance signal.
The luminance~or chrominance signal may be restored'with a level different from that of the original signal dare 'to the linear/inverse-linear=quantization prodesses: However, the DCT
and inverse DCT are known to' have a peculiar property that raw data can be estimated from a relation among adjacent coefficients, so that large errors can be prevented which avo ids serious problems.

fV~ 94/0427 PGT/.DP93/~131 ~r.~~~''s,~~;'' 24 s> .._ ~:
An encoding apparatus according to the present invention will now be described in more detail with reference to Figs. 13-17. The present invention can be applied to a case in which the picture structure is a frame or field. However, the following description is for a case in which the picture._.structure is a frame. For convenience, it is assumed that the required picture quality may be changed only at each sequence, GOP, picture or s1 ice portion of a video signal . One ski iled in the art wi 11 appreciate how to modify the fol lowing apparatus if the requi red picture q~rality may also change at each macroblock or block pot~~ti on of the vi deo si final .
Fi g. 13 shows an encodi ng apparatus accordi ng to the present invention, and includes input terminals 110, 131, output terminals 132, 133, field memories 111, motion predictor 112, subtr~actor 113, DCT circuit 114, quantizer 115, scan converter 116, inverse scan converter 117, inverse quantizer 115, inverse DCT circuit 119, adder 120, field memories 121, motion c~mpensator 122, reference picture controller 123, field memory controller 124, di~fferenl:iator 125, VL:C encoder 126, buffer m~mory 127, macrobl~ck (6HS) counter 128;,picture counter 129, encoding control memory 130, and control information ci rcuit 134.
Tie signals used by the encoding apparatus of Fig. 13 include the following signals: pixel block S1, difference S2, DCT
coefficient S3, quantized DCT coefficient S4, sequential coefficient S5, restored sequence S6, recovered coefficient S7, WO 14108427 ,.~ ~~~ ',~ 'm .~,~ ~~ PC'f/JP93/~1381 '.~ ~ ~,, a a decoded pixel block S8, recovered picture S9, prediction S10, reference picture command S11, motion vector S12, motion vector S13, motion compensation mode S14, motion compensating reference picture command S15, picture commend signal 516, output picture command 517, quantization, step width ,'...,18, vertical synchronization 519, video sequence start flag S20, GOP start flag S21, picture start flag S22, slice start flag S23, differentiated coefficient S24, control information S25, intra'dc-precision 526; MB address S27, picture read out S30, MB
start X31; and motion compensation mode 532.
A control information circuit 134 is adapted to store information for controlling the basic operation of the encoding apparatus and to provide the'stored information to an encoding contrcrl,memory 130 when picture encoding is to occur. The information includes, among other data, a screen size, an output bit rate of encoded information; a picture structure signal and a picture encoding type. The picture structure signal is an identification signal fog indicating whether a picture has a frame or field structure. The picture type is an identification s i final f o r i nd i cati ng whethe r a -pi ctu re to be encoded i s an I , P or B'picture: The ehcoding control memory 130 i~ adapted to read out this information es a control information signal S25, and to supply it to a motion. predictor 112, a reference picture controlle r 123, a motion compensator 122, a field memory control'~er 124, a VLC encoder 126; a buffer memory 127, a MB

W~ 9410427 PCT/3P931~1381 counter 128 and a picture counter 729.
The memory 13(9 also is adapted to store an intra_dc_ precision code S26 used to vary the encoding precision of the DC
coefficients. The intra~dc_precision code signal S26 corresponds to the CTL signal ofi Fig. 7. explained earlier:__. To switch the dncoding precision of the DC coefficients for a layer, the intra_ do~precision code S26 must be present in the appropriate one of the video sequence header, GOP header, picture header or slice heads r o As s hown i n the sampl a p i ctu re l aye r heads r of F i g .
10B; the intra de-precision code S26 may comprise a two bit code for specifyin~'four different encoding previsions. For example, intra dc~precision codes S26 having values '00', '01', '1fl' and '11' may specify encoding previsions of S, 9, 10 and 11 quantization bits per DC component coefficient, respectively.
The memory; 130 supplies he intra~dc_phecision code S26 to a quantization circuit 1t5, an inverse-quantization circuit 118, a DC-coefficient differ~enti'ator 125 and the YLG unit 126.
An input terminal 13i serves to 'receive a vertical-sy~ch~onization signa'1 S19 and to supply it to -the reference picture controller'123;which functions to produce.a reference picture command signal-S11 to field memories 111 synchronou 1y with the vertical synchronization signal Si9.
An input terminal 110 secwes to receive blocks of pictures and to supply these blocks to the field memories 111 which are adapted to store these blocks.and to sequentially read them out WO 94!08427 PGTlJP93/01381 2 '~
as a pixel block signal S1 separately to a motion predictor 112 and a subtractor 113 from addresses specified by the reference-picture command signal S11. Although the informatitrn is read out in block units, it is actually processed in macroblock units.
That is to say, six blocks YO to Y3, Cr and Cb, ~_as shown in Fig.
2 undergo the same processes in the apparatus simultaneously.
The f i e! d memnri es -1 1 1 are al so adapted to produce a pi ctu re read out signal S30'. when a picture to be encoded begins to be read out therefrom; and to produce a MB start flag signal S31 when a macroblock portiAn' of a picture to be encoded begins to be read out the ref rom:
Themation predictor is operable to process picture data of each field as an I, P or B picture based on the control i nfo rmati on si gnal 525'. The dete rmi nati on as to whethe r the picture data of each field is °to be processed as an I, ~ P or S
picture is done in advancer Whether processing is to occur in GOP units, for example is also determined in advance.
The motion predictor 112 is also operable to detect a motion vector between a forward raw picture: read out from the field memories 111 and a cu~~es~t reference 'picture also read from the field memories 111; and a motion vector'between a backward raw picture read out from the field memories 111 and the current reference picture. A forward raw picture is a picture temporally precedi0~ a current picture to be encoded: A backward raw picture is a picture temporally succeeding the current picture ewo ~4rosa2a ~crita~~i~a3sa ,, kr, .P~ ;~a. : ~, ~~ih j~' , uar fc ~~:.1 N , 28 to be encoded. A current reference picture is the current picture to be encoded.
The motion predictor 112 computes sums of absolute values of prediction errors (differences among fields for each block) to select the minimum among intra picture pred.i_ction, forward prediction, backward prediction or bidirectional prediction.
For intra picture prediction, the difference between ~~ Aij~ and ~ ~ Ai j' i s found , whe re - ~ ~ Ai, j' i s the absol ute val ue of the sum o~ signals Ai j of macroblocks of a reference picture whereas I Ai j f i s the sum of the absolute val ues of the si final s Ai j . For forward prediction; the sum of absolute values F fAij - Bij~ is found, where Aij are the macroblock signals of a reference picture, Bi j are the macroblack signals of a forward raw picture, and (Aij Bij~ is the absolute value of the difference between Aij and Bia. The sum of the absolute values of prediction errors for the backward prediction and that for the bidirectional prediction can be found in the same way as the forward prediction excepihat, for the backward prediction, the forward raw picture isreplaced by a backward' raw picture whereas, in the case of the bidirectiona'~ prediction, the forward raw picture is replaced typically by an average value of the forward and backward raw pictures:
The motion predictor 112 further selects a minimum among the sums of the absolute values of predictiop errors for the forward, backward and bidirectional predictions as a sum of the absolute wc~ 94rosaz~ pcriJi~3ro~~m 2 ~ ~ ~ '.-~r~ t values of prediction errors f or the inter picture prediction.
The motion predictor 1i2 then~compares this minimum to the sum of the absolute values of prediction errors for the intra picture prediction described above in order to identify the smaller of the two. A mode corresponding to the identified_sma7ler one is finally selected as a motion-compensation mode. That is to say, if the sum of the absolute values of prediction errors for the intra picture prediction is smaller, an intra picture-prediction mode is set. Otherwise, a forward, backward or bidirectional-predictioh mode corresponding to the minimum selected ab~ve is set.
From the above calculation based on the macroblock signals of the :reference signal, the motion predictor 112 detects a motion vector between' the reference picture and a predicted picture in one of four motion compensation modes: intra picture, forward, backward or bidi sectional prediction.
The, motion predictor 112 operates to output the minimum value as a motion vector S12 and a motion compensation mode signal S32 to a motion-compensator 122.
When the motion compensation mode signal S32 indicates intra field (ihtra picture) encoding (prediction) mode, the pixel block signal Si for the picture to be encoded is read out from the field-memory unit 111 to the subtractor 113 which functions to simply pass it through 'unchanged as a difference signal S2.to a DCT circuit i 14.

W~ 94/08427 P(.°T/.DP93/01331 :,.,..
' 30 V~hen the motion compensation mode signal S32 indicates the forward, backward or bidirectional prediction mode, the subtractor 113 functions to subtract a prediction signal S10 from the pixel block signal Si to produce the difference signal S2 which is supplied to the DCT circuit 114. __ The DCT circuit 114 functions to apply an orthogonal transformation, specifically the DCT, to the difference signal S2 supplied thereto to produce a DCT coefficient signal S3 and to supply the signal S3 to the quantizer 115.
The quawiizer 115 is adapted to quantize the DCT
coefficients S3 in accordance with a quantization step width signal S1S to produce a quantized DCT coefficient signal S4 and to supply the'signal S4 t~ a scan converter 116. The quantizer 115 serves to perform either linear or non-linear quantization, in accprdanpe with a qscale~type signal supplied thereto, although not shown in Fig: 13. ~ code "qscala type", shown in Fig: 108 immediately blow the intra~d;;~precision code, is a sing7d-bit code for specifying which of linear and non-linear quantiz~tion is to'be performed, for example, by the values 0 and 1~.:..respectiveiy...The quantizer 115 is explained in detail below with reference to Fig, 14.
The scan converter 116 serves to scan the quantized DCT
coeff i c i ants S4 i n a z i gzag manna r~ f rom l owest-f requency coefficient to highest-frequency coefficient to produce a sequential coefficient signal S5, and to supply the signal S5 to !~V~ 94/98427 PCf/JP93/Q1381 ~~,.~rlt~;~~~r an inverse scan converter 117 and the differentiator 125. The scan converter 116 outputs only data f or I and P pictures to the inverse-scan converter 117 and does not output data for a S
picture.
The inverse scan converter 117 is adapted,.to operate in a manner complementary to the scan converter 116, that is, the inverse scan converter 117 performs an inverse-zigzag scanning process on the sequential coefficient signal S5 to produce a restored sequence signal SS and supplies the signal S6 to the inverse quantizer 118.
The i nve rse quanti ze r 1 18 i s adapted to ope rate i n a manna r complementary to the quantizer 115, that is, genera lly to multiply the coefficients in the signal S6 by the quantization step width 518 to produce a recovered coefficient signal ST and to supply the signal ST to an inverse DCT circuit 119. The i nve rse quant i ze r 118 se rve~ to pe rf o rm a i the r 1 i nea r o r non-lin~ar inverse quantization, in accordance with the qscale_type signa't supplied thereto; although not shown in Fig. 13. The inverse quantizer 118 is explained in detail below ~rith reference to Fig: 15,. 1 The inverse DCT circuit 119 is adapted to operate in a manner c~mplementary to the DCT ci rcuit 114 to produce a decoded pixel block signal a8, and ao supply the signal S8 to an adder 120: .
In the intra picture prediction mode, the adder 120 VirU 94I08~27 ~ ~ ~ ~ ~ ~ ~ PCTlJP93l01381 ,..,?..

functions to simply pass the decoded pixel block signal SS to field memories 121 as a recovered picture signal S9. In the forward, backward or b'idi sectional prediction mode, the adder 120 functions to add the decoded pixel block signal S8 to the prediction signal SlO on a pixel by pixel basis to produce the recovered picture signal S9.
The field memories 121 are adapted to store the recovered picture S9 at addresses specified by a picture command signal 516. The recovered picture S9 is identified as a picture used in backward or forward prediction by a motion compensating reference picture command signal SlS. Since the scan converter 116 outputs only data for-I and P pictures to the inverse-scan converter 117, only data for I and P pictures is stored in the field-memory unit 121: There is no need ~ store data for a B
picture because B pictures are not used in predictive encoding.
The field memories 121 are also adapted to transmit the pictures stored therein to an output terminal 133 at a timing determined by an output pidture command signal S17 so that it may be displayed on a monitor for verification.
The motion compensator' 122 functions to receive the signals 512, S32 and to perform motion compensation on a picture stored ih the field memories t21 to.produce the prediction signal 510.
Specifically, when the forward, backward or bidirectional-pr~diction- modes are indicated by the motion compensation mode signal S32; the motion compensator 122 shifts WQ 94/08427 ~ ~ ,~ ;~ Pt.'f/J~'93/013~1 the read addresses applied to the field memories 121 by a displacement corresponding to the motion vector S12, and t ransmi is the data read out f rom the she fted add reuses of f e a 1 d memories 121 as the prediction signal 510. In the bide rectional-prediction mode, picture portions__~for each of the forward and .backward predictions are read out from the field memori es 121 e n accordance we th the mote on compensate ng refe rence picture command signal S15 and summed to compute an average value to be output as the prediction signal S10.
The motion compensator 122 also functions to supply the motion vector signs) Sl2 as a motion vector signal 513, and to supply the motion compensation mode signal S32 as a motion compensation mode signal S14.
A field memory c~ntro7ler 124 is operable to receive a picture start flag S22 and the control information signal 525, and to gar~duce the motion compensating reference picture command s e anal 515 ~ the pi ctu re command se final Si 6 and the output pi ctu re command signal Sl7 synchronously with a picture-start flag 522, and to supply the 'signa'9s S15, S16; S17 to the field memories 127:.
The differentiat~r 125 is operable t~ differentiate the DC
c~mponent coeff e d e ants e n the sequenti al coeff e c e ants S5 supp 1 e ed thereto to produce a differentiated coefficient signal 524, and to supply the signal S24 to the VLC encoder 126. The differdntiator 125 is explained in detail below with reference C a f p~fa~~~~~~~~1 i yi w4 fw '.W ~.o.

to Fig. 16.
The VLC encoder i26 is adapted to encode the motion vector 513, motion compensation mode 514, differentiated coefficients S24 and quantization step width S18 to produce Huffman encoded data and to supply the encoded data to a buffe~_,.memory 132.
A video.sequence start flag S20, a GOP start flag 521, the picture start flag 522, a slice start flag 523 and a MB address signal S27 are also supplied to the VLC encoder 126. Setting of one of the flags S20, S21, S22, S23 prompts the VLC encoder 126 to generate a start code f or a video sequence, GOP, picture and slice; respectively. Control information for the encoded data of the respective signal layer portion is then read out from the memory 130 as header data. The start codes and header data are part of the signal output from the VLC encoder 126 to the buffer memory 127s.
The buffer memory 127 serves to temporarily store the ~uffman encoded data, and then to apply it to an output terminal 13Z ~s a bit stream at a constant transmission rate. The buffer memory 127 also serves to supply the quantization step width signal Sl8 representing the amount of-data stored therein to the qu~ntizer 115. If thb amount of data in the buffer memory 127 exceeds an allowable maximum limit, the quantization step width S15 i s i nc ceased to dec cease the amount of quanti zed coeff i c i ants 54. Tf the amount of data in the buffer memory 127 falls below an allowable minimum limit, the quantization step width S15 is t~0 94/16427 c ,~ , PCTlJP93/01381 ~.~~~~!~
decreased to increase the amount of quantized coefficients S4.
The buffer memory 127 thereby adjusts the amount of data to be generated as a bit stream, ensuring a proper data output rate which avoids both overflow and underflow in the buffer memory 127: .
The bit stream output by the buffer memory 127 is typically multiplexed with, among other things, an encoded audio signal and a synchronization signal. Error-correction codes are further added to the bit stream and, after undergoing predetermined modulation; the bi stream is stored on a recording medium such as ~h optical disk using a laser beam.
The MB counter t28 is adapted to receive ithe picture read out si gnal S3o and to be reset to ze ro i n response the reto . The MB counter 128 is also adapted to receive the MB start flag S31 and to count v the numbs r ' of b1 ocks read out f rom the f i a l d memories 111 in response thereto: The MB counter 128 supplies its macroblock count as the MB address signal S27.
For more 'efficient compression of a ~oideo signal, only the f i'r~st ~ mac r, ob1 ock - i n each s1 i ce may have an absol ute add ress .
indicating its position in a picture. Subsequent macroblacks in the slice may each have an address relative to the absolute address ' of the fi rst macroblock in the slice. The macroblock address signal X27 provides the relative address for these subsequent macroblocks.

W~ 9~/0~427 ~'C~'/J~'93/~131 .~ t a ~~ ~,,.<..., ..

The MB. counter 128 is also adapted to receive a slice length, that is, the number of macroblocks which constitute a slice, as part of the control information signal S25. When the macroblock count reaches a predetermined multiple of the slice 1 ength , the MB counts r i s adapted to gene rate, .(.set ) the s 1 i ce start flag 23. At other times, the slice start flag is in a reset statb. The slice length can change a bit stream output from the buffer-memory unit 127, depending upon an error state of a transmission line f or transmitting the bit stream, that is, depending upon the reliability of the transmission line. In general, the higher the probability that a transmission error occurs on the transmission line, the shorter the value at which the slice 'length is set.
The pi ctu re counts r 129 i s adapted to be reset to ~e ro when th~ encoding of a video sequence begins, and to generate (set) a video sequence start flag S20 upon being reset. The picture counter 129 is also adapted receive the picture read out signal S30 and to generate (set) the picture start flag S22 in synchronism with ttie picture read out signal 530..
The pi ctu re counts r '! 29 i s f a rthe r adapted to rece i ve a GOP
length, that is, the number of pictures which constitute a GOP, as part of the control information signal 525. A typical GOP
length may be 12 or 15 frames. The picture counter '~29 counts the numbs r of pi ctu res read out f rom the f i a 1 d memo r i es 1 1 1 , and when its count of the number of pictures reaches a predetermined t~V~ X4/98427 PCf/JP~3l~1381 ' 37 multiple of the GOP length, the picture counter 129 is adapted to generate or set the GOP start flag S21.
Fig. 14 shows a detailed embodiment of the quantizer 315.
The quantizer 115 is seen to include input terminals 300, 312, 314, 315, quantization units 304, 305, DC,~AC coefficient separator 305., DC coeff i ci ent quanti zati on uni t 301, quanti zati on step generator 308, blocking circuit 309, output terminal 310, intra flag generator 311, and switch 313.
The motion compensation mode signal S14 is supplied to an input terminal 312 which applies the signal S14 to an intra flag generator 311. The intra flag generator 311 is adapted to set an intra flag 5309 whqn the motion-compensation mode signal S14 indicates that intra picture encoding is to be performed. For example; if the intra flag S309 is normally at the logic value 0, the generator 3i1 sets the signal 5309 to 1 when intra picture encoding is to be done:
The ACT coefficient signal S3, an 8 x 8 block of DCT
coefficients, is supplied to an input terminal 300, which applies the signal S3 to a switch 313. The-switch 313 functions to select a p~le l~ when the intra flab 5309 'ndicates that forward, backward or bidireeti~na1 encoding is to be performed.
Accordingly, the DCT coefficients S3 are supplied to a quantization unit 304 as a signal S302. The switch 313 also functions to select a pole B when the intra flag S309 indicates that intra picture encoding is to be performed. In this case, W~ 94!0842? PCf/J~3/01381 'py~z~t~~,~~~
~' '' 3s the DCT coefficients S3 are supplied to a DCfAC-coefficient separator 306.
The quantization step width signal S18 is supplied to an i nput to rmi nal 314 , and i s then app! i ed to the quanti zati on un i is 304, 305. ~.._ The quantization unit 304 is adapted to receive the DCT
coefficient signal S302 and the quantization step width signal S18, and to quantize the signal S302 in accordance with the signal S18 to produee quantized DCT coefficients, and to supply the quantized DCT coefficients as a signal S305 to a blocking c ~cuit 309. In the case of ~iPEG data, the fractional part of a quanti zed coeff i ci ant i s normal! y truncated by the quanti zati on unit 304 during quantization.
~'he blocking circuit 309 serves 'to block the quantized coefficients S305 into a block of 8 x 8 coefficients which are then-supplied to an output terminal 310 for application to the scan converter 11f> shown in Fig. 13.
the DC/AC coeff i cient separator 306 i s operabl a to spl a t the ~CT coif f i c i ants S3 i nt~ AC coeff i c i en~ts 5303 and ~C coef f i c i ants .~304;.and ~ supply he AC ccefficisnts'S303 t~ the quantization snit. 305 end the DC coefficients S304 to a DC coefficient quantization unit 307.
The quantization snit 305 is adapted to receive the AC
coefficients 5303 and the quantization step width signal 518, and to quantize the signal S303 in accordance with the signal S18 to iaVil X4/08427 PC.°f/JP93/~1381 w: .tu ~ ''.J: ~i, produce quantized AC coefficients, and to supply the quantized AC coefficients as a signal 5306 to the blocking circuit 309.
In the case of MPEG data, linear quantization is normally carried out.
The intra_dc_precision signal S26, representing a specified encoding precision expressed in terms of quantization bits for the DC coefficients, is supplied to an input terminal 315 and is then applied to a quantization step generator 308.
a The quantization step generator 308 functions to generate a signal 5308 representing a quantization step in accordance with the intra_dc_precision code 526, and to supply the signal S308 to 'the DC coefficient quantization unit 307. Then the intra_dc~precision code S26 has the value '00', '01', '10' or '11~, the quantization step signal S308 specifies that DC
c~efficients are to be enc~ded with a precision of 8, 9, 10 or .~~ ~it~, respectively.
The DC coeff i ci ent quar~ti zati on uni t 307 i s adapted to 1 i pearl y quanti ze tie DC coeff i ci ents 5304. i n accordance wi th the qu~ntiz~tion step ~ignal'..5308. The rounding method adopted for the resu7.t of ~ahe 1 i near quanti zati on courts a f racti on of at 7!east 0.5 as a ~rh~1d number and disregards the rest. The linearly quantized DC coefficients, as rounded, are supplied to the blocking circuit 309 as quantized coefficients 5307:
The AC coeff i ci ants S306 quanti zed by the quanti zati on up i t 305 and the DC coefficients S307 quantized by the quantization WAD 94/U8421 PGT/JP33101~81 r..:.., s ~

4, ~ ~ "f. y~ ~..~ i~ 4v _. .
unit 307 are blocked by the blocking circuit 309 into a block ~of 8 x 8 coeff i ci ants whi ch are then output as the blocked quanti zed coefficients S4 to the scan converter 116 shown in Fig. 13 through the terminal 310.
Thus , when the motion compensati on mode s i ~n~l S14 i ndi Gates infra picture-encoding (intra picture-prediction) mode, DC
coeff ici ants are quanti zed i n the DC coeff i ci ant quanti zati on unit 307 at the encoding precision specified by the intra~dc~precision signal S26.
Fig. 15 shows a detailed embodiment of the inverse quantizer 118:
The i nve rse quant i ze r 1 18 i s seen to i nc 1 ude i nput to rmi nal s 500, 507, 511, 512, switch 501, inverse quantization uniis 502, 503, DC coefficient inverse quantizatian unit 504, blocking circuit 505, DC/AC coefficienir separator 506, intra flag generator 508, inverse quac~tization Step generator 508, and output terminal 510.
The motion compensation mode signal 514 is supplied to an i nput to rmi nal 507' whi ch appl i es the si final SI 4 to: an i nt ra f 1 ag generator 50g. The intra,flag generator 508 is adapted to set an intra flag 5501 when the motion-compensation mode signal 514 indicates that intra picture encoding i to be performed. For example, if the intra flag S501 is normally at the logic value 0; .the generator 508 ets the signal- S501 to 1 when infra picture encorJ i ng i s to be done .

W~ ~4/~8427 PGT/,1P93/Ql X81 :::,: ,~. ~.''_~v y The restored sequence signal S6, that is, an 8 x 8 block of DCT coefficients, is supplied to an input terminal 500, which applies the signal S6 to a switch 501. The switch 501 functions to select a pole A when the intra flag S501 indicates that forward, backward or bidirectional decoding is,t.o be performed.
Accordingly,,the DGT coefficients S6 are supplied to an inverse quantization unit 502 as a signal S502. The switch 501 also functions to select a dole B when the intra flag S501 indicates that intra picture decoding is to be performed. In this case, the DCT coefficients S6 are supplied to a DC/AC-coefficient separator 506.
The quantization step width signal 518, to be more precise, the ind~rse quantization step width signal S18, is supplied to an input terminal 511, and is then applied to the inverse quantization units 502; 503.
The quantization unit 502 is adapted to receive the DCT
coefficient signal S502 and the quantization step width signal S18-; and to inverse quantize the signal S502 in accordance with the signal 518 toproduce recovered DCT coefficients, and to supply:the recovered DCT coefficients as a signal 5505 to a blocking circuit 505.
The blocking circuit 505 serves to block the recovered coefficients S505 into a block of 8 x 8 coefficients which are then supplied to an output terminal 510 for application to the inverse DCT circuit 119 shown in Fig. 13 as the recovered vv~ ~~~o~aa~ PcriJ~~i~msi _. , ,, =; rs r f~
coeff i c i ent s i~g=°S~ . I n the case of MPEG data, 1 i nea r i nve rse quantization is normally carried out.in the inverse quantization unit 502 and a value equal to half the inverse quantization step S18 is added as an offset to a result obtained from the 'linear i nve rse--quant i z at i on .
The DC/AC coefficient separator 506 is operable to spl it the DCT coeff i c i ents S6 i nto AC coeff i ci ants S503 and DC coeff i c i ents S504, and to supply the AC coefficients S503 to the inverse quantization unit 503 anc9 the DC coefficients S504 to a DC
coefficient quantization unit 504.
The inverse quantization unit 503 is adapted to receive the AC coefficients 5503 and the quantization step width signal 518, and to i>lverse quantize thq signal S503 in accordance with the signal Si8 to produce recovered AC coefficients, and to supply the recovered AC ~coeffzcients as a signal 5506 to the blocking circuit 505. In the case of MPEG data, linear inverse quant-~zation is normally- carried out.
The intra_dcopreeision signal 526, representing a specified encoding p~'~cision'~ expressed in terms of quantization bits for the DC co~i"ficients, is supplied to an input t~rminal 512 and is then applied to an iwerse quantiz~tion step generator 509.
The inverse qdantization step generator 509 functions to generate a signal 5508 representing an inverse quantization step in accordance with the infra dc_precision code 526, and to supply the signal S508 to the DC coefficient inverse quantization unit '!aV~ ~4/~427 ~ ~ ~ ~ t~ ~~ =~ ~(.T/3P93/013~1 504. When the intra dc-precision code S26 has the value '00', '01', '10' or '11', the inverse quantization step signal 5508 specifies that DC coefficients are to be decoded with a precision of 8, 9, 10 or 11 bits, respectively.
The DC coef f i c i ent i nve rse quanti zati an uni.l;- 504 i s adapted to linearly. inverse quantize the DC coefficients S504 in accordance with the inverse quantization step signal 5508. The recovered DC coefficients are supplied to the blocking circuit 505 as recovered coefficients 5507.
The AC coefficients S506 recovered by the inverse quantization unit 503 and the DC coefficients S507 recovered by the inverse quantization unit 504 are blocked by the blocking C'1 rCU'lt 505 into a blOCk Of ~ 3C 8 COeff'iClentS whlCh are then output as the recovered coefficients S7 to the inverse DCT
circuit 119 sh~Wn in Fig. 13 through the terminal 510.
Fig. 16 shows a detailed embodiment of the differentiator 125.
'fhe differenti~tor 125 is seen to include input terminals 2~0, 2~3, 421, 423y~ 425; 427y bl~ck csaunter 201, flag generator 202; switches 4~0, 4~3, 4~4, 407, ~41~, ~C~AC coefficient separator 401; blocking circuit 4~2, registers 405, 411, register initial value generator 406, OR gate 408, intra flag generator 409, subtractors 412, 413, and output terminal 420.
The sequential G~efficient signal S5, representing the quantized DCT coefficients, is supplied to an input terminal 200 ~~ 94141842? PCT/JP93/01381 ,..,r~

which applies it to a block counter 201 and a switch 400.
The macroblock start flag S31 is supplied to an input terminal 203 which applies it to the block counter 201.
The b1 ock counte r 201 f uncti ons to count the numbe r of blocks in each macroblock of the coefficient si~n.a.1 S5 to produce a block count signal S201 and to supply the signal S201 to the flag generator 202. Specifically, the block count S201 has a value of 1, 2; 3, 4, 5; ~ as the respective blocks Y0, Y1, Y2, Y3, Cb, Cr in each macroblock are supplied: When the macroblock s art flag S31 is set, the-block counter 201 is reset.
The f l ag gene rator 202 i s adapted to gene rate ( set ) a Y f 1 ag S202 when- the val ue of the b1 oc.k count S201 i s 4 o r smal l a r to indicate that a luminance Y block is being supplied. The generator 202 is also adapted to set a Cb flag S203 when the val ue of the b1 ock count 5201 i s edual to 5 , to i ndi cats that the chrominance'Cb block is being SUQplied. The 'generator 202 is f a rthe r adapted to set a Cr f 1 ag 5204 when the val ue of the block count S.201 is equal to 6, to indicate that the chrominance Cr block is being supplied. 'i'he gene rat~r 202 supplies the signals 5202, 5203, S204 to switches 403, 404.
The motion compensation mode signal S14 is supplied to an input terminal 421 which applies it to an intra flag generator 409.
T'he i ntra f 1 ag gene r~ator 409 functi ons to set an i ntra f i ag 5406, to a value of; for example 1,' when the motion compensation ~V~ 94/0$427 ~~'. ~ ~ ~. r~ ~3 ,~~. P~'f/~P93/01381 mode signal S14 indicates the intra picture-encoding (intra picture-prediction) mode. The generator 40~ supplies the intra flag 5406 at the logic value 0 when the signal S14 does not indicate intra picture encoding, that is, indicates forward, backward or bidirectional encoding. The intr-.a flag S406 is supplied to.switches 400 and 470.
The swi tch 400 se rues to se 1 act a pol a A o r S when the i nt ra flag 5406 has the logic value 0 or 1, respectively, so that when a non-intra picture encoding is indicated, the coefficient signal S5 is supplied as a signal S4D1 to a blocking circuit 4D2, and when intra picture encoding is indicated, the coefficient signal S6 is supplied to the DC~AC coefficient separator 409.
The blocking circuit 402 is adapted to block the quantized coefficients 5401 int~ an 8 x 8 block of coefficients, and to supply the blocked coefficients to a terminal 420 for application to the VLC unit 926 shown in Fig. 13 as the differentiated signal S16:
The DC/AC coefficient separator 401 is adapted to split the copffipient aignal~S5 into quantiled AC coefficients S402 which ire supplied to the blocking circuit 402; and into quantized DC
coe~ficlents 5403 which are supplied to the switch 403 and a subtractor 493.
The switch 403, registers 405, the switch 404 and the sdbtractor 413 function to differentiate adjacent blocks forming mac robl ocks , as was desc ri bed wi th refe rence to F i gs . 4A and 5A .

W~ 94108427 PGT/JP93/01381 . ~ f~

The four chrominance blocks YO to Y3 and the two chrominance blocks Cb and Cr undergo differentiation processes independently.
More specifically, when the flag generator 202 sets the Y
flag S202 and resets the Cb and Cr flags S203 and S204, i ndi cati ng that the quanti zed DC coeff i ci ents~._..5403 are f rom a luminance block, the switches 403 and 404 select poles C and C' respectively, to supply the quantized DC coefficients S403 to a Y register of the registers 405. The Y register 405 delays the luminance coefficients by a time corresponding to one block, then suppl i es these coeff i ci ents to a pol a C' of the swi tch 404 , whi ch applies the coefficients as a delayed signal to the subtractor 413:
The subtracto~ 413 serves to receive the delayed signal 5404 and the quantized OC coefficients S403 and to subtract the signal S404 f rom the s i gna l S403 ( S403 - S404 ) to p roduce a s i gnal S405 representing the difference between DC coefficients of twa acljacen~t chrominance blocks. The subt~actor 413 supplies the difference signal S405 to the blocking circuit 402.
When .the f lag ~ gene rator 202 sets the Cb f l cg S203 and resets the.Y and:Cr flagsS2Q2, 5204, indicating that the-quantized DC
coeff~ocients S403 are from a chrominance Cb block, the swi'tches 403 aid 404 select poles D and D' respectively, to supply the quantized DC coefficients S403 to a Cb register of the registers 405: The Cb register 405 delays the chcominance Cb coefficients by a time corresponding to one mac~-oblock, then supplies these dV0 94108427 PCT/JP931g1381 ~~~Lilr~.,l .. .. _ coefficients to a pole D' of the switch 404, which applies the coefficients as a delayed signal to the subtractor 413. In similar manner as described above for the luminance Z' blocks, the subtractor 413 produces a signal 5405 representing differences i n - DC coeff i ci ents between chromi nance b1 ocks, '.i.r~ two adjacent macroblocks.
When the f l ag gene rato r 202 sets the C r f l ag S204 and resets lahe Y and Cb flags S202 and S203, indicating that the quantized DC coefficients S403 are from a chrominance Cr block, the swi tches 403 and ' X04 se;l ect pol es E and E' respecti vel y . The chrominance Cr coefficients is delayed for one macroblock of time, then applied to the subtraetor 413.
The blocking circui 402 also blocks the differentiated DC
caeff i c i ants bf a block wig th quant i zed AC coeff i c i ants S402 f rom the'D~/AC coefficient eparator 407; and suppYies the result as the signal S24 to the vLC unit 126 of Fig. 13.
When the h1B address signal 527 for the macroblocks being encoded; pr~duced vby the MB counter 128 of Fig. 13, does not convey eonti guous val ues or the DC coeff i ci ants bel ong to a f i rst macroblock of a slice, the Y; Cb and Cr registers 405 are reset 'to an initial value 5413 by a register initial-value generator The intra dc-precision code 526, which represents the encoding precision for DC coefficients, is supplied to an input terminal 427 that applies it to the register initial value WO 94/fl8427 PLT/,TP93/01381 ~ i p .,~.r..
~.~:' ~~~~~~s~

generator 406.
The register initial value generator 406 is operable to generate the initial value S413 for the 1f, Cb and Cr registers 405 in accordance with the intra_dc_precision code S26 as shown in the following table. , .._ PRECISION

00 8 bi is 128 01 9 bits 256 ~0 ~0 bits 512 11 bits 1024 The swi tch 407 i s put i nto an OFF o r ON state when a cont rol signal S420 has a value of; for example, zero or one, respectively: When the switch 407 switches into the ON state, the initial va'tue S413 is applied to each of the registers 405.
The control signal S420 puts the switch 407 into the ON state when the MB add re s s i gnal S27 of the MBs exile ri enci ng the i nt ra pi cture e~codi ng process does not bonvey coati guous val ues or the OC coefficients belong o a first macroblock of a slice.
The control signal S420 may be produced as folcows.
Tt~e macrobl'ock address signal S27 is suppl led to an input terminal 423 which applies ~it to the switch 410 and to a subtractor 412. The twitch 410 functions to supply the MB
add ress S27 to a regi ste r 41 1 when tie i ntra f 1 ag 5406 i ndi Gates intro picture encoding: The register 411 is .operable to delay ~3'~ 94!03427 PCT/3P93/01381 ~: _~ ~ -~°- t~ ~ i ~
H

the MB address S27 by a time corresponding to one MB, and to supply the delayed signal S407 to a subtractor 412.
The subtractor 412 serves to subtract the signal S407 from the signal S27 to produce a signal S408 - S27 -- S407, and to apply the signal S408; representing address dif'f-erences between adjacent macroblocks, to an input of an OR gate 408.
The slice start flag S23 is supplied to an input terminal 425 which applies it to another input of the OR gate 408.
The OR gate 408 functions to output the logic value 1 when the difference signal 5408 is greater than unity (S408 > 1~ or the slice start flag S23 is set. The OR gate 408 functions to otherwise autput the logic value 0.
As described above, the differentiator 125 differentiates DC coefficients in accordance with the required encoding precisipn for the DC coefficients which can be changed at each video sequence, OOF; picture or slice unit.
Fig. 17 shows a detai'ied embodiment of the VLC encoder 126.
The ~ILC encoder 126 is seen to include input torminals 700, 721, T23,- 725, b'Iock counter T01, flag generator 702, DCJAC
coefficient e~parator 7~g, two-dimensiona'1 variable length encoder 704, DC coef°F~cient variable length encoder 705, variabla length encoding table modifier 706; variable length encoding table storage 707, DCJAC coefficient multiplexer 708, intra flag generator 709, switch 710 and output terminal 732.
The differentiated coefficient signal S24 is supplied to an PGT/JP93/~I3~1 1~a1941~8~dZ7 C~ 4~
input terminal 700 which applies it to a block counter 701 and a switch 710.
The macroblock start signal S31 is supplied to an input terminal 725 which applies it to the block counter 701.
The block counter 701 functions to count._. the number of blocks in each macroblock of the differentiated coefficient si gnal 524 to produce a block count si gnal S701 and to suppl y the signal S701 to the flag generator 702. Specifically, the block count S701 has a value of 1, 2, 3, 4, 5, 6 as the respective blocks YO, Y1, Y2, Y3, Cb, Cr in each macroblock are supplied.
When the macroblock start flag S3l is set, the block counter 701 is reset.
Thd f 1 ag gene rato r 702 i s adapted to gene rate ( set ) a Y f 1 act 5702 when the value of the block count S701 is 4 or smaller to indicate that a :luminance Y block is being supplied. The gene rator 702 i s al so adapted to set a Cb f 1 ag 5703 when the val ue oi' the b1 ock count S701 i s equal to 5 , to i ndi Gate that the chrominance Ct~ block is being supplied: The generator 702 is gurther adapted t~ set a. Cr flag S704 when the value of the block count ST01. is equal td 6; to indicate that the chrominance Cr block is being supplied: The generator 702 supplies the signals S702.; 5703; S704 to a variable length encoding table modifier 706.:
The motion compensation mode signal S14 is supplied,to an input terminal 721 which applies it to an intra flag generator 'WO 94/027 PGT/JP93/~1381 ~~~~'~~=~'v 709.
The l nt ra f 1 ag gene rator 709 f uncti ons to set an l nt ra f 1 ag S705, to a value of, for example 1, when the motion compensation mode signal S14 indicates the intra picture-encoding (intra picture-prediction) mode. The generator 709 supplies the intra f 1 ag 5705 to, swi tch 710 at the 1 og l c val ue 0 when the s l gnal S 14 does not indicate intra picture encoding, that is, indicates forward, backward or bidirectional encoding.
s The swi tch 710 se rues to set act a pol a A or B when the l nt ra flag S705 has the logic value 0 or 1, respectively, so that when non-intra picture encoding is indicated, the differentiated coefficient signal S24 is supplied as a signal S706 to a two-dimensional variable length encoder 704, and when intra picture enc~di ng l s l ndi Gated, the dl ffe renti aced cdeff l ci ant si gnal S24 is strppli~d to a DC/AC coefficient separator 703.
The two-dimensional variable-length coder 704 is adapted to encode the differentiated DCT coefficients 5706 using a variable length code such as the well known two-dimensional Huffman code t~o praduce a V~,C c~de.signal 5709, and to output the signal 5709 to a DC/AC_coefficient multip7exer 708:
The DC/AC coefficient separator 703 functions to split the differentiated DCT coefficients S24 into AC coefficients S707 Whiph are supplied to the two-dimensional variable length encoder 7~4, and l nto DC coeff l ti ants S708 whi ch are suppl l ed to a DC
coefficient variable length encoder 705.

i~YO 94!08427 ~~ ~ '~~ ~ i~~ ~ ~ PCflJP93/01381 ',:,, The two-dimensional variable-length coder 704 also serves to encode the AC coefficients, and to output encoded AC
coefficients as part of the VLC code signal S709.
The DC coefficient variable length coder 705 is operable to encode the DC coeff i c i ents 5708 , fo r exampi a , i n~...~cco rdance wi th the computer program shown in Fig. 8, and to supply the encoded DC coefficients as a signal S710 to the DCjAC coefficient multiplexer 708.
A variable length encoding table storage 707 serves to store the tables used by the coder 705. These tables may be as shown in Figs: 9A-9C.
More specifically, the variable length encoder 705 uses a DC coefficient, in the DC coefficient signal S708 to search the table shown in Fig: 9A for a size, that is, number of bits, and a code corresponding to the differential DC coefficient. The siZef ound from the table is, in turn, used to search the table shown in either Fig. 98 or 9C for a corresponding variable length code. 'The code found from the table shown in Fig. 9A is concatenated with the VLC code found from the table shown in one of Fig: 9B and 9C to produce a VAC-code signal 5710 f or the DC
coefficient which is output to the DC/AC coefficient multiplexer 708.
The intro de_preeision signal S26 is supplied to an input terminal 723 which applies it to a variable length encoding table mod i f i a r 706 .

fV~ 94/g8427 , ~ ~ ~° PC't/JF93/41381 The variable-length encoding table modifier 706 functions to control the storage 707, based on the intra_dc_precision code S26, to suppl y onl y a requi red porti on of the table shown l n Fi g .
gA to the variable length encoder 705. Specifically, when the intra~dc_precision c~de S26 has the value '00' , ,'.-01' , ' 10' , ' 7 1' , the modifier. 706 controls the storage 707 to output only the portion of the table shown in Fig. 9A corresponding to the size values 0-8; 0-9, 0-i0, 0-11 bits, respectively.
The modifier 706.can also control the storage 707 to supply the entire table shown in Fig. 9A to the variable length encoder 705 irrespective of the value of the intraldc-precision code S26.
However, this may cause supplying of unnecessary portions of the tabl a to the vari abi e-l ength encoder 705 , which may l ncrease the encoding time. Thus, it is desirable to output only the required portion of the table shown in Fig. 9A.
The modifier 706 also functions to control the storage 707 to supply the table shown in Fig. 9B to the encoder 705 when the Y flag: X702 is set, indicating that the DC coefficients 5708 correspond to a 'i~uminance block: The modifier 706 further f unction to c~ntr~ol the storage 707 to supply the table shown l n Fi'g . gC to the encode r 705 when eithe r the Cb f l ag S703 o r the Cr f'~ag: 5704 is set, indicating that the DC coefficients 5708 correspond to a chrominance block. Thus, the storage 707 outputs only the required and of the tables shown in Figs. 9B and 9C to the encoder 705.

9N~0 94/08427 PCf/JP93/01381 M..
~4 The DC/AC coefficient multiplexer 708 functions to multiplex the signal 709, representing the VLC encoded non-intra picture coefficients and the VLC encoded intra picture AC coefficients, with the signal 710, representing the VLC encoded intra picture DC coef f i c i ents , to p roduce an output s i gnal , arid. to supp l y thi s output signal to an output terminal 732 and thence to the buffer-memory unit 127 shown in Fig. 13.
As explained above with respect to Fig. 13, setting of one of the vi deo sequence start f 1 ag S20 , the GOP start f 1 ag S21 , the picture start flag 522, and the slice start flag S23 prompts the VLC encoder 126 to' generate a start code for a video sequence, GOP; picture and slice; respectively. The multiplexer 708 also multiplexes the start codes, the control information signal S25 used in the header,' and the motion vector signal S13, the quantization step width signal S18 and macroblock address signal 527; as appropriately encoded, and supplies this multiplexed i nf~ormati on to the ouirput to rmi na7 732 A decoding apparatus according to the present invention will now be described in m~re detail with reference to Figs: 18-20.
F.ig. 15 shows a decoding apparatus according to the present iwvention, and includes input terminal 150, buffer 151, VLC
decoder 152, inverse cfifferentiator 153, inverse scan converter 154,.inverse quantizer 155; inverse DCT circuit 156, adder 157, field memories 158, motion compensator 159, output terminal 160, field memory controller 161 and control information storage 162.

WO ~41084~7 ~ cc~~rT PCT/JF93101381 ~~~a~~~~,15 ._~, , '' ~ 5 5 A bit stream encoded by, for example, the encoding apparatus shown in Fig. 13 is supplied to an input terminal 150 which applies it to a buffer 151 that functions to store the encoded bit stream and then supply it to a VLC decoder 152.
As expl ai ned wi th ref a rence to Fi g . 2 ,~ '....the bi t st ream coonprises si.x layers: video sequence, GOP, picture, slice, macroblock (MS) and block. The encoded bit stream includes a star code at the beginning of each layer portion, followed by appropriate header information.
The encoding apparatus of Fig. 13 outputs a bit stream in which the encoding precision of DCT DC component coefficients can be switched from one precision (number of quantization bits) to another in video sequence; GOP; picture or slice units in.
accordance with the demanded picture quality. Accordingly, the decoding apparatus shown in Fig. l8 receives decoding precisions expressed in terms of quantization bits in video sequence, GOP, picture or slice units so that the technique of decoding di reci-current component coefficients can be changed adaptively.
~n more detail; a wn-bit intra_dc~,precision code, expressed ' in.v-quantization bits, is included in a- sequence, GOP, picture or slice header as information regarding the decoding precision of DC coefficients. The header is output by the encoding apparatus as part of the bit stream: The VLC decoder 152 shown in Fig. 15 receives the sequence; GOP; picture or slice header, and decodes the intro dc_precision code included therein as a signal S63 to W~ 9410~4Z7 PCTIJP93/~131 :r.~R:~.~ a ,<."
_;a 56 .
obtai n the decodi ng prec l s l on to be used for DCT DC coeff l c l ents .
The vLC decoder 152 supplies the intra_code_precision code S63 to an inverse differentiator 153 and an inverse q~antizer 155.
The vLC decoder 152 is operable to detect a start code indicating the beginning of a video sequence in_.-the bit stream, to set a sequence°start flag S100, and then to decode the vari abl a 1 ength encocJed sequence heade r l nformati on . The decode r 152 is further operable to detect a start code indicating the s beginning of a GOP, a picture or a slice in the bit stream, to set a GOP-start flag 5101, a picture-start flag S102 or a slice-start flag S103, and to decode the header information for the GOP, the picture or the slice, respectively, using a variable length decoding techqique. The decoder 152 supplies the decoded header information to a control information storage 162.
The control l nformati on storage 162 se rues to suppl y the .dontrol information stored therein as a control-information signal 5114 to a variety of blocks in the motion video picture dec~ding apparatus.
The YLC decoder 152 i~s also operable to detectrthe beginning of- a macrobl oc6c- l n the bi t stream and to set a MB-start f l ag S104 at each such ddtecti~n. The decoder 152 decodes the MB header iof ormation to obtain a MB address indicating a location of the MB in the picture being decoded. The VLC deeoder 152 is additionally operable to decode the encoded picture data in the bit stream to produce an output signal 550, a quantization step .. ' WO ~41iD8427 ~y ~,~, ~'~ ~ ~~ ~ P(.T/JP93/01381 gin= ..
..., (or, strictly speaking, inverse quantization step) signal S57, a motion vector signal S61 and motion compensation mode signal S62. The decoder 152 supplies the signal S50 to the inverse differentiator 153. The VLC decoder 152 is explained in detail below with reference to Fig. 19.
The inverse differentiator 153 is adapted to operate in a manner complementary to the differentiator 125 of Fig. 13 to produce a quantized DCT c~efficient signal S51 and to supply the signal S51 to an inverse scan converter 154. The inverse differentiator 153 is explained in detail below with reference to Fig. 20.
The inverse scan converter 154 is adapted to scan the quantized DC~' coefficients S51 in a zigzag-scan manner in an o rde r f rom a lowest-f requency coeff i ci ant to a hi ghest-f requency coefficient t~ pPOduce a signal S52, and to output the signal S52 t~ the inverse quantizer 155.
The inverse qu~ntizer 155 is adapted to receive the inverse-~dantizatibn step signal S57 and to carry out inverse quanti zati on on the si gr~al S52 to produce a b1 ock DCT coeff i ci ant signal S53; an~i o supply the signal 553'to an inverse DCT
circuit i56. The inverse quantizer i55 has the same construction as the inverse quantizer 115; shown in cJetail in Fig. i5.
The inverse DCT ca rcuit 156 functions to perform an inverse DCT transformation on the coefficients in the signal S53 to produce a signal S54; and to supply the signal S54 to an adder W~ 94/0427 PGTlJP93/01381 157.
The motion compensator 159 functions in a similar manner as the motion compensator 122 shown in Fig. 13. The motion compensator 159 produces a predicted picture S56 from an already decoded picture stored in field memories 158,,and supplies the predicted picture S56 to the adder 157.
More specifically, in the forward, backward or bidirectional prediction mode, the motion compensator 159 shifts the read address of the field memories 158, from a position which corresponds to a 1~cation of a block of difference data S54 being output to the adder 157, by a displacement corresponding to the motion vector 561. The motion.compensator 159 then reads out picture data at the shifted read address and supplies it to the adder 157 as the predicted picture S56. Motion compensation is typically carried out in block units each comprising 16 x 16 pixels:
Zn lthe iptra picture prediction mode, the motion compensator doss not supply a pied cted picture S56 to the adder 157 because the signal 554 repre5en~s standalone picture data, that is, picture data which was not predictiveiy enc~ded relative to ana~the r p i ctu re The adder 157 serves to predi~tively decoded the data supplied thereto by adding the difference signal S54 to the predicted picture S56 on a pixel-by-pixel basis to produce decoded picture data S55, and to supply the picture data S55 to a i . y ;
fnr i~. 'x ":L 4i .:.
i~0 X4/08427 PCT/JP93/OI381 the field memories 158.
The field memories 158 se we to store the decoded picture data S55 at addresses specified by a picture command signal 559, to output the stored picture data to the motion compensator 159 in accordance with a motion compensating reference picture command signal 558 for use in generating a predicted picture which will, in turn, be used for decoding a picture encoded with forwaed, backward or bidireetional predictive encoding. The memori es 158 al so se rve to output the stored pi ctu re data to a termina't 160 as a playback picture at a timing determined by an output picture command signal S60. Only data for I and P pictures is stored in the field memories 158, that is, data for a B
pi ctu re i s not stoked the re i n . Thi s i s because data fo r a B
picture is not used in the forward; backward and bidirectional predictive decoding.:
The field memory controller 1f1 functions in the same manner as the-field memory unit controller 124 shown in Fig. i3. The controller 161 generates the motion compensating ref erence picture command signal S58; the picture command signal S59 and th~~-~~output , picture : command vsi final S60 in synchronism , with the picture-start flag S102.
Fi g. 19 shows a detai 1 ed embodi ment of the VLC decode r 152 .
The VAC decoder 152 is seen to include input terminals 800; B21, 823, 825; block: counter 801, flag generator 802, DC/AC
caefficient separator 803, VLG decoder 804, DC VLC decoder 805, '~ .~~~~., ,~: '_x .~ : w.
VLC table modifier 806, VLC table storage 807, b-~ocl~ing circuit 808, intra flag generator 8U9, output terminal 827 and switch 830.
In a processing circuit not shown in Fig. 19, a portion corresponding to the picture data is extracted from the bit stream supplied from the buffer 151. The extracted portion is then suppl l ed as a l gna7 S81 1 to an l nput to rmi nal 800 whi c,h apple's it to a switch 830.
The motion compensation mode signal S62 is supplied to an input terminal 821 which applies it to an intra flag generator 809.
The l nt ra f l ag gene rato r 809 f unct l ons to set an l nt ra f 1 ag S805 , to a val ue of , for exampl a 1 ; when the moti on compensati on mode signal S62 indicates the intra picture-encoding (intra picture-prediction) mode. The generator 809 supplies the intra flag 5805 to switch 830 at the logic value 0 when the signal S62 does not indicate intra picture. encoding; that is, indicates forward, backward or'bidirectional encoding;
The switch 83Q serves to select a pole ~ 'or Bwhen the intra flag S805 has the logic value 0 or 1, respectiVeiy; so that when non-infra picture encoding is indicatQd, ttse extracted portion of ' the encoded pi ctu re data S811 l s suppl l ed as a s l final S806 to - a two-dimensional VLC decoder 804, and when infra picture encoding is indicated, the signal S811 is supplied try a DC/AC
coefficient separator 803.

~O 9/08427 ~ ~ ~ ~ (~ ~~ ~ PG'T/JP93/OI381 The two-dimensional VLC decoder 804 is adapted to decode the encoded coefficients 5811 using a variable length code such as the well known two-dimensional Huffman code to produce a signal S809; and to output the signal S809 to a blocking circuit 808.
The DC/AC coefficient separator 803 functions to split the signal 5811 into AC coefficients S807 which are supplied to the two-dimensional VLC decoder 804, and into DC coefficients 5808 which are supplied to a DC coefficient VLC decoder 805.
The decode r 804 also serves to decode the encoded AC
coefficients, and to output decoded AC coefficients as part of the signal S809.
The DC coefficient; VLC decoder 805 is operable to decode the DC coefficients S8~8, for example, in accordance with the computer program shown in Fig. 12, and to supply the decoded DC
coefficients as a signal S810 to the blocking circuit 808.
A YLC ta.bla storage 807 serves to store the tables used by the decoder 805. These tables .may be as shown in Figs. 9A-9C.
More specifically, the decoder 805 uses a DC coefficient in the DC c~effacient~si~nal S808 to search the table shown in Fig.
8B-:°or 9C for a size, that is, number of bits: The size found from the table is; in turn, used to search the tabla shown in F~g.:9A for a corresponding decoded DC coefficient. The decoded DC coefficient found from the table shown in Fig. 9A is output tofihe blocking circuit 808 as a signal S801.
The blocking circuit 808 functions to receive coefficients Wed 94/084Z? P(.'T/JP93/01381 ,."., _ ~~~~ ~ f s2 =x x from the decoders 804, 805, to block these coefficients into a block of 8 x 8 coefficients, and to supply these coefficients to an output terminal 827 as the signal S50 for application to the inverse differentiator 152 of Fig. 18.
The blocking circuit 808 also functions to_.$et a flag 5820 each time it. outputs a block to the output terminal 827.
The MB-start f l ag 5104 i s suppl i ed to an i nput to rmi nal 823 which applies it to a block counter 801.
The block counter 801 is adapted to receive the flag 5820, to count the number of times the flag S820 is set to produce a block count signal S801; and to supply the block count 5801 to a f i ag gene rato r 802 : Vdhen the MB-start f 1 ag S 104 i s set , the ~ldck counter 801 is reset to an initial value of unity.
The f 1 ag gene rat~r 802 i s adapted to gene rate ( set ) a Y f 1 ag 8802 when the value of 'tie block count S801 is 4 or smaliar to indicate that a luminance Y block is being supplied. The ger~erato~ X02 is also adapted to set a Cb flag 5803 when the value of the block count S801 is equal to 5, to indicate that the clirominance Cb b7~ck is being-supplied. fibs generator 802 is f a r.the r adapted to set a Cr f l ag S804 when the val ue of the b1 oc k count S~01 i s equal tip 'f , to i.ndi ca Ve that the chromi nance C r b'i ock i s bei ng suppl i ec9: The generator 802 suppl i es the si final s 502., 5803, 5804 to a VLC table modifier 806.
The intra_dc_precision code S63 is supplied to an input terminal 825 which applies it zo the VLC table modifier 806.

aW~ 94188427 PG°~/JP~3/01381 ''~' ~. '~.' fi_y ' ~' y The VLC table modifier 806 functions to control the storage 807, based on the intra dc_precision code S63, to supply only a requi red portion of the table shown in Fig. 9A tc the decoder 805. Specifically, when the intra_dc_precision code S63 has the value '00', '01', '10', '1i', the modifier 80.6 controls the storage 807 to output onl y the porti on of the tabl a shown i n Fi g .
9A corresponding to the size values 0-8, 0-9, 0-10, 0-11 bits, respectively.
The modifier 806 can also control the storage 807 to supply the entire table shown in Fig. 9A to the decoder 805 irrespective of the value of the intra dc_precision code S63. However, this may cause supplying of unnecessary portions of the table to the decoder 805, which may increase the encoding time. Thus, it is desirable to output only the required portion of the table shown in Fig: 9~.
The modifier'806 also functions to control the storage 807 'to supply the table shown in Fig. 9B to the decoder 805 when the Y f'Dag 5802 is set, indicating that the QC coefficients 5808 correspond to a luminance block. The modifier 806 further functions to control the storage 801 to supply the table shown ~i n F i g . 9C to the decode r 805 when ei the r the Gb f 7 ag 5803 o r the Cr flag 5804 is set, indicating that the DC coefficients 5808 correspond to a chrominance block. Thus, the storage 807 outputs only the required one of the tables shown in Figs. 9B and 9C to the encoder 805.

WO 94/0847 PC°T/JP93/01361 '~'~ ~!~ l~~c Fig. 20 shows a detailed embodiment of the inverse differentiator 153.
The inverse differentiator 153 is seen to include input terminals 600, 621, 623, 625, 627, 629, DC/AC coefficient separator 601, blocking circuit 602, block coynter 603, flag generator 604., registers 605, 611, initial value generator 606, switches 607, 610, 614, 615, 616, OR gate 608, intra flag generator 609, subtractor 612, adder 613 and output terminal 620.
The quanti zed DCT coeff i ci eats S50 output by the i nve rse-VLC
obit 152 are supr~lied to an input torminal 600, which applies the signal S50 to a block counter 603 and a switch 610.
The MB-start flag 5104 is supplied to an input terminal 625 which applies it to the block counter 603.
The block counter 603 functions to count the number of blocks in ~adh macroblock of the signal S50 to produce a block count signal S601 and to supply the signal 5601 to the flag generator-60~. Specifically, the bloc k count S601 has a value of 1 , 2, 3, 4; 5, 6 as the respective blocks Y0, Y1 , Y2, Y3, Cb, Cr;in each maer~block are supplied. '~hqn the mac-roblock start flag S104-is set, the bl~ck counter 603 is res~t.v Tie f l ag gene cato r 604 i s adapted to gene rate ( set ) a Y f 1 ag S602 when the value of the block couht 5601 is 4 or smaller to indicate that a luminance Y block is being supplied. The generator 604 is also adapted to set a Cb flag 5603 when the val ue of the b1 ock count S601 i s equal to 5 , to i ndi cate that the W4 941042? PG°IlJg'93/01381 ., chrominance Cb block is being supplied. The generator 60~ is f a rthe r adapted to set a C r f 1 ag S60~ when the val ue of the b1 oc k count S609 is equal to 6, to indicate that the chrominance Cr block is being supplied. The generator 604 supplies the signals S602, S603, 5604 to switches 695, 696.
The motion compensation mode signal S62 is supplied to an input terminal 621 which applies it to an intra flag generator 609.
The i nt ra f 1 ag gene rator 609 f uncti ons to set an i nt ra f 1 ag S~06, to a dalue of, for exempla 1, when the motion compensation mode signal S62 indicates the intra picture-encoding (intra picturd-prediction) mode. The generator 609 supplies the intra f1'ag 5606 at the logic value 0 when the signal S62 does not indicate infra picture encoding, that is, indicates forward, backward or bidirectional enc~ding. The intra flag S606 is supplied to switches 61O and 6i4:
Theswitch 61O serves to select a pole A or B when the infra f l ag S606 has the ~ l ogi c vai ue 0 'or 7 , respectivel y, so that when non--infra picture enc~ding is ind~catsdthe coefficient signal 56~ is Supplied as a signal 5609 to a blocking circuit 602,. and when intra picture encoding is indicated; the coefficient signal 550 is supp'i.ied to the DC/AC coefficient separator 601.
The blocking circuit 602 is adapted to block the coefficients 5609 into an 8 x 8 block of coefficients, and to supply the blocked coefficients to a terminal 620 for application W~ 94/084x7 PGT/31a93/01381 ss to the inverse scan converter 154 shown in Fig. 16 as the signal 551.
The DC/AC coefficient separator 601 is adapted to spl it the coefficient signal S50 into AC coefficients S610 which are supplied to the blocking circuit 602, and into~.._DC coefficients S605 which are supplied to an adder 613.
The adder 613 serves to receive a delaged signal S615 and the quantized DC coefficients S605 and to add the signals 5605, S615 to produce a signal S6S1 representing the original DC
coefficients. she four chrominance blocks YO to Y3 and the two ~hrominance blocks Cb ahd Cr undergo inverse differentiation processes independently. The adder 613 supplies the signal S611 to the blocking circuit 602 and a switch 616.
'The adder 613; switches 615, 616 and registers 605 function to perform inverse differentiation of received coefficients, as was described with' reference to Figs. 5A and 5B.
More specifically, when the flag generator 604 sets the Y
flag X602. and resets the Cb and Cr flags 5603 and 5604, i nd i cat i ng that he DC coeff i ci ants S605 are f rom a l umi nance block, the. switches 615 and 616 select poles C and C' respectively, to supply'the DC cosfficie0ts S611 to a Y' register of the'registers 405. The Y register 405 delays the luminance c~efficients by a time corresponding to one block, then supplies these coefficients to a pole C of the switch t15, which applies the coefficients as the delayed signal 5615 to the adder 613.

9~() 94/~427 PCT/JP931013~1 ' ~ s7 When the f 1 ag gene rator 604 sets the Cb f 1 ag S603 and resets the Y and Cr flags 5602, S604, indicating that the DC
coefficients 5605 are from a chrominance Cb block, the switches 615 and 616 select poles D and D' respectively, to supply the DC
coef f i c i ants S6'i 1 to a Cb rag i ste r of the rag i s~e.rs 605 . The Cb register 605. delays the chrominance Cb coefficients by a time corresponding to one macroblock, then supplies these coefficients to a pole D of the switch 615, which applies the coefficients as a delayed signal to the adder 613.
When the f lag generator 604 sets the Cr flag S604 and resets the Y and Cb flags S602 and S603, indicating that the DC
coefficients S605 are from'a chrominance Cr block, the switches 615 aid 616 select poles ~ and E' respectively. The chrominance Cr c~efficients is delayed for one macroblock of time, then ~Pplied to the adder 613.
The bl~cking circuit 602 also blocks the DC coefficients S611 ~f a block with AC coefficiants S610 from the DC/AC
coefficient separai<or 601, and supplies the result as the signal 551 too the invbrse-scan converter 154 shown in Fig. 18.
When ;the MB address signal 564 for the macroblocks being d~coded.does not convey contiguous values or the DC coefficients belong to a first macroblock of a slice, the Y, Cb and Cr registers 605 are reset to an initial value S613 by a register initial value generator 606.
The intra_dc~predision code S63, which' represents the 1~V~ 94/118427 P1:'f/JF93/~1381 ~,,<,y 6g encoding precision f or DC coefficients, is supplied to an input terminal 629 that applies it' to the register initial value generator 606. , The register initial value generator 606 is operable to generate the initial value S673 for the Y, Cb ,arsd Cr registers 405 in accordance with the intra dc_precision code S63 as shown i n the tabl a p resented above wi th respect to the regi ste r i ni ti al value generator 406 shown in Fig. 16.
The switch 607 is put into an OFF or ON state when a coot rot sigyal S620 has a value of, for example, zero or one, respectively: When the switch 607 switches into the ON state, the initial value S6t3 is applied to each of the registers 605.
The control signal S620 puts the switch 60T into the ON state when thc~ MB address- signal S64 of the MBs experiencing the intra picture decoding process does not convey contiguous values or the DC .coefficients belong to a first macroblock of a slice.
The control signal S620 may be produced as follows.
The macroblock address signal S64 is supplied to an input terminal 623 which applies it to the switch 614 and to a subtractor -612: Ttae switch 614 functions to suppl y the MB
add ress S64 to a regi ste r 611 when the i nt ra f 1 ag 5606 i nd i Gates intra picture encoding. The register 611 is operable to delay the MS address S64 by a time corresponding to one MB, and to supply the delayed signal S60T to a subtractor 612.
The subtractor 612 serves to subtract the signal S60T from ~f~ 9418427 ~ ~ ~ ~ L~ ~ ~~ PCT/JP93/01381 the si anal S64 to produce a si gnal S608 - S6~ - S607, and to apply the signal 5608, representing address differences between adjacent macroblocks, to an input of an OR gate 60b,.
The slice start flag 5103 is supplied to an input terminal 627 whi ch appi i es i t to anothe r i nput of the O)~~-gate 608 .
The OR gate 608 functions to output the logic value 1 when the difference signal 5608 is greater than unity (S608 > 1) or the slice start flag S103 is set. The OR gate 608 functions to otherwise output the-logic value 0.
The present invention can also be applied to a motion video picture signal to be encoded with an encoding precision of other than eight quantization bits.
When the range of the val ue of the DC component coeff i c i ents resulting from a aCT process on an input signal in an encoding apparatus is N bits, and an encoding precision of M biis, 1<_M<_N, is specified using the intra dc~precision code, then the quanti zati on step wi dth used i n the eluanti ze r 115 of the encodi ng apparatus shown i n Fi g . 13 i s set at 2H~ and the i ni ti al val ue 5413 shown in Fig. i6 is set at 2H/2v The ~/LC processing carried ocat- by the. VLC uni t 126 of Fi g . 13 i s based on data f rom the t~bl es shown i n Fi gs . ~ 21A and 21 B i nstead of Fi gs . 8B and 9C .
The data i n the tabl es of Fi gs . 21A, 2 7 B does not have to be fixed. Instead, it may be variables that result in an optimum post-encoding compression factor. The values of the variables are dete rmi ned f rom stati sti cal observation of the i nput pi ctu re yV~ 9~41m8~27 PCf/JP93/01381 ~) f t r ~~ .,.
N:~:<~.
signal.
Decoding of a picture encoded using the technique described above now will now be explained.
A value 2H~ is used as the inverse quantization step'width in the inverse quantizer 155 of the decoding apparatus shown in Fi g . 18 . A oral ue 2M/2 i s used as an i ni ti al val ue S6 i 3 shown i n Fig. 20 f or the inverse differentiation process. The inverse VLC processing carried out by the VLC decoder 152 is based on data in the tables of Figs. 21A, 21B instead of the Figs. 9B, 9C.
A technique for manufacturing the optical disk referred to above will now be described with reference to Figs. 22-23.
As shown in Fig. 22, a raw disk made of glass or the like is prepared. The surf ace of the raw disk is then coated with a recording material made of, typically, a photoresist substance to produce a raw disk for recording.
As shown in Fig. 73, picture data (or video data) resulting from ~n encoding pr~cess performed by an encoding apparatus (or a vidieo encoder) as described above is stored in a temporary buffer: At the same ~me;~audio data resulting from an encoding pr~c~ss performed by an audio encader is stored in another temporary buffers The picture and audio data stored in the temporary buffers are multiplexed with a synchronization signal by a multiplexer MUX. Error-correction codes are then added to the output of the multiplexer MUX by an error-correction circuit ECC. Subsequently, the output of the error-correction circuit W~ 94/~8427 Z ~ ~ ~.'~ t~ ~ y PGT/.1P93/01381 ECC undergoes predetermined modulation in a modulator MOD. The modulated data output by the modulator MOD is finally stored in a certain format temporarily in a magnetic tape Lypically to produce the desired software.
If necessary, the software is edited during~a premastering process to produce a formatted signal that can be recorded into an optical disk. As shown in Fig. 11, modulated in accordance with this formatted signal, which is also known also as a a reco rdi ng s i final , a 1 ase r beam i s then appl i ed to the photo res i st on the raw disk. In this way, the photoresist experiences an exposure process to record information conveyed by the recording signal thereon.
iVk~en the raw disk is de~reloped, pits appear on the surface thereofa The raw disk processed in this way then undergoes, typically; an electroforming process and the like to transfer the pits from the glass raw disk to a raw disk made of a metal. A
metallic scamper is further produced from the metallic raw disk to b~ used as a mAld.
A material such as pMMA-~acrylate) and P~ ~polycarbonate) i s ;vthen ~rou red i nto the mol d through an i n jecti on process o r the l i ke and hardened therein. As an alternatieoe, the metal l is stamper can be coated with an ultraviolet-ray hardened resin referred to as 2P and then an ultraviolet ray is applied to the resin for hardening it. In this way, the pits are transferred f rom 'the metal l i c stamps r to a repl i ca, the real n hardened by the VV~ 94/042'7 PCT/JP93ltli381 '~~.~~~~~!~
r..

ultraviolet ray.
Subsequently, a reflective film is created on the replica produced in the processes described so far by deposition, sputtering or the like. As an alternative, a spin-coating process can also be used to create such a reflective film.
The raw disk then undergoes a machining process to trim the raw disk to its inner and outer diameters or another necessary process, for example, to attach the raw disk to another raw disk.
Further, a label and a hub are affixed thereon. Finally, the raw disk is put in a cartridge, completing the process of producing an optical disk.
In this embodiment, the generation of difference data based ~n a predicted piqture and the DCT processing of data are carried out in field units., However, processing can be switched from f i a l d uni is to f rime units i n orde r to i nc cease the post-encodi ng cc~mpressi~n factor. By switching the unit of the processing, the generation of difference data based on a predicted picture and the DCT p rocessi ng' of data can then be pe rf ormed i n f rams un i is .
Although an illustrative embodiment of the present i nventi on, and vari ous 'moth f i cati ons th~reof ; have been desc ri bed in detail herein with reference to the accompanying drawings, it i ~ t~ be uncle rstood that the i nvention i s not l i mi ted to thi s precise embodiment and the described modifications, and that various changes and further modifications may be effected therein by one skilled in the art without departing from the scope or WCD 94/0&827 :~ .~ ~ :'~. ~ ~ ~ ~ ;~ PGT/.~P93I013~1 c4; .~ ,,~

spirit cf the inventi~n as defined in the appended claims.

Claims (28)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY OR
PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A method of encoding a video signal having pixels represented by n bits, n being an integer, comprising the steps of:

receiving a picture quality signal;

selecting an encoding precision of n+m bits, m being a non-negative integer, in accordance with said picture quality signal;

orthogonally transforming said video signal to produce direct current component coefficients and alternating current component coefficients;

quantizing only said direct current component coefficients using the selected encoding precision;

obtaining a difference between a first of said quantized direct currentcomponent coefficients and an initial value set in accordance with said selected encoding precision; and variable length encoding the differentiated direct current component coefficients using variable length coding tables, each of said coding tables having a length that is a function of said selected encoding precision.

2. A method according to claim 1, wherein said picture quality signal corresponds to a portion of said video signal selected from a video sequence, group of pictures, picture, slice, macroblock and block.

3. A method according to claim 2, wherein said block has a size of 8 pixels × 8 lines.

4. A method according to claim 1, wherein n has a value of eight and n+m has a value of eight to eleven.

5. A method according to claim 1, wherein the step of orthgonally transforming comprises performing a discrete cosine transformation.

6. A method according to claim 1, wherein said direct current component coefficients include luminance direct current component coefficients and chrominance direct current component coefficients.

7. A video recording medium having recorded thereon instructions for allowing an encoding apparatus to read and write a video signal according to the method of claim 1.

8. A video recording medium according to claim 7, wherein said video recording medium is an optical disk.

9. An apparatus for encoding a video signal having pixels represented by n bits, n being an integer, comprising:

means for receiving a picture quality signal;

means for selecting an encoding precision of n+m bits, m being a non-negative integer, in accordance with said picture quality signal;

means for orthogonally transforming said video signal to produce direct current component coefficients and alternating current component coefficients;

means for quantizing only said direct current component coefficients using the selected encoding precision;

means for obtaining a difference between a first of said quantized direct current component coefficients and an initial value set in accordance with said selected encoding precision; and means for variable length encoding the differentiated direct current component coefficients using variable length coding tables, each of said coding tables having a length that is a function of said selected encoding precision.

10. An apparatus according to claim 9, wherein said picture quality signal corresponds to a portion of said video signal selected from a video sequence, group of pictures, picture, slice, macroblock and block.

11. An apparatus according to claim 10, wherein said block has a size of 8 pixels × 8 lines.

12. An apparatus according to claim 9, wherein n has a value of eight and n+m has a value of eight to eleven.

13. An apparatus according to claim 9, wherein said means for orthgonally transforming comprises means for performing a discrete cosine transformation.

14. An apparatus according to claim 9, wherein said direct current componen coefficients include luminance direct current component coefficients and chrominance direct current component coefficients.

15. A video recording medium having recorded thereon instructions for allowing the apparatus of claim 9 to encode a video signal.

16. A video recording medium according to claim 15, wherein said video recording medium is an optical disk.

17. A method of decoding an encoded video signal corresponding to an original video signal having pixels represented by n bits, n being an integer, comprising the steps of:

receiving a picture quality signal;

selecting a decoding precision of n+m bits, m being a non-negative integer, in accordance with said picture quality signal;

extracting encoded direct current component coefficients from said encoded video signal;

variable length decoding only said encoded direct current component coefficients using variable length coding tables, each of said coding tables having a length that is a function of the selected decoding precision;

obtaining an inverse difference between a first of the variable length decoded direct current component coefficients and an initial value set in accordance with the selected decoding precision; and inverse quantizing the inverse differentiated direct current component coefficients using the selected decoding precision.

18. A method according to claim 17, wherein said picture quality signal corresponds to a portion of said video signal selected from a video sequence, group of pictures, picture, slice, macroblock and block.

19. A method according to claim 18, wherein said block has a size of 8 pixels ×
8 lines.

20. A method according to claim 17, wherein n has a value of eight and n+m has a value of eight to eleven.

21. A method according to claim 17, further comprising the step of inverse orthogonally transforming the inverse quantized direct current component coefficients.

22. A method according to claim 17, wherein said encoded direct current component coefficients include encoded luminance direct current component coefficients and encoded chrominance direct current component coefficients.

23. An apparatus for decoding an encoded video signal corresponding to an original video signal having pixels represented by n bits, n being an integer, comprising:
means for receiving a picture quality signal;
means for selecting a decoding precision of n+m bits, m being a non-negative integer, in accordance with said picture quality signal;
means for extracting encoded direct current component coefficients from said encoded video signal;
means for variable length decoding only said encoded direct current component coefficients using variable length coding tables, each of said coding tables having a length that is a function of the selected decoding precision;
means for obtaining an inverse difference between a first of the variable length decoded direct current component coefficients and an initial value set in accordance with the selected decoding precision; and means for inverse quantizing the inverse differentiated direct current component coefficients using the selected decoding precision.

24. An apparatus according to claim 23, wherein said picture quality signal corresponds to a portion of said video signal selected from a video sequence, group of pictures, picture, slice, macroblock and block.

25. An apparatus according to claim 24, wherein said block has a size of 8 pixels × 8 lines.

26. An apparatus according to claim 23, wherein n has a value of eight and n+m has a value of eight to eleven.

27. An apparatus according to claim 23, further comprising the step of inverse discrete cosine transforming the inverse quantized direct current component coefficients.

28. An apparatus according to claim 23, wherein said encoded direct current component coefficients include encoded luminance direct current component coefficients and encoded chrominance direct current component coefficients.