CA2126743A1 - Programmable error-checking matrix for digital communication system - Google Patents
Programmable error-checking matrix for digital communication systemInfo
- Publication number
- CA2126743A1 CA2126743A1 CA002126743A CA2126743A CA2126743A1 CA 2126743 A1 CA2126743 A1 CA 2126743A1 CA 002126743 A CA002126743 A CA 002126743A CA 2126743 A CA2126743 A CA 2126743A CA 2126743 A1 CA2126743 A1 CA 2126743A1
- Authority
- CA
- Canada
- Prior art keywords
- error checking
- data fields
- fields
- communication
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
- H04L1/0083—Formatting with frames or packets; Protocol or part of protocol for error control
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Communication Control (AREA)
- Detection And Correction Of Errors (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Maintenance And Management Of Digital Transmission (AREA)
- Computer And Data Communications (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
A programmable system for checking for protocol errors in a communication system includes a matrix for generating error checking signals selected by data fields utilized to implement a communication. If the configuration or protocol is changed the system facilitates reprogramming to compensate for the change.
A programmable system for checking for protocol errors in a communication system includes a matrix for generating error checking signals selected by data fields utilized to implement a communication. If the configuration or protocol is changed the system facilitates reprogramming to compensate for the change.
Description
212~7~3 " 1 PROGRAMMABLE ERROR-CHECKING MATRIX FOR DIGITAL
COMMUNICATION SYSTEM
j 5 Field ~$ t~ Inven~iQn The present ~nv~ntion relate~ gener~lly to error ~'' checking sy~tem~ and moro particularly relates to programmably :~ 10 checking the intersection ~atrix o multiple contrsl and 11 identifier fields ~n digital com~unication sy~tem~.
.~ .
Des~iption o~ the Rel~va~t Art All digital communication systems requir~ a set of ~5 rules, called a protocol, to control communication~ between different module~ in ths ~y~tem. It is well known to ~ implement error checking systems to assure that a particular : communica~ion does no~ violate the protocol.
In many ~ystems a communication includes a handshaking operation to establish a link between two modules.
Various data fields are transferred during various phases of : an operation that allow the modules to gain control of a communication channel, identify each other and the type of operation to be performed, to verify thQ readiness of each module to perform the operation, and to trans~er data over the . ~ communication chann~l. The protocol specifie~ the value~ of . data fields that may be g~nerated during each o~ these phases.
One of the advantages of digital systems i8 the . ability to recon~igure the hardware by adding or deleting modules or functions and to change th~ protocol to change the . field value~ utilized during the di~ferent phase~. Howev~r, - existing error checking function are generally not . reconfigurable thereby limiting their utility in digital ; communication systems.
. 35 ~ma~y of the I W ention The present invention is a reconfigurable error . checking syste~ ~or u5e in digital co~munication ~yste~. The , .
,, ':
21267~3 error checking ~ystem utilize~ the values of an error checking function to check whether the data field~
generated during a particular communication are allowed or forbidden by a communication protocol, The system can be reconfigured by modifying the error checking function.
According to one aspect of the invention, error checking ~ignals are programmably stored and selected by particular combinations of fields generated during a communication operation. The value of the selected error checking ~ignal indicates whether the values of the particular combination of fields is allowed by the protocol.
According to another aspect of the invention, the error checking ~ignals are generated by a hard-wired matrix decoder. The particular error signal generated is selected by a particular combinations of fields generated during a communication operation. If the error signal has a predetermined value then the particular comblnation of fields is forbidden by the protocol. Row and column mask registers programmably ~tore error mask/configuration signals, having either a masking or non-masking value, which are selected by the fields included in the particular combination. The selected error signal and error mask/configuration ~ignals are provided to a logic circuit which ahanges the value of the selected error signal if its value is the predetermined value and a selected mask/configuration signal has the masking value.
I According to another aspect of the invention, 1 30 the error ahecking system is included in every module of a communication system to provide for fault-tolerance to - allow checking of the communication channel for errors.
Further features and advantages will become apparent in view of the appended drawing~ and following detailed description.
Brie~ Description of the Drawinqs Aspects of the present invention are illustrated, merely by way of example, in the . ~ . .. ... .. . . .
212~7~3 2a accompanying drawings in which:
Figure 1 depict~ a shared bus communication sy~tem that can be monitored by the error checking systems of the present invention;
Figure 2 shows the arbitration, command, and databases of a basic shared bu~ operation;
Figure 3 is a block diagram of an embodiment of the present invention which supports full programmability of the error conditions to be checked;
Figure 4 i8 a block diagram of a second pxeferred embodiment of the invention which reduces the number of storage elements required in the first ~bodiment, and in many application3 reduce~ the gate count;
Figure 5 depicts a fully programmable error checking matrix according to the present invention;
Figure 6 depicts a matrix decoder having columns identified by different transfer length values and rows identified by different bus commands; and Figure 7 depict~ a COMMAND/HANDSHAKE hard-wired error checking matrix.
D2scription of the Preferred Embodiments The present invention is an error checking system having general utility in many types o~ digital communication 3y~temY. Many of the features of the system can better 21267~3 appreciated when described in the context of a particular bus system. In the following detailed description the error checking system will be described with reerence to a bus subsystem utilized in computer~ manufactured by Tandem Computer~, Inc. The bus subsystem will be de~cribed only in sufficient detail to support the detailed description of the invention.
Fig. 1 depicts a shared bus communication system including a CPU board 10 having several modules that communicate via a shared bus (IBUS) 12. These modules include i a processor interface chip (PIC) 14, a maintenance diagnostic chip (MDC) 16, a memory interfac~ chip (MIC) 18, and two bus interface modules (IPB X and IPB_Y) 20 and 22.
, Th~ IBUS 12 is synchronous parallel data path over i 15 which independent module~ may transfer address and data ~ information in a structured environment. The bus operations ,~ are synchronous with a basic system clock. All ev~nts on the IBUS occur relative to the rising edge of the clockO Two basic operations over the bus are defined; Arbitration and Transfer, each capable of occurring simultan~ously.
The Arbitration operation allows one of the module~
to become a master to gain sole ownership of the IBUS.
Modulee desiring to gain ownership of the IBUS (Requestor modul~s) must arbitrate and gain ownership of the IBUS before ~25 attempting to trans~er information.
The Transfer operation allows a Requestor that has gained ownership of the ~BUS to send data to or receive data from a Responder module and includes Command and Data Phases.
During the Command Phase, the Requestor, after arbitrating and gaining ownarship of the IBUS, places and address of a selected module on the Address~Data lines and a command on the ,l Handshake lines~ During the Data Phase, data is transferred rj between the Requestor and Responder. The length of the tran~fer i~ determined by the Reque~tor during the Command ~,l 35 Phase and can range from a 6ingle byte to many word~.
Fig. 2 depicts ~he arbitration, command, and data phase~ of a basic IBUS opera~ion. Requestors X and Y a~sert their Arb lines to request ownership o~ the IBUS and SC
~1 ,~1 ;l ": . :' . . ~
COMMUNICATION SYSTEM
j 5 Field ~$ t~ Inven~iQn The present ~nv~ntion relate~ gener~lly to error ~'' checking sy~tem~ and moro particularly relates to programmably :~ 10 checking the intersection ~atrix o multiple contrsl and 11 identifier fields ~n digital com~unication sy~tem~.
.~ .
Des~iption o~ the Rel~va~t Art All digital communication systems requir~ a set of ~5 rules, called a protocol, to control communication~ between different module~ in ths ~y~tem. It is well known to ~ implement error checking systems to assure that a particular : communica~ion does no~ violate the protocol.
In many ~ystems a communication includes a handshaking operation to establish a link between two modules.
Various data fields are transferred during various phases of : an operation that allow the modules to gain control of a communication channel, identify each other and the type of operation to be performed, to verify thQ readiness of each module to perform the operation, and to trans~er data over the . ~ communication chann~l. The protocol specifie~ the value~ of . data fields that may be g~nerated during each o~ these phases.
One of the advantages of digital systems i8 the . ability to recon~igure the hardware by adding or deleting modules or functions and to change th~ protocol to change the . field value~ utilized during the di~ferent phase~. Howev~r, - existing error checking function are generally not . reconfigurable thereby limiting their utility in digital ; communication systems.
. 35 ~ma~y of the I W ention The present invention is a reconfigurable error . checking syste~ ~or u5e in digital co~munication ~yste~. The , .
,, ':
21267~3 error checking ~ystem utilize~ the values of an error checking function to check whether the data field~
generated during a particular communication are allowed or forbidden by a communication protocol, The system can be reconfigured by modifying the error checking function.
According to one aspect of the invention, error checking ~ignals are programmably stored and selected by particular combinations of fields generated during a communication operation. The value of the selected error checking ~ignal indicates whether the values of the particular combination of fields is allowed by the protocol.
According to another aspect of the invention, the error checking ~ignals are generated by a hard-wired matrix decoder. The particular error signal generated is selected by a particular combinations of fields generated during a communication operation. If the error signal has a predetermined value then the particular comblnation of fields is forbidden by the protocol. Row and column mask registers programmably ~tore error mask/configuration signals, having either a masking or non-masking value, which are selected by the fields included in the particular combination. The selected error signal and error mask/configuration ~ignals are provided to a logic circuit which ahanges the value of the selected error signal if its value is the predetermined value and a selected mask/configuration signal has the masking value.
I According to another aspect of the invention, 1 30 the error ahecking system is included in every module of a communication system to provide for fault-tolerance to - allow checking of the communication channel for errors.
Further features and advantages will become apparent in view of the appended drawing~ and following detailed description.
Brie~ Description of the Drawinqs Aspects of the present invention are illustrated, merely by way of example, in the . ~ . .. ... .. . . .
212~7~3 2a accompanying drawings in which:
Figure 1 depict~ a shared bus communication sy~tem that can be monitored by the error checking systems of the present invention;
Figure 2 shows the arbitration, command, and databases of a basic shared bu~ operation;
Figure 3 is a block diagram of an embodiment of the present invention which supports full programmability of the error conditions to be checked;
Figure 4 i8 a block diagram of a second pxeferred embodiment of the invention which reduces the number of storage elements required in the first ~bodiment, and in many application3 reduce~ the gate count;
Figure 5 depicts a fully programmable error checking matrix according to the present invention;
Figure 6 depicts a matrix decoder having columns identified by different transfer length values and rows identified by different bus commands; and Figure 7 depict~ a COMMAND/HANDSHAKE hard-wired error checking matrix.
D2scription of the Preferred Embodiments The present invention is an error checking system having general utility in many types o~ digital communication 3y~temY. Many of the features of the system can better 21267~3 appreciated when described in the context of a particular bus system. In the following detailed description the error checking system will be described with reerence to a bus subsystem utilized in computer~ manufactured by Tandem Computer~, Inc. The bus subsystem will be de~cribed only in sufficient detail to support the detailed description of the invention.
Fig. 1 depicts a shared bus communication system including a CPU board 10 having several modules that communicate via a shared bus (IBUS) 12. These modules include i a processor interface chip (PIC) 14, a maintenance diagnostic chip (MDC) 16, a memory interfac~ chip (MIC) 18, and two bus interface modules (IPB X and IPB_Y) 20 and 22.
, Th~ IBUS 12 is synchronous parallel data path over i 15 which independent module~ may transfer address and data ~ information in a structured environment. The bus operations ,~ are synchronous with a basic system clock. All ev~nts on the IBUS occur relative to the rising edge of the clockO Two basic operations over the bus are defined; Arbitration and Transfer, each capable of occurring simultan~ously.
The Arbitration operation allows one of the module~
to become a master to gain sole ownership of the IBUS.
Modulee desiring to gain ownership of the IBUS (Requestor modul~s) must arbitrate and gain ownership of the IBUS before ~25 attempting to trans~er information.
The Transfer operation allows a Requestor that has gained ownership of the ~BUS to send data to or receive data from a Responder module and includes Command and Data Phases.
During the Command Phase, the Requestor, after arbitrating and gaining ownarship of the IBUS, places and address of a selected module on the Address~Data lines and a command on the ,l Handshake lines~ During the Data Phase, data is transferred rj between the Requestor and Responder. The length of the tran~fer i~ determined by the Reque~tor during the Command ~,l 35 Phase and can range from a 6ingle byte to many word~.
Fig. 2 depicts ~he arbitration, command, and data phase~ of a basic IBUS opera~ion. Requestors X and Y a~sert their Arb lines to request ownership o~ the IBUS and SC
~1 ,~1 ;l ": . :' . . ~
2~2~743 (system control) is asserted at CYCLE 1 granting ownership to the bus to Requestor X (which in this example has higher priority than Requestor Y). During the Command Phase, Requestor X drives the high and low addresses o~ the selected Responder on the Address/Data lines during CYCLE 1 and CYCLE 2 and drive-~ the command (CMD) on the ~andshake lines during CYCLE 1 and the length of the data transfer (LENGTH) on the Handshake lines during CYCLE 2. During the Data Phase, data is trancferred between the Requestor and Responder on the Addre6s/Data lines during CYCLES 3 and 4. ~lso, during the Data Phase, the Responder handshakes on the handshake line~
with READYODD for the first word in a trans~er and READYEVEN
for all subsequent words in a transfer.
Fig. 3 is block diagram of an embodiment of the present invention which supports full programmability of the error ~onditions to be checked. As described above, a bus operation requires the transfer of several data ~ields which represent information required to implement a data transfer.
The bus transfer protocol establishes whether particular values of a pair o~ fields, M and N, are allowed. For example, the M and N fields may respectively identify a requestor module and responder module. In this case the error checker would be programmed to output a true value if a communication between the particular modules identified by the ~25 M and N values were not allowed by the protocol.
Thus, the embodiment of Fig. 3 implements the error chQcking ~unction:
F~M,N)-T only when the values encoded by M and N are not allowed and F otherwise.
If ~ is an m-bit data field and N is an n-bit data field then the data fields may encode up to 2m and 2n values respectively. The symbols M and N in the above equation reprQsent pairings of the values o~ a particular pair of M and N fieldæ. Thus, i~ the values encoded by a particular pair of N and N ~ields are forbidden by the protocol then the value o~
2~ 267~3 the function value is true (T) and if the values are not forbidden the function value is false (F).
Turning to Fig. 3, a ~ully programmable check matrix 30 is implemented in a gate array. The matrix is formed by scannabla re~isters and has scan_d~ta_in input and a scan data_outputO The fields being checked, M and N, have wid~hs m and n respectively. Accordingly, the matrix has 2 columns and 2m rows.
The ~ and N fields generated on the bus are latched at the appropriate time by M and N latches 32 and 34 and are applied, respectiv~ly, to a row I~UX 35 and a column MUX 36 for selecting a unique row and column corresponding to the applied field~. The selected output is applied to one input o~ an output AND gate 38 and a timing window signal (optional) is 1~ applied to the other input to provide a clocked error signal.
The operation of the embodiment depicted in Fig. 3 will now be described. The F(M,N) values corresponding to a selected hardware configuration and bus transfer protocol are selected and arranged in a scan pattern having 2n x 2m bit positions. The order of the bits will be determined by the particular scan path established in the matrix. After the scan pattern is read into the matrix through the scan_data-in input each value of F(M,N) will be stored at the particular storage location selected by the received pair of M and N
~25 fields. If the system is recon~igured or protocol is changed a diP~erent scan pattern i~ read into ~he matrix to recon~igure the error checking system.
Fig. 4 is a block dia~ram of a second preferred embodiment of the invention which reduces the number o~
storage elements required in the first embodiment and in many applications reduces the gate count.
In Fig. 4, a matrix decoder logic 40 block r~ceives pairs of M and N signals at it~ row and column inputs and provides an unmasked error checking signal at i~s output selected by the received pair of M and N signals~ Scannable row and column registers 42 and 44 have a scan data in input and a scan data out output. The scannable row and column registers store l'error mask/configuration bits" which are .. : . , : ~ - . -2~267~3 selectable by particular row inputs, column input~, or row/column cross-section inputs.
The selection of the error mask/con~iguration bits is performed by an error tree 46 implemented in hardware, The hardware includes a maskinq AND gate 48 for receiving the selected error mask/configuration bits a~ gating inputs and the selected unmasked error checking signal as the signal input and provides a maskable error checking signal at its output. The outputs o~ the masking AND gate6 are coupled to the input of an OR gate 50 having its output coupled to the input of a timing ~ND gate 52~ The other input of the ti~ing AND gate 52 receives a timing window signal (optional) and it6 output is a timed error checking signal.
The operation of the embodiment depicted in Fig. 4 will now be described. The predetermined error checking function for a particular protocol is hardwired into the gate array of the matrix decoder logic block. If the selected row and column error checking bits are all TRUE then the masking AND gate 48 i8 open and ma~kahle error checking signal is equal to the unmaeked error checking signal.
Although the error function is hardwired into the matrix decoder logic, the scannable configuration registers 42 and 48 allow the error checking bit for particular received row inputs, column inputs, or row/column intersection inputs ~25 to be programmably changed fr,om TRUE to FALSE. As is apparent from Fig. 4, i~ either the row or column configuration bit for a given M or N field is FALSE then the output o~ the correspondiny masking AND gate is always FALSE. Accordingly, a TRUE unmasked error bit may be programmably changed to FALSE. The converse is not possible however, that is, a FALSE
unmasked error bit cannot be programmably changed to TRUE.
Thus, a particular row input, column input, or row/column intersection input that was previously forbidden can allowed in the new protocol 80 speci~ies by reprogram~ing the corresponding masking/con~iguration bits to the ma~king ~tate.
one of the embodiment~ depicted in Fig~. 3 and 4 ~ay be more ~uitable ~or a particular application. Figs. 5-7 ar~
s, : .
... .. . . .
7 ~ 3 diagrams depicting specific applications of the pre~erred embodiments.
The fully programmable embodiment of Fig. 3 may be better suited to an application having a great deal of flexibility and reconfigurability. For example, the allowable and forbidden responder/requestor pairs may be changed and the fully programmable embodiment may be more suitable.
Fig. 5 depicts a fully programmable error checking matrix. In this configuration the responder ID data field values and reque~tor ID data field values for a particular bus transaction are utilized as the column and row identifiers.
These ID~ are generated on the bus during CYCLE 2 (Fig. 2) of the bus transfer. A zero value at the intersection of a particular requestor/responder pair designates that the pair is allowed by the bus protocol. If the protocol were changed the inter~ection values would be recoded via scan. Note al~o that i~ another module were connected, e.g., an asynchro~ous transfer module, one of the unused rows and columns could be designated for this module and modified error checking signal stored in the designated row or column.
The mask programmable embodiment of Fig. 4 may be better suited to an application having a small degree of flexibility. For example, for a par~icular protocol certain data type~ of data tran~fer operation~ may be allowable for a ~5 small set of data transfer lengths. For another protocol the number of data transfer lengths allowable for some types of data transfers may be changed. These changes can be implemsnted by reprogramming the configuration bits in the mask registers~ Fig. 6 depicts a matrix decoder having columns identified by dif~erent transfer length value~
and rows identified by dif~erent bus commands. Tbe dia~ram include~ a mapping pairing the actual field value~, i.e., O
through F, to the sy~bolic command and word length parameter~.
~or example, a command field value equal to "6" symbolize~ a Block Write command and a txansfer length field value equal to "6" symbolize~ a 7 word tran~er length. The "pre" or "protocol error" area~ of the matrix are hardwired to TRUE
values and "ok" area~ are hardwired to FA~.SE values.
21267~3 Referring back to Fig. 2, the CMD and LENGTH
handshakes are generated on the handshake line in successive clock cycles. The command field is latched and provided to the error checking decoder when the length field is generated.
The advantage of the hard-wired embodiment to reduce gate count i8 now apparent. Note that for row inputs ~ through F
transfers for less than one word are defined by the command field. Accordingly, a protocol error i~ de~ined for the row/column intersection of rows 8 through F and columns 1 through F because columns 1 through F are ~or transfer lengths of greater than one word. Thus, a simple gate configuration generates the error checking signal for 120 possible row/column intersections.
The versatility of the masking function i5 also demonstrated. For example, in the matrix of Fig. 6 the row inputs 2, 4, and 5 are undefined commands that produce unmasked error checking signals when received. However, if the row input 4 were later defined as a command that transferred 1 to 8 words, then unmasked error checking signal would be masked if the UC4L mask bit were reset so that no error signal would be generated for a command field egual to 4. Additionally, if it were desired to remove the length error checking function from the system the L mask bit would be reset.
Fig. 7 depicts a COMMAND/HANDSHAKE hard~wired error checking matrix. Note from Figs. 6 and 7 that if the protocol error mask bit (P) is reset then both the CMD/LENGTH and CMD/HANDSHAKE error checking fun.tions are masked. Thus, tbe error tree includes a masking gate for masking the unmasked error checking signals generated by both hard-wired decoder~.
Further, from Fig. 7, if any of the handshake signals 1-6 are later defined, the unmasked error checking signal can be masked by a respective one of the masking bits UHSl-UHS6.
Additionally, the handshake error checker ma~rix can be masked by resetting the HS masking bit.
Referring back to Fig. 1, in the pre~erred embodiment the error checking matrices are redundantly included on each module and the error checking signals are ', ', , . , , . ' . .' ' t.~ "r . J ' ' ~ ~
9 2~2~743 received and processed by the MDC 16. This redundancy provides for fault-tolerant operation in the event of the failure of a particular error checking matrix. Additionally, electrical problems with the bus can be detected if the results of cheaking on the dlfferent modules are inconsistent.
The invention has now been described in detail with reference to the preferred embodiment. Alternatives and substitution will be apparent to persons of ordinary skill in the art A For example, although the invention has been defined with reference to a shared bus communiaation system, it is equally applicable to digital communication system utilizing other communication channels such as telephone line, optical fiber, microwave, or radio-~requency links. Additionally, th~
checking matricas in the preferred embodiment are implemented in gate arrays, but any suitable storage medium such as RAM, ROM, or general purpose registers can be utilized. The intersection of two fields has been described but error cheaking based on more than two Pields can also be implemented. Accordingly, it is not intended to limit the invention except as provided in the claims.
:.: , .
:.: . : .. . . . .
with READYODD for the first word in a trans~er and READYEVEN
for all subsequent words in a transfer.
Fig. 3 is block diagram of an embodiment of the present invention which supports full programmability of the error ~onditions to be checked. As described above, a bus operation requires the transfer of several data ~ields which represent information required to implement a data transfer.
The bus transfer protocol establishes whether particular values of a pair o~ fields, M and N, are allowed. For example, the M and N fields may respectively identify a requestor module and responder module. In this case the error checker would be programmed to output a true value if a communication between the particular modules identified by the ~25 M and N values were not allowed by the protocol.
Thus, the embodiment of Fig. 3 implements the error chQcking ~unction:
F~M,N)-T only when the values encoded by M and N are not allowed and F otherwise.
If ~ is an m-bit data field and N is an n-bit data field then the data fields may encode up to 2m and 2n values respectively. The symbols M and N in the above equation reprQsent pairings of the values o~ a particular pair of M and N fieldæ. Thus, i~ the values encoded by a particular pair of N and N ~ields are forbidden by the protocol then the value o~
2~ 267~3 the function value is true (T) and if the values are not forbidden the function value is false (F).
Turning to Fig. 3, a ~ully programmable check matrix 30 is implemented in a gate array. The matrix is formed by scannabla re~isters and has scan_d~ta_in input and a scan data_outputO The fields being checked, M and N, have wid~hs m and n respectively. Accordingly, the matrix has 2 columns and 2m rows.
The ~ and N fields generated on the bus are latched at the appropriate time by M and N latches 32 and 34 and are applied, respectiv~ly, to a row I~UX 35 and a column MUX 36 for selecting a unique row and column corresponding to the applied field~. The selected output is applied to one input o~ an output AND gate 38 and a timing window signal (optional) is 1~ applied to the other input to provide a clocked error signal.
The operation of the embodiment depicted in Fig. 3 will now be described. The F(M,N) values corresponding to a selected hardware configuration and bus transfer protocol are selected and arranged in a scan pattern having 2n x 2m bit positions. The order of the bits will be determined by the particular scan path established in the matrix. After the scan pattern is read into the matrix through the scan_data-in input each value of F(M,N) will be stored at the particular storage location selected by the received pair of M and N
~25 fields. If the system is recon~igured or protocol is changed a diP~erent scan pattern i~ read into ~he matrix to recon~igure the error checking system.
Fig. 4 is a block dia~ram of a second preferred embodiment of the invention which reduces the number o~
storage elements required in the first embodiment and in many applications reduces the gate count.
In Fig. 4, a matrix decoder logic 40 block r~ceives pairs of M and N signals at it~ row and column inputs and provides an unmasked error checking signal at i~s output selected by the received pair of M and N signals~ Scannable row and column registers 42 and 44 have a scan data in input and a scan data out output. The scannable row and column registers store l'error mask/configuration bits" which are .. : . , : ~ - . -2~267~3 selectable by particular row inputs, column input~, or row/column cross-section inputs.
The selection of the error mask/con~iguration bits is performed by an error tree 46 implemented in hardware, The hardware includes a maskinq AND gate 48 for receiving the selected error mask/configuration bits a~ gating inputs and the selected unmasked error checking signal as the signal input and provides a maskable error checking signal at its output. The outputs o~ the masking AND gate6 are coupled to the input of an OR gate 50 having its output coupled to the input of a timing ~ND gate 52~ The other input of the ti~ing AND gate 52 receives a timing window signal (optional) and it6 output is a timed error checking signal.
The operation of the embodiment depicted in Fig. 4 will now be described. The predetermined error checking function for a particular protocol is hardwired into the gate array of the matrix decoder logic block. If the selected row and column error checking bits are all TRUE then the masking AND gate 48 i8 open and ma~kahle error checking signal is equal to the unmaeked error checking signal.
Although the error function is hardwired into the matrix decoder logic, the scannable configuration registers 42 and 48 allow the error checking bit for particular received row inputs, column inputs, or row/column intersection inputs ~25 to be programmably changed fr,om TRUE to FALSE. As is apparent from Fig. 4, i~ either the row or column configuration bit for a given M or N field is FALSE then the output o~ the correspondiny masking AND gate is always FALSE. Accordingly, a TRUE unmasked error bit may be programmably changed to FALSE. The converse is not possible however, that is, a FALSE
unmasked error bit cannot be programmably changed to TRUE.
Thus, a particular row input, column input, or row/column intersection input that was previously forbidden can allowed in the new protocol 80 speci~ies by reprogram~ing the corresponding masking/con~iguration bits to the ma~king ~tate.
one of the embodiment~ depicted in Fig~. 3 and 4 ~ay be more ~uitable ~or a particular application. Figs. 5-7 ar~
s, : .
... .. . . .
7 ~ 3 diagrams depicting specific applications of the pre~erred embodiments.
The fully programmable embodiment of Fig. 3 may be better suited to an application having a great deal of flexibility and reconfigurability. For example, the allowable and forbidden responder/requestor pairs may be changed and the fully programmable embodiment may be more suitable.
Fig. 5 depicts a fully programmable error checking matrix. In this configuration the responder ID data field values and reque~tor ID data field values for a particular bus transaction are utilized as the column and row identifiers.
These ID~ are generated on the bus during CYCLE 2 (Fig. 2) of the bus transfer. A zero value at the intersection of a particular requestor/responder pair designates that the pair is allowed by the bus protocol. If the protocol were changed the inter~ection values would be recoded via scan. Note al~o that i~ another module were connected, e.g., an asynchro~ous transfer module, one of the unused rows and columns could be designated for this module and modified error checking signal stored in the designated row or column.
The mask programmable embodiment of Fig. 4 may be better suited to an application having a small degree of flexibility. For example, for a par~icular protocol certain data type~ of data tran~fer operation~ may be allowable for a ~5 small set of data transfer lengths. For another protocol the number of data transfer lengths allowable for some types of data transfers may be changed. These changes can be implemsnted by reprogramming the configuration bits in the mask registers~ Fig. 6 depicts a matrix decoder having columns identified by dif~erent transfer length value~
and rows identified by dif~erent bus commands. Tbe dia~ram include~ a mapping pairing the actual field value~, i.e., O
through F, to the sy~bolic command and word length parameter~.
~or example, a command field value equal to "6" symbolize~ a Block Write command and a txansfer length field value equal to "6" symbolize~ a 7 word tran~er length. The "pre" or "protocol error" area~ of the matrix are hardwired to TRUE
values and "ok" area~ are hardwired to FA~.SE values.
21267~3 Referring back to Fig. 2, the CMD and LENGTH
handshakes are generated on the handshake line in successive clock cycles. The command field is latched and provided to the error checking decoder when the length field is generated.
The advantage of the hard-wired embodiment to reduce gate count i8 now apparent. Note that for row inputs ~ through F
transfers for less than one word are defined by the command field. Accordingly, a protocol error i~ de~ined for the row/column intersection of rows 8 through F and columns 1 through F because columns 1 through F are ~or transfer lengths of greater than one word. Thus, a simple gate configuration generates the error checking signal for 120 possible row/column intersections.
The versatility of the masking function i5 also demonstrated. For example, in the matrix of Fig. 6 the row inputs 2, 4, and 5 are undefined commands that produce unmasked error checking signals when received. However, if the row input 4 were later defined as a command that transferred 1 to 8 words, then unmasked error checking signal would be masked if the UC4L mask bit were reset so that no error signal would be generated for a command field egual to 4. Additionally, if it were desired to remove the length error checking function from the system the L mask bit would be reset.
Fig. 7 depicts a COMMAND/HANDSHAKE hard~wired error checking matrix. Note from Figs. 6 and 7 that if the protocol error mask bit (P) is reset then both the CMD/LENGTH and CMD/HANDSHAKE error checking fun.tions are masked. Thus, tbe error tree includes a masking gate for masking the unmasked error checking signals generated by both hard-wired decoder~.
Further, from Fig. 7, if any of the handshake signals 1-6 are later defined, the unmasked error checking signal can be masked by a respective one of the masking bits UHSl-UHS6.
Additionally, the handshake error checker ma~rix can be masked by resetting the HS masking bit.
Referring back to Fig. 1, in the pre~erred embodiment the error checking matrices are redundantly included on each module and the error checking signals are ', ', , . , , . ' . .' ' t.~ "r . J ' ' ~ ~
9 2~2~743 received and processed by the MDC 16. This redundancy provides for fault-tolerant operation in the event of the failure of a particular error checking matrix. Additionally, electrical problems with the bus can be detected if the results of cheaking on the dlfferent modules are inconsistent.
The invention has now been described in detail with reference to the preferred embodiment. Alternatives and substitution will be apparent to persons of ordinary skill in the art A For example, although the invention has been defined with reference to a shared bus communiaation system, it is equally applicable to digital communication system utilizing other communication channels such as telephone line, optical fiber, microwave, or radio-~requency links. Additionally, th~
checking matricas in the preferred embodiment are implemented in gate arrays, but any suitable storage medium such as RAM, ROM, or general purpose registers can be utilized. The intersection of two fields has been described but error cheaking based on more than two Pields can also be implemented. Accordingly, it is not intended to limit the invention except as provided in the claims.
:.: , .
:.: . : .. . . . .
Claims (8)
1. In a system having a plurality of modules coupled by a communication channel and having a communication protocol utilizing first and second data fields, each encoding one of a plurality of values, transmitted on the channel to define and control communication operations, a method for checking for protocol errors comprising the steps of:
writing an error checking signal to a storage location for each one of a set of possible pairs to said first and second data field values, with the written error checking signal indicating whether the possible pair is allowed by the communication protocol;
receiving a given pair of said first and second data fields transmitted on said channel during a particular communication operation;
utilizing said given pair of first and second data fields to select said error checking signal indicating whether said given pair of first and second data fields are allowed by the communication protocol; and aborting the particular communication operation if the selected error checking signal indicates that the given pair is not allowed by the communication protocol.
writing an error checking signal to a storage location for each one of a set of possible pairs to said first and second data field values, with the written error checking signal indicating whether the possible pair is allowed by the communication protocol;
receiving a given pair of said first and second data fields transmitted on said channel during a particular communication operation;
utilizing said given pair of first and second data fields to select said error checking signal indicating whether said given pair of first and second data fields are allowed by the communication protocol; and aborting the particular communication operation if the selected error checking signal indicates that the given pair is not allowed by the communication protocol.
2. The method of claim 1 further comprising the step of:
rewriting said selected error checking signal if the protocol is modified.
rewriting said selected error checking signal if the protocol is modified.
3. In a system having a plurality of modules coupled by a communication channel and having a communication protocol utilizing first and second data fields, each encoding one of a plurality of values, transmitted on the channel to define and control communication operations, a method for checking for protocol errors comprising the steps of:
storing an error checking signal, for each one of a set of possible pairs to said first and second data field values indicating whether the possible pair is allowed by the communication protocol;
receiving a given pair of said first and second data fields transmitted on said channel during a particular communication operation;
utilizing said given pair of first and second data field to select said error checking signal indicating whether said given pair of first and second data fields are allowed by the communication protocol;
utilizing said given pair of first and second data fields to select a masking signal having either a masking value or a non-masking value;
masking the selected error checking signal to generate a masked selected error checking signal indicating that the given pair of said first and second data fields are allowed by the communication protocol if said selected masking signal has a masking value;
aborting the particular communication operation if the masked selected error checking signal indicates that the given pair is not allowed by the communication protocol.
storing an error checking signal, for each one of a set of possible pairs to said first and second data field values indicating whether the possible pair is allowed by the communication protocol;
receiving a given pair of said first and second data fields transmitted on said channel during a particular communication operation;
utilizing said given pair of first and second data field to select said error checking signal indicating whether said given pair of first and second data fields are allowed by the communication protocol;
utilizing said given pair of first and second data fields to select a masking signal having either a masking value or a non-masking value;
masking the selected error checking signal to generate a masked selected error checking signal indicating that the given pair of said first and second data fields are allowed by the communication protocol if said selected masking signal has a masking value;
aborting the particular communication operation if the masked selected error checking signal indicates that the given pair is not allowed by the communication protocol.
4. A system for receiving first and second data fields generated on a communication channel during a communication operation, each data field encoding one of a plurality of values, and for checking whether the first and second values of a particular pair of received data fields are allowed or forbidden by a selected rule, said system comprising:
programmable storage means, having a first plurality of storage locations, for storing a first plurality of unique error checking values, each unique value corresponding to a unique possible pairing in a first plurality of possible pairings of the values of said first and second fields and stored in one of said storage locations;
means, coupled to receive said particular pair of first and second data fields, for selecting a stored unique error checking value corresponding to the received particular pair of first and second data fields;
means, coupled to said means for selecting, for generating an error checking signal if said error checking value indicates that the particular pair is forbidden by the selected rule.
programmable storage means, having a first plurality of storage locations, for storing a first plurality of unique error checking values, each unique value corresponding to a unique possible pairing in a first plurality of possible pairings of the values of said first and second fields and stored in one of said storage locations;
means, coupled to receive said particular pair of first and second data fields, for selecting a stored unique error checking value corresponding to the received particular pair of first and second data fields;
means, coupled to said means for selecting, for generating an error checking signal if said error checking value indicates that the particular pair is forbidden by the selected rule.
5. The system of claim 4 further comprising:
means, coupled to said means for generating said error checking signal, for aborting the communication operation when said error checking signal is generated.
means, coupled to said means for generating said error checking signal, for aborting the communication operation when said error checking signal is generated.
6. In a digital system including multiple modules coupled by a communication channel and that performs operations specified by first and second data fields transmitted on the channel to govern inter-module communication and operations, an error checking system, responsive to selected data fields, for indicating whether operations specified by the selected fields are allowed according to a particular hardware configuration and communication protocol, said error checking system comprising;
a first matrix decoder, having row and column inputs for receiving first and second fields respectively and an output for transmitting an unique unmasked error checking signal selected by said first and second fields received at said inputs, with said error checking signal having a value equal to a predetermined value if the first and second fields are not allowed by the particular hardware configuration and communication protocol;
means for providing selected first and second data fields specifying an operation to be performed by the digital system, to respective row and column inputs of said matrix decoder;
a programmable row mask register for storing a second plurality of row configuration bits, each bit programmably set to either a masking state or non-masking state;
a programmable column mask register for storing a third plurality of column configuration bits, each bit programmably set to either a masking state or a non-masking state;
mask logic means, coupled to the output of said matrix decoder and coupled to said row and column mask registers to receive the unmasked error checking value, the column configuration bit, and/or the row configuration bit selected by said first field and/or said second field, for changing the value of the unmasked error checking signal if either the row or column configuration bit is in the masking state and the value of the unmasked error checking signal is equal to the predetermined value.
a first matrix decoder, having row and column inputs for receiving first and second fields respectively and an output for transmitting an unique unmasked error checking signal selected by said first and second fields received at said inputs, with said error checking signal having a value equal to a predetermined value if the first and second fields are not allowed by the particular hardware configuration and communication protocol;
means for providing selected first and second data fields specifying an operation to be performed by the digital system, to respective row and column inputs of said matrix decoder;
a programmable row mask register for storing a second plurality of row configuration bits, each bit programmably set to either a masking state or non-masking state;
a programmable column mask register for storing a third plurality of column configuration bits, each bit programmably set to either a masking state or a non-masking state;
mask logic means, coupled to the output of said matrix decoder and coupled to said row and column mask registers to receive the unmasked error checking value, the column configuration bit, and/or the row configuration bit selected by said first field and/or said second field, for changing the value of the unmasked error checking signal if either the row or column configuration bit is in the masking state and the value of the unmasked error checking signal is equal to the predetermined value.
7. The error checking system of claim 6 wherein said first matrix decoder comprises:
a hard-wired logic circuit for generating one unmasked error checking signal for any pair of first and second data fields having a first data field included in a plurality of selected first data fields and a second data field included in a plurality of selected second data fields.
a hard-wired logic circuit for generating one unmasked error checking signal for any pair of first and second data fields having a first data field included in a plurality of selected first data fields and a second data field included in a plurality of selected second data fields.
8. The error checking system of claim 6 further comprising:
a second matrix decoder, having row and column inputs for receiving first and third fields respectively and an output for transmitting an unique unmasked error checking signal selected by said first and third fields received at said inputs, with said error checking signal having a value equal to a predetermined value if the first and third fields are not allowed by the particular hardware configuration and communication protocol;
and wherein:
said mask logic means further includes means coupled to said first and second matrix decoders and coupled to said row and column mask registers to receive the unmasked error checking signals from said first and second matrix decoders and a selected row configuration bit selected by said first field, for changing the value of the received unmasked error checking signals if the selected row configuration bit is in the masking state and the value of the unmasked error checking signals is equal to the predetermined value.
a second matrix decoder, having row and column inputs for receiving first and third fields respectively and an output for transmitting an unique unmasked error checking signal selected by said first and third fields received at said inputs, with said error checking signal having a value equal to a predetermined value if the first and third fields are not allowed by the particular hardware configuration and communication protocol;
and wherein:
said mask logic means further includes means coupled to said first and second matrix decoders and coupled to said row and column mask registers to receive the unmasked error checking signals from said first and second matrix decoders and a selected row configuration bit selected by said first field, for changing the value of the received unmasked error checking signals if the selected row configuration bit is in the masking state and the value of the unmasked error checking signals is equal to the predetermined value.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/087,545 US5396505A (en) | 1993-07-06 | 1993-07-06 | Programmable error-checking matrix for digital communication system |
| US08/087,545 | 1993-07-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2126743A1 true CA2126743A1 (en) | 1995-01-07 |
Family
ID=22205816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002126743A Abandoned CA2126743A1 (en) | 1993-07-06 | 1994-06-24 | Programmable error-checking matrix for digital communication system |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US5396505A (en) |
| EP (1) | EP0637881B1 (en) |
| JP (1) | JP2622357B2 (en) |
| KR (1) | KR0177197B1 (en) |
| CN (1) | CN1103221A (en) |
| AU (1) | AU681656B2 (en) |
| CA (1) | CA2126743A1 (en) |
| DE (1) | DE69433155T2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5515506A (en) * | 1994-08-23 | 1996-05-07 | Hewlett-Packard Company | Encoding and decoding of dual-ported RAM parity using one shared parity tree and within one clock cycle |
| US6266782B1 (en) | 1998-11-30 | 2001-07-24 | Siemens Information And Communication Networks, Inc. | Apparatus and methods for inband protocol correction in distributed object networking |
| US7725945B2 (en) * | 2001-06-27 | 2010-05-25 | Intel Corporation | Discouraging unauthorized redistribution of protected content by cryptographically binding the content to individual authorized recipients |
| US7043495B1 (en) * | 2001-07-27 | 2006-05-09 | Cypress Semiconductor Corp. | Techniques for JEDEC file information integrity and preservation of device programming specifications |
| US7062680B2 (en) * | 2002-11-18 | 2006-06-13 | Texas Instruments Incorporated | Expert system for protocols analysis |
| TWI575532B (en) * | 2016-03-02 | 2017-03-21 | 群聯電子股份有限公司 | Decoding method, memory control circuit unit and memory storage apparatus |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA1127747A (en) * | 1977-12-09 | 1982-07-13 | Joseph C. Engel | Wireless emergency power interrupting system |
| US4418384A (en) * | 1980-10-06 | 1983-11-29 | Honeywell Information Systems Inc. | Communication subsystem with an automatic abort transmission upon transmit underrun |
| US4545055A (en) * | 1983-07-20 | 1985-10-01 | Loral Corporation | Error analyzer for data communicated by bus protocol |
| US4646300A (en) * | 1983-11-14 | 1987-02-24 | Tandem Computers Incorporated | Communications method |
| US4567590A (en) * | 1983-12-27 | 1986-01-28 | International Business Machines Corp. | Message stripping protocol for a ring communication network |
| US5007051A (en) * | 1987-09-30 | 1991-04-09 | Hewlett-Packard Company | Link layer protocol and apparatus for data communication |
| EP0310360B1 (en) * | 1987-09-30 | 1995-02-22 | Hewlett-Packard Company | Data communication method and apparatus |
| US4908823A (en) * | 1988-01-29 | 1990-03-13 | Hewlett-Packard Company | Hybrid communications link adapter incorporating input/output and data communications technology |
| US4939735A (en) * | 1988-07-21 | 1990-07-03 | International Business Machines Corporation | Information handling system having serial channel to control unit link |
| US4991133A (en) * | 1988-10-07 | 1991-02-05 | International Business Machines Corp. | Specialized communications processor for layered protocols |
| US4932023A (en) * | 1989-06-20 | 1990-06-05 | International Business Machines Corporation | Frame stripping protocol for early token release in a ring communication network |
| US4975882A (en) * | 1989-10-30 | 1990-12-04 | Motorola, Inc. | User programmable redundant memory |
| US5128945A (en) * | 1989-12-21 | 1992-07-07 | Stratacom, Inc. | Packet framing using cyclic redundancy checking |
| US5206952A (en) * | 1990-09-12 | 1993-04-27 | Cray Research, Inc. | Fault tolerant networking architecture |
| EP0478175B1 (en) * | 1990-09-13 | 1995-11-22 | Hewlett-Packard Company | A protocol analyzer |
| EP0474932A1 (en) * | 1990-09-13 | 1992-03-18 | Hewlett-Packard Company | Network fault analyzer |
| JP2803764B2 (en) * | 1990-10-15 | 1998-09-24 | キヤノン株式会社 | Facsimile machine |
| US5271020A (en) * | 1990-12-21 | 1993-12-14 | Intel Corporation | Bus stretching protocol for handling invalid data |
| US5293784A (en) * | 1991-09-06 | 1994-03-15 | Gebruder Buhler Nachfolger Gmbh | Drive device for a vehicle rear-view mirror |
| US5293384A (en) * | 1991-10-04 | 1994-03-08 | Bull Hn Information Systems Inc. | Microprocessor bus interface protocol analyzer |
-
1993
- 1993-07-06 US US08/087,545 patent/US5396505A/en not_active Expired - Lifetime
-
1994
- 1994-06-24 CA CA002126743A patent/CA2126743A1/en not_active Abandoned
- 1994-06-30 AU AU66087/94A patent/AU681656B2/en not_active Ceased
- 1994-07-05 KR KR1019940015988A patent/KR0177197B1/en not_active IP Right Cessation
- 1994-07-05 JP JP6153445A patent/JP2622357B2/en not_active Expired - Fee Related
- 1994-07-06 CN CN94108179A patent/CN1103221A/en active Pending
- 1994-07-06 EP EP94304962A patent/EP0637881B1/en not_active Expired - Lifetime
- 1994-07-06 DE DE69433155T patent/DE69433155T2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| KR950004796A (en) | 1995-02-18 |
| AU6608794A (en) | 1995-01-19 |
| DE69433155D1 (en) | 2003-10-23 |
| AU681656B2 (en) | 1997-09-04 |
| EP0637881A3 (en) | 1996-10-09 |
| JPH07154451A (en) | 1995-06-16 |
| JP2622357B2 (en) | 1997-06-18 |
| CN1103221A (en) | 1995-05-31 |
| KR0177197B1 (en) | 1999-05-15 |
| EP0637881B1 (en) | 2003-09-17 |
| EP0637881A2 (en) | 1995-02-08 |
| US5396505A (en) | 1995-03-07 |
| DE69433155T2 (en) | 2004-08-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4862347A (en) | System for simulating memory arrays in a logic simulation machine | |
| US5060145A (en) | Memory access system for pipelined data paths to and from storage | |
| US5999725A (en) | Method and apparatus tracing any node of an emulation | |
| US8443422B2 (en) | Methods and apparatus for a configurable protection architecture for on-chip systems | |
| US7206891B2 (en) | Multi-port memory controller having independent ECC encoders | |
| US5666515A (en) | Information processing system having multiple modules and a memory on a bus, where any module can lock an addressable portion of the memory by sending retry signals to other modules that try to read at the locked address | |
| AU615688B2 (en) | State machine checker | |
| EP2294581B1 (en) | A system for distributing available memory resource | |
| JPH08249U (en) | Encoding / decoding circuit | |
| US6460174B1 (en) | Methods and models for use in designing an integrated circuit | |
| CA2126743A1 (en) | Programmable error-checking matrix for digital communication system | |
| JP2002525747A (en) | Methods for detecting memory component failures and single, double, and triple bit errors | |
| KR100772287B1 (en) | Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner | |
| US7293155B2 (en) | Management of access to data from memory | |
| EP0357342B1 (en) | Processor array system | |
| US6525557B1 (en) | Method for watermarking a register-based programmable logic device core | |
| US10409624B1 (en) | Data array compaction in an emulation system | |
| US5692161A (en) | Method and apparatus for operating a microcomputer in an emulation mode to access an external peripheral | |
| GB2483884A (en) | Parallel processing system using dual port memories to communicate between each processor and the public memory bus | |
| US6937061B1 (en) | Address decoder for programmable logic device | |
| US7003422B2 (en) | Method for connecting test bench elements and shell device | |
| US6701418B2 (en) | Automatic detection and correction of relatively rearranged and/or inverted data and address signals to shared memory | |
| JPS62226367A (en) | Digital computer system | |
| JPS6132758B2 (en) | ||
| CA1219372A (en) | Flexible computer control unit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| FZDE | Discontinued |