CA2126926C - Modem with firmware upgrade feature - Google Patents

Modem with firmware upgrade feature

Info

Publication number
CA2126926C
CA2126926C CA002126926A CA2126926A CA2126926C CA 2126926 C CA2126926 C CA 2126926C CA 002126926 A CA002126926 A CA 002126926A CA 2126926 A CA2126926 A CA 2126926A CA 2126926 C CA2126926 C CA 2126926C
Authority
CA
Canada
Prior art keywords
modem
operating code
updated operating
packet
updated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA002126926A
Other languages
French (fr)
Other versions
CA2126926A1 (en
Inventor
Greg Johnson
Richard David Johnson
David A. Weinzierl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Multi Tech Systems Inc
Original Assignee
Multi Tech Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Multi Tech Systems Inc filed Critical Multi Tech Systems Inc
Priority to CA002261214A priority Critical patent/CA2261214C/en
Publication of CA2126926A1 publication Critical patent/CA2126926A1/en
Application granted granted Critical
Publication of CA2126926C publication Critical patent/CA2126926C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/60Software deployment
    • G06F8/65Updates
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/02Details
    • H04L12/12Arrangements for remote connection or disconnection of substations or of equipment thereof
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/40Network security protocols
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04MTELEPHONIC COMMUNICATION
    • H04M11/00Telephonic communication systems specially adapted for combination with other electrical systems
    • H04M11/06Simultaneous speech and data transmission, e.g. telegraphic transmission over the same conductors
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00Reducing energy consumption in communication networks
    • Y02D30/50Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Updated operating code and parameters can be reprogrammed into a modem system with no disassembly of the modem hardware. The modem system includes an in-circuit reprogrammable memory chip in which operating code and parameters are stored. Two control programs control the reprogramming of updated operating code. One of the control programs is designed for manufacturing and testing purposes. The other control program allows remote reprogramming of updated operating code or parameters from a remote location such as a customer site. The modem system is portable, obtaining power from a standard 9 volt battery. Therefor, various power saving features are also incorporated into the modem system.

Description

2 ~ 6 9 ~n~M ~r~ FT~R~ upOE~n~ E~rr -~
F;~l~ ~ f ~h~ Tnv~nl-;nn The present inv~ntion relates to c~m~ m;cations systems and in particular to a modem in which the firmware which controls the operation of the modem can be changed or upgraded remotely.

Presently, there are several m~hAn;.~m~
through which software upgrades, bug fixes and the like are distributed to users. In systems employing f;nr~re storage of operating ~LoyLdll~, such as Electrically PLo~L~I"~ble Read Only Memory (EPROM) and the like, bug fixes or P-nhAnc~mP~t~q to system firmware require ~loy~ ng a new EPROM with the llp~te~ code ~ -and shipping the new EPROM to the customer. A
tP~hn;c;~n then travels to the site, ~iqA~q~mhles the hardware, and replaces the old EPROM with the new one.
Unfortl~n~tPly, these ~m~ethods are very inconv~n;~nt. First, a considerable time delay is encountered while waiting for the mAnllf~cturer to ~IO~L~II and ship the replA.~"~r,l parts. 9~c~n~, the hardware may not be operable if the user is waiting for a bug fix. ~ pec;Ally true in cases of bug fixes where the hardware might not be operable without the l~At~ operating code. Also, the replAc~m~nt of the old with the new EPROM requires a te~hn;cian to travel to the site and use special tools to ~;sA~s~mhle the hardware and replace the ol]t~Ate~ on faulty part or parts. Thi.s results in an increased expense for repairs or upgrades because technician time and special too].s are required. Current l~r~Ate methods are thus time consuming, expensive and inefficient.
There is a need in the art, therefore, for a m.~dem which allows remote changes and/or upgrades to be made to the firmware stored o~e~dLing code, without requiring disassemhly and replacement of parts, technician time, or special tools, thus resulting in the more efficient and cost effective means of updating f;n~ ~re.
S=y To overcome the shortc~m;ng~q in the art described above, and to provide other adv~nt~Ps which will heco~ apparent upon r~;ng and understAn~;ng the present specification, the present system is a .-modem system which includes hardware and software c~~ .nt.q. The system allows the user to c~nn~ct to remote locAt;ons equipped with a .q;m;lAr system or with ll~d~ll~ or fAc~;m;le mA~h;n~q over a single analog tele~h~n~ line. The incorporation of various power :
saving features allo~ practical im.pl~m~ntAtion of a 15 smalll lightweight and easily transportable modem ~ :~
~ystem powered from a standard g volt battery. The present modem system also inco,~ordLes storage of .~:
operating code and parameters in an in-circuit .
.~.o~ ble memory chip. A user can thus remotely l~JrAA~ system firmware with updates, bug fixes, ~"h~ q or other new releases of system operating code by do~nl OA~ the l~Ate over a phone line and le~?~y~ ;ng the memory chip in-circuit over the ~ :
serial port.
Rr; ~f ] )P~r~ f 1-ha r~r~g~
In the drawings, where like numerals refer to like ~ x.,~ .. q throughout the several views, :~
Figure 1 shows the telecc~n~n;cat;~n~
envi-v...,~..l. within which the present system may ~e,d~e;
Figure 2 is a block diagram of the hardware com~on~nt.q of the present ~ystem; ~
Figure 3 is a key for viewing the detailed . .;;:
electrical schematic diagrams of Figures 4A-7C to :
f~c;l;tate understAn~;ng of the inteL~ ections between the drawings;

, , . ,~ . . .. .
3 2~26926 Figures 4A-4E, 5A-5C and 6A-6C are detailed electrical s~.hPmAt;c diay~ of the circuitry of the hardware c~l~.. ,~ s of the present system; ~
Figure 7 shows a flow diagram of the process ~-for do~lo~;n~ the HEX files c~ntA;n;ng the updated operating c~de from a bulletin board to the host PC;
Figures 8A-8C show a flow diagram of the upgrade control ~ ~-- from the perspective of the host PC; and - i Figures 9A-9D show a flow diagram of the ~-upgrade control ~L~yr~ll from the perspective of the modem. ~ ~
1~1-a;l~ l~Rr~ ~n nf 1-h~ Ei-~f~ X)di~tR ~ ,:
In the following ~t~;led description of the preferred ~mhc~;m~n~l~reference is made to the ~ ing drawings which form a part hereof, and in which is shown by way of illustration spec;f;c ~mho~;m~nt,q in which the inv~nt;~nq may be practiced. ;~
These ~c~ nts are described in sufficient ~tAi to enable those skilled in the art to practice the inv~.ntion, and it is to be ~l~el~Lood that other e~ im~nt~ may be llt-il;7e~ and that structural ~ J~ may be mad~ without ~alLing from the spirit and scope of the present inVpnti~nq. The following 25 det~ile~ description is, therefore, not to be taken in , a limiting sense, and the scope of the present i~Ivp-ntit~nq iS ~ f;n~ by the ~,~nrl~3 cl~;m.q.
Figure 1 shows a typical a~L~ J ~-.l for the use of the present mcdem system. Hardware ~u~ nts 20 c~ntA;n the present modem system and are connPcted to laptop c~rllt~r 10. Hardware C~~ l S 20 com~ m;CAte over a stand_rd t~l~rh~n~ line 30 to one of a variety of remote sites. For example, one of the remote sites may be e~ pe~ with the present modem system including hardware ~~~ ~.ls 20a and laptop c~rl~tPr lOa. The present modem system can also c~nn~ct over phone lines 30 to fax mA~h;ne 60, to a personal computer and A~o~;Ated modem 40, or to a 4 212692~
network of personal computers 90. Those skilled in the art will readily recognize the wide variety of com~]n;cation interconnections possible with the present system by reading and underst~n~;n~ the following det~;le~ description.
Har~ ~re ac~n~ "
Figure 2 is a block diagram of the hardware ~ nts of the present system corresp~n~;n~ to reference number 20 of Figure 1. These compo~nts 10 form the link between the user, the laptop or personal cc~ t~r (PC) and the tel~hnn~ line interface.
The preferred embo~;m~nt of the present ;~
system preferably includes a data pump circuit 211, which includes a digital tele~hon~ coder-decoder 15 (CODEC) and a digital~signal processor (DSP) for com~n;c~t;n~ over the telerh~n~ line interface 209.
The data pump DSP of circuit 211 performs functions such as mn~ tl~n, ~mn~ t;~n and echo c~n~ t;on to con~;C~te cver the tel~hnnP line interface 209 20 using a plurality of telecom~ m;c~t;~n.q standards including FAX and modem protocols. The main controller circuit ~13 directly c~llLr~ls th~ DSP data pump circuit 211.
As described more fully below, the main 25 ~ Llvller circuit 213 includes, in the preferred ~mhc~;m~nt, a ~m~ Locessor which controls the functions and operation of all of the hardware c~"entq shown in Figure 2. The main controller is c~nn~cted to RAM circuit 216 and a pro~l~".,~hle and 30 electrically erasable read only memory or Flash PROM
circuit 217. The Flash PROM circuit 217 includes non-~olatile memory in which the executable control ~LUyl~l~ for the main controller circuits 213 are stored.
The RS232 serial interface 215 com~ mlcates to the serial port of the personal computer which is rllnn; n~ the software c~ n~ of the present system.
The RS232 serial interface circuit 215 is connected to '' 2126926 a serial input/output circuit 214 with main controller circuit 213. ~ -Data is received from the tel~hnn~ line over tel~hnnP line interface circuit 209 and 5 forwarded by the data pump circuit 211 and the main -L~oller circuit 213 over the serial line interface circuit 215 to the personal computer.

The detailed electrical s~h~m~t;c diay-rams comprise Fiyures 4A-E, 5A-C, 6A-C and 7A-C. Figure 3 shows a key for how the s~h~m~t;c diagrams may be conv~n;Pntly a-,~ly~d to view the p~.~s;ng of signals on the electrical lines between the diay,~l~. The electrical c~nn~ctions between the electrical .~rh~m~t;c diagrams ar~e through the designators listed next to each wire. For example, on the right side of Figure 4A, address lines A0-Alg are att~h~ to an address bus for which the individual electrical lines may ~pe~r on other pages as A0-A19 or may collectively be c~nn~cte-~ to other s~h~m~t;c diagrams through the ~Ps;~n~tor "A" in the circle c~nn~cted to the collective bus. In a like f~h;~n, other electrical lines desi~n~te~ with symbols such as RNGL
on the lower left-hand side of Figure 4A may c~nn~ct to other ~rhpmut;c diagrams using the same signal designator RNGL.
Re~;nn;ng with the electrical s~h~ut;c diagram of Figures 4D and 4E, the DAA circuitry (tel~rh~n~ line interface) is shown. The telerh~n~
line c~nn~ction in the preferred embo~;m~nt is through c~nn~ctor J201 which is a standard six-pin modular RJ-11 jack. In the s~h~m~t;c diagram of Figure 4E, only the tip and ring conn~ctions of the first tel~rh~n~
circuit of the RJ-11 modular connector are used.
Ferrite beads ~3201 and FB202 are placed on the tip and ring wires of the t~l~rh~n~ line c~nn~ctions to reduce high frequency or RF noise that may ra~;~t~
from tel~hon~ line. The ; n~om; ng telep~h~nP line is ~ 2126926 also overvoltage protected through SIDACTOR R205. The ;n~om;n~ telerhnne line is full wave rectified by the full wave bridge comprised of diodes CR230, CR226, CR227 and CR228 of Figure 4D.
Also conn~cted across the incoming teleph~nP
line is a ring detect circuit. Optical isolator U220 (part model m ~h~r CNY17) senses the ring voltage ~-~
threshold when it exceeds the breakdown voltages on zener diodes CR201 and CR202.
The ~A~ circuitry is physically isolated from the rest of the system by transformer T1, optocoupler U220 and two solid state relays X215 and ~-X202 which are optically coupled. Cnnn~ctor J203 is a -~
four pin h~A~r used for ~l~tcmAt;c testing during 15 mAmlfActuring and for~diagnostics. ~-Relay X215 shown in Figure 4D is used to ' Accgm~lish pulse ~;Al;ng by opening and shorting the tip and ring wires. Transistor Q203 along with the assoc;~t~ discrete resistors comprise a holding circuit to provide a current path or current loop on the tPlPrhnn~ line to grab the line. The DA~
circuitry shown in Figures 4D and 4E can be custom;~e~
to interface to the varying tel~rhnn~ standards used in the United States and in many different European colmtries~
Chnn~ctor J202 shown in Figure 4D conn~cts the telPrhnn~ line interface circuitry described above to c~nn~ctor J102 shown in Figure 6A and thusly to the rest of the circuit. Tn~o~;n~ RXA signals are buffered by the two operational amplifiers U104 as shown in Figure 6B. me first stage of buffering is used to drive the transmit carrier signal to the t~ hnn~ line. The second stage of the input ~-buffering is configured for a mcderate amount of gain before driving the s;~n~l into CODEC U101. m is stage is also used to reduce the amount of transmit signal that is fed back into the receiver. me signal from 7 212692~
amplifiers U104 is also fed to speaker driver U105, which drives speaker X101.
Data and address buses A and B shown in Figures 4A and 4B c~nn~ct the Z80180 mi~ ocessor in mi~ocullL,oller U5 with the Z80 KIO circuit U4 and a gate array circuit U3, and to other portions of the '~
electrical scl~,~lic diayr~l~. Gate array U3, also shown in Figures 4A and 4B, includes the "glue logic"
used to sly~port various fl]n~t;onq in the hardware c~.~ ..ls of the present invention. Gate array U3 ;nc~llA~q m;-qcell~n~ous latch and buffer circuits for the present system which n~rmAlly would be found in discrete SSI or MSI ;nte~rated circuits. By combining a wide variety of m;qcell~n~ous .Y~rport circuits into a s;n~l~ gate array, a much r~ e~ design complexity and mAn~lf~tllring cost is achieved.
CODEC chip U101 shown in Figure 6B, interface chip Ul shown in Figure 5A and digital s;~Al processor (DSP) chip U2 shown in Figure 5A
ccmprise a data pump chip set mAnl~fActl]red and sold by AT&T Microele.~r~,lics. A ~t~;le~ descr;pt;Qn of the o~e~dLion of these three chips in direct c~nn~ction and coo~e~dLion with one another is described in the pllhl; C~t; ~n entitled "AT&T V.32bis/V.32/FAX High-Speed Data Pump Chip Set Data Book" pllhl;qh~ by AT&T
Microele-lt~l,ics, neC~mh~r 1991, which is inco,~o~ted herein by reference. m is AT&T data pump chip set comprises the core of an ;nt~rated~ two-wire full duplex m~dem which is cApAhle of operation over sta"~d,d telerh~nP lines or leased lines. The data pump chip set conforms to the telecon~m;cat;ons ~~ec;ficAt;~n.q in CCITT r~c~ At;nn.~ V.32bis, V.32, V.22bis, V.22, V.23, V.21 and is co~pAt;hle with the Bell 212A and 103 m~R. Speeds of 14,400, 9600, 4800, 2400, 1200, 12,000 and 300 bits per second are ~ ~ported. This data pump chip set consists of a ROM-coded DSP16A digital signal processor U2, and interface chip Ul and an AT&T T7525 l;n~Ar CODEC U101.
~.

212692~ ~
The AT&T data pump chip set is available from AT&T
Microelectronics.
The chip set Ul, U101 and U2 on Figures 5A
and 6B perform all A/D, D/A, modulation, ~pm~ t;on and echo c~ncPll~t;on of all signals placed on or taken from the tele~hnn~ line, and performs DTMF tone y~leLdtion and detection, signal analysis of call ~i--~uy~ess tones, etc. The tr~n~mi~;on of infor~ut;on on the tele~hnn~ line from CODEC U101 is through buffers U104, and through line buffer U105 as described above. ;~
The ~ain c~ntroller of controller circuit 213 and the support circuits 212, 214, 215, 216 and -~
217 are shown in Figures 4A-4C and 5A. In the preferred emkc~'m~nt of the present system, the main ~u~lLIoller U5 shown in Figures 4A and 4B is a Z80180 eight-bit mi~Locw~Lroller chip. In the preferred implPmpnt~tinnl microc~lLLuller chip U5 is a Z80180 -~
m~ ,u-cessorl by Zilog, Inc. of Campbell, California. The Zilog Z80180 eight-bit microprocessor operates at a 12.288 MHz ;nt~rn~l clock speed by means of an ext~rn~l crystal XTAL, which in the preferred Pmh~;mPnt, is a 24.576 MHz crystal. The crystal circuit includes c~p~c;tors Cl and C2 which are 20 pf c~c;tors and resistor R15 which is a 33 ohm resistor. The crystal and support circuitry is c~nnPcted according to m~mlf~cturer~s specifications found in the Zilog TntPll;gent Peripheral Controllers -~
Data Book pllhl;.~h~ by Zilog, Inc. The product description for the Z80180 Z180 MPU from the Z80 CPU
Product Specification pages 351-392 of the Zilog 1991 Tntell;~nt Peripheral Controllers databcok is inco~o~dLed herein by reference.
The Z80180 mi~.u~ucessor in microcontroller chip U5 is ;nt;mAtely c~nn~cted to a serial/parallel I/O counter timer chip U4 which is, in the preferred ~mho~lm~nt, a Zilog 84C90 CMOS Z80 KIO
~erial/parallel/counter/timer integrated circuit 2126~26 9 . .
available from Zilog, Inc. This multi-function I/0 chip U4 combines the functions of a parallel input/output p~rt, a serial input/output port, bus control circuitry, and a clock timer circuit in one chip. me Zilog Z84C90 product .spec;fic~t;on describes the ~t~;le~ ;nt~rn~l oper~t;on.~ of this circuit in the Zilog Tntell1gent Peripheral Controllers 1991 ~ R~oh available from Zilog, Inc.
Z84C90 CMOS Z80KI0 Product specific~t;on pgs. 205-224 of the Zilog 1991 T~te11;gent Peripheral Controllers ~t~ho~k is illcoLko~dted herein by reference.
The memory chips which operate in conjlm~-t;~n with the Z180 mi~L~ c~ssor in mi~ /~ller chip U5 are shown in Figure 4C. The co....~;~n~ A, B corr~.spnn~ to the conn~ctions to the ad~L~s and data buses, respectively, found on Figure 4~. Memory chip U7 is a read-only memory (RoM) chip which is elec~rically L~ yL.... ~hle in circuit. This ~LoyL~nnable RoM, typically referred to as a flash PRoM, holds the ~eL~Ling code and operating parameters for the present system in a non-vol~t;le memory. Upon power-up, mi~Loc~l-LLvller chip U~
e~ tes the ~r~.l code that is stored in the flash PRaM U7. In the preferred ~mho~;mPnt, R~M chip U6 is 25 a p~ell~t~At;c RAM which is a dynamic R~M with a built-in refresh. Those skilled in the art will readily Lec~J,~;~e that a wide variety of memory chips may be used and substituted for pse~-static R~M U6 and flash PROM U7 without departing from the scope of 30 the present inv~nt;~n.
The interface between the main c~ L~ller circuit 213 and the ~e~s~lldl com~llt~r is through SIO
circuit 214 and RS232 serial interface 215. RS232 :.
conn~ct;~n J103 is shown on Figure 6A with the 35 A-~soc;Ate~ RS232 driver circuit U102 and interface and ring detect circuitry used to generate and receive the d~r ~r iate RS232 St~l~dld S; ~nAl ~ for a serial co~n;cAt;~n~ interface with a personal computer.

-" 212692~ :

Figure 6C is a detailed electrical s~hPm~t;c -~
diagram showing the generation of various voltages for -powering the hardware c~~ nt~s of the electrical s~h~m~t;c diayL~-~ described herein. The power for ,~
the present hardware comrnn~nts described herein is received from either a st~l~dr~ 9 volt battery or -~ ~-through AC adaptor J104 which is a standard 3 Pin -~
Power Jack. When the AC adaptor is plugged in, the battery is ~;~cv...,~cted. Power is cwlLI~lled by power switch S101. The preferred modem system is designed to run off of a st~ rd 9 Volt battery, thus resulting in a small, lightweight and easily trAnqportable package. However, it shall be ~l~el~Lood that the modem could also be run from any ~ -~
15 other power source using standard interfaces and ~ ~
c~llv~Y~ion circuitry known well in the art. 5 volt -re~lAt~r Ul07 is a l;n~Ar regulator with a low drop ~-out voltage of about 5.3. Q102 is a MOSFET which c~-Lr~ls on/off as directed by power switch S101.
Power 8witch S101 turns on MOSFET Q102, and has three positions, on, off, or auto. In auto position, power ~m ;
8witch S101 ~nqe~ the Data T~rm;nAl Ready Signal from the computer, and if that is not present, then the power to the modem i8 turned off completely. Thus, if - ~ ;
no com~m;C~t;~nq software is lo~ , the modem is Antom~t;cally off such that no power is wasted. From the circuitry of Figure 6C, the +9 volts DC is r~llAt~ down to 5 volts, and is also inverted via Ul06 to get a nP~t;ve voltage. The n~t;ve voltage is used to drive the RS232 driver Ul02 shown in Figure 6A. As a result, five volts are derived for operating the various memory, logic and coll~L~ller chips and support circuitry of the present system.
Figure 5B shows connPctor J1 which interfaces with cnnn~ctor J101 shown in Figure 6A.
Figure 5C shows the intelc~..,..~ction of the status TFn~s found on the front display of the modem of the ~ -present inv~nt;nn. ;

., : ~.

-' 2126926 PnW~t- ~A~ r~ F~A I ~
Referring again to Figure 5A, the interface chip U~, discussed in detail above is shown. Also shown in the upper left portion of Figure 5A is power -saving circuitry which is inc~L~oLd~ed into the present mcdem sy~tem to enable the practical implem~ntAt;~n of a small, lightweight and easily portable mcdem suitable for use with a laptop computer, for example. me power saving features of the ~s~lL modem system allow the design to be powered from a St~ 9 volt battery as discussed above with re.spect to Figure 6C.
In order to c~,~eL~e power, various power saving features are provided which allow the present modem system to be put in a low power, or "sleep"
mode. In sleep mode the power to the modem is greatly re~l~e~. There are three main power saving features in the sieep mode. First, addit;~nAl circuitry has been added in the preferred ~o~ nt to allow addi~;onAl power savings to be re~l;7e~ Pc~n~, the AT&T data pump chip set has a built in low power mode.
Third, the Z180 MPU U5 also has a built in low power mode.
The AT&T data pump chip set Ul, U2 and U101 described in detail above has the ability to be put into a low power mode. When in low power mode, the CODEC bit clock ~ generated by interface chip Ul shown on Figure 5A is slowed to 115kHz to provide a required clock signal to DSP chip U2 and CODEC U101.
The data pump chip set enters sleep mode Allta~t;cAlly after a reset, a di~c~ ct or by user ~ . The chip set Al~to~t;cally wakes up when a ring signal or host c~ ,w~ is received. The built-in sleep mode of the AT&T data pump chip set is described in more detail in the afo~"~ ;PnP~ publication entitled "AT&T V.32 bits/V.32/FAX High-Speed Data Pump Chip Set Data Book" pllhl; ~hP~ by AT&T Microelectronics, ~lec~ 1991. ''~ ' In addition to the power saving sleep mode provided by the AT&T data pump chip set U1, U2 and U~Ol, the present inv~nt;~n provides addit;~n~l power saving features. These features include providing an ~x~rn~l clock o~c;ll~tor XTLl. Circuitry is provided such that ext~rn~l clock osc;llAtor XTL1 can also be put in sleep mode (disabled). This results in a s;~n;f;c~nt power savings as the osc;ll~tor would -;
c~n~nn~ power lmnece$s~rily when the modem is not in use. When XTL1 is disabled, the clock to CODEC U101 is switched to a low fre~l~n~y, d~U~;m~tely 100 kHz signal y~ler~Led from K10 U4 of Figure 4A via N~ND
gate U10 of Figure 5B.
Crystal XTL2 is a 20.275 MHZ crystal which -~
is used in conjunction with an ;nt~rnAl osc;llAtor provided on interface chip U~. The ;nt~rnAl -o~c;ll~tor is described in the above listed ~nn~nt~t;on for interface chip Ul.
The ~,eselL modem system can be ~s~mhled with either the crystal XTL2/C17/C18 comh;n~t;on or the e~tern~l clock oSc;ll~tor XTL1/Cl9 c~mh;n~tion.
With either ccmh; nAt;~n, the power saving feature built into the AT&T data pump chip set U~, U2 and UlO1 can be used. However, with the XTL1/C19 csmb;n~t;on the AT&T data pump chip set power saving feature and also the addition~l feature of disabling e~ternAl osc;ll~tor XI~Ll can be used for even greater power savings. E~t~rnAl clock osc;llAtor XTLl is part m mhPr ao2810 av~ hle from Raltron C~l~oIdtion of Miami, Florida. E~t~rn~l clock osc;ll~tor XTL1 has a fre~]~n~y of 40.5504 MHz and is described in more detail in the pl1hi;c~t;~n entitled "CLOCK OSC, Model 0~2810 Series (SMD Type OSC)", pUbl;~qh~ by Raltron ~;
C~oLdtion, which is incorporated herein by refeLell~e. In the preferred ~mho~;m~nt, ext~
clock osc;ll~tor XTL1 is used as the main clock for the AT&T data pump chip set Ul, U~ and U101 and runs at 40.5504 MHZ to drive the interface chip U1.

.~, , . ;~

-' 21~692B
' 13 When the present modem system is off-hook and the Z180 MPU U5 is not processing, the Z180 MPU U5 can be put into a low power or STT~'T~P mode. The Z180 MPU ST.FEP mode places the CPU into a state in which 5 the ;nt~rn~l CPU clock stops, thereby consuming less current. The Z180 MPU U5 wakes up when one of the interrupts INT0, INT1 or INT2 shown in Figures 4A and 4B is asserted.
INT0 wakes up the Z180 MPU U5 in response to interrupts generated by K10 U4. INT1 wakes up the Z180 MPU U5 in re,qp~n~e to a RNGL or ~ t~h~ timer (WDOUT-) signal. The ~-t~h~g is a slow timer (in the sec~n~) which allows the processor to keep track of time. For example, the processor must keep track of 15 the time for which the modem cannot call a blacklist of forbidden phone numbers. INT2 wakes up the Z180 MPU U5 in rP~p~ e to a DTE data signal (TD shown in Figure 5B).
me built in SLEEP mode of the Zilog Z180 MPU U5 is described in more detail in the afo~"-,.l;oned public~t;~n Zilog TntPll;gent Peripheral Controllers 1991 ~n~ho~k.
Flmrl I r~ns l l~r~1- ~ nm ~f T~ ; r~ ~rr~l p The preferred modem system includes two 25 c~llLlol ~loy~ which c~lL~l the remote in-circuit yl~l,.";n~ of system firmware, a flash control ~r~y ~" and a boot c~llLr~l ~LOYL~II. ~he flash control ~I~YL~II runs in the host PC and receives updated operating code downloA~P~ from a bulletin board. The updated code is downloaded to the host PC in the form of Intel HEX files. me flash control program processes the HEX files and creates the packets cQ~ta;n;n~ the updated code which are actually sent to the modem. Each packet c~ntA;n~ a field cont~;nln~
the packet length, the address at which to store the llp~te~ code, the actual ~royL~" data and a checksum.
The boot CU11~LO1 ~1UYL~II ~mn;ng in the modem checks that the packet was correctly transmltted and ~royL~,~

.
. ::, ~:
.

212~926 ;;

the updated operating code at the address specified in the address field of the packet.
. ~ .. .
In summary, the flash control ~yL~Ils uu~ ol the host PC side of the process of in-circuit reprogr~~;ng of flash PROM U7. The boot control yL~II controls the modem side. As described above, flash PRoM U7 is an in-circuit ~LoyL~--~ble and electrically erasable read only memory. As is well known to those of skill in the art, these memory chips ~
10 allow in-circuit L~ yL~Il.";ng of the operating code ~ - -and par~m~t~rs which are stored in the flash PROM chip ~M-U7. Although the present modem system is described with respect to a particular flash PROM U7, it shall be understood that any in-circuit ~ yL~-.-~ble 15 memory configuration could be used without departing ~-from the scope of the ~LesellL inv~nt;~n.
Before flash PRoM U7 is ~.~~~mhle~ in the modem circuit, the boot o~llL~ol ~L~yL~ll iS hllrn~, or ~LuyLdmmed into flash PRoM U7 using conv~nt;~n~l PRoM . :-: :~
~yr~..ners and ~l~yL~l~ing te~hn;~l~s.
When a bug fix, ~"h~ ..~..l or other new rele~e of system u~eLdLing code beco~.s available, ~ ;
the flash control ~LUyL~.. iS used to control the remote lsAA;ng and proc~ss;ng of u~e~d~ing code dow~lo~ over tel~rh~n~ line from a o~l~al bulletin board. The boot control ~UyL~II receives the updated code from the host PC over the serial port and uull~Lols in-circuit L~roy~ "ing of the new operating code into flash PROM U7. , ;
The field ~LuyL~~ ble feature of the modem system of the present inv~nt;nn has several advAnt~e~. RerAll~e a user can remotely load new - -~;-operating code over a remote tele~h~ c~nn~ction, code llp~Ates can be obtA;n~ ;mr~ t~ly as soon as they are available instead of waiting for new parts to be sh;rp~. In addition, no physical removal or rPplA~m~nt of parts is required thus significantly re~uc;n~ the ~hAnce of breakages. Further, no special : , . ''' ~1269~
~ ,, tools are required to L~ and replace parts, and no special PROM ~oyL~ n;ng e~l;rm~nt is required to L~loyL~I the memory chips. Finally, the need for a techn;c;An to travel to the remote site to perform the upgrade is avoided thus significantly re~l]~;ng costs ~-~.soc;~t~ with the upgrade.
nPtA;le~ descriptions of the flash c~llLLol ~yL~Il and boot c~llLLol p~oyLdln will now be given.
The illustrative embc~;m~nts of the flash control 0 ~L~yL~I and boot C~ L~1 ~LoyL~n described and shown herein is with srec;~l reference to a PC-based DCS
u~eldLing system. It shall be understood, however, that the present inv~nt;~n is in no way limited to a -~
DOS o~eLdLing system. The preferred modem system can also be used with a UNIX-based operating system, ntosh o~eLd~ing system, or any of a m ~h~r of ~e~dLing system plAtfor~ simply by cust~m;~;ng the user interface to run on the desired operating system.
~1-~;1~ T~J~r~ f Fl :-~h t~n1-~1 p~r~
The flash c~llLLol ~L~yL~I~ is used to c~lLLol the L~LUY~ ;n~ of l~Ate~ operating code and ~a~ ~L~rs into the flash part of the modem.
me l~r~Ate~ operating code is distributed to the user according to the proce~]re shown in Figure 7.
Tb get the l~r~te~ HEX files cnntA;n;n~ the l~Ate~
u~eLdLing code are do~nlQA~ over a phone line from a c~mrllt~r hllllet;n board to the host PC. m e HEX files are preferably in the Intel MCS-86 HEX format. This is an industry standard for HEX files.
The HEX files cont~;n entirely ASCII
characters and ;n~ P three record types: Data ~-~
Record, End Record and FX~n~ Address Record. The form~ts of the three record types are described in ~A;1e~ at page 27 of the User Manual for the Gtek EPROM ~L~yr~l~l~L model 9000, dated 01-11-88, which is in~o~oL~Led herein by reference, and are as follows:

212fi92~
., Data Record Ryte nlnnher Contents Colon(:) 5 2-3 N~nber of binary data bytes 4-5 Load address, hlgh byte 6-7 Load address, low byte 8-9 Record type, must be "00'~
10-x Data bytes, 2 ASCII-HEX characters 10 x+l - x+2 Checksum, two ASCII-EIEX characters x+3 - x+4 carriage return (CR), line feed (LF) , ; '~
~ C~L~
Byte ~ mher ~ontents Colon(~
20 2-3 Record length, must be "00"
4-7 ~xecution address 8-9 Record type, must be "01"
10-11 Checksum -12-13 CR,LF ~ -dg~3 Reco ~yte rn~ r ConteTlts 30 1 Colon(~
2-3 Record length, should be "02" ~
4-7 Load address field, should be "0000" ~-8-9 Record type, must be "02"
10-13 US13A-this m~h~r multiplied by 16 is the new load offset address For our use only the first digit is ~;
used as the 64K bank offset value 14-15 Checksum -~
16-17 CR,LF - ~ -Figures 8A shows a detailed flow diagram of the flash control ~ro~ " 800. The beg;nn;n~ of the flash collLLol program 800 is shown. First, the -;nt~rn;ll envir(,",~ and variables are init;~ e~.
The preferred flash control ~ yr~ 800 accepts either 45 c~,~ line parameters or can be run in a menu driven mode. I~e present state of the user interface screen is saved and cleared while the field upgrade control ~L~LC:IIII iS rl~nn;tl~. The screen is saved for later restoration after the ~;e~loy~c",.l,in~ is completed.

212692~

Flash control pL~II 800 cont;n~s at c~ ol block 802, which starts the help system. The help system ~oLLs onscreen status me.ss~es to the user during various stages of ~ oyL~I,..,;ng. At times inform~t;on may be requested from the user. Also, error m~ss~s and po!~s;hle courses of ~ti ~n are ~;~plAyed when ~L~.iate.
Next, flash c~ ol p~yl~ll 800 reads the setup file to ~t~r~;n~ which serial port the modem is c~nn~cted through, the a~r~iate baud rate and other n~ceS,S~ry setup inform~t;on. The serial port is then init;Ali7e~ according to the setup information QbtAin~.
Control block 804 allocates a 128 kbyte memory buffer in the host PC. This memory buffer is used to store ~cesse~l HEX files contAin;n~ the te~ ~e~ n~ code to be ~oyL~...~d into the flash PRCM in the modem. Proc~;n~ of the HEX files is ~-described in ~t~;l below with respect to Figure 8B.
If "ADTOM~TIC MODE" is set at query 806, flash C~ L~1 ~yr~ 800 ~l]to~t;c~11y runs the user ~ ;
through the re~o~L---;n~ ~L~ce~ure. However for certain m~nlfActllring and R&D purposes, it is desirable for the user to have more control over the 1'e~LOYL~ ;n~ procedure. Thus, Al~to~At;c m~de can be ~;~Ahle~. When AlltamAt;c mode is disabled, the flash ~11LL~1 ~1~YL~II checks whether the name of the HEX
file to be ~LuyL~l~ed is present on the c~,.,~ 1 line. ~;
If not, a user "~KO~SS MENU" will ~pe~Ar on the screen at control block 807 with the choices "PORT
SETUP," "READ FILE," 'l~Kc~KAM~ll or "EXIT." me user can then select the functions to be perfonmed. If the HEX file name was on the c~1-1~11(3 line, the flash control ~OyL~ll c~nt;ml~ with READ AND PROCESS FILE
routine 810 described in detail below.
Otherwise, in AUIOMATIC MODE, flash control ~r~YL~II 800 cnnt;ml~ at the top right portion of Figure aA with control block 808. Here all HEX files present in the host PC are found and their names ~ ~
displayed onscreen. The user chooses the name of the -~- -file to be ~LcyL~I~l~d into the modem. If the desired file is not listed, the user can press the ESC key to exit the ~LUyL~--.
Although the bytes of each record in the HEX
files dow~lo~ from the bulletin board are - ~ -~
.~e~l~n~; Al, the HEX records themselves are in no ~ -particular order within the file. The file must --~
therefore be process~rl and sorted into a format which can be pruyL~ into the modem. READ AND PROCESS
FILE rollt;n~ 810 reads the standard Intel HEX files stored in the host PC and performs the n~c~s~sAry HEX
file proces.~; n~.
Figure 8B spows a detailed flow diagram of the RE~D AND PROCESS FILE routine 810. The purpose of READ AND PROCESS FILE nol~t;n~ 810 is to convert the ASCII HEX characters c~ntA;n~ in the HEX recor~s to a -binary fonmat a~Lu~iate for ~yL~ ;n~ into flash PROM U7. R~llt;ne 810 he~;n~ with an l ~ Ate of the Le~l help display. Next, the memory buffer is ~ dlll i.e., set to all FF hex (all 1 binary).
This c~Lr~G~ to the erased state of flash PRoM U7.
Next the HEX file is o~x~ed for read ~ccess and the first HEX record is read. The lecuL~ is then ~aL~ed to check syntax and to ~t~r~in~ the record type ;n~1CAt~ by the record type field of each HEX
record as described above.
If the record is type 0 the record is a data record. The record is processed as a data to be lo~ in the memory buffer at the current memory pointer, where the pointer is the current 64k page plus the address supplied in the record. After the data is converted from a ASCII text to binary and stored to the memory buffer, the po;nter is in~r~"~.~le~ to the next available space in the buffer.
Record type 02 ;n~;c~tes an ext~n~ address -~
record. The infor~t;on in these records is converted , . ..; ., ---' 21269~

from ASCII text to binary and processed as a 64k page number to be added as an offset to all of the following records until a new record type 02 is re~h~
Record type 01 indicates an End of File (EOF) record. If address 0000, 0001 or 0002 were ~y.~l~led, these addresses are forced to 0c3h, 00 and 01, respectively. This is the code for a jump to boot cu~lL~ol area, rather than the n~rm~l modem code. This step ensures that the boot control area of the flash part is not corrupted. -READ AND PROCESS FILE routine 810 reads --through the records in the HEX file until all records have been read, processed and stored into the memory buffer in the host PC~ After the last record has been processe~, the READ AND PROCESS FILE routine 810 is cc~pleted.
Referring again to Figure 8A, after READ AND
PROCESS FILE routine 810 is completed, flash c~lLlol ~1UYL~II 800 queries the user ensure that the correct file to be ~r~L~I~l~d into the modem has been ;~nt;fied. If not, the ~LVY~II exits. Otherwise, flash control ~LU'YL~II 800 c~nt;m~s with PROGRAM FILE
INTO ~K~U~l routine 820.
Figure 8C shows a detailed flow diagram of PROGRAM FILE rNTO PRODUCT routine 820. The present modem system uses the well-known and widely used AT
c~l.l~.l.l set. As is well-known in the art, the AT
c~l.~ll.l set allows a user to control a modem by entering c~ through a computer key~oard. The AT
c~,.,~"(l set can be used to direct the modem to perform functions such as accessing a tele~ho~ line, taking the receiver off-hook, ~;Al;n~ and hanging up. The AT
c~ rl(l set can also be used for more intelligent functions such as do~nlo~-ng or uplo~ng files.
Many of these more intelligent functions of the AT
~ .,(l set are used in the present modem system, as 2~ 26926 ~: ~

described in more detail below. The AT ~ 7 set is used in the PROGRAM FILE rNTO PRODUCT ROUTINE 820.
A general overview of the PROGRAM FILE INTO
PRODUCT routine 820 will now be described with ~ ~ -reference to Table 1 and Tahle 2. The hAn~.qh~king ~r~c~h]re which negotiates the transfer baud rate between the host PC and modem, which was discussed above is shown in Table 1. The AT ~ w~ set shown and described in Table 2 is used to control the modem. ~
10 All data sent is 8 bits, no parity and 1 stop bit. - ~ -T~hle 1 -~Q~ Mbdem Power up or AT*FS triggers ; ~ -~ t; on of the boot code.
Send 'M's at 19200 ~ with 'U' at 19200 baud baud if 'M's received within 30 ms of power u~ or AT*FS ~.
C~~ 7. Otherwlse jumps to maln code on time out.
.
Send 'D' at 19200 If 'D' received within 300 ms 25 baud of when 'U' sent, then modem r~ with - -'J': can receive at 19200 baud 'K'- can receive at 19.2k or 38.4k baud 'M': can receive at 9.6k, 19.2k, 38.4k, 57.6k or 115.2k ;
baud. - ' -Otherwise jumps to main code on time out.
If 'J' then 19200 baud -Otherwise may send 'I': 9600 b~ud 'J': 19200 baud 'K': 38.4k baud 'L': 57.6k baud 'M': 115.2k baud ~ ~ ~
45 Configure for Configure for negotiated ~v negot-Ate~ speed. speed.
Referring now to Figure 8C, the serial port is init;Al;~e~ to 19200 baud, and is set for packets of 8 bits, no parity and 1 stop bit. AT*FS is a .
. .
-special c~ l which tells the modem to jump to address zero, which is equivalent to powering on the -mDdem. At that point, the host PC and modem ~ in a h~n~h~king procedure to negotiate the transfer baud rate, shown in t~h~ r form in Table 1 above.
Pursuant to this hAn~h~king procedure, the host PC -starts s~n~;n~ capital 'M's to the modem at an initial baud rate of 19200. me host PC sends 'M's until it receives a 'U' r~pQnqe from the modem. Timeout is 10 controlled by the modem side as described below with ~ ~ -r~rect to Figure 9A. m e host PC cQnt;ml~s to send 'M' at 19200 baud until a 'U' is received.
In the norm~l case, the modem will respond with a 'U' within 30 m;ll;qecQn~. At that point, the PC will send back a 'D' and the modem r~r~n~q within 300 mLq with either 'J', 'K' or 'M', dep~n~;n~ on the modem version and the corresp~n~;n~ baud rate at which it can run. If the modem r~ with a 'J', the cQmrllt~r ~ s a baud rate of 19200.
If the modem r~ with a 'K', the cQmrl~tPr can ~ ose 38400 or 19200 baud. A re~,..qe of 'M' means that the modem can be run at 9600, 19200, 38400, 57600 or 115.2k baud. The PC sends I, J, K or M to set the speed. The host PC and m~dem then each init;~ e the negot;~t~ baud rate and configure accordingly.
me modem is now ~h~a~ed to receive the AT
1 set as shown in Table 2:
T~hl~ ~
30 ~.... ~.. l Descr;pt;on ATIx, where x=0, 1, 2, or 3 special codes ATFLEND exit program and jump to main code ATFLP ~yL~II a packet Next, the host PC sends an ATIl me ATIl c~ cont~;nq the boot control ~y~
. ,. . ~ .. .

22 2 1 2 ~ 9 '~ 6 version number. The version number det~rm;nes the packet size, which can range from 128 bytes to 4k byte -packet size depPn~lng on the version number received.
me host PC then sets the max packet size according to the version number received.
Next, as shown in control box 880 in the top right of Figure 8C, the host PC initializes pointers to the top of the R~M buffer which was allocated in ~ ~
control box 804 shown on Figure 8A, and in which the ~ - -10 proce.~se~ and sorted updated operating code to be ~ ~ -~L~L~I~l~d into the flash PROM in the modem is stored.
Once the pointers are init;~ e~ to the top of the RAM buffer in the host PC, control block 882 c~,.,~"~ the PC to check a software protect switch which when enabled prevents overwriting of the ~yLdlll area of the flash PROM in which the boot control ;~~L~yl~ll iS stored, or which when disabled allows ~ -portions of the boot C~lLLOl p~yL~II to be u~t~
For n~rm~l use the software protect switch is enabled to prevent erroneous overwriting of the boot C~llLL~
~L~yL~I~ area. However, for R&D or m~nl~facturing purposes it may be n~c~.q~ry to update or L~OyL~III
the boot c~lLLol area. The software protect switch thus provides a software "back door" which allows ~ce.~.~ to the area of the flash PROM where the boot control ~L~yL~II iS stored.
Referring again to Figure 8C, the host PC
h~;n~ to build a packet which will be sent to the modem over the serial port. -In the control blocks 884 and 886 the host PC builds a packet by searching through the HEX files in the RAM buffer, searching for contiguous non-blank pages. A HEX file blank page is ~f;n~ as a page ~yL~I~lied to all FF. Whenever a non-blank page is found the packet length is in~L~"~,le~. Variable length packets may be sent in sizes up to the ~peclfied max packet length determined by version number as described above. Once a blank page is found or the max packet length is re~he~, the - ., .,, : ,. , . - . , 23 212692~ ~ -packet is complete and ready to be transferred to the modem over the RS232 serial port. -me packet built by the process shown in control blocks 884 and 886 includes a h~ r portion 5 and a data portion. me he~r portion includes a - -~
length field created by the hQst PC as it builds of ;
the packet. me h~A~r portion also includes an address field which cnnt~;n.~ the physical starting address of where the data is to be placed in the flash -PROM. me data portion includes the updated ~lOy-~"
data bytes and an XOR'd checksum. The packet format is shown in Table 3~
T~hl~ 3 P~ket F;~l~ F;~l~ T~n~th Length High 1 byte ~
Length Low 1 byte - -Address High 1 byte (only lowest order 4 bits used, upper 4 bits set to ~
Address Middle 1 ~yte -- --Address Low 1 ~te Pr~y~ll Data x ~tes XOR'd checksum 1 ~te After the packet is built, the host PC sends the c~ ATFLP to the modem, the ~ "~ for ~UyL~I a packet. Upon receipt of the ATFLP c~.~.,~l, the modem re~ with a 'G'. The host PC then ~r~ ~..uts the data packet pointed to by the RAM buffer pointer.
After the packet is received by the modem, 35 the modem generates its own checksum based on the data ~-received and compares it to the checksum sent by the ~ -~
host PC. If they are equivalent, the modem re.spnn~
with 'OK', and the received code is proyL~~ ed into the flash PROM address pointed to by the Address High, Middle, and Low bytes. Otherwise the modem responds with an error.

' ..

.. ~
The host PC will run through the ~oyl~"~.,in~
loop, searching through the RAM buffer, cre~ting packets and sen~;ng packets to the modem until the ~lUyL~ .,.;ng is complete or until 5 consecutive errors occur.
After the host PC has sent all the packets, as ~PtPrm;n~ by the DONE PROGRAMMING query, the host -PC sends an ATFLEND c~ ..(l to signal that ~r~y~ ;ng is c~m~leted. After the file has been ~y~ l~d, an exit rollt;n~ shown in Figure 8A is run in which timers are shut down and the state of the screen is restored. m e user is infonmed that the ~OyL~II iS
completed or was tPr~;nAteA due to error. me ~yl~ll -~ - -then jumps to the n~ l modem code.
~ ;loA nO~p~inn ~f ~h~ Rnnt ~hn~.rnl pr~gr~m Figures 9A and 9B show a flow diagram of the boot c~~ ol ~r~yl~ll. Figures 9A and 9B show the same ;ng ~L~ce~re as described above with re~p~ct to Figures 8A-8C, ~q~ that Figures 8A-8C were 20 described from the ~e~ective of the host PC and -Figure 9A and 9B are described from the perspective of the ~n~m. The ~,~y~,.be~;nq with power up or AT*FS. ~-~
The serial port ~eL-t~}l modem and host PC is init;~l;7~ for 19200 baud. At this point the modem also cop;es the ~o~r~.. code into RAM. The boot c~l,LL~l ~r~yl~ll is run out of RAM while the flash PROM
is .e~uy~ e~. This is because certain bits in flash PROM U7 are to~le~ during ~ y~ in~ and therefore the boot control p~y~ll must be copied to 30 RAM to avoid corruption of the boot control code.
Next, the hA~ h~king protocol described above with respect to Figure 8C is performed. The modem init;~ es a counter for 30 ~;ll;.qec~n~q. If the modem receives an 'M' from the host PC, the modem r~spon~q with a 'U'. If no 'M' is received, the counter is de~ le~. The loop will timeout after 30ms if no M is received. The m ~her of times ' "''''.' ''''.

through the loop is dep~n~nt on the crystal speed of the modem, but is equivalent to 30 m;ll;.qec~n~
When the 'M' is received and the 'U' --re,~n.qe is sent, another counter is init;Al;~e~ to 300 ~;ll;qec~n~q. If a 'D' is received from the host PC within the 300ms timeout, the modem re,~wl~s with a 'J', 'K' or an 'M', ~p~n~;n~ of the baud rate at ~-which the modem can run.
The host PC then sends either 'I', 'J', 'K', 10 'L' or M, and both the host PC and the modem confiyure -their baud rates according to the negot;Ate~ speed.
The AT c~..,~ ATFLP, ATFLEND or ATIx can now be received by the modem. Flow diayrt~l~ showing the ~royL ~;n~ procedures on receipt of these 15 c~ 7~ are shown in Figures 9B-9D. ~ -Figure 9B shows the control flow upon receipt of the ATFLP c~ ,~--(l. The modem first re~J..~l~ with a 'G' to ;n~;cAte that the ATFLP C.~
was received. Next, the packet length bytes and ~ ~ -~L~t~yL~ n~ address bytes are received from the host PC. A colmter iS init;Al;~ to the length of a packet, and the ~lle~,~,b,~m is init;~ e~ to 0.
m e modem next runs through a loop, getting each data byte and cAl~lAt;n~ a new checksum by XOR'ing the ~lle~ m from the previous iteration through the loop with the data received. m e modem cnnt;mlPs through the loop, de~ -,l-;n~ the counter each iterAt;~n until the count equals 0, indicA~;n~
that the entire packet was received.
Next, the modem receives the checksum data byte which was generated by the host PC. If the checksum data byte generated by the host PC is equal to the checksum generated by the modem, the data bytes are ~yLt~I~ into the pro~rAmm;n~ address sent with ~ -the packet into the flash PROM and an 'OK' resp~n~e is sent to the host PC. If the checksums are not equal, an error m~.s,s~e is sent to the host PC.
Figure 9C shows the flow diagram for the . .

'::. ' ' ' ~ 212692~

ATFLEND ~ 1. As discussed above, the ATFLEND .
c~.. ~ l occurs when ~r~y~ ing of the flash PROM is ;~
completed. If the c~...~-~ ATFLEND is received, the serial port is disabled and a jump to the normal modem 5 code is performed. ;
Figure 9D shows other c~ q ATIx, where - ~;-x=O, 1, 2 or 3. ATIO C(~ the mcdem to respond with a product ;~"t;fication code. ATIl c(~ q the modem to respond with a boot version m ~h~r, which is the version of the boot c~llLIol ~cy,~" installed in the m~dem. The boot version number is important hec~ e different versions may require different packet lengths.
ATI2 is for ;~nt;f;c~t;~n of a basic modem 15 or hardware platform. MT1432xx indicates a derivative -of the basic M11432 platform, for example. These ~-could ~P~.~ more qpec;f;c to f~c;l;tate a more ;ntell ;~nt host interface. ATI3 can be used to - -~
;n~;C~te colmtry types, ~pec;~ f~lllts, or for ~-future ~Y~ n of making a smarter PC host inteLLa~

''' ,' ' ~ :

: "' .: ,,,~, : , ..... ....
' ~: -' " ' ' ~ ~:

Claims (8)

1. A system for updating operating code in a reprogrammable modem the updated operating code being downloaded from a remote computer via telephone lines, comprising:
a field-upgradable modem having;
communications interface means connected for communicating with a local host computer and operable for transferring data between the local host computer and the modem:
telephone line interface means for connection to the telephone line;
control means connected to the telephone line interface means and the communications interface means for executing existing operating code to control the modem;
memory means connected to the control means for storing the existing operating code and for storing a boot program;
the control means further operable for executing the boot program to receive updated operating code packets from the local host computer, for checking the validity of the packets and replacing the existing operating code in the memory means with the updated operating code received by the communications interface means from the local host computer;
the local host computer executing software to communicate with the remote computer through the modem connected to the telephone line and operable for initiating a telephone call to the remote computer in response to the commands by a local user of the local host computer and for controlling downloading of the updated operating code from the remote computer to the local host computer; and the local host computer further executing software to communicate with the modem through the communications interface, to place the updated operating code into updated operating code packets and to control transfer of said updated operating code packets from the local host computer to the modem over the communications interface.
2. The system of claim 1 wherein the memory means comprises an Electrically Eraseable Programmable Read Only Memory.
3. The system of claim 1 further including:
power saving means connected to the control means for conserving power when the modem is not in use, the power saving means comprising:
external oscillator means for providing an external clock signal to the control means during use of the modem by the local host computer;
low frequency oscillator means for providing a low power, low frequency clock signal to the control means when the modem is not in use;
the control means further for operating in a first power mode when the modem is not in use;
the control means further for operating in a second power mode when the modem is in use.
4. The system according to claim 1 wherein the control means is further operable for executing the boot program for programming the updated operating code into the memory means by performing the steps of:
(a) reading a packet of the updated operating code having a first format and transferred from the local host computer;
(b) converting the packet of the updated operating code from a first format to a second, binary format;
(c) storing the binary format of the updated operating code in a memory means;
(d) reading a next packet of the updated operating code transferred from the local host computer; and (e) repeating steps (b)-(d) until all of the updated operating code is stored in the memory means.
5. The system according to claim 1 wherein the control means is further operable for programming the updated operating code into the communications module by performing the steps of:
(a) negotiating a baud rate between the first device and the communications module;
(b) creating a packet having a packet identifier, a length indicator, a programming address and a variable amount of the processed updated operating code;
(c) transmitting the packet to the communications module;
(d) programming the processed updated operating code in the packet into the memory means at the programming address; and (e) repeating steps (b) - (d) until all processed updated operating code is programmed into the memory means.
6. The system according to claim 1 further including:
an external oscillator adapted to output an external clock signal;
the modem further including a data pump circuit connected to the telephone line interface means and adapted to control modulation on the telephone line, the data pump circuit requiring a clock signal when not in use;
a low frequency oscillator connected to the data pump circuit adapted to output a low frequency clock signal and adapted to operate using low power; and sleep means for disabling the external oscillator when the communications module is not in use, and further for enabling the low frequency oscillator to provide the required clock signal to the data pump means.
7. A modem which handles communication between a remote computer connected to the modem over a telephone line, and a local computer connected to the modem over a communications interface, the modem operating under control of operating code to which periodic updates are made, comprising:
storage means in the modem for storing the existing operating code, for storing a boot program and for receiving and storing updated operatingcode;
data pump means in the modem for receiving the updated operating code from the remote computer over the telephone line;
control means connected to the storage means and the data pump means for programming the updated operating code into the storage means, said control means including:
receive means for receiving the updated operating code from the remote computer and passing it to the local computer;
protocol means for transferring the updated operating code from the local computer to the modem over the communications interface according to a predetermined communications protocol and using a packet format;
check means for verifying that the updated operating code was accurately transferred; and conversion means for converting the packet of the updated operating code from a first format to a second, binary format.
8. A method of upgrading the operating code which controls a modem comprising the step of:
(a) storing in a remote computer updated operating code;
(b) transferring the updated operating code in a first format from the remote computer to a local computer;
(c) storing the updated operating code in a first memory buffer in the local computer;
(d) reading a first portion of the updated operating code;
(e) creating a packet having a packet identifier, a length indicator, a programming address and the read portion of the updated operating code;

(f) transmitting the packet to the modem;
(g) storing the packet of the updated operating code into the modem [system] at the address specified in the programming address;
(h) reading a next portion of the updated operating code;
(i) repeating steps (e) - (h) until all of the updated operating code is stored into the modem.
CA002126926A 1993-07-02 1994-06-28 Modem with firmware upgrade feature Expired - Fee Related CA2126926C (en)

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Publication number Publication date
EP0632629B1 (en) 2004-09-22
US6526092B1 (en) 2003-02-25
JP2002247226A (en) 2002-08-30
US6031867A (en) 2000-02-29
EP0632629A1 (en) 1995-01-04
US20020114384A1 (en) 2002-08-22
US6928108B2 (en) 2005-08-09
DE69434017D1 (en) 2004-10-28
US5644594A (en) 1997-07-01
US6341143B1 (en) 2002-01-22
ATE277472T1 (en) 2004-10-15
CA2126926A1 (en) 1995-01-03
JPH07147611A (en) 1995-06-06

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