CA2128767A1 - Control architecture for atm networks - Google Patents

Abstract

Abstract of the Disclosure A control method and architecture is described for an ATM network carrying connections data traffic. The method is capable of integrating connection-oriented as well as connectionless traffic. The method takes advantage of the quasi-deterministic nature of the traffic emanating from a source that is being shaped by the leaky bucket shaping algorithm. Alternative methods are provided if such a shaping algorithm is not provided by the CPE which methods still guar-antee performance that equals or exceeds shared media networks such as FDDI.
Hardware and software embodiments of the methods are disclosed. The invention is particularly applicable to LANs and hubs.

Description

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Background of the Inventioll The present invention relates to a control architecture for asyncllronous trans-fer mode (ATl~/l) networL;s, and specifically relates to a burst-level control for controlling access in an ATM network While the following description describes tlle invention in conjunctioll with a ~AN, the invention is not so limited and is applicable to any ATM network There is tremendous interest in the development of ATM based LANs that provide connectivity between local work-stations and servers and are also suitable for use as a hub.
Current LAN technologies have media access control which ensures that ollce a station gains access to the medium, no frame loss results (except due to random noise). Many ATM-based switch architectures, on the other hand, do not have such control. Moreover, because of the limited amount of high speed memory that is provided in a switch, it is possible for there to be significant cell loss, especially when there is hot spot traflic from several bursty sources all directed to a single output port. For example, such a condition occurs in a client server model. The resulting cell loss leads to large frame loss when compared to systems having media access control. Therefore, it is essential that during periods of overload the bandwidth at a hot-spot output port be shared in a manner similar to that in a shared mediurn network.
A solution to implementing media access control and shared bandwidth at a hot-spot output port is to institute a burst-level control that manages media access in an ATM LAN. Burst level control is preferable in an ATM LAN when the following conditions are met: sources generate large bursts (compared to.tl1e amount of buffer mernory in the switch) that will result in buffer overlflows inthe absence of any control; blocking a burst at the beginning of the burst is preferable to having retransmissions of bursts already in progress and frequent retransmissions due to cell loss increases the effective load Oll the system, resulting in an end-to-end throughput that is several times slower than that of a share(l medium networl;.
However, it is iml)ortal)t that tl~e l)urst level control l)e dol~e il~ real tillle so tl)at the latel)cies iu admittil)g uew bursts do not becollle a sisnifical)l. l)ottleuecl;.
The presellt iu\,el)tiol) (lescril)es a I)urst level control ll)etllod al)~l a.l~pala.t~ls ~;, ` ' . , ~ 212~7~
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for use il~ al~ ATI\I LAN. Tlle bulst leve1 plovides botl~ a Ille~lia access col~trol al~l .. a fast and efficient call admissioll. control.
By using such a burst level control not only can ATM LAN performance be comparable to the performal~ce of media access based technologies e.g. FDI)I
5 with respect to hot spot traffic but the ATl~iI LAN is able to provide a totalbandwidth that is N times the bandwidth of a shared media system (where N is ~i the number of ports). Moreover the burst level control is scalable to wide area networks because tlle control does not rely Oll reactive mecllanisms as a primary method of congestion control and is a sn1all add-on function that is useful for i o Public l~et-~iorks.' ' ' ' ' ' ' ' ' Summary of the Invention In accordance with the teachings of the present invention it is assumed that the source and the network l~ave usage parameter control (UPC) parameter nego-tiation. The present invention provides a burst-level control scheme based upon UPC parameters. Specifically a new cell transmission accept/reject methodology is used to modify individual bursts. Novel circuitry detects the presence of a new burs t .
A principal object of the present invention therefore, is the provision of burstZ 20 level control in a~ ATM network.
~nother object of the present invention is the provision of an accept/reject method for modifying a burst.
A further object of tlle preseDt invention is a circuit for detecting the presence ` of a new burst.
Further and still other objects of the present invention will become more clearly apparent when the-following description is read in conjunctiou with the accompanying drawings .

Brief Description of the Drawings ~`~30 Figure 1 is schematic representation of a prior art leaky bucket shaper circuit.
Figure 2a is a graphical representation of an inpllt burst of new cells to tl1e leaky bucket shaper circuit.
` 35 Figure 2b is a schel1latic representatioll of al) output of the leaky l)ucket sl~a~)er circuit of Figure 1.
E'igure 3 is a schel11atic represel~tatioll of pl ef :rred el1ll)odimel1t of a leal;~ lcl;(~t r 21287~
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shal)er circuit including all idie/l)urst detector comprisillg the present jllvell-. tiOl~ .... . ..... . . . ......... .. . ......... .. . . ..
Figure 4 is a schematic representatioll of a circuit for computing residual cells in the burst yet to be trallsmitted.. .
Figure 5 schematically depicts the working of a priority queue used in a virtual clock based control implementation of the invention.
Figure 6 is a schematic representation of a RAM implementatioll of a leaky bucket sllaper circuit.
Figure 7 is a schematic representation of a preferred embodiment of a virtual c]ock based imp]ementatioll of the present invention.
Figure 8 is a schematic represel~tation of a RAM implemelltation of a leaky bucket s]laper circuit.
. Figure 9 is a schematic representation of a circuit used for measuring the sum :~ of the e:cisting comp]iant cells.
:~ Figure l0 is a schernatic representation of the ram-based implementation of the ~o residual RAM unit showD in Figure 9.
i Detailed Description of the Invention Referring now to the figures and to Figure 1 in particu]ar, there is shown scher,natically a prior art dual leaky bucket sllaper circuit. Leaky bucl~et algo-rithms and tlleir application to ATM networks are described in artic]es such as ? ~Leaky Bucket Analysis for AT~I Networks" by J. Monteiro et al, and UPerfor-. mance I,imitation of Leaky Bucket Algorithm for Usage Parameter Control and Bandwidth Al10catioD Methods" by N. Yamanaka et al in IEICE Trans. Com-mun., Vol 75-B No. 2~ Feb. 1992.
¦ Customer premises equipment (CPE) is assumed to implemeLlt a dual leaky il bucket of the kind showll in Figure I based shapillg mechanism on a per VC
(Virtual Cllannel) basis. Shapillg refers to the changillg of the spacing of the cells comprisi~lg the l)urst or pacl;et of itlforlllatiol) or clata. In orcler to assure proper i, o,~)eration, a switch (not showll) must ilnl)lelllellt the sallle criteria as the CPE
for policillg mechatlisll~. Whell botll tlle switch ~nd the CPE iml)letl~el-t the sall~c criteri~, the two act in tlle nlal)llel of a sel of ll~alcl)e~l fillels tllerel~y potelltiall~
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saving signallil~g l>and\vidth alld latellcy time. The describecl arrallgelllel~t ll~s .. limitations for initial. deploymel~t so. it .~il] be assumec7 tl~at sigualling ~vill .l~e from the switch to the CPE.
The dual leaky bucket shaping circuit 10 comprises a pair of counters 12 alld 5 14. Counter 12 controls the peak rate ~p at which the source is permitted to sellcl bursts. The size of counter 12 is Cl. For simplicity, the counter 12 is assumed to be a one bit counter. Counter 14 controls a parameter referred to as the sustained rate ~D to be described hereinafter. The size of counter 14 is C2.
The operation of the dual leaky bucket shaping circuit 10 is rule-based and 10 shapës'the user tra~c' as-describ`ed'in th'e foliowing manner. A cell i's transmitted along couductor 16 if the current value of counter 12 is one less than Cl and the current value of counter 14 is one less than C2. Otherwise, the cell is held back either ;D the i~oterface card or a CPU comprising a portion of the traffic source, until the conditions are satisfied. When both of tlle conditions are met, the cell is 15 transmitted, and both of the counters are incremented by one. The counter 12 is continuously decremented at a constant rate equal to the peak rate ~p by virtue of an input signal Tp. Similarly, the counter 14 is continuously decremented at a constant rate ~\D by virtue of an input signal T~. The minimum value of the counters is ZERO. Hence, if only the counter 12 is full (Cl) when a cell arrives, 20 the cell is delayed at most for a period ~-pl or Tp, before being transmitted.
The output of counter 12 is provided as a first input to comparator 18. The size of counter 12 is provicled as a second input to comparator 18. As describedabove, when the output of counter 12 is less than the size o-f counter 12 a signal is manifest from comparator 18 as a first input to AND gate 20.
The output of coullter 14 is provided as a f~rst input of comparator 22. The size of counter 14 is provided as a seconcl input to comparator 22. As describedabove, when the output of counter 14 is less than the size of counter 14 a signal is manifest from comparatoI 22 as a second input to AND gate 20.
New cells are provided as third input signals to AND gate 20. When all three inputs to AND gate 20 are present simultaneously, the cell is manifest at conductor 16 for transmissioll. The output of AND circuit ~0 is also provided asa respective inputs to counter 12 and to counter 14.
For givel~ set of leal;y l~ucket parameters (~p,~D,Cl = l,C2)1 there is a l~Ia:Yimum C~omplial~t Burst Size, B"laI~ givell l)y t'ue equation:
'I 35 B~ c = (C~
" 50~ rl~ ls~ or B ccll~ B,~"~

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rate Ap as Sl~O~ if Figure 2a. Tlle traffic pattern at tl~e output of tl~t leal;y .... bucket.shaper.circuit is sllown i~l Figure 2b. There ar.e .tllree motles of operatio represented in Figure 2b.
In a compliant mode1 the leaky bucket shaper circuit output comprises at 5 most BMaI cells at the peak rate ~p. In a sustained mode, the leaky bucket shaper circuit output comprises the remaining B--BMaI cells at the sustained rate ~D. After the sustained mode the VC becomes idle, iu an idle mode.
A method for detecting the beginning and end of each mode and a method for using the detected information form the basis of the control comprising the 10 present invention.
In order to understand the invention, assume there are l\i VCs connected to a given output port and that it is possible to detect the beginning and end of each burst. Further assume that ~ of the VCs are active at a particular time. The remaining (N--L) VCs are declared inactive and their resources are deallocated.
15 If a new VCL+I becomes active with parameters ~p+, ~LD , BL+', ~,vhether the burst is accepted or rejected depends upon how conservative or optimistic the accept/reject decision criteria is made.
In a conservative approach all ~ active VCs are assumed to be in the com-pliant M Mode. That is, each active VC is in the process of generating their 20 maximum burst at their respective peak rate. A new burst is accepted on the premise that there are BQ buffers and the output port speed is ~c, then the new burst is accepted only iE no cell loss will result. The approach is conservativebecause in practical situations not all VCs are likely to be in the compliant mode.
In an optimistic approach all L active VCs are assumed to be in the sustained 25 mode. In this case, a new burst is accepted when i=l ~Lt l + ~, ~D ~ ~C
i=L
This approach is too optimistic since in practical situations at least some of 30 the VCs are in the compliaut mode. Therefore, accepting a new burst under the optimistic approach rnay result in cell loss.
In a more practical a~oproach, use is made of knowledge regarding the quantity of active VCs that are in the comyliant mode, aud the qualltity of VCs tllat arein the sustained mode or are being tiuled out, to make an acceptance decisioll.
35 An implemelltatioll of this apl)roach is described below.
The basic princil)le of the present inventioll results in USillg the traffic sllapillg perforlIled by the dual leaky bucket shaper circuit.

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For tl)e purposes of descril~ g coul-ectiollless service it will be assuli~ed tl~at . ..' the local ATI\I L~l~i cal~ l)e divided into t~vodomaills, ~.e.', the (:~PE clorrlaill and the switch domaim The CPE comprises a workstation, the applications in the work-station that need the transport provided l)y the switch, the transport protocols5 and the interface to the s~vitcln The CPE can also be a router or an access node.
In this case, the AT~I LAl\~ could be viewed as a hub. Current data applicationsuse a connection-less mode for transport of infor~natioll. The ATM LAN which is inherently based on connection oriented transport, will provide connectioll-less service based on fast VC setup provided that there is a signalling scheme tllat io can: request'ne-v VCs'to be setup'and existing'VCs'to'bë disco~inected; detect activity levels on a given VC; request existing VCs be either deactivated or ac-tivated based Oll the activity level of the VC; and associate a unique VC with agiven application. It is assumed that the application uses the socket feature ofthe UNIX OS for communication. In this case, at the time of a fast VC setup, the15 CPE must be able to associate the new VC with the socket port number used by the application. This may require either a new implementation of the Transport protocols, or a violation of the protocol layering f~mction. The Service Access Point (SAP) may be one way oE accomplishing this result.
If each AT~I LAM s~vitcll has a maximum of N = 16 ports tllat are switched 20 using a single stage s-vitch, then, between any given input-output-port there is only one path. When large switches are required, many 16 port switches are interconnected. In the latter case there can be more than one path from the iuput port of one switch to the output port of another switch. First collsider the control of a single switch only. Assume that both the CPE interface and the 25 switch interface have a dual leaky bucket shaper circuits for shaping and policing respectively.
Using a single stage switch and N ports, between any given input port and a given OUtpllt port there is only one possible path. Associated with each port (input or output), there are a set of I~ VCs. For example, input port i(i = I,...lN), 30 has a set of K .Vs numhered as VjlN (k - 1,2,..., l~). Similarly, therc are I~
VCs numbered as V,UT(k = 1,2,...,K). A fast call setup between a source Si physically connected to input port i of the switch, al~d a destination Dj tllat is ~,' physically connected to output port j of the switch, now comprises identifyillg an '~ approprial;e free VC V~ = 1,2,.. ,1~') on iuput port i and an approl)riate l'ree 3s VC V~UT(l~ = I, 2, ..., Ir) at OUtpl.lt port j. If tlle necessary resources are availal)le oll this patll tl~e conllectioll setup proceeds allead. Next, an association nlust l)e lnacle l~etween cllosell incolllillg VC vjl.N al; in~ t pOlt i of the switclll ancl the ;~

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2~237~7 ~rc~i~2.-~ '7 outgoing VC ~ lT at outl~ut port j. Whell sucll a setup is dolle, tlle re(~ ed resources on tllis ,3ath are reserved for this coul~ectioll; and the shal)illg. (levices on the CPE and the monitorillg devices Oll the switch are illformed accordingly.Tear-do~vn of conl~ections involves disassociation-association of the illCOInillg 5 and outgoing VCs. When such a tear-down occurs, the resources allocated to tlle connectiorl are also deallocated. The resources of interest are the output port transmission bandwidth and the output port buffers. The VCs are IlO~v free.
In additioll to facilitating fast setup and tear down of conrlectiolls (or VCs),the switch and the CPE should also monitor the activity level of VCs and declare0 an ACTIVE VC as IDLE. Ill this case, instead of tearilig down down the conllec-tion at tlle end of every burst, the corresponding VC is to declared as IDLE, and the resources are deallocated but the VC is marked as BUSY. When activity is again detected Oll this connection, the resources are restored to this connection and the connectioll is declared as ACTIVE. This requires the capability to detect 15 the beginning of new bursts and the end of current bursts. In accordance witll the present invention hardware based timeout will actually be used to declare the VCIDLE. Detection of ACTIV~IDLE states increases the resource utilization (and thereby reduces blocking), and also reduces the load on the call processor. Thatis, call setups (and tear downs) are not performed at the beginning (and end) of20 each burst.
Every time a new connection i9 opened by an application1 a fast call setup will be performed and the appropriate VCs will be set. The necessary resources will be allocated and the leaky bucket parameters will be updated. A state machine is maintained for each VC which can be ~CTIVE or IDLE. When the connection 25 becomes IDLE (determined by timing out the idle periocl after the end of a burst), the resources are deallocated and the state of the VC is marked IDLE. When the connection becomes active again (b~y detecting the beginning of a new burst while in the IDLE state), the necessary resources are reallocated.
',There are several issues that have to be addressed with tllis fast VC setup !,; 30 and burst-level control procedure. When a request for new collnection setup is ~,made and the resources are not available on the path, alternatives are available.
For e~ample, in response to the request it is possible to send a NACI~ signal (indicating that the VC is not available) and ask the CPE to retry after a back-off interval. Alter~latively, the request may be passed to a queue tl~at is conlnlol~
; 35 to all the patlls tllat have tlle same output ,vort. This queue will be reEerred to as the Resource Request Queue (RRQ). If the wait tiMe ill the cluel.le e:~ceeds a predeternlilled time Tl~/, thell the request is removecl Eronl the cl~lel.le ancl a ; l . ,, ",. ..

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I~ACI~ is sent to tlle CPE ancl tl~e CPE must retry after a l)acl;-o~f inter~-al.
Th.e.resour.ce a!locatiolL scl~en~e is disp.ersed in such a way that tl~e .prol)al)ility of sendin(r a NAC~K in this case as well as tlle maximum wait time T", are botl~ very low. The advantage of this method is tllat signalling traffic is reduced.
As a further alternative it is possil)le to offer a bandwidth tllat is less tllan the requested bandwidtl~ (if it is available) and inform the CPE of the modified traffic parameters. If no resources are available thell the request is queued in tl~e RRQ.
a~ A key issue is the latency involved in making these decisions and commullicating ,! them.
The descril~ed burst-level control can significantly increase the utilization ofavailable bandwidtl1. A high utilization is achieved by trading cell or frame loss with burst level blocking for example to achieve a burst level blocking of 10-3 with a cell loss probability of 10-6.
~l The burst level control requires detecting the activity of the VC and declar-ing it as being either ACTIVE (resources are committed in this state) or IDLE
(resources are deallocated).
A VC can be in any one of three states: active compliant active sustained and idle. 1~ order to detect which state a VC is in1 a third counter is added to the dual leaky bucket shaper circuit that is monitoring the connection. In the embod;mentshown in Figure 3, the counter 30 has a maximum count Cld~. The counter 30 is incremented at a constaut rate Ro. Whenever a cell arrives the counter is cleared. However if there is no activity for a time out interval To = Co/Ro, : the counter will reach the value Co. Upon the counter reaching the value Co a signal is generated indicating that the connection is inactive. The parameters ho and Co are functions of the parameters declared by the connection. The value of the time out interval To can be dynamically altered if necessary. The time To is chosen to be larger than the reciprocal of the sustained rate ~ but smaller than the estimated time in an IDLl~ state. A counter-based implementation of the:` leaky bucket shaper circuit with an idle state detector is shown in Figure 3. In the embodiment shown in Figure 3, the idle counter is incremented at tlle drain-ratetime constant Td 50 long as the peak rate counter 12 is zero. Whenever the peal;rate couDter is non-zero7 tl~e idle counter 30 is cleared. The count fron1 counter 12 is provided as a first input to AND gate 32 and to flip flop 34 The draill rate ~l time contrast pulses T,l are provided as a seconcl iul)ut to AND gate 32. A clocl;
signal is provided as a seconcl inpllt to flip flop 34. The output of AND gate 32 is providecl as an illp-lt iclle to coul~ter 30. The output of flil) fiop coul1ter :34 is use(l ~,1; to clear idle counter :30. ~ la.tcll 3~ receives as its first il~pl.lt tlle c~arl! OUl"Ut '."1 2 ~ 2 3 ~ ~ I
6rc~,~2.~ ,q, from iclle couuter ~0 all~l receives as its secoud iul)ut tlle clocl; pulses. Tlle outl~ut signal ~rom latch 36 is iudicative of whetller tlle ~ssociated VC being eucoulltered is in its ACTIVE or lD~E states.
The output sigllal ~rom latch 36 is provided as a first iuput to AND gate s 3S. The otller iuput to AND gate 38 is the uew cell (burst) signal. Upoll the simultaneous occurrence o~ the idle signal aDd the burst signal, an outl~ut signal is routed ~rom AND gate 38 to fli~ flop 40. The clock pulse is provided as a secolld input to flip flop 40. An output signal from flip flop 40 indicates receipt of a new burst. The described embodiment assumes the receipt of an ACI~ signal prior to 10 the cell being queued for transmission of a new burst by means of AOI 42. Theinputs to AOI 42 are new burst signal, not new burst signal, new cell signal andthe ACK signal. The output of AOI 42 is provided as the third input to AND
gate 20 and is indicative to the transmission of a new burst.
As can be seen, the additional complexity required in Figure 3 to the prior 15 art counter-based implementation shown in Figure 1, is minimal.
Having described a preferred burst level control embodiment of the iuveution, it will be apparent are several alternative control mechanisms are possible. In a first alternative arrangement, once a connection is declared inactive the CPE isinformed and the resources are deallocated. The state of the VC at the CPE
20 and the switch will be marked as IDLE. (The CPE can also accomplish the same results by using a value CO that is sl;ghtly smaller than Co. That is, the CPE
~vill detect the connection to be inactive before the switch does) then, the CPEsubsequently detects activity (i.e., the beginning of a new burst while in the IDLE
state)1 the CPE withholds the burst and asks tlle switch to activate the connection 25 first through an ACTIVATE connection request. The CPE can ask for the same ~,~ last set of UPC parameters that was used previously, or the CPE can ask for a new J~ set of UPC parameters. If the CPE transmits without restoring the connection to an ACTIVE state, the transmitted data will be treated as violating traffic by the .~ switch. The switch is able to achieve the connection since its leaky bucket shaper 30 circuit parameters would have already been modified. When the switch receives~~ the ACTIVATE request, the request is queued in the appropriate RRQ o~ tlle 1~ associated output port. Tlle request is serviced when resources become availal~le (uutil tllen the VC is blocked and maintailled in a wait state). Whe~l a transitioll occurs from au IDLE state to au ACTIVE state, l~o NACI~ signal is seut if the VC;:~ 35 is blocked. Ouce the resources become available, all ACI~TOSEND sigual is seut to tl)e CPE a.ud the CPE l)egius trauslnissioll of the burst. Lf tlle VC is blocl;e~l for a tim~. greater th;lll T~v, ~he switcl~ returus al~ AC,I( sigl~al ~ith a se.t of leal;y l~ucl;et ,, ....
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2~2~7~7 ~rC~*~2,1~ 0, .parallletel-s that offers a snlaller l)al~clwidtln The aclvat~tage of tl~is ilnplelnelllatioll . . is tl~at no l)ursts are lost. It.also provides tin~e for tl~e switcl).to process tl~e l~urst request. The disadvalltage of this ilnplementatiou is the additiollal sigl~allil~g required, and the possible iucompatibility with interfaces that do not implelllellt 5 the required additional signallillg (ACTIVATE and ACKTOSEND) sigl~als.
In a second alternative arrangement, when a CPE has informatioll to trans-j} mit, it translllits at the rate determined by the current leaky bucket shaper circuit setting. This is doue without an ACTIVATE signal. If the VC has been declared as being IDLE, the switch detects the transition, and makes a decision in real time 10 whether t}ie burst can be accepted, or not, without incurring cell loss. If the burst`can be accepted, the burst is admitted. If not, the burst is rejected. If the burst is rejected, it has to be retransmitted. An ACCEPT or REJECT-SEI\IDAGAIN
signal is sent to the CPE, indicating whether the burst has beell accepted or uot.
The CPE interface will store the burst until the ACCEPT signal is received. The 15 switch can request a new set of leaky bucket shaper circuit parameters for the CPE
to transmit the burst again through the REJECT-SENDAGAIN signal. With the changed parameters the burst will be accepted. The REJECT-SENDAGAIN sig-nal can be delayed by tlle switch. In this arrangement, the retransmission is done at the media-access level, at the cost of additional signalling. However, the 20 method has the advantages of being compatible with conventional CPE interfacecards that do not llave extensive signalling capability and also that if the addi-tional signalling is not implemented, the burst will be lost and will have to beretransmitted by a higher level protocol. A lirnitation of the method is that the time to process the acceptance of a new burst is very short (one cell time). One25 rnethod to overcome tlle disadvantage is to bufFer n cells of the burst, here 7li cell times are sufficient to process the burst. This can be implemented by usingeither a shift register or a circular ~AM-based buffer.
The primary objectives of a resource management scheme are (1) to min-imize signalling overhead. In conventional connection oriented communication, 30 call setup involves negotiation of parameter values. In the local ATlvl I.AN euvi-ronment it is desirable to avoid such negotiations, and thereby keep the signallillg overhead lo-v. The signalling overhead is the processing power recluired to do the fast call setup, fast resource allocation and deallocation. Since the turn aroul~cl time should to l)e snli311, these functiolls may have to be iml)lelllellte~ arcl-35 ware/firmwale alld hellce are ~referably kept simple. Ultimately, it will l~e atrade-off l~etweell implelllelltatioll conlplexity and efficiel-t utilization of nel\voll;
resources al)cl col~secluellt fralne loss rate. (2) Whell tlle nel;~vorli is ligl~tly loaclecl, 2l2~7 ~rc~.e2.-~
any user sl~oulcl be able to capl.ure tl~e full capacity of tbe patl~ en tlle l)et-~vork is heavily loaded, the patl~ cal)acity must be shared betweell all contel~cling users. Such an approacl~ ~vill make tl~e LAN appear like a sl~ared mediull~. This has to be achieved with little or no frame loss. (~) To efficiently utilize s~vitch 5 capacity and have lo~v latency.
'~J In accordance with the teachings of the present inventiol~, a gel)eral resource allocation method based Oll a dual leaky bucket shaper circuit will l)e described.
The method is applicable to both connection oriented ancl connection-less services.
The connection oriented service is a special case of connection-less service as far as .. 10 `resource allocatio~i and deallocation are concerned. The following embodimellts ;¦ relate to resource alloocation methods and apparatus that facilitate hard~vare embodiments.
A dual leaky bucket sl~aper circuit is used to monitor two traffic parameters, na-nely the peak cell rate, and the maximum sustained burst size at the peak rates.
15 The dual leaky bucket shaper circuit, has four parameters Cl and C2, the peakand the sustained rate bucket sizes, and ~p and ~D, the peak and the sustained rate. Assume that the value of the peak cell rate counter is set equal to Cl = 1.
. This would be the case when there is no jitter in the peak rate. Given the four .i parameters, there is a rnaximum compliant burst size. That is, for a given peak 20 rate, and sustained rate, there is a maximum burst size that one can transmitwithout being shaped by the leaky bucket shaper circuit shown in Figure 1. The maximum compliant burst size Bc is given by:

Bc = (l(C2~ + 1 ~I For a given set of leaky bucket parameters, the maximum burst size that can be transmitted at the peak rate ~p is Bc. If the actual burst size is larger than BC1 therl the first Bc cells are trausmitted at the peak rate ~D < ~p (see Figure '~ 2). Once a burst equal to the compliant burst size is transmitted at the peak rate, ~ 30 in order to transrnit another burst of the same size at the peak rate1 it is necessary j~` to wait a time C2/~D for the counter value of the secoud bucket to decrement to .` zero. Hence, the dual leal;y bucket shaper circuit which is rule-l)ased mal;es the i~ traffic more predictable, ollce the parameters are determined. For a gi~ell set :~ of leaky bucket parameters, it l)econ~es easy to determine tlle ~volst-case out~)ut .: from the correspoll~.ling source. If the ~vorst-case output is kno~vn, call acllllissiol~
and burst aclmission call no~v be contlollecl to give zero fralne loss l~rol)~bilitv.
Alternati~ely1 it is alr.o possil)lt to perlllit loss ~vitll a very slnall l)rol~ Tlle 2~2~7~7 trc-~e2 ~ . 12.
re(luired ~robability values for tbe worst case source-traff~c n~odel sbal~e~ by tbe .. .. Ieaky bucket sbaper circuits can be easily deternlined. . ..
In a preferred resource allocatiou method whell a new collnection is to be established or w}len a VC makes a transition from an Il)LE state to an AC-5 TIVE state the resource requirements are determined by means of the parameters (B1AP,~D), where B is the compliant burst length. It is assumed that a peakrate bucl;et size C, = 1 (however1 if cell delay variatioDs are to be accounted For then Cl can be greater than 1). If the switcb cannot accept the connectioll based on the parameter values theu the call or burst can either be blocked or tllere can 10 be a renegotia~ion of pararneters between the source and tlle switcli.
When there is either a request for a NEW connection or a VC makes a tran-sition from an IDLE state an ACTIVE state and the VC1s resource requirements be defined by the parameters B~, lp, AD. The switch first identifies the appropri-ate output port and its associated resource request queue (RRQ). Each of these 15 VCs can belong to differel~t source destination pair. Assume that the amount of buffering in the output port is BQ and the output port speed is lc. Let the ilh active VC have the traffic descriptors Bi, lp, 1D
The Bi is the compliant burst length at the second leaky bucket, then the leaky bucket counter value C12 is giveD by:

C2 = (Bi - 1)(1 - ~D/~i ) + 1 For a given size of the second bucket C2, the compliant burst length depends on the choice of the peak rate and the sustained rate.
The following analysis are based ou the following assumptions: the number 25 of bufEers in the switch is small, thereby placiug an upper limit Oll tbe compliant burst size, ancl hence the size of the second leaky bucket couDter. The size of the peak rate bucket counter is 1. If a source has a burst length that is largerthan the compliant burst lengtb for a given peal; and sustained rate, after the - compliant burst is adrnitted at the peak rate, the remaining portion of the burst 30 will only be admitted at the sustained rate. That is, traffic shaping occurs only when the burst length is larger than the compliant burst length. If the source traffic is sllaped, thell that the burst will be held bacl; in tl-e CPE.
Let 1CBR be the capacity allocated to continuous bit rate (CBR) traffic on . a linli. Such allocation can be connectiol) oriented service. 11l tbis case tbe traffic 35 parallleters will be (l,~p,lp). That is7 tbe burst size is 1, and tlle ,neal; rate ancl tbe sustainecl rate are the salne. In a first case the resource allocation nletllod is sucll tbat no cell loss occurs.
.

` 21287~7 c ~,~2 . t e ~
:~ The follo~ving rules are al)plied il- or~ler to determille if the ~ueue cal) accept the ne~v VC without incllrrillg cell loss.

IJ~P + ~, ~P + ~CBR < ~7C
, 5 ') the queue can accel)t the traffic from the new VC.
2. Else if p + ~ p + ~CBR < ~C
.1 Assume that all sources have bursts to transmit that are larger than their compliant burst sizes. In this case, at steady state, all sources will be forced to transmit at their sustained rate after the initial transient. For no cells to be lost -~ during this steady state the requirement is:
7''~! i=N
.:~ 15 ~`D + ~ ~D ~ ~CBR < ~C

~ However, during the transient interval, when sources are transmitting at the ;~ peak rate, cells can still be lost due to buffer overflow. In the worst case all the active sources are transmitting their bursts at the peak rate. For no cells to be 2û lost, it i5 required that during a time interval TQ (that is equal to the amount of buffering in the queue), the number of bits arriving from all the active VCs must be less than the number of bits that can be transmitted by the queue it during ~ the same interval. Define i~ 25 TQ = ~Q
Fori= ,1,2~...,N

L C+[TQ-- ,\i ] ~D,~pTQ¦~

~YC8R = TQ~\C8R
TheD the new \IC can be accepted without any cell loss at the output port ;~ queue if: i=N

+ ~, Xi -~ XCEJR < BQ

1~ tllis ~cllrli~,io~ q.~l,is i~rl, tl;e VC ~olmectioll is setul~ i tlle lei l;y bllche~

~`
21'~7~7 ~, r~ c2 I~s 1~
paralneters are ul~datecl. The illcomillg and outgoing V~ s are also Inarl;ect as E3USY and tl~e connection is Inarked as ACTIVE.
If tl~e above conditions are l~ot satisfied tlle VC~ is blocl;ed~ wl1icl~ case several alternatives are possible. First ask the connection to try again. Second5 put the request il~ the output queue and check each time resources are deallocated due to a disconnection or a connection going idle. Third attempt to determine a new set of traffic parameters that is acceptable. For example:
. Set ~`, 1.
. . . i=N ~- . ..
'F~V = M i n ~D, ~C ~, ~D = )I C B R) ,~ . .:i 2 .~.j . - i=jv BN~1V = BQ _ X + ~ Xi t~ ;S'CBR
5 and . ~\N~W TQ
P = BN~W' . In a more optimistic resource allocation method each VC can be in one of . three states; ACTIVE IDLE ACTIVE and Being TIlvIED OUT. If the VC is ACTIVE it can be in the compliant mode in the sustained mode or be waiting to be timed out. In the conservative approach it was assumed tllat all active VCs are in the compliant rnode.
In the present embodiment, all VCs that are ACTIVE and in the compliant mode are determined. Let the total number of ACTIVE VCs be N, of which L are in the compliant mode. The remaining (N - ~) VCs are either in the sustainecl mode or waiting to be timed out. The instant a new request arrives with parameters (B-,AP,~D) for VCs i(i = 1,2,... ~) let ~,~/;30 X ~Ilin ~B t- (TQ~ D ~pTQl ~
wllere Bi- ~ B' is the residual or remail1ing number of cells iu the burst yet ;. to be transnlittecl.
Al~ estimator for B-' is SllOWn SChelllatiCal]y in Figllre L. Any time a new ~!,"~ request is accel~tecl ~vith values (B z7 Tp ) a counter bank j 44 sl-owll in Figure 3 ~j~ is chosell frolll an unllsecl set. Tlle relevant address for that counter l~ank is Illarked ii~ as beillg used. B~ r is loaded into the ul)-do~vl) countel 4G whic.l) is clecrelllelltecl ~`!1" every Tr llsing a nlodlllo-~`l coulltel u~til the vall.le o~ the ul)~clowll roul)tel 4G is i ~1 2 g 7 g r~) 6r~r2 ~'I
zero ~t ~vllicl~ tinle the coul~ter l)anl; is clearecl al~d its aclclress is seut l~acl; to tl~e unused tokeu pool. Tl~e output count frolll up/clown coul~ter 46 is coln~ectecl to one input of AND gate S0. Tl~e otller input to AND gate 50 is conllected to al~
output of cllosell coul~ter ballk j 44 and is a logic level 1 state wllel~ tl~e VC is S chosell. Tllus ~vhell up/dowll counter 4~ reacl~es zero tlle output of AND gate .~0 is in a logic level I state. The output of AND gate 50 is provided as an input to AIND gate S2. The other input to AND gate 52 are the pulses at rate Tc. Tl~e alue of tlle up-down counter at any given time is an estimate of B- . The VCs L + 1 L = 2, ..., N are either in the sustained mode or are being timed out.
Let pi be tl~e probal~ility that source i that is being timed out ~vill switcl~
to a compliant mode (and generate a burst) before tl~e time out expires. The computation Of pi is given below.
Let yi = pixi + (1--pi)TQ~D
The above expression gives the average contribution from sources that are not in the cornpliant mode.
A new request from a new connection or a VC making a transitioll from an IDLE to ACTIVE state is accepted if i=l, t=N
y~ yi < B
=1 The above implementation is considered to be optimistic, since it only takes the average coDtribution from those sources that are not in the compliant mode.
25 Cell loss can result in this implementation.
In a further alterrlative method the probability is determined that cell loss can result if a new burst is accepted. The burst is accepted only if the probability is less than a specified value ~. If ~--0, the result is in the conservative arrangement described above. If ~ = 1 the result is a scheme that employs no control.
The key to the present metllod is the ability to determine the probability that a source that is being timed-out as IDLE will become active before the timeout ;S3 expires. The leaky bucket parameters of a source are (Bc, ~p, ~o). Assume that ~i the source makes transitions between an ON state and an OFF state. While in the Oi\ state the source is trallslllittil)g cells. Wl~ile in tlle OFI; state it tral~smits I~O
35 cells. If tllis latter state persists for a sufficielltly long lellgtll of tinle tlle source can l~e tilned-out.
~ie a~ssume the cll.lratioll of tl)e OI; F time is exponel~tially clistril)ute(l \~itl ~!
,!'l ~ ` .
2~2~7~7 ; Irc~2.~ IG.
mean value:
Bc Bc Bc To~,r = ~ - alId TOFF = ~ -- ~
It is assumed that tl~e sustained rate is equal to the average r ate. Tl~e till~eout interval is TOUT l`he time out interval must be chosen such that the probabilityof a burst being timed out before the end of the burst is very low. The timeout interval is se~ected to be TOUT = 1l/la2[1~1~D-1,T~ where M > 1 and for e~ample T~ = 1 millisecond.
Then the probability that source i becomes active before its time e~;pires is g~veu by Pi = 1 -- e A wllere A = T
OFF
The total number of ACTIVE VCs is N, of wllich L are in the compliant mode. The remaiuing (N- L) VCs are either in the sustained mode or are in process of being timed out. Consider the instant when a new request arrives withparameterS B ~ ~p ~\D)-For VCs i(i = 1, 2 ..1 L), let Xi- = min Bi- t (TQ - .~ PTQ

where Bi- < Bi is the remaining burst length.
For VCs L + 1, L ~ 2, ...,N which are either in the sustained mode or are 25 being timed out. In a conservative approach assume that these VCs are being timecl out.
Let each source I = L + 1, ..., N, not in the compliant mode have a random variable ~; which takes one of two values:

[ ( ~i ) p ~
l~i = AiDTQ with probability (I - t)i) Assign randolIl variables S given by:
i=N
S= ~
i= L= I

~: 2~2~7~
6rC~.C2.1C~ ~_ Tlle new co~ e( tiOll or bllrst is acceptecl if p~S' > Z] < ~i Where P~S > Z] is the probability one can have. cell loss by acceptillg tlle 5burst. In the present example, choose ~ to be o~ order of 10-3.
When connectiol1less service is involved there are special cases of tlle metllod.
For example, in case the CPE is unable to provide a leaky bucket sllaper circuit, the ability of the IJPC to detect the start of the burst can be used to emulate n1edia access control. These methods ensure that even in the worse case, perforlnance will never of worse than that of a shared media LAN sucil as FDDI.
In another sl~ecial case where there is at most one active VC key output port, no use is made of any sllaping mechanism but rather use is made of the concept of detecting a chauge of state ~rom the idle to active mode ancl vice versa. This can be implemented by looking at the UPC or by looking at the adaptation layer 5at the CPE and signalling to the switch. The adaptation layer state machines are able to recognize the beginning of a PDIJ. In this method the total bandwidth of~ithe output port is allocated to a requesting VC. The peak rate and the sustained rate are set equal to the port speed. That is, ~p = )~D = ~C, and the bucl;et size rf~C2 = 1. In this case, any burst size will be compliant and there can only be one ~j ~active VC at the output port at any time. The methods works as follows:
,~A path between an input/output port pair can be in one of three states: in ~'!a Free state where the output port bandwidth is not allocated to any VC; in aBusy state with a single VC using the full capacity or in a Blocked state because ~ianother path using the same output port (but from a dif~erent input port) is being ~'!, 25used by an active VC.
When a new connectioll setup arises, the appropriate RRQ of the associated output port is selected aud the request is put in the queue. If the output port bandwidth is ~ree, the path is assigned to the connection aud the leaky bucket rates are set equal to the port speed. The path and the OUtpl1t port used by the30path are marked busy. Also, all other free paths that use the same output portare marked blocked.
Wheu a conllection is released or declared iuactive, first the resourcess on thepath and the output port used by the connection are released. Ne~;t, the resultillg ~1 1possible patlls tl~at cal) now become unblocked (because they l~ave tl~e same out,out ~; ~ 35 port in common) are determined and are unblocked or marked ~ree. Several patlls could become ~ree. Then ~rom the RRQ whose output port balldwidtl~ was just .released, the longest wailillg custonler is assigned a new ,oatll. Tlle resolllce ~"i:
",:";
''' ~

21~87~7 f r ~ e 2 . ~ e r allocation on tl~e output port is u~dated a~d tl~e correspol~ding l)atl~ al~d VCs are marke-l BUSY and As~TlVE. All other free vatl~s that share the same output port as tl~e ne~vly assigned path (from above) are marl;ed as blocked. If there are no requests ~vajtjn~r to utilize tl~e resources released by a connection then all 5 the paths thdt w/ere blocked because of the unavailability of tl~ese resources are marked free.
The above method has the ~ollowing advantages. The signalling is simple There is very little negotiation involved with the CPE. The method is efficient at lo~v loads (with low latency). This method will perform ~s well as an equivalent10 FDDI if all the inputs ~vhat to communicate to the same output. Further the method also allows simultaneous communication to other output ports as vell.
Some disadvantages of this method include the following factors: .
The method presupposes that all the input ports will be transmitting at the output port speed. If this is not true, there will be waste of bandwidth. If the15 bursts are very long, or several burst get merged into one long burst and thevariability in response time can increase. The methods allow the input port to communicate to only one output port at any given time. Connection oriented services can block an output port for a prolonged period of time.
In an alternative arrangement, many paths share the output port capacity 20 where each new connection or a connection making a transition from an lDLE
to ACTIVE state can ask for a peak bandwidth \p that is less than the port bandwidth ~c. The leaky bucket parameters would be 1,~p1~pa, with ~p <
~c- The method involves identification of the appropriate output port for the connection request. The RRQ of the output port has the following information:
'; 25 (a) paths that are E;~REE~ BllSY, BLOCKED on this output port; (b) VCs that !~, are marked FREEs BUSY1 IDLE on this port; (c) resource allocated to each of l`l the BUSY VCs that are associated with their outpout port, and (d) the total'' bandwidth t'hat has been allocated.
When a new request arrives with a request for a peak rate of ~ tlle controller 30 checks whether , 1 ~p ~ c "~., i= I
vhere the inde~ ~p, is tlle barld~vidtll allocatecl to ACTIVE VC j usirlg tlle ~5 gi~en OUtpllt port.
ij If the required balldwidtll allo~vs it is oossible to o~er a peal; ballclwicltll ,'E~ C ~ p or place the queue oll ~vait ill the resource quelle al~cl wait for ba~ vicltll to be freecl or asl; tl~e i~ t l)or(; to retry later.
~;,, 212~ fi~
c ~ 3 . t The al~ove ll~etho(l allows sill~ultalleous Illulti rate-switcllillg7 al]ci C~BR sources cau now he easily accomlnodated. The metllod has ulil)illlal siguallillg, but caoperate with a higher efficiellcy thau tl~e previous n~ethod.
In the first method7 a connection was either assigned tlle full capacity if it was 5 available7 or it had to ~vait until the full capacity was available. The qualltum size was the capacity of the port. In the second method7 a connectiou could request any bandwidth less than or equal to output port bandwidth. In the third method, the band~vidth allocation is quantized. This later method may l~ave the advantage of each resource mallagement7 but at the e~cpense of some efficiency.
0 The advantage of this metllod is that at low loads (with respect to a givenoutput port), the input ports caD access whatever bandwidth they request. At higher loads, there is natural sharing of the limited bandwidth betweel~ the con-tending connections. The result is higher efficiellcy and lower variauce in delay.
The most general case as discussed before is an allocation of capacity based on the three leaky bucket parameters. An input port specifies all three parameters (B, ~p, ~D). The input port and the controller can negotiate and rede~ne the lea~;y bucket parameters as necessary. The principle advantage of the method is that traffic negotiatiou will now be compatible with resource negotiation procedures for wide area networking.
The leaky bucket monitors have to monitor every active VC in a system, even in systems containing a large quantity of VCs. If these monitors are provided ona per VC basis, the resulting hardware cost can be astronomical. ~owever1 it is possible to ha~e an efficient implementation for a large quantity of VCs. This implementation takes advantage of two factors. Namely, that given the ~ine rate L~ the number of active virtual circuits on a giveu link is limited to L where , ~ d iS less than ~1. This impl;es that if the drain rate on each VC is large, !1 thell the number of active VCs on a given liuk will be small. However if the drain ! rates are small, then the number of active VCs could be large but the rate of change of their counter states could be sufficiently slow aud the method could be implemented in software, rather than hardware. The other salient feature of the leaky bucket implementation is the face that as the ratio of the peak rate to the i,~, drain rate becomes large, the maximum sustailled burst effectively becomes equal '~ to C2. If this ratio approaches olle, this burst size approaches infinity and we are l~ack to allocatiug resources only at the peak rate.
i 35 The first fact;or al)ove clearly points to the possil~ility of a R.A~ asecl im,ole-~` melltatiol~ ~vllere the states are storecl iu a RAM aud for slo-v V(~s the colltrol is " ilnplemellted l)y updatillg tlle RAM ~vhile the fact V~s call I)e coutlollecl il~ halcl-,.....
.' ~287~7 ff;lC~2.1e~ .20.
~-~are One eml)odilllel)t is to llave onl~y a limited set of LEAI~Y 17ucket Inollitors tllat will be sl~ared by all the VCs usillg a givell linl;. Tlle statfs inforlllatioll of eacll VC ~ould be sorted in a RAi\/l alld at appropriate times state inforl1lation is loaded into tlle LEAKY BUCKET~S and updated. Here some of tlle lligll speed VC states may al~vays be maintailled in tbe leal;y bucket circuit alld only tlle lo~v speed VC status be stored in RAM. The scheme can lead to a certain amount of blocking i.e. the leal;y bucket circuitry is not available ~vhen needed. If this blocking probability is lowf the effect of missing an occasional update would beinconsequential. On the other hand the embodiment leads to significant reduc-tion in l1ardware. One of the problems witll this implementation is synchronizing the counters. It is possible that a numl~er of counters may need to be updated simultaneously and keeping track of that becomes very difficult.
ln a virtual clock based implemel1tatiol1 there is a UOtiOI1 of a counter keep-ing track of time where time is quantized to the system clock and a tim.estamp is used for a particular event. It is assur.ned that the system clock is runnirlg at a much high rate than the peak aud drain rates of the individual VCs. For example if the usual clock chip is designed to operate at a rate of 40 MHz it is several orders of magnitude larger than the cell trausEer time at the peak line rate of 155 Mb/s which is 2.f~f microseconds and corresponds to about 300 KHz.
The number of VCs able to be multiplexed on a chip is obviously a function of the maxirnum system clock rate and the line rate. A virtual clock based im-plementation of the leaky bucket is described in article by H. J. Chao entitled "Design of Leaky Bucket Access Control Schernes in ATM Networks" in the 1991 ;.il IEEE International Communications Conference. The implementation in Chao can be optimized further aLld instead of the 256 VCs tllat are described ill Cllao f the present invention is capable of providing support for several thousal1d VCs in hardware and ultimately supporting 64,000 active VCs (some in hardware and the rest through R.AM-manipulations in software).
~; A preferred method of implemeuting a virtual-clock based control is the use of a priority queue. F'igure 5 schernatically shows the basic working of a priority . ~ quene. A priority queue cau be viewed as a cllain of D Flip-Flops or sllift registers connected tl1rougll combinatorial logic. A broadcast bus will broaclcast a 2-hlple ~'~r''"' to this priority queue tlle 2-tuple COIlsists of a value tl~at is used for compariso ~`~ . (for e~ample a tilne-stanlp) a~cl an ~ssociated adclress or contlol infollllatioll ~vllicll is carried alollg ~vitll it. Ollce tlle. value is receivecl tlle coml~illatiol)al logic (l~asically a col~lpare alld all allcl-or-illvert circllit) compares tlle lle~ value to tlle e~istillg value If tlle. llc~ value is less tllall tlle e~istillg vall~e tlle existinO ~-tul)le ::

,.
,;

2~37~
~ r e ~ . 21.
is sllifted one step to tl~e left other\vise the existil~g 2-tuple is reloacled witl~oul any shiftillg. Tl~is creates a hole in the priority queue whicll gets fil]ed. At any given clock pulse tlle priority queue is either shiftillg right (I>usil~ess as usual) reloading the old value or shi~tillg left. Thus tlle priority queue at any given5 time has an ordered list of time stamps and the entry at the heacl of the queue is con~pared to the real-time counter value TnoW to see if the time for this event has occurred or not. Figure 5 is not tlle way al~ optimal priority queue can be implemented but is preseuted rather for tllis purpose of describing in principle. In practiceT the broadcast bus is eliminated and kllown retiming techniques are used 10 to make the queue esse~tially ripple free. Tl~e length of the priority queue has to be sufficiently large that all the active VCs are able to cycle tllrougll tl~e RAM
manipulatiolls witllout fallirlg off at the end of the queue due to faster VCs. .
The leaky bucket counters aDd the idle/burst detectors are implemel~ted in a RAM. Tlle RAM is sho~vll in Figure 6. Tl~e RAM is indexed by the particular 15 VC and colltains fields for Tp, Td which are the peal; and drain rate timers Cp and Cd which are the leaky bucket maximum counter values for the two buckets Np aud Nd which are the actual values of the counters and Tor which is tlle timeoutvalue for this particular VC before it is declared idle (equivalent to N Tc~ in Figure 3). Also needed is iuformation whether the VC is active or idle. AIId for time out 20 purposes, it is necessary to know the time of arrival of the last cell. A preferred embodimeut of the virtual clock based implementation is shown in Figure 7. Tl isthe time-stamp for the event. The control information tllat the time stamp carries is tl~e VC number 1 and the type of event (peak time-stamp drai7n time-stamp and timeout time-stamp). The event at the head of the queue Tl in RAM 60 is 25 compared to Tnou/ in comparator 62. If tlle compare is true (time for the event has occurred), the control i~formation is latched in latch 64. The address part of the information Z is used to obtain the relevant information from the shaper RAM 66.T7ne type field sig7~al from latch 64 to microprocessor 68 determines the fields that will be modified. If the field to be modified is the peak Np is decremented by one.
30 If 1~ is zero then it is necessary to also seud a timeout time-stamp (TlU~) whicll is equal to TC~r~-~TT~ou~ to the priority queue. A l~e~v peak time-stamp lPI-- T7 0W-~'T~
also llas to be sent to the priority queue. If the peak counter time-stamp is IIIUCh smaller thell the time-out then the time-out ~vill overtake all tlle time-out values for tlle ~'C (~.hicll ~vill fall ofF tlle edge Or the queue) I)ut in order to ll~aintail~
35 control the tilne T70 is ~ritten into the field for the last cell arrival crol this VC
~vllen a request for a ne~ cell cloes arrive as sllo~vn in Figure S. If the tyl)e of the tilne-slc~ ) coullter is a draill rate type. I\;cl is al)l)lol)rialely declelllellted in , ' , ' . i:: ~ .,. ,' ', ~ ' , ,i 2~237~7 Crc.~i~2.1~ .27.
RAi\~l 7S, the ne~-t e~el~t time calculated and sent l~acl; to tlle clueue. If tl~ type is timeout, then the c~lrrent tilne is conlparecl in RAM oO to deterl1lille wllether it actually does exceed tl~e value of the last cell arrival by T~r If it does, tlle circuit is determined to be idle and marked accorclingly ill the lnocle fielcl of tl~e RAi\l 5 72.
Whenever a new cell arrives for a given VC i, compliancy (Np' < 'Cp) and /Vd/ < /Cd and if it is complialIt~ the relevaut fielcls are iucremeuted in RA~I 7S as well as the current value of time Tn~w into the last arrival field and que~le the cell for transmission of a new burst. If the conclitiolI is llot co~npliant, it is necessar~, IO to either wait, discard the cell or mark it as llon-com])lialIt aud queue the cell for transmissiolI. If the VC is idle and a ne~-~ cell arrives, it is treated as a ne~v burst and the new burst register is set for this VC. There is uo "fly-wheel effect".ondeclaring a ne~v burst, but tl~ere is such an effect OII declarinO id]e. Tllis is sho-~/n in Figure 8.
IS A similar implementation of estimating B-i and the sum of existing compliant cells is sho~vn in Figure 9. The hardware embodiment in Figure 9 maiutains tracl;
of the residual time Bnl remaining from a particular virtual cha~nel n and in addition, computes the sum of the residual times from all of the virtual channels.
When a call is admitted, the sum of all the residual worl; from the e~isti~g 20 VCs, sum B', is incremented in unit 92 by B' and B-' and is set to Bi.
At lock clock pulse Tp both B-i and sum B are decrernented by one. The value of Xi is calculated in unit 90 from the equation:
,y;- - Tnin ~.B~ (rQ ~ D, ~pT4 ¦
Wheuever B-; is zero, the correspondiug VC is assumed to cllange from the compliant mode to tlle sustained mocle. Resources allocations for future bursts assume that tlle VC will only be transrnitting at tlle sustained rate of 1/~D~
A RAM-based implementatioll o~ tlle event in Figure 9 and the contents of tlle RAM is sllown in Figure 10. TlIis RAM keeps tracl; of each of the VCs in tlle compliant mode and their residual load OII the system.
A problelIl ~vith the above ilnplemelltation may i)e the size of the queue ueeded to ensure that it is possible to cycle thlougll all the possible elltries iu the RAM in Figure 6. Ol)e method of sin1l)lification is l)y maii1tail1illg a liul;-list of tllc l~e~;t ~T e~,ents that lleed to be increl~1el)lecl or cte.cre.n~elltecl in the RA~l. N is chosel1 such that there is sufTricient tinle to c)~cle througll the eutile ~/C.' space of lhe R..'\l\l. If N is IllllCh smallel tllall the size of the pliority lueue thell it n1ay be ol ~ ~ffi(~iel1t il1ll~lell1ellt~tiol~ ~

.. .. ~ ~ ,~ .
.,: ., , ,., . ,,,.; . .

2 12 ~ 7 ~ ~
~rc~,~2 ~-ll~ a preferred elnl)odilllent` the harclware elelnent.s are replacecl l~y lnel1loly elelnents. In a RA~ l)c~sed en1bodil11eut, a dedicated processor, ancl comlnoclity memory ICs, are used to esselltially simulate the operatiou of the hardware il-lustrated in Figures 3 and 4. Tlle embodiment comprises of a sil~gle processol, 5 a~1d some associated D~Al`vl lCs. Even thougl1 none of the conllollers is actually e:~plicitly implemented, the "state" of each controller is saved in a preassigned locatioll in DRAI\/I.
Such an implemelltation strategy is workable, because each cell-acceptal1ce decisioll depeDds only ol1 the state of a single controller. Sillce new cell-accepta~1ce lO decisions must be made at a rate typically of over 3001~Hz, it is difficult to l;eep tlle states of each of the controllers constalltly up-to-date. Since al1y new cell acceptance decision is based on the state of ouly a single controller, it is possible to calculate the up-to-date state of that particular coQtroller "Oll demand," and thus, obtain the required correct state.
E~egardless of the number of controllers beillg implemented, irl a preferred embodiment, the counter values of each controller are always updated every 64K
maximum-rate cell transfer times. In order to update a counter value of a con-troller, two pieces of information are needed: the number of couuter decremerltsthat would have occurred since the last counter-value update, and the number 20 of counter-value increments that have occurred since the last update. By fixing the amount of time between updates, it is possible to calculate the the i~rst piece of informatiorl by knowing both the rate at which the decrements occur, and the amount of time between the time of the last update arld the first decrement of the counter that would have occurred if the counter had been directly implemented 25 iu hardware; this last "decrell~ent o~Fset" value is subtracted from 6asK alld the result is divided by the rate of the decrements. It is possible, that the decrement ot~set may change after each update, and hence, it is necessary to associate addi-tional state with each counter. The nulllber of couuter value iucrements is keptup-to-date as cell-acceptance decisions are made, aud is "zeroed" each time that30 the counter value is updated.
In order to facilitate the ability to malie l1ew acceptallce decisiol~s, tlle con-trollers are updated in sequellce, alld the updates of eacl~ controller are equally-spaced over time. Witl~ these last two facts, the up-to-date state of ally particular coutroller can be calculatecl "Ol~ demand," wl~ene~er a new acceplallce decision.
35 The on-dell1and upclate is ~erforl~1ed in the san1e fasllioll as the previously de-scribecl ' standarcl" coul~tel-value update, e~cept that the tilne sil~ce the last stan-dald upclate ~nllst l)e colnl)utecl froln tlle currel)t time (mocllllo G'll~)~ lhe colltrollel .; , ~ ., 1 :,.', ~, ,., " " .:. . .

2~ 2~7~i7 ~c~2 ~.~ '7~' de.~7l, allr~ tlle spacillg l)et\~eel) tl~e ul)dates of tlle clil~erent col~trollers.
If it is assull1ecl tl~at all coul]ters l~ave a n~a~ ulll value of 256, ancl are ~ecre-mellted at a millimUIIl rate of ollce e~ery 641~ cell transfer tin1es, two 256K X 4-bit ~Ons DRAMs could supl)orts as n1ally as 41< Leal;y-Bucket controllels. Tlle limit S of 4K is not due to memory capacity, but rather to memory band~idtl1 difficulties.
In particular, the need to detect "idle" VCs in a timely fashiol1 (e.g, withil1 5ms of the time that would be illclicated by a explicit im,vlemel1tation of the idle counter), it is necessary for the processor to "send" itself queries that are analogous to new acceptance decisions; each (luery needs to compute the up-to-date value of the "peak-count" leaky bucket, and the up-to-date value of the idle counter. The fre-quency at which tbese queries must be processed gro-vs linearly ~vitll the numl~er of contro11ers that are being implemeuted, and the available memory bal1dwidth using current techllology effectively limits the number of controllers to 4K.
A RAl~I-base implementation is, however, reasonably scalable. For example, if the additional cost of a custom processing IC is acceptable, 32K of (nou-trench) DRAM could be integrated onto the processor die, and a one-package, 128 leaky-bucket controller implementation could be realized. In addition, by addiug more DRAMs, the described implemeutation should scale to 16K Leaky-Bucket Cou-trollers, using 8 DRAMs Eor Controller state.
While there has been described and illustrated a control nnethod and archi-tecture for ATM networks, it will be apparent to these skilled in the art that variations aud modifications are possible without deviating from the broad spirit and teaching of the present invention which shall be limited solely by scope of tl~e claims appended hereto.
2S What is claimed is:

Claims (11)

1. A method of controlling an ATM network comprising the steps of:
determining a state of a channel between an input port and an output port;
when the state is determined to be idle, resources are allocated and a new burst of information is transmitted through said channel; and when the state is determined not the be idle, a new burst of information is not transmitted through said channel.

2. A method of controlling a channel in an ATM network as set forth in claim 1,wherein when the state is determined to be active, a request to transmit a burstof information is queued for later transmission of the burst of information.

3. A method of controlling a channel in an ATM network as set forth in claim 1, wherein the burst of information is transmitted at different rates whenthe channel is in a compliant mode and in a sustained mode.

4. A method of controlling a channel in an ATM network as set forth in claim 1, wherein resources are allocated when said new burst of information is to be transmitted.

5. A method of controlling a channel in an ATM network as set forth in claim 1, wherein resources are deallocated when the state changes from active to idle.

6. A circuit for controlling a channel in an ATM network comprising:
means for determining the state of a channel between an input port and an output port, means for requesting transmission of a new burst of information when the state of a channel is IDLE and for not transmitting a new burst of information when the state of a channel is ACTIVE.

7. A circuit for controlling a channel in an ATM network as set forth in claim 6, further comprising means for requesting transmission of burst information when the state of a channel is determined to be active.

8. A circuit for controlling a channel in an ATM network as set forth in claim 6, further comprising means for transmitting said burst of information at different rates when the state of a channel is in a compliant mode and is a sustained mode.

9. A circuit for controlling a channel in an ATM network as set forth in claim 6, further comprising means for allocating resources when a new burst of information is to be transmitted.

10. A circuit for controlling a channel in an ATM network as set forth in claim 6, further comprising means for deallocating resources when the state of a channel changes form an active to idle.

11. A circuit for determining a state of a channel in an ATM network com-prising:
a first counter for receiving as a first input a signal commensurate with a cell of information and for receiving as a second input pulse signals defining a peak rate and for providing an output signal at said peak rate;
a first comparator coupled for receiving as a first input said output sig-nal from said first counter and for receiving as a second input a signal commensurate with the size of said first counter, said first compara-tor providing an output signal commensurate with the first compara-first counter being less than the size of said first counter;
a second counter for receiving as a first input a signal commensurate with a cell of information and for receiving as a second input pulse signals defining a sustained rate and form providing an output signal at said sustained rate;
a second comparator for receiving as a first input said output signal of said second counter and for receiving as a second input a signal commensurate with the size of said second counter said second com-parator providing an output signal commensurate with the output of said second counter being less than the size of said second counter;
first AND gate means coupled for receiving as first input a signal in-dicative of the count of said first counter being zero and for receiving as a second input said pulse signals defining a sustained rate and for providing an output signal at said sustained rate when said count of said first counter is zero;
first flip-flop means coupled for receiving as a first input a signal indica-tive of the count of said first circuit being zero and for receiving as a second input clock pulses and for providing an output signal when the count is non-zero;
third counter means coupled to said first AND gate means for counting the quantity of pulses at said sustained rate when the count of said first counter is zero and for being coupled to said flip-flop means for being cleared responsive to said output signal from said first flip-flop means;
latch means coupled to said third counter means for receiving as a first input a carry output from said third counter means and for receiving as a second input said clock pulses and for providing an output signal indicative of the channel being in an idle state;
second AND gate means coupled to said latch means for receiving as a first input said output signal from said latch means and for receiving as a second input a new cell signal and for providing an output signal indicative of a new cell signal being received when said output signal from said latch means indicates the channel being in an idle state;
second flip-flop means coupled to make second AND gates means for receiving said output signal from said second AND gate means as a first input and for receiving as a second input said clock signal and for providing an output signal indicative of a new burst of information;
means coupled for receiving as inputs new cell information, said output signal from said second flip-flop means indicative of a new burst of information; not a new burst of information signal and an ACK
signal and for providing an output signal indicative of a cell being ready for transmission; and third AND gate means coupled for receiving as inputs said output signal indicative of a cell being ready for transmission from said means for receiving said output signal from said first comparator and said output signal from said second comparator and for providing as an output signal a signal indicative that a cell is ready for transmission, and said second counters.