CA2129497A1 - Variable accuracy indirect addressing scheme for simd multi-processors and apparatus implementing same - Google Patents
Variable accuracy indirect addressing scheme for simd multi-processors and apparatus implementing sameInfo
- Publication number
- CA2129497A1 CA2129497A1 CA002129497A CA2129497A CA2129497A1 CA 2129497 A1 CA2129497 A1 CA 2129497A1 CA 002129497 A CA002129497 A CA 002129497A CA 2129497 A CA2129497 A CA 2129497A CA 2129497 A1 CA2129497 A1 CA 2129497A1
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- Prior art keywords
- processing element
- local memory
- shift register
- processing
- transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
Abstract
ABSTRACT OF THE DISCLOSURE
In a parallel processing architecture following the Single Instruction stream Multiple Data stream execution paradigm where a controller element is connected to at least one processing element with a local memory having a local memory address shift register adapted to receive and retain therein a globally broadcast memory base register address value received from the controller element for use by the processing element for access and transfer of data between the processing element and its respective local memory, a computer architecture for implementing indirect addressing and look-up tables includes a processing element shift register associated with the at least one processing element and adapted to receive and retain therein a local memory offset address value calculated or loaded by the associated processing element in accord with a first predetermined set of instructions. The processing element shift register transfers its contents bitwise to the local memory shift register of the local memory associated with the processing element, with the bit value of the most significant bit position being sequentially transferred to the least significant bit position of the local memory shift register in accord with a second predetermined set of instructions. A parallel transfer of the contents of the two shift registers is also disclosed.
In a parallel processing architecture following the Single Instruction stream Multiple Data stream execution paradigm where a controller element is connected to at least one processing element with a local memory having a local memory address shift register adapted to receive and retain therein a globally broadcast memory base register address value received from the controller element for use by the processing element for access and transfer of data between the processing element and its respective local memory, a computer architecture for implementing indirect addressing and look-up tables includes a processing element shift register associated with the at least one processing element and adapted to receive and retain therein a local memory offset address value calculated or loaded by the associated processing element in accord with a first predetermined set of instructions. The processing element shift register transfers its contents bitwise to the local memory shift register of the local memory associated with the processing element, with the bit value of the most significant bit position being sequentially transferred to the least significant bit position of the local memory shift register in accord with a second predetermined set of instructions. A parallel transfer of the contents of the two shift registers is also disclosed.
Description
` 2~2~97 A V~RIAB~ ACCURACY I~DIR~CT ADDRE~ING ~C~
FO~ 8IMD MULTI~PROCE880R8 AND APPARAT~ IMPLEME~TI~G ~AM~
1 BACRGRo~ND OF T~E INVEN~ION
FO~ 8IMD MULTI~PROCE880R8 AND APPARAT~ IMPLEME~TI~G ~AM~
1 BACRGRo~ND OF T~E INVEN~ION
2 1. Field of the Invention 3 This invention relates in general to computer architectures, 4 and, more particularly, to a method and an apparatus for enabling indirect addressing and lookup table impl~mentation on Single 6 Instruc~ion stream Multiple Data stream (SIMD) multi-processor 7 architectures.
9 2. Description of the Related Art In existing SIMD computer architectures, memory is generally 11 accessed by the processor array as a single plane of memory 12 locations.
13 In conventional SIMD architectures, the memory address 14 location is broadcast, along with the instruction word, to all processing elements by the controller. This configuration 16 normally results in the processing elements accessing a single 17 plane of data in memory. Offsets from this plane of data cannot 18 be done using this architecture, as there is no provision for 19 specifying, or modifying, the local memory address associated with each processor based on local data in each processor.
21 As a consequence of this lock-step approach, it is 22 especially difficult to implement efficiently indirect addressing 23 and look-up tables in a parallel processing architecture 24 following the Single Instruction stream ~ultiple Data stream execution paradigm. Indirect addressing requires serialization 26 of operations and thus uses O(N) cycles to perform the memory 27 access in an N processor syste~-29 ~NNaRY OF T~E INVENTION
Generally, the present invention is embodied in a method and 31 computer architecture for implementing indirect addressing and 32 look-up tables in a parallel processing architecture following 33 the Single Instruction stream Multiple Data stream execution 34 paradig~.
, . .
.,~ , . . , ~
~` 212~97 1 SIMD architecture utilizes a controller element connected 2 to an array of processing elements where each processing element 3 has associated with it a local memory that has a local memory 4 address shift register. The local memory addres~ shift register 5 i5 adapted to receive and retain a globally broadcast memory base 6 register address value received from the host, or from the 7 controller element, for use by the processing element in 8 accessing and transferring data between the processing element 9 and its respective local memory.
Each of the processing elements is further as~ociated with 11 a processing element shi~t register that is adapted to receive 12 and retain a local memory offset address value calculated or 13 loaded by the processing element in accord with a first 14 predetermined set of instructions. ~he processing element shift register is also further adapted to transfer its contents bitwise 16 to the local memory shift register of its associated local 17 memory, with the bit value of the most significant bit position 18 being sequentially transferred to the least significant bit 19 position of the local memory shift register in accord with a second predetermined set of instructions.
21 As an alternative, the processing element shift register can 22 also be adapted to transfer its contents to the local memory 23 shift register of its associated local memory, in a parallel 24 transfer as described more fully below.
The description of the invention presented is intended as 26 a general guideline for the design and implementation of the 27 invention into a specific implemen~tion. Therefore, specific ~ 28 details of the design, such a~ c~oc?~ rates, the number of bits i 29 in each register, etc., are left-to be determined based on the ; 30 implementation technology and the allotted cost of the final 31 product. In the following, the special details of the present 32 invention, which are unique to this invention, are elaborated.
1 33 The novel features of construction and operation of the 34 invention will b~ more clearly apparent during the course of the following description, reference being had to the accompanying :`
212~37 1 drawings wherein has been illustrated a preferred ~orm of the 2 device of the invention and wherein like characters of xeference 3 designate like parts throughout the drawings.
B~I~F DE8C~IPTIO~ OF ~ FIG~RES
6 FIG. l is an idealized block schematic diagram illustrating 7 the top level design of a computer architecture e~bodying the 8 present invention;
9 FIG. 2 is an idealized block schematic diagram illustrating the ~op level design of the processing slements forming the 11 processor array in a computer architecture similar to that of 12 FIG. 1 embodying the present invention;
13 FIG. 3 is an idealized block schematic diagram illustrating 14 the processor and memory level design in a computer architecture similar to that of FIG. 1 embodying the present invention.
17 DESCRIP~ION OF T~ PREF~RR~D EMBODIMENT
18 With reference being made to the Figures, a preferred l9 embodiment of the present invention will now be described in a method and an apparatus for providing a platform for efficient 21 implementation of the computation associated with processing a 22 wide variety of neural networks.
23 The invention is embodied in a computer architecture that 24 can roughly be classified as a Single Instruction stream Multiple Data streams (SIMD) medium or fine grain parallel computer. The 26 top level architecture of such an embodiment is depicted in 27 Figure 1 where each Processing Elemen~ 10 is arranged on a two 28 dimensional processor array lattice l~o, 29 This architecture is most easily` discussed in three major yroupings o~ functional units: the host computer 16, the 31 controller 18, and the Processor Array 20~
32 The controller unit 18 interfaces to both the host computer 33 16 and to the Processor Array 20. The controller 18 contains 34 a microprogram mem.ory area 32 that can be accessed by the host 16. High level programs can be written and compiled on the host .
212~7 1 16 and the generated control in~ormation can be downloaded from 2 the host 16 to the microprogram memory 32 of the controller 18.
3 The controller ~8 broadcasts an instruction and possibly a memory 4 address to ~he Processor Array 20 cluring each processing cycle.
The processors 10 in the Processor Array 20 perform operations 6 received from the controller 18 based on a mask flag available 7 in each Processing Element 10.
8 The Processor Array unit 20 contains all the processing 9 elements 10 and the supporting interconnection network 14. Each Processing Element 10 in the Processor Array 20 has direct access 11 to its local column of memory within the architecture's memory 12 space 23. Due to this distributed memory organization, memory 13 conflicts are eliminated which consequently simplifies both the 14 hardware and the software designs.
In the present architecture, the Processing Element 10 makes 16 up the computational engine of the system. As mentioned above, 17 the Processing Elements 10 are part of the Processor Array 20 18 subsystem and all receive the same instruction stream, but 19 perform the required operations on their own local data stream.
Each Processing Element 10 is comprised of a number of Functional 21 Units 24, a small register file 26, interprocessor communication 22 ports 28, s shift register (S/R) 29, and a mask flag 30 as 23 illustrated in FIG. 2.
24 In addition to supplying memory address and control instructions to the Processor Array 20, each instruction word 26 contains a specific field to control the loading and shifting of 27 data into the ~emory address modifyins xegister 29. This field 28 is used when the memory address suppliecl by the instruction needs 29 to be uniquely modified based on some local information in each processor 10, as in the case of a table lookup.
31 A novel feature of a computer architecture embodying the 32 present invention is its hardware support mechanism for 33 implementing indirect addressing or a variable accuracy lookup 34 table in the SIMD architecture.
:, , 212~97 1 Neural network models are a practical example o~ the use of 2 the present invention in a SIMD architecture. Such neural 3 network models use a variety of non-linear transfer functions 4 such as the sigmoid, the ramp, and the threshold functions.
These functions can be efficiently implemented through the use 6 of a lookup table. Implementation of a table lookup mechanism 7 on a SIMD architecture requires a method for 8 generation/modification of the memory address supplied by the 9 controller 18, based on some local value in each Processing Element 10.
11 A prior art architecture named BLITZEN developed by D.W.
12 Blevins, E.W. Davis, R.A. Heaton and J.H. Rief and described in 13 their article titled, "BLITZEN: A Highly Integrated Massively 14 Parallel Machine," in the 30urnal of Parallel and Distributed Computing (1990), Vol. 8, pp 150 - 160, performs this task by 16 logically ORin~ the 10 most significant bits of the memory 17 address supplied by the controller, with a local register value.
18 Such a ~cheme does not offer sufficient flexibility as required 19 for general-purpose neurocomputer design. The accuracy, or level of quantization of the neuron output values tolerated by neural 21 networks can vary significantly (from 2 to 16 bits) among 22 different neural network models and different applications o~
23 each model.
24 In order ~o accommodate lookup tables of varying sizes, an architecture embodying the present invention incorporates two 26 shift registers 44, 46 in FIG. 3 (shift register 44 in FIG. 3 i5 27 the equivalent of shift register 29 in ~IG. 2) that are used to 28 modify the address supplied by the ~onirQller 18. One shift 29 register 44 is associated with the Processing Element 10 and keeps the data value used for addressing the lookup table. The 31 other shift register 46 is associated with the Processing 32 Element's local memory 38 and is used to modify the address 33 received from the controller 18. See FIG. 3. The table lookup 34 procedure for a table of size 2~ is initiated when the controller 18 loads the base address of the table to each of the shift .
.
. :: . - . ~ .. ~
6 ~2~97 1 registers 46 associated with each Processing Element's local 2 memory 38 using a broadcast instruction. The base address value 3 is right shifted by k bits befors being broadcast by the 4 controller 18. This will insure that the proper value ~s being used after the augmentation of the k bit offset value. The 6 offset value is then shifted into this reqister 46 one bit at the 7 time from the local register 44 in the Processing Element 10 8 starting from the most significant bit into the least signi~icant 9 bit of the memory address register 46. The control signals for this shifting operation are generated by th~ controller 18 and 11 are broadcast to all Processing Elements 10 as part of the 12 microinstruction word. With this procedure, an address for a 13 table of size 2~ can be generated in k time steps by each 14 processor. By using a bitwise shifting operation, variable accuracy can be achieved in accessing data from memory array 22.
16 If variable accuracy retrieval is not necessary, the present 17 invention may be implemented by a parallel transfer into register 1~ 46 the contents of the local register 44 in the Processing 19 Element 10. The advantage of the parallel shifting of data between these two registers over that of the bitwise serial 21 shifting scheme is that only a single cycle of the architecture 22 is needed. However, it requires more physical pins and wires for 23 interconnection of the physical chips comprising the various 24 functional components of the architecture and provides only a fixed accuracy into the desired table held in memory.
26 Similarly, the bitwise shifting scheme described a~ove has 27 as advantages over the parallel trans~er scheme that it requires 28 only a single pinout and wire, and provides variable accuracy 29 into the desired memory table. However, it requires more machine cycles to shift out the register contents in a bitwise fashion 31 than the parallel transfer of the alternate scheme.
32 The invention described above is, of course, susceptible to 33 many variations, modifications and changes, all of which are 34 within the skill of the art. It should be understood that all suoh variations, modifioations and changes are vithin the spirit . , .
.". . ,., .................................... ~.
- ., 7 2~2~97 1 and scope of the invention and of the appended claims.
2 Similarly, it will be understood that Applicant intends to cover 3 and claim all changes, modi~'ications and variations of the 4 example of the preferred embodiment of the invention herein disclosed for the purpose of illustration which do not constitute 6 departures from the spirit and scope of the present invention.
., j~; . . , . ~ . - - . . . .
9 2. Description of the Related Art In existing SIMD computer architectures, memory is generally 11 accessed by the processor array as a single plane of memory 12 locations.
13 In conventional SIMD architectures, the memory address 14 location is broadcast, along with the instruction word, to all processing elements by the controller. This configuration 16 normally results in the processing elements accessing a single 17 plane of data in memory. Offsets from this plane of data cannot 18 be done using this architecture, as there is no provision for 19 specifying, or modifying, the local memory address associated with each processor based on local data in each processor.
21 As a consequence of this lock-step approach, it is 22 especially difficult to implement efficiently indirect addressing 23 and look-up tables in a parallel processing architecture 24 following the Single Instruction stream ~ultiple Data stream execution paradigm. Indirect addressing requires serialization 26 of operations and thus uses O(N) cycles to perform the memory 27 access in an N processor syste~-29 ~NNaRY OF T~E INVENTION
Generally, the present invention is embodied in a method and 31 computer architecture for implementing indirect addressing and 32 look-up tables in a parallel processing architecture following 33 the Single Instruction stream Multiple Data stream execution 34 paradig~.
, . .
.,~ , . . , ~
~` 212~97 1 SIMD architecture utilizes a controller element connected 2 to an array of processing elements where each processing element 3 has associated with it a local memory that has a local memory 4 address shift register. The local memory addres~ shift register 5 i5 adapted to receive and retain a globally broadcast memory base 6 register address value received from the host, or from the 7 controller element, for use by the processing element in 8 accessing and transferring data between the processing element 9 and its respective local memory.
Each of the processing elements is further as~ociated with 11 a processing element shi~t register that is adapted to receive 12 and retain a local memory offset address value calculated or 13 loaded by the processing element in accord with a first 14 predetermined set of instructions. ~he processing element shift register is also further adapted to transfer its contents bitwise 16 to the local memory shift register of its associated local 17 memory, with the bit value of the most significant bit position 18 being sequentially transferred to the least significant bit 19 position of the local memory shift register in accord with a second predetermined set of instructions.
21 As an alternative, the processing element shift register can 22 also be adapted to transfer its contents to the local memory 23 shift register of its associated local memory, in a parallel 24 transfer as described more fully below.
The description of the invention presented is intended as 26 a general guideline for the design and implementation of the 27 invention into a specific implemen~tion. Therefore, specific ~ 28 details of the design, such a~ c~oc?~ rates, the number of bits i 29 in each register, etc., are left-to be determined based on the ; 30 implementation technology and the allotted cost of the final 31 product. In the following, the special details of the present 32 invention, which are unique to this invention, are elaborated.
1 33 The novel features of construction and operation of the 34 invention will b~ more clearly apparent during the course of the following description, reference being had to the accompanying :`
212~37 1 drawings wherein has been illustrated a preferred ~orm of the 2 device of the invention and wherein like characters of xeference 3 designate like parts throughout the drawings.
B~I~F DE8C~IPTIO~ OF ~ FIG~RES
6 FIG. l is an idealized block schematic diagram illustrating 7 the top level design of a computer architecture e~bodying the 8 present invention;
9 FIG. 2 is an idealized block schematic diagram illustrating the ~op level design of the processing slements forming the 11 processor array in a computer architecture similar to that of 12 FIG. 1 embodying the present invention;
13 FIG. 3 is an idealized block schematic diagram illustrating 14 the processor and memory level design in a computer architecture similar to that of FIG. 1 embodying the present invention.
17 DESCRIP~ION OF T~ PREF~RR~D EMBODIMENT
18 With reference being made to the Figures, a preferred l9 embodiment of the present invention will now be described in a method and an apparatus for providing a platform for efficient 21 implementation of the computation associated with processing a 22 wide variety of neural networks.
23 The invention is embodied in a computer architecture that 24 can roughly be classified as a Single Instruction stream Multiple Data streams (SIMD) medium or fine grain parallel computer. The 26 top level architecture of such an embodiment is depicted in 27 Figure 1 where each Processing Elemen~ 10 is arranged on a two 28 dimensional processor array lattice l~o, 29 This architecture is most easily` discussed in three major yroupings o~ functional units: the host computer 16, the 31 controller 18, and the Processor Array 20~
32 The controller unit 18 interfaces to both the host computer 33 16 and to the Processor Array 20. The controller 18 contains 34 a microprogram mem.ory area 32 that can be accessed by the host 16. High level programs can be written and compiled on the host .
212~7 1 16 and the generated control in~ormation can be downloaded from 2 the host 16 to the microprogram memory 32 of the controller 18.
3 The controller ~8 broadcasts an instruction and possibly a memory 4 address to ~he Processor Array 20 cluring each processing cycle.
The processors 10 in the Processor Array 20 perform operations 6 received from the controller 18 based on a mask flag available 7 in each Processing Element 10.
8 The Processor Array unit 20 contains all the processing 9 elements 10 and the supporting interconnection network 14. Each Processing Element 10 in the Processor Array 20 has direct access 11 to its local column of memory within the architecture's memory 12 space 23. Due to this distributed memory organization, memory 13 conflicts are eliminated which consequently simplifies both the 14 hardware and the software designs.
In the present architecture, the Processing Element 10 makes 16 up the computational engine of the system. As mentioned above, 17 the Processing Elements 10 are part of the Processor Array 20 18 subsystem and all receive the same instruction stream, but 19 perform the required operations on their own local data stream.
Each Processing Element 10 is comprised of a number of Functional 21 Units 24, a small register file 26, interprocessor communication 22 ports 28, s shift register (S/R) 29, and a mask flag 30 as 23 illustrated in FIG. 2.
24 In addition to supplying memory address and control instructions to the Processor Array 20, each instruction word 26 contains a specific field to control the loading and shifting of 27 data into the ~emory address modifyins xegister 29. This field 28 is used when the memory address suppliecl by the instruction needs 29 to be uniquely modified based on some local information in each processor 10, as in the case of a table lookup.
31 A novel feature of a computer architecture embodying the 32 present invention is its hardware support mechanism for 33 implementing indirect addressing or a variable accuracy lookup 34 table in the SIMD architecture.
:, , 212~97 1 Neural network models are a practical example o~ the use of 2 the present invention in a SIMD architecture. Such neural 3 network models use a variety of non-linear transfer functions 4 such as the sigmoid, the ramp, and the threshold functions.
These functions can be efficiently implemented through the use 6 of a lookup table. Implementation of a table lookup mechanism 7 on a SIMD architecture requires a method for 8 generation/modification of the memory address supplied by the 9 controller 18, based on some local value in each Processing Element 10.
11 A prior art architecture named BLITZEN developed by D.W.
12 Blevins, E.W. Davis, R.A. Heaton and J.H. Rief and described in 13 their article titled, "BLITZEN: A Highly Integrated Massively 14 Parallel Machine," in the 30urnal of Parallel and Distributed Computing (1990), Vol. 8, pp 150 - 160, performs this task by 16 logically ORin~ the 10 most significant bits of the memory 17 address supplied by the controller, with a local register value.
18 Such a ~cheme does not offer sufficient flexibility as required 19 for general-purpose neurocomputer design. The accuracy, or level of quantization of the neuron output values tolerated by neural 21 networks can vary significantly (from 2 to 16 bits) among 22 different neural network models and different applications o~
23 each model.
24 In order ~o accommodate lookup tables of varying sizes, an architecture embodying the present invention incorporates two 26 shift registers 44, 46 in FIG. 3 (shift register 44 in FIG. 3 i5 27 the equivalent of shift register 29 in ~IG. 2) that are used to 28 modify the address supplied by the ~onirQller 18. One shift 29 register 44 is associated with the Processing Element 10 and keeps the data value used for addressing the lookup table. The 31 other shift register 46 is associated with the Processing 32 Element's local memory 38 and is used to modify the address 33 received from the controller 18. See FIG. 3. The table lookup 34 procedure for a table of size 2~ is initiated when the controller 18 loads the base address of the table to each of the shift .
.
. :: . - . ~ .. ~
6 ~2~97 1 registers 46 associated with each Processing Element's local 2 memory 38 using a broadcast instruction. The base address value 3 is right shifted by k bits befors being broadcast by the 4 controller 18. This will insure that the proper value ~s being used after the augmentation of the k bit offset value. The 6 offset value is then shifted into this reqister 46 one bit at the 7 time from the local register 44 in the Processing Element 10 8 starting from the most significant bit into the least signi~icant 9 bit of the memory address register 46. The control signals for this shifting operation are generated by th~ controller 18 and 11 are broadcast to all Processing Elements 10 as part of the 12 microinstruction word. With this procedure, an address for a 13 table of size 2~ can be generated in k time steps by each 14 processor. By using a bitwise shifting operation, variable accuracy can be achieved in accessing data from memory array 22.
16 If variable accuracy retrieval is not necessary, the present 17 invention may be implemented by a parallel transfer into register 1~ 46 the contents of the local register 44 in the Processing 19 Element 10. The advantage of the parallel shifting of data between these two registers over that of the bitwise serial 21 shifting scheme is that only a single cycle of the architecture 22 is needed. However, it requires more physical pins and wires for 23 interconnection of the physical chips comprising the various 24 functional components of the architecture and provides only a fixed accuracy into the desired table held in memory.
26 Similarly, the bitwise shifting scheme described a~ove has 27 as advantages over the parallel trans~er scheme that it requires 28 only a single pinout and wire, and provides variable accuracy 29 into the desired memory table. However, it requires more machine cycles to shift out the register contents in a bitwise fashion 31 than the parallel transfer of the alternate scheme.
32 The invention described above is, of course, susceptible to 33 many variations, modifications and changes, all of which are 34 within the skill of the art. It should be understood that all suoh variations, modifioations and changes are vithin the spirit . , .
.". . ,., .................................... ~.
- ., 7 2~2~97 1 and scope of the invention and of the appended claims.
2 Similarly, it will be understood that Applicant intends to cover 3 and claim all changes, modi~'ications and variations of the 4 example of the preferred embodiment of the invention herein disclosed for the purpose of illustration which do not constitute 6 departures from the spirit and scope of the present invention.
., j~; . . , . ~ . - - . . . .
Claims (4)
1. In a parallel processing architecture following the Single Instruction stream Multiple Data stream execution paradigm where a controller element is connected to at least one processing element with a local memory having a local memory address shift register adapted to receive and retain therein a globally broadcast memory base address value received from the controller element for use by the processing element for access and transfer of data between the processing element and its respective local memory, a computer architecture for implementing indirect addressing and look-up tables comprising:
a processing element shift register associated with the at least one processing element and adapted to receive and retain therein a local memory offset address value calculated or loaded by the associated processing element in accord with a first predetermined set of instructions, said processing element shift register further adapted to transfer its contents bitwise to the local memory shift resister of the local memory associated with the processing element, with the bit value of the most significant bit position being sequentially transferred to the least significant bit position of the local memory shift register in accord with a second predetermined set of instructions.
a processing element shift register associated with the at least one processing element and adapted to receive and retain therein a local memory offset address value calculated or loaded by the associated processing element in accord with a first predetermined set of instructions, said processing element shift register further adapted to transfer its contents bitwise to the local memory shift resister of the local memory associated with the processing element, with the bit value of the most significant bit position being sequentially transferred to the least significant bit position of the local memory shift register in accord with a second predetermined set of instructions.
2. In a parallel processing architecture following the Single Instruction stream Multiple Data stream execution paradigm where a controller element is connected to at least one processing element with a local memory having a local memory address shift register adapted to receive and retain therein a globally broadcast memory base address value received from the controller element for use by the processing element for access and transfer of data between the processing element and its respective local memory, a computer architecture for implementing indirect addressing and look-up tables comprising:
a processing element shift register associated with at least one processing element and adapted to receive and retain therein a local memory offset address value calculated or loaded by the associated processing element in accord with a first predetermined set of instructions, said processing element shift register further adapted to transfer its contents to the local memory shift register of the local memory associated with the processing element, in a parallel transfer of bits between the two registers.
a processing element shift register associated with at least one processing element and adapted to receive and retain therein a local memory offset address value calculated or loaded by the associated processing element in accord with a first predetermined set of instructions, said processing element shift register further adapted to transfer its contents to the local memory shift register of the local memory associated with the processing element, in a parallel transfer of bits between the two registers.
3. A computer architecture for implementing indirect addressing and look-up tables in a parallel processing architecture following the Single Instruction stream Multiple Data stream execution paradigm, the architecture comprising:
a controller element connected to at least one processing element, said processing element associated with a local memory having a local memory address shift register adapted to receive and retain therein a globally broadcast memory base register address value received from said controller element for use by said processing element for access and transfer of data between the processing element and its respective local memory, said at least one processing element further associated with a processing element shift register adapted to receive and retain therein a local memory offset address value calculated or loaded by said processing element in accord with a first predetermined set of instructions, said processing element shift register further adapted to transfer its contents bitwise to said local memory shift register of said local memory associated with the processing element, with the bit value of the most significant bit position being sequentially transferred to the least significant bit position of said local memory shift register in accord with a second predetermined set of instructions.
a controller element connected to at least one processing element, said processing element associated with a local memory having a local memory address shift register adapted to receive and retain therein a globally broadcast memory base register address value received from said controller element for use by said processing element for access and transfer of data between the processing element and its respective local memory, said at least one processing element further associated with a processing element shift register adapted to receive and retain therein a local memory offset address value calculated or loaded by said processing element in accord with a first predetermined set of instructions, said processing element shift register further adapted to transfer its contents bitwise to said local memory shift register of said local memory associated with the processing element, with the bit value of the most significant bit position being sequentially transferred to the least significant bit position of said local memory shift register in accord with a second predetermined set of instructions.
4. In a computer system having a controller connected to a plurality of processing elements, and associated with each processing element a local memory with a local memory shift register for access and transfer of data between the associated processing element and its associated local memory, a system for implementing indirect addressing look-up tables in a parallel processing architecture following the Single Instruction stream Multiple Data stream execution paradigm, the architecture comprising:
a plurality of processing element shift registers, each associated with a respective one of the processing elements and each adapted to receive and retain therein a local memory offset address value calculated by each associated processing element in accord with a first predetermined set of instructions, each of said processing element shift registers further adapted to transfer its contents bitwise to the local memory shift register of the local memory associated with the processing element with the bit value of the most significant bit position being sequentially transferred to the least significant bit position of the local memory shift register in accord with a second predetermined set of instructions.
a plurality of processing element shift registers, each associated with a respective one of the processing elements and each adapted to receive and retain therein a local memory offset address value calculated by each associated processing element in accord with a first predetermined set of instructions, each of said processing element shift registers further adapted to transfer its contents bitwise to the local memory shift register of the local memory associated with the processing element with the bit value of the most significant bit position being sequentially transferred to the least significant bit position of the local memory shift register in accord with a second predetermined set of instructions.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/106,343 US5526501A (en) | 1993-08-12 | 1993-08-12 | Variable accuracy indirect addressing scheme for SIMD multi-processors and apparatus implementing same |
| US08/106,343 | 1993-08-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2129497A1 true CA2129497A1 (en) | 1995-02-13 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002129497A Abandoned CA2129497A1 (en) | 1993-08-12 | 1994-08-04 | Variable accuracy indirect addressing scheme for simd multi-processors and apparatus implementing same |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5526501A (en) |
| EP (1) | EP0638868A3 (en) |
| JP (1) | JPH0764853A (en) |
| CA (1) | CA2129497A1 (en) |
| IL (1) | IL110607A0 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP3276782B2 (en) * | 1994-08-18 | 2002-04-22 | 本田技研工業株式会社 | Electric assisted bicycle |
| FR2737589B1 (en) | 1995-07-31 | 1997-09-12 | Suisse Electronique Microtech | ORGANIZATION SYSTEM AND METHOD FOR SEQUENCING THE CIRCUITS OF A MICROPROCESSOR |
| CN1120413C (en) * | 1998-04-01 | 2003-09-03 | 北京多思科技工业园股份有限公司 | Crossed parallel processing method utilizing data correlation and serial operation |
| US6334176B1 (en) * | 1998-04-17 | 2001-12-25 | Motorola, Inc. | Method and apparatus for generating an alignment control vector |
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| US5212777A (en) * | 1989-11-17 | 1993-05-18 | Texas Instruments Incorporated | Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) modes and method of operation |
-
1993
- 1993-08-12 US US08/106,343 patent/US5526501A/en not_active Expired - Lifetime
-
1994
- 1994-08-04 CA CA002129497A patent/CA2129497A1/en not_active Abandoned
- 1994-08-09 IL IL11060794A patent/IL110607A0/en unknown
- 1994-08-09 EP EP94112404A patent/EP0638868A3/en not_active Withdrawn
- 1994-08-12 JP JP6190729A patent/JPH0764853A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| EP0638868A3 (en) | 1995-11-15 |
| EP0638868A2 (en) | 1995-02-15 |
| IL110607A0 (en) | 1994-11-11 |
| JPH0764853A (en) | 1995-03-10 |
| US5526501A (en) | 1996-06-11 |
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