CA2137046A1 - Processing System and Method of Operation - Google Patents

Processing System and Method of Operation

Info

Publication number
CA2137046A1
CA2137046A1 CA2137046A CA2137046A CA2137046A1 CA 2137046 A1 CA2137046 A1 CA 2137046A1 CA 2137046 A CA2137046 A CA 2137046A CA 2137046 A CA2137046 A CA 2137046A CA 2137046 A1 CA2137046 A1 CA 2137046A1
Authority
CA
Canada
Prior art keywords
instruction
processing stage
execution
dispatched
dispatch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2137046A
Other languages
French (fr)
Other versions
CA2137046C (en
Inventor
Seungyoon P. Song
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CA2137046A1 publication Critical patent/CA2137046A1/en
Application granted granted Critical
Publication of CA2137046C publication Critical patent/CA2137046C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers

Abstract

A system and method for dispatching instructions in a processing system are provided. A dispatch processing stage dispatches a first instruction to execution circuitry. After the first instruction is dispatched, a dispatch processing stage dispatches a second instruction to the execution circuitry. After dispatch of the second instruction, a third instruction is dispatched to the execution circuitry and an execution processing stage of the third instruction is initiated prior to initiating an execution processing stage for the dispatched second instruction.
CA002137046A 1994-03-31 1994-11-30 Processing system and method of operation Expired - Fee Related CA2137046C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US22099394A 1994-03-31 1994-03-31
US220,993 1994-03-31

Publications (2)

Publication Number Publication Date
CA2137046A1 true CA2137046A1 (en) 1995-10-01
CA2137046C CA2137046C (en) 2000-01-18

Family

ID=22825892

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002137046A Expired - Fee Related CA2137046C (en) 1994-03-31 1994-11-30 Processing system and method of operation

Country Status (13)

Country Link
US (1) US6041167A (en)
EP (1) EP0753173B1 (en)
JP (1) JP2742392B2 (en)
KR (1) KR0145035B1 (en)
CN (1) CN1099082C (en)
AT (1) ATE177546T1 (en)
CA (1) CA2137046C (en)
DE (1) DE69417071T2 (en)
HU (1) HUT75816A (en)
PL (1) PL177392B1 (en)
RU (1) RU2150738C1 (en)
TW (1) TW353732B (en)
WO (1) WO1995027246A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999008184A1 (en) * 1997-08-06 1999-02-18 Advanced Micro Devices, Inc. An apparatus and method for accessing special registers without serialization
JP5093237B2 (en) * 2007-06-20 2012-12-12 富士通株式会社 Instruction processing device
EP2169539A4 (en) * 2007-06-20 2010-12-29 Fujitsu Ltd Instruction control device and instruction control method
US7913067B2 (en) * 2008-02-20 2011-03-22 International Business Machines Corporation Method and system for overlapping execution of instructions through non-uniform execution pipelines in an in-order processor
WO2015145191A1 (en) * 2014-03-27 2015-10-01 Intel Corporation Instruction and logic for sorting and retiring stores
CN108255743A (en) * 2017-12-06 2018-07-06 中国航空工业集团公司西安航空计算技术研究所 One kind is used to write back arbitration circuit in kernel is dyed
KR20220146835A (en) * 2021-04-26 2022-11-02 한국전자통신연구원 Method and apparatus for disaggregation of computing resource

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5776634A (en) * 1980-10-31 1982-05-13 Hitachi Ltd Digital signal processor
JPH069028B2 (en) * 1986-02-18 1994-02-02 日本電気株式会社 Arithmetic unit
US5051940A (en) * 1990-04-04 1991-09-24 International Business Machines Corporation Data dependency collapsing hardware apparatus
JPH06103494B2 (en) * 1986-11-18 1994-12-14 株式会社日立製作所 Vector processor control system
JPH02103656A (en) * 1988-10-12 1990-04-16 Fujitsu Ltd System for controlling successive reference to main storage
US5075840A (en) * 1989-01-13 1991-12-24 International Business Machines Corporation Tightly coupled multiprocessor instruction synchronization
JPH0630094B2 (en) * 1989-03-13 1994-04-20 インターナショナル・ビジネス・マシーンズ・コーポレイション Multiprocessor system
JP2519798B2 (en) * 1989-05-30 1996-07-31 富士通株式会社 Verification method of serialization function in multiprocessor system
US5136697A (en) * 1989-06-06 1992-08-04 Advanced Micro Devices, Inc. System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache
US5129067A (en) * 1989-06-06 1992-07-07 Advanced Micro Devices, Inc. Multiple instruction decoder for minimizing register port requirements
US5075846A (en) * 1989-09-29 1991-12-24 Motorola, Inc. Memory access serialization as an MMU page attribute
US5471593A (en) * 1989-12-11 1995-11-28 Branigin; Michael H. Computer processor with an efficient means of executing many instructions simultaneously
US5487156A (en) * 1989-12-15 1996-01-23 Popescu; Valeri Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched
US5185871A (en) * 1989-12-26 1993-02-09 International Business Machines Corporation Coordination of out-of-sequence fetching between multiple processors using re-execution of instructions
JPH07101410B2 (en) * 1990-01-17 1995-11-01 インターナショナル、ビジネス、マシーンズ、コーポレーション Method for synchronizing instruction stream execution for testing serialization means in a data processing network
US5077692A (en) * 1990-03-05 1991-12-31 Advanced Micro Devices, Inc. Information storage device with batch select capability
US5261066A (en) * 1990-03-27 1993-11-09 Digital Equipment Corporation Data processing system and method with small fully-associative cache and prefetch buffers
IL94115A (en) * 1990-04-18 1996-06-18 Ibm Israel Dynamic process for the generation of biased pseudo-random test patterns for the functional verification of hardware designs
US5197135A (en) * 1990-06-26 1993-03-23 International Business Machines Corporation Memory management for scalable compound instruction set machines with in-memory compounding
US5214763A (en) * 1990-05-10 1993-05-25 International Business Machines Corporation Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism
JP2535252B2 (en) * 1990-10-17 1996-09-18 三菱電機株式会社 Parallel processor
JP2532300B2 (en) * 1990-10-17 1996-09-11 三菱電機株式会社 Instruction supply device in parallel processing device
JPH04172533A (en) * 1990-11-07 1992-06-19 Toshiba Corp Electronic computer
US5222244A (en) * 1990-12-20 1993-06-22 Intel Corporation Method of modifying a microinstruction with operands specified by an instruction held in an alias register
US5257354A (en) * 1991-01-16 1993-10-26 International Business Machines Corporation System for monitoring and undoing execution of instructions beyond a serialization point upon occurrence of in-correct results
ATE200357T1 (en) * 1991-07-08 2001-04-15 Seiko Epson Corp RISC PROCESSOR WITH STRETCHABLE ARCHITECTURE
EP0529303A3 (en) * 1991-08-29 1993-09-22 International Business Machines Corporation Checkpoint synchronization with instruction overlap enabled
US5269017A (en) * 1991-08-29 1993-12-07 International Business Machines Corporation Type 1, 2 and 3 retry and checkpointing
US5274818A (en) * 1992-02-03 1993-12-28 Thinking Machines Corporation System and method for compiling a fine-grained array based source program onto a course-grained hardware
US5257216A (en) * 1992-06-10 1993-10-26 Intel Corporation Floating point safe instruction recognition apparatus
US5257214A (en) * 1992-06-16 1993-10-26 Hewlett-Packard Company Qualification of register file write enables using self-timed floating point exception flags
US5268855A (en) * 1992-09-14 1993-12-07 Hewlett-Packard Company Common format for encoding both single and double precision floating point numbers
CA2123442A1 (en) * 1993-09-20 1995-03-21 David S. Ray Multiple execution unit dispatch with instruction dependency
EP0779577B1 (en) * 1993-10-18 2002-05-22 VIA-Cyrix, Inc. Micoprocessor pipe control and register translation
DE69429061T2 (en) * 1993-10-29 2002-07-18 Advanced Micro Devices Inc Superskalarmikroprozessoren
JP3311462B2 (en) * 1994-02-23 2002-08-05 富士通株式会社 Compile processing unit

Also Published As

Publication number Publication date
ATE177546T1 (en) 1999-03-15
HUT75816A (en) 1997-05-28
EP0753173A1 (en) 1997-01-15
KR0145035B1 (en) 1998-08-17
EP0753173B1 (en) 1999-03-10
JPH07271582A (en) 1995-10-20
PL177392B1 (en) 1999-11-30
WO1995027246A1 (en) 1995-10-12
TW353732B (en) 1999-03-01
CN1099082C (en) 2003-01-15
US6041167A (en) 2000-03-21
KR950027573A (en) 1995-10-18
CN1121210A (en) 1996-04-24
CA2137046C (en) 2000-01-18
HU9602595D0 (en) 1996-11-28
DE69417071T2 (en) 1999-10-14
PL316566A1 (en) 1997-01-20
DE69417071D1 (en) 1999-04-15
RU2150738C1 (en) 2000-06-10
JP2742392B2 (en) 1998-04-22

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EEER Examination request
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