CA2145553C - Multi-processor system including priority arbitrator for arbitrating request issued from processors - Google Patents
Multi-processor system including priority arbitrator for arbitrating request issued from processorsInfo
- Publication number
- CA2145553C CA2145553C CA002145553A CA2145553A CA2145553C CA 2145553 C CA2145553 C CA 2145553C CA 002145553 A CA002145553 A CA 002145553A CA 2145553 A CA2145553 A CA 2145553A CA 2145553 C CA2145553 C CA 2145553C
- Authority
- CA
- Canada
- Prior art keywords
- requests
- request
- circuit
- processor system
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
Abstract
In a multi-processor system, a priority arbitrator receives a request issued from each processor of the system, and arbitrates conflicts that occur among the requests. The requests derived from the respective processors are inputted via selectors to fixed priority arbitrating circuits. Only one request is selected by each fixed priority arbitrating circuit, and the selected request is held in an output register. The pending request is detected by an AND circuit, and the detection result is held in a pending register. When there is such a request held in the pending register, the subsequent request is not selected by the selector.
The priorities of the plural fixed priority arbitrating circuits within the multi-processor system may be made different from each other, depending upon the use conditions of the multi-processor system.
The priorities of the plural fixed priority arbitrating circuits within the multi-processor system may be made different from each other, depending upon the use conditions of the multi-processor system.
Description
MULTI-PROCESSOR SYSTEM INCLUDING PRIORITY ARBITRATOR FOR
ARBITRATING REQUEST ISSUED FROM PROCESSORS
The present invention generally relates to a multi-processor system.
More specifically, the present invention is directed to a multi-processor system including a priority arbitrator for arbitrating requests issued from the respective processors.
In multi-processor systems, requests should be sent out from a plurality of processors to a plurality of memory modules, or between a plurality of processors. For instance, in the multi-processor system of Figure 1, each of the priority arbitrators 401 to 404 outputs to the output port, any one of the request signals supplied from its four input ports. As a consequence, each of the selectors 501 to 504 selects any one of the four request data. In this case, various methods have been conventionally proposed as to how to arbitrate these requests in the priority arbitrators 401 to 404.
As the most primitive priority arbitrator, the fixed priority arbitrating method has been proposed; in this method, fixed priority is given to the respective input ports, and then the arbitration is continuously performed in accordance with this priority. In this fixed priority arbitrating method, the specific input port is always treated at a high priority. Thus, there is the problem that throughput of the overall multi-processor system cannot be increased. An example of such a fixed priority arbitrating circuit is shown in Figure 6.
Also, the round robin method has been proposed, wherein the priority orders of the respective input ports are modified in a cyclic form. For the conventional round robin method, a large amount of hardware is required for the circuit to cyclically change the priority orders. A more serious problem is that many requests are processed out of order.
One solution to the above-described problems is suggested in U.S.
Patent No. 4,991,084, entitled "NxM ROUND ROBIN ORDER ARBITRATING
SWITCHING MATRIX SYSTEM", issued to W. K. Rodiger et al. In that reference, a next request is only accepted after it has been confirmed that all of the previously-accepted request groups have been outputted; the next request is accepted so as to avoid that request being passed. That is, referring to Figure 7, each of the priority arbitrating circuits 401 to 404 in Figure 1 includes the register 930 for holding the input request group, the NOR gate 960 for detecting that the not-yet-outputted request is left in this register 930, the fixed priority arbitrating circuit 920 for arbitrating the respective requests by applying the fixed priority orders to those requests, and the AND gate 950 for acquiring the new request group from the input port when the NOR gate 960 detects that there is no remaining request. When the requests held in the register 930 are arbitrated for being outputted, the outputted requests are reset. As a result, the succeeding request cannot be entered into the register 930 until all of the requests which have been held at the same time have been outputted. In other words, the requests produced at the different timings are processed in order.
This round-robin-order arbitrating switching matrix system has the following problems.
Referring to Figure 7 and Figure 8, assuming that the requests are inputted at the port 1 and port 3 at the time instant T1, this request signal is held in the register 930 at the next time instant T2. Then, the request of the port 1 is selected by the fixed priority arbitrating circuit 920. "1" is outputted at only the output port 1, and "0" is outputted at other output ports. As a consequence, the request supplied from the port 3 is held and is outputted at the subsequent time instant T3.
When the request from the port 3 is outputted at the time instant T3, all of the storage contents of the register 930 become "0". Therefore, all the outputs are equal to "0" at the time instant T4. The NOR gate 960 informs the AND gate 950 that all the outputs have become "0". As a consequence, the request which has remained as an input at the port 2 from the time instant T2 is fetched by the register 930 at the time instant T5, and is then outputted therefrom without any conflict.
Considering the above-described operation ofthis system, although the request supplied from the port 2 has been inputted since the time instant T2, no request is issued at the time instant T4. This is because such a judgement is _2_ made as to whether or not the subsequent request should be received based on the storage content of the register 930.
Another problem is caused by the fixed priority arbitrating circuit 920 employed in the respective priority arbitrators 401 to 404 being operated in accordance with the same priority order. In other words, the specific input port is treated with a high priority in all of the priority arbitrators 401 to 404, so that the requests are processed unevenly. As a result, the problem produced is that performance of the overall system cannot be increased.
An object of the present invention is to solve the above-described problem, and therefore to arbitrate requests at high throughput without providing any interruptions among the requests in a multi-processor system.
Another object of the present invention is to execute a request arbitration in such a manner that requests entered from the respective input ports are substantially evenly processed.
Accordingly, the invention provides a multi-processor system comprising: a plurality of processors, a plurality of ports for outputting first requests from said processors, and a plurality of priority arbitrators for arbitrating the first requests from said processors for each of said plurality of ports;
wherein each of said plurality of priority arbitrators includes: a fixed priority arbitrating circuit; a pending circuit for detecting, by comparing between an input and an output of said fixed priority arbitrating circuit, such second requests which have not been selected by said fixed priority arbitrating circuit but have been suspended, and for holding said second requests; and, a selector which selects either one of said second requests from said pending circuit and said first requests from said processors; wherein said fixed priority arbitrating circuit arbitrates to select one request from the output of said selector in accordance with a fixed priority order, wherein said selector accepts further requests from any of said processors when there is no request in said pending circuit, wherein said selector does not newly accept further requests from any of said processors when said second requests are held in said pending circuit, and wherein sets of requests are processed such that there is no delay between adjacent sets of requests.
The present invention will be readily appreciated from the following description of preferred embodiments with reference to the accompanying drawings, in which:
Figure 1 is a schematic block diagram of an overall arrangement of a multi-processor system to which the present invention is applied;
Figure 2 is a schematic block diagram of a priority arbitrator according to an embodiment employed in the multi-processor system of the present invention;
Figure 3 is a timing chart for explaining request arbitration by the priority arbitrator, according to the embodiment of the present invention;
Figure 4 is a timing chart for representing one process operation of the priority arbitrator, according to the embodiment of the present invention;
Figure 5 is a timing chart for showing another process operation of the priority arbitrator, according to the embodiment of the present invention;
Figure 6 is a schematic block diagram of one example of a fixed priority arbitrator;
Figure 7 is a schematic block diagram of a conventional priority arbitrator; and, Figure 8 is a timing chart for explaining the conventional request arbitration.
Referring to the drawings, a multi-processor system according to an embodiment of the present invention is next described in detail.
In Figure 1, there is schematically shown a multi-processor system to which the present invention is applied. This multi-processor is constructed of four processors 101 to 104, input buffers 201 to 204 connected to the corresponding processors 101 to 104, and decoders 301 to 304 for decoding destination addresses. The multi-processor further includes priority arbitrators 401 to 404 for arbitrating conflicts occurring in output ports of the decoders 301 to 304, and selectors 501 to 504 for selecting requests issued from the input buffers 201 to 204 in response to the outputs from the priority arbitrators 401 to 404. The requests issued from the four processors 101 to 104 are entered together with the destination addresses into the input buffers 201 to 204, respectively.
Then, the respective destination addresses are decoded by the decoders 301 to 304 and are outputted as request signals therefrom, which are supplied to the priority arbitrators 401 to 404. In response to the request signals supplied by the decoders 301 to 304 to the input ports of the priority arbitrators 401 to 404, those arbitrators select one request to be supplied as a control signal to the corresponding one of the selectors 501 to 504. Upon receipt of the control signal derived from the priority arbitrators 401 to 404, the selectors 501 to 504 output the requests from the input buffers 201 to 204. Request outputs 601 to 604, selected by the selectors 501 to 504, may be connected to a memory module or to the processors.
The processors 101 to 104 output the memory access requests and the data transfer requests to other processors into each of the corresponding input buffers 201 to 204. These input buffers are arranged as FIFO (first-in first-out) buffers. When the preceding request is reserved, subsequent requests are held in a waiting condition at the input buffers 201 to 204.
The decoders 301 to 304 decode the 2-bit destination address into the 4-bit destination address. The decoded signals are one-by-one entered into the priority arbitrators 401 to 404 of the corresponding output ports.
Each of the selectors 501 to 504 is such a selector, having 4 inputs and 1 output. Also, the respective selector owns a bit width equal to the bit width of the request derived from the input buffers 201 to 204.
Referring now to Figure 2, each of the priority arbitrators 401 to 404 includes a selector 410, a fixed priority arbitrating circuit 420 for arbitrating the output selected from the selector 410, and an output register 430 for holding the output from the fixed priority arbitrating circuit 420. The priority arbitrator further employs an AND circuit 450 for detecting the request suspended by the fixed priority arbitrating circuit 420, a pending register 440 for holding the output from the AND circuit 450, and an OR circuit 460 for detecting whether or not a request is maintained in the pending register 440.
It should be understood in this embodiment that, although the description is made of use of a reference numeral like "410" for the selector shown in Figure 2, when a more restrictive explanation is required for the arrangement of the specific priority arbitrator, it may be specified by using the least significant numeral. For instance, when the selector 410 provided within the priority arbitrator 401 is specified, it is referred to as "selector 411 ".
The selector 410 has one input terminal for receiving the 4-bit request signals supplied from the decoders 301 to 304, and another input terminal to receive the 4-bit output signal derived from the pending register 440. Which input signal this selector 410 may output is determined upon the basis of output from the OR circuit 460. That is, if at least 1 bit of the output signal from the pending register 440 is "1 ", then the output from the OR circuit 460 becomes "1 ". In this case, the output signal value of the pending register 440 is outputted from the selector 410. On the other hand, if all the output signals of the pending register 440 are "0", then the output from the OR circuit 460 becomes "0". In this case, the request signals derived from the decoders 301 to 304 are outputted from the selector 410.
The fixed priority arbitrating circuit 420 arbitrates the 4-bit signals outputted from the selector 410 in such a way that if one or more of the bits is equal to "1", only one bit at that value is allowed through. In other words, in the case that either all the bits are "0", or only 1 bit is "1", the input signal to this fixed priority arbitrating circuit 420 directly outputs this input data. When a plurality of bits among the input data are "1", only 1 bit is selected from these plural bits equal to "1 ", and all of other bits are set to "0". One exemplified circuit of the fixed priority arbitrating circuit is represented in Figure 6. In Figure 6, the upper bit is selected with a high priority. That is, when data such as "0110"
(sequenced from top to bottom) is supplied to this fixed priority arbitrating circuit, the third bit "1" of this data is masked by the AND circuit, so that data "0100" is outputted.
As described above, referring back to Figure 2, the output register 430 holds the arbitrated result from the fixed priority arbitrating circuit 420.
The outputs of the output registers 431 to 434 are used as control signals of the selectors 501 to 504, respectively.
The AND circuit 450 detects the request signal held by the fixed priority arbitrating circuit 420. That is, this AND circuit 450 AND-gates an inverted signal of the output signal from the fixed priority arbitrating circuit 420 and the input signal thereof, so that the remaining request signal which has not been selected is outputted from the fixed priority arbitrating circuit 420.
The output signals from the AND circuit 450 are held by the pending register 440 and may be arbitrated in the next cycle. In other words, when at least 1 bit of the output (data) signal from the pending register 440 is equal to "1 ", since the output signal of this pending register 440 is selected by the selector 410, the subsequent request signal is not acceptable but the request signal held in the pending register 440 is processed with a high priority.
With employment of the above-described circuit arrangement, one of the problems belonging to the conventional multi-processor can be solved as follows:
Referring to Figure 2 and Figure 3, a request signal "1010" inputted into the selector 410 at a time instant T1 implies that request signals appear at the first port and the third port. Assuming that all the storage contents of the pending register 440 are "0", the request signal at the time instant T1 is selected by the selector 410. Also, assuming that the input ports of the fixed priority arbitrating circuit 420 are prioritized from the first port via the second port and the third port to the fourth port with a high priority, the first port is selected, and a request signal "1000" is held in the output register 430 whereas another request signal "0010" is held in the pending register 440 at a time instant T2.
At this time, since the output signal of the pending register 440 contains "1 ", the output signal of this pending register 440 is selected by the selector 410. In this case, since the output signal of the pending register 440 is "0010", a request signal "0010" is stored in the output register 430 and another request signal "0000" is stored in the pending register 440 at a time instant T3.
As the storage content of the pending register 440 corresponds to "0000" at this time instant, the inputted request signal is selected at the time instant T3.
Accordingly, the subsequent request signal "0100" is stored into the output register 430.
_7_ Comparing the arbitration timing of Figure 3 according to one embodiment of the present invention with that of Figure 8 in the prior art, the output signal becomes "0000" at the time instant T4 in this conventional multi-processor, so that there is an empty slot at the issuance of the request during each cycle. To the contrary, the succeeding request signal "0100" is issued at the time instant T4 in the multi-processor of the present invention. This is caused by a judgement based on the resultant request signal, held in the register 930 of the conventional multi-processor. On the other hand, according to the present invention, by a judgement based on the resultant request left in the pending register 440, the remaining request is directly arbitrated for the next issuance.
Next, a description will be made of another feature of the priority arbitrator employed in the multi-processor system of the present invention.
In the priority arbitrators 401 to 404 of the multi-processor system indicated in Figure 1, the fixed priority arbitrating circuits 421 to 424 of Figure 2 may separately define the priority from each other. As an example, it is conceivable (as in the circuit of Figure 6) that the ports of all of these fixed priority arbitrating circuits 421 to 424 are prioritized from the first port to the fourth port in that order. As another example, it is conceivable that the input ports of the first fixed priority arbitrating circuit 421 are prioritized, from the first port via the second and third ports to the fourth port, with higher priority in that order, while the input ports of the second fixed priority arbitrating circuit 422 are prioritized from the second port via the third and fourth ports to the first port with higher priority in that order. Further, the input ports of the third fixed priority arbitrating circuit 423 are prioritized from the third port via the fourth and first ports to the second port with higher priority in that order, and the input ports of the fourth fixed priority arbitrating circuit 424 are prioritized from the fourth port via the first and second ports to the third port with higher priority in that order.
In particular, according to the latter method, which will be referred to as "fixed rotate allocation" hereinafter, the priority orders may be more evenly given to the respective input ports.
First, a description will now be made of operations of the fixed priority arbitrating circuits 421 to 424 with reference to Figure 4. In this case, the input _g_ ports of all the fixed priority arbitrating circuits 421 to 424 are prioritized from the first port via the second and third ports to the fourth port with higher priority in that order. It should be noted in Figure 4 that, for instance, symbol "C [3-->1]"
indicates a "request C outputted from the third processor 103 to the first output 601 ". A first-line signal represents a request issued from a processor at each of the inputs. A second-line signal shows a request held at a head element of input buffers. A third-line signal denotes a request held in a second element of the input buffers.
When at a time instant T1, a request A from the first processor 101, a request B from the second processor 102, a request C from the third processor 103, and a request D from the fourth processor 104 are entered, since both the request A and the request C own the same first output as destination, a conflict will occur. Then, these requests A and C are arbitrated by the priority arbitrator 401. Since the input from the first port has a higher priority in this case, the request A is outputted to the first output 601 at the time instant T2. The request C is momentarily held in the input buffer 203, and then is outputted with a delay of 1 cycle at the time instant T3.
At the time instant T2, the request E competes with the request F at the second port, so that the request E derived from the first port owns a high priority and thus is outputted at the time instant T3. The request F is once held in the input buffer 202, and thereafter is outputted with a delay of one cycle at the time instant T4. Since the request C is held in the head of the input buffer at the third port of the input port, the request G is not subject to the output, so that this request G is held at the head element of the input buffer 203 at the time instant T3.
At the time instant T3, a request I from the first port competes with a request G of the input buffer 203 of the third port at this third port, and the request I from the first port owns a high priority. Since this request G is held in the input buffer 203, the request K is not subject to the output, and is held at a second buffer of the input buffer 203.
At a time instant T4, a request M from the first port competes with a request J of the input buffer 202 of the second port at the fourth port, and then _g_ the request M from the first port owns a high priority. The request J
continues to be held in the input buffer 202, and is outputted at a time instant T6.
As described above, the respective requests are sequentially outputted, and all of the request A to P are outputted at a time instant T7.
Subsequent operations of the multi-processor system when the priority is determined in accordance with the above-explained "fixed rotate allocation"
are explained with reference to Figure 5.
At a time instant T1 shown in Figure 5, when a request A is inputted from the first processor, a request B is entered from the second processor, a request C is supplied from the third processor, and a request D is inputted from the fourth processor; since both the request A and the request C are outputted from the same first port, a conflict occurs. Thus, both requests A and C are arbitrated by the priority arbitrator 401. In this case, since the request A
inputted from the first port can have the higher priority, the request A is outputted to the first output 601 at a time instant T2. The request C is momentarily held in the input buffer 203, and then is outputted with a delay of 1 cycle at a time instant T3.
At the time instant T2, a request E competes with a request F at the second port. In accordance with the fixed rotate allocation, since the second port of the input port owns the higher priority than the first port at the second port of the output port, the request F from the second port has a high priority and is outputted at the time instant T3. Since a request C is held in the head of the input buffer 203 at the third port of the input port, the request G is not subject to the output, and is held at the head element of the input buffer 203 at the time instant T3.
At the time instant T3, as the request E is held in the head of the input buffer 201 at the first port of the input port, a request I is not subject to the output. As a result, no conflict occurs among these requests at this time instant T3.
Similarly, also at a time instant T4, since the request I is held at the head of the input buffer 201 at the first port of the input port, a request M
is not subject to the output. As a consequence, no conflict occurs between the requests even at this time instant T4.
The respective requests are successively outputted in the above-described manner, and all of the requests A through P are outputted at a time instant T6.
Comparing now Figure 4 with Figure 5, it may be understood that the performance of the entire multi-processor system in the case of Figure 5, having the priority of the fixed priority arbitrating circuits 421 to 424 determined based on the fixed rotate allocation, is an improvement when compared with that of the Figure 4 case where all the priorities thereof employed in the priority arbitrators 401 to 404 are the same. It should be noted in this exemplification that relatively even requests are issued. When there are an extremely large number of requests from the first port of the input port, high performance may be expected when all the priorities of the fixed priority arbitrating circuits 421 to 424 are identical to each other.
As previously explained in detail, in the multi-processor system of the present invention, the requests can be arbitrated in such a manner that these requests are outputted without unnecessary empty slots. There is a further merit that the requests produced from the respective processors are evenly arbitrated, so that the performance of the entire system could be increased.
ARBITRATING REQUEST ISSUED FROM PROCESSORS
The present invention generally relates to a multi-processor system.
More specifically, the present invention is directed to a multi-processor system including a priority arbitrator for arbitrating requests issued from the respective processors.
In multi-processor systems, requests should be sent out from a plurality of processors to a plurality of memory modules, or between a plurality of processors. For instance, in the multi-processor system of Figure 1, each of the priority arbitrators 401 to 404 outputs to the output port, any one of the request signals supplied from its four input ports. As a consequence, each of the selectors 501 to 504 selects any one of the four request data. In this case, various methods have been conventionally proposed as to how to arbitrate these requests in the priority arbitrators 401 to 404.
As the most primitive priority arbitrator, the fixed priority arbitrating method has been proposed; in this method, fixed priority is given to the respective input ports, and then the arbitration is continuously performed in accordance with this priority. In this fixed priority arbitrating method, the specific input port is always treated at a high priority. Thus, there is the problem that throughput of the overall multi-processor system cannot be increased. An example of such a fixed priority arbitrating circuit is shown in Figure 6.
Also, the round robin method has been proposed, wherein the priority orders of the respective input ports are modified in a cyclic form. For the conventional round robin method, a large amount of hardware is required for the circuit to cyclically change the priority orders. A more serious problem is that many requests are processed out of order.
One solution to the above-described problems is suggested in U.S.
Patent No. 4,991,084, entitled "NxM ROUND ROBIN ORDER ARBITRATING
SWITCHING MATRIX SYSTEM", issued to W. K. Rodiger et al. In that reference, a next request is only accepted after it has been confirmed that all of the previously-accepted request groups have been outputted; the next request is accepted so as to avoid that request being passed. That is, referring to Figure 7, each of the priority arbitrating circuits 401 to 404 in Figure 1 includes the register 930 for holding the input request group, the NOR gate 960 for detecting that the not-yet-outputted request is left in this register 930, the fixed priority arbitrating circuit 920 for arbitrating the respective requests by applying the fixed priority orders to those requests, and the AND gate 950 for acquiring the new request group from the input port when the NOR gate 960 detects that there is no remaining request. When the requests held in the register 930 are arbitrated for being outputted, the outputted requests are reset. As a result, the succeeding request cannot be entered into the register 930 until all of the requests which have been held at the same time have been outputted. In other words, the requests produced at the different timings are processed in order.
This round-robin-order arbitrating switching matrix system has the following problems.
Referring to Figure 7 and Figure 8, assuming that the requests are inputted at the port 1 and port 3 at the time instant T1, this request signal is held in the register 930 at the next time instant T2. Then, the request of the port 1 is selected by the fixed priority arbitrating circuit 920. "1" is outputted at only the output port 1, and "0" is outputted at other output ports. As a consequence, the request supplied from the port 3 is held and is outputted at the subsequent time instant T3.
When the request from the port 3 is outputted at the time instant T3, all of the storage contents of the register 930 become "0". Therefore, all the outputs are equal to "0" at the time instant T4. The NOR gate 960 informs the AND gate 950 that all the outputs have become "0". As a consequence, the request which has remained as an input at the port 2 from the time instant T2 is fetched by the register 930 at the time instant T5, and is then outputted therefrom without any conflict.
Considering the above-described operation ofthis system, although the request supplied from the port 2 has been inputted since the time instant T2, no request is issued at the time instant T4. This is because such a judgement is _2_ made as to whether or not the subsequent request should be received based on the storage content of the register 930.
Another problem is caused by the fixed priority arbitrating circuit 920 employed in the respective priority arbitrators 401 to 404 being operated in accordance with the same priority order. In other words, the specific input port is treated with a high priority in all of the priority arbitrators 401 to 404, so that the requests are processed unevenly. As a result, the problem produced is that performance of the overall system cannot be increased.
An object of the present invention is to solve the above-described problem, and therefore to arbitrate requests at high throughput without providing any interruptions among the requests in a multi-processor system.
Another object of the present invention is to execute a request arbitration in such a manner that requests entered from the respective input ports are substantially evenly processed.
Accordingly, the invention provides a multi-processor system comprising: a plurality of processors, a plurality of ports for outputting first requests from said processors, and a plurality of priority arbitrators for arbitrating the first requests from said processors for each of said plurality of ports;
wherein each of said plurality of priority arbitrators includes: a fixed priority arbitrating circuit; a pending circuit for detecting, by comparing between an input and an output of said fixed priority arbitrating circuit, such second requests which have not been selected by said fixed priority arbitrating circuit but have been suspended, and for holding said second requests; and, a selector which selects either one of said second requests from said pending circuit and said first requests from said processors; wherein said fixed priority arbitrating circuit arbitrates to select one request from the output of said selector in accordance with a fixed priority order, wherein said selector accepts further requests from any of said processors when there is no request in said pending circuit, wherein said selector does not newly accept further requests from any of said processors when said second requests are held in said pending circuit, and wherein sets of requests are processed such that there is no delay between adjacent sets of requests.
The present invention will be readily appreciated from the following description of preferred embodiments with reference to the accompanying drawings, in which:
Figure 1 is a schematic block diagram of an overall arrangement of a multi-processor system to which the present invention is applied;
Figure 2 is a schematic block diagram of a priority arbitrator according to an embodiment employed in the multi-processor system of the present invention;
Figure 3 is a timing chart for explaining request arbitration by the priority arbitrator, according to the embodiment of the present invention;
Figure 4 is a timing chart for representing one process operation of the priority arbitrator, according to the embodiment of the present invention;
Figure 5 is a timing chart for showing another process operation of the priority arbitrator, according to the embodiment of the present invention;
Figure 6 is a schematic block diagram of one example of a fixed priority arbitrator;
Figure 7 is a schematic block diagram of a conventional priority arbitrator; and, Figure 8 is a timing chart for explaining the conventional request arbitration.
Referring to the drawings, a multi-processor system according to an embodiment of the present invention is next described in detail.
In Figure 1, there is schematically shown a multi-processor system to which the present invention is applied. This multi-processor is constructed of four processors 101 to 104, input buffers 201 to 204 connected to the corresponding processors 101 to 104, and decoders 301 to 304 for decoding destination addresses. The multi-processor further includes priority arbitrators 401 to 404 for arbitrating conflicts occurring in output ports of the decoders 301 to 304, and selectors 501 to 504 for selecting requests issued from the input buffers 201 to 204 in response to the outputs from the priority arbitrators 401 to 404. The requests issued from the four processors 101 to 104 are entered together with the destination addresses into the input buffers 201 to 204, respectively.
Then, the respective destination addresses are decoded by the decoders 301 to 304 and are outputted as request signals therefrom, which are supplied to the priority arbitrators 401 to 404. In response to the request signals supplied by the decoders 301 to 304 to the input ports of the priority arbitrators 401 to 404, those arbitrators select one request to be supplied as a control signal to the corresponding one of the selectors 501 to 504. Upon receipt of the control signal derived from the priority arbitrators 401 to 404, the selectors 501 to 504 output the requests from the input buffers 201 to 204. Request outputs 601 to 604, selected by the selectors 501 to 504, may be connected to a memory module or to the processors.
The processors 101 to 104 output the memory access requests and the data transfer requests to other processors into each of the corresponding input buffers 201 to 204. These input buffers are arranged as FIFO (first-in first-out) buffers. When the preceding request is reserved, subsequent requests are held in a waiting condition at the input buffers 201 to 204.
The decoders 301 to 304 decode the 2-bit destination address into the 4-bit destination address. The decoded signals are one-by-one entered into the priority arbitrators 401 to 404 of the corresponding output ports.
Each of the selectors 501 to 504 is such a selector, having 4 inputs and 1 output. Also, the respective selector owns a bit width equal to the bit width of the request derived from the input buffers 201 to 204.
Referring now to Figure 2, each of the priority arbitrators 401 to 404 includes a selector 410, a fixed priority arbitrating circuit 420 for arbitrating the output selected from the selector 410, and an output register 430 for holding the output from the fixed priority arbitrating circuit 420. The priority arbitrator further employs an AND circuit 450 for detecting the request suspended by the fixed priority arbitrating circuit 420, a pending register 440 for holding the output from the AND circuit 450, and an OR circuit 460 for detecting whether or not a request is maintained in the pending register 440.
It should be understood in this embodiment that, although the description is made of use of a reference numeral like "410" for the selector shown in Figure 2, when a more restrictive explanation is required for the arrangement of the specific priority arbitrator, it may be specified by using the least significant numeral. For instance, when the selector 410 provided within the priority arbitrator 401 is specified, it is referred to as "selector 411 ".
The selector 410 has one input terminal for receiving the 4-bit request signals supplied from the decoders 301 to 304, and another input terminal to receive the 4-bit output signal derived from the pending register 440. Which input signal this selector 410 may output is determined upon the basis of output from the OR circuit 460. That is, if at least 1 bit of the output signal from the pending register 440 is "1 ", then the output from the OR circuit 460 becomes "1 ". In this case, the output signal value of the pending register 440 is outputted from the selector 410. On the other hand, if all the output signals of the pending register 440 are "0", then the output from the OR circuit 460 becomes "0". In this case, the request signals derived from the decoders 301 to 304 are outputted from the selector 410.
The fixed priority arbitrating circuit 420 arbitrates the 4-bit signals outputted from the selector 410 in such a way that if one or more of the bits is equal to "1", only one bit at that value is allowed through. In other words, in the case that either all the bits are "0", or only 1 bit is "1", the input signal to this fixed priority arbitrating circuit 420 directly outputs this input data. When a plurality of bits among the input data are "1", only 1 bit is selected from these plural bits equal to "1 ", and all of other bits are set to "0". One exemplified circuit of the fixed priority arbitrating circuit is represented in Figure 6. In Figure 6, the upper bit is selected with a high priority. That is, when data such as "0110"
(sequenced from top to bottom) is supplied to this fixed priority arbitrating circuit, the third bit "1" of this data is masked by the AND circuit, so that data "0100" is outputted.
As described above, referring back to Figure 2, the output register 430 holds the arbitrated result from the fixed priority arbitrating circuit 420.
The outputs of the output registers 431 to 434 are used as control signals of the selectors 501 to 504, respectively.
The AND circuit 450 detects the request signal held by the fixed priority arbitrating circuit 420. That is, this AND circuit 450 AND-gates an inverted signal of the output signal from the fixed priority arbitrating circuit 420 and the input signal thereof, so that the remaining request signal which has not been selected is outputted from the fixed priority arbitrating circuit 420.
The output signals from the AND circuit 450 are held by the pending register 440 and may be arbitrated in the next cycle. In other words, when at least 1 bit of the output (data) signal from the pending register 440 is equal to "1 ", since the output signal of this pending register 440 is selected by the selector 410, the subsequent request signal is not acceptable but the request signal held in the pending register 440 is processed with a high priority.
With employment of the above-described circuit arrangement, one of the problems belonging to the conventional multi-processor can be solved as follows:
Referring to Figure 2 and Figure 3, a request signal "1010" inputted into the selector 410 at a time instant T1 implies that request signals appear at the first port and the third port. Assuming that all the storage contents of the pending register 440 are "0", the request signal at the time instant T1 is selected by the selector 410. Also, assuming that the input ports of the fixed priority arbitrating circuit 420 are prioritized from the first port via the second port and the third port to the fourth port with a high priority, the first port is selected, and a request signal "1000" is held in the output register 430 whereas another request signal "0010" is held in the pending register 440 at a time instant T2.
At this time, since the output signal of the pending register 440 contains "1 ", the output signal of this pending register 440 is selected by the selector 410. In this case, since the output signal of the pending register 440 is "0010", a request signal "0010" is stored in the output register 430 and another request signal "0000" is stored in the pending register 440 at a time instant T3.
As the storage content of the pending register 440 corresponds to "0000" at this time instant, the inputted request signal is selected at the time instant T3.
Accordingly, the subsequent request signal "0100" is stored into the output register 430.
_7_ Comparing the arbitration timing of Figure 3 according to one embodiment of the present invention with that of Figure 8 in the prior art, the output signal becomes "0000" at the time instant T4 in this conventional multi-processor, so that there is an empty slot at the issuance of the request during each cycle. To the contrary, the succeeding request signal "0100" is issued at the time instant T4 in the multi-processor of the present invention. This is caused by a judgement based on the resultant request signal, held in the register 930 of the conventional multi-processor. On the other hand, according to the present invention, by a judgement based on the resultant request left in the pending register 440, the remaining request is directly arbitrated for the next issuance.
Next, a description will be made of another feature of the priority arbitrator employed in the multi-processor system of the present invention.
In the priority arbitrators 401 to 404 of the multi-processor system indicated in Figure 1, the fixed priority arbitrating circuits 421 to 424 of Figure 2 may separately define the priority from each other. As an example, it is conceivable (as in the circuit of Figure 6) that the ports of all of these fixed priority arbitrating circuits 421 to 424 are prioritized from the first port to the fourth port in that order. As another example, it is conceivable that the input ports of the first fixed priority arbitrating circuit 421 are prioritized, from the first port via the second and third ports to the fourth port, with higher priority in that order, while the input ports of the second fixed priority arbitrating circuit 422 are prioritized from the second port via the third and fourth ports to the first port with higher priority in that order. Further, the input ports of the third fixed priority arbitrating circuit 423 are prioritized from the third port via the fourth and first ports to the second port with higher priority in that order, and the input ports of the fourth fixed priority arbitrating circuit 424 are prioritized from the fourth port via the first and second ports to the third port with higher priority in that order.
In particular, according to the latter method, which will be referred to as "fixed rotate allocation" hereinafter, the priority orders may be more evenly given to the respective input ports.
First, a description will now be made of operations of the fixed priority arbitrating circuits 421 to 424 with reference to Figure 4. In this case, the input _g_ ports of all the fixed priority arbitrating circuits 421 to 424 are prioritized from the first port via the second and third ports to the fourth port with higher priority in that order. It should be noted in Figure 4 that, for instance, symbol "C [3-->1]"
indicates a "request C outputted from the third processor 103 to the first output 601 ". A first-line signal represents a request issued from a processor at each of the inputs. A second-line signal shows a request held at a head element of input buffers. A third-line signal denotes a request held in a second element of the input buffers.
When at a time instant T1, a request A from the first processor 101, a request B from the second processor 102, a request C from the third processor 103, and a request D from the fourth processor 104 are entered, since both the request A and the request C own the same first output as destination, a conflict will occur. Then, these requests A and C are arbitrated by the priority arbitrator 401. Since the input from the first port has a higher priority in this case, the request A is outputted to the first output 601 at the time instant T2. The request C is momentarily held in the input buffer 203, and then is outputted with a delay of 1 cycle at the time instant T3.
At the time instant T2, the request E competes with the request F at the second port, so that the request E derived from the first port owns a high priority and thus is outputted at the time instant T3. The request F is once held in the input buffer 202, and thereafter is outputted with a delay of one cycle at the time instant T4. Since the request C is held in the head of the input buffer at the third port of the input port, the request G is not subject to the output, so that this request G is held at the head element of the input buffer 203 at the time instant T3.
At the time instant T3, a request I from the first port competes with a request G of the input buffer 203 of the third port at this third port, and the request I from the first port owns a high priority. Since this request G is held in the input buffer 203, the request K is not subject to the output, and is held at a second buffer of the input buffer 203.
At a time instant T4, a request M from the first port competes with a request J of the input buffer 202 of the second port at the fourth port, and then _g_ the request M from the first port owns a high priority. The request J
continues to be held in the input buffer 202, and is outputted at a time instant T6.
As described above, the respective requests are sequentially outputted, and all of the request A to P are outputted at a time instant T7.
Subsequent operations of the multi-processor system when the priority is determined in accordance with the above-explained "fixed rotate allocation"
are explained with reference to Figure 5.
At a time instant T1 shown in Figure 5, when a request A is inputted from the first processor, a request B is entered from the second processor, a request C is supplied from the third processor, and a request D is inputted from the fourth processor; since both the request A and the request C are outputted from the same first port, a conflict occurs. Thus, both requests A and C are arbitrated by the priority arbitrator 401. In this case, since the request A
inputted from the first port can have the higher priority, the request A is outputted to the first output 601 at a time instant T2. The request C is momentarily held in the input buffer 203, and then is outputted with a delay of 1 cycle at a time instant T3.
At the time instant T2, a request E competes with a request F at the second port. In accordance with the fixed rotate allocation, since the second port of the input port owns the higher priority than the first port at the second port of the output port, the request F from the second port has a high priority and is outputted at the time instant T3. Since a request C is held in the head of the input buffer 203 at the third port of the input port, the request G is not subject to the output, and is held at the head element of the input buffer 203 at the time instant T3.
At the time instant T3, as the request E is held in the head of the input buffer 201 at the first port of the input port, a request I is not subject to the output. As a result, no conflict occurs among these requests at this time instant T3.
Similarly, also at a time instant T4, since the request I is held at the head of the input buffer 201 at the first port of the input port, a request M
is not subject to the output. As a consequence, no conflict occurs between the requests even at this time instant T4.
The respective requests are successively outputted in the above-described manner, and all of the requests A through P are outputted at a time instant T6.
Comparing now Figure 4 with Figure 5, it may be understood that the performance of the entire multi-processor system in the case of Figure 5, having the priority of the fixed priority arbitrating circuits 421 to 424 determined based on the fixed rotate allocation, is an improvement when compared with that of the Figure 4 case where all the priorities thereof employed in the priority arbitrators 401 to 404 are the same. It should be noted in this exemplification that relatively even requests are issued. When there are an extremely large number of requests from the first port of the input port, high performance may be expected when all the priorities of the fixed priority arbitrating circuits 421 to 424 are identical to each other.
As previously explained in detail, in the multi-processor system of the present invention, the requests can be arbitrated in such a manner that these requests are outputted without unnecessary empty slots. There is a further merit that the requests produced from the respective processors are evenly arbitrated, so that the performance of the entire system could be increased.
Claims (20)
1. A multi-processor system comprising:
a plurality of processors, a plurality of ports for outputting first requests from said processors, and a plurality of priority arbitrators for arbitrating the first requests from said processors for each of said plurality of ports;
wherein each of said plurality of priority arbitrators includes:
a fixed priority arbitrating circuit;
a pending circuit for detecting, by comparing between an input and an output of said fixed priority arbitrating circuit, such second requests which have not been selected by said fixed priority arbitrating circuit but have been suspended, and for holding said second requests; and, a selector which selects either one of said second requests from said pending circuit and said first requests from said processors;
wherein said fixed priority arbitrating circuit arbitrates to select one request from the output of said selector in accordance with a fixed priority order, wherein said selector accepts further requests from any of said processors when there is no request in said pending circuit, wherein said selector does not newly accept further requests from any of said processors when said second requests are held in said pending circuit, and wherein sets of requests are processed such that there is no delay between adjacent sets of requests.
a plurality of processors, a plurality of ports for outputting first requests from said processors, and a plurality of priority arbitrators for arbitrating the first requests from said processors for each of said plurality of ports;
wherein each of said plurality of priority arbitrators includes:
a fixed priority arbitrating circuit;
a pending circuit for detecting, by comparing between an input and an output of said fixed priority arbitrating circuit, such second requests which have not been selected by said fixed priority arbitrating circuit but have been suspended, and for holding said second requests; and, a selector which selects either one of said second requests from said pending circuit and said first requests from said processors;
wherein said fixed priority arbitrating circuit arbitrates to select one request from the output of said selector in accordance with a fixed priority order, wherein said selector accepts further requests from any of said processors when there is no request in said pending circuit, wherein said selector does not newly accept further requests from any of said processors when said second requests are held in said pending circuit, and wherein sets of requests are processed such that there is no delay between adjacent sets of requests.
2. The multi-processor system as in claim 1, wherein said pending circuit further includes:
a first detecting circuit for detecting, by comparing between said input and said output of said fixed priority arbitrating circuit, such said second requests which have not been selected by said fixed priority arbitrating circuit but have been suspended;
a pending register for holding said second requests by said first detecting circuit; and, a second detecting circuit for detecting whether there is a request left in said pending register.
a first detecting circuit for detecting, by comparing between said input and said output of said fixed priority arbitrating circuit, such said second requests which have not been selected by said fixed priority arbitrating circuit but have been suspended;
a pending register for holding said second requests by said first detecting circuit; and, a second detecting circuit for detecting whether there is a request left in said pending register.
3. The multi-processor system as in claim 2, wherein said selector selects the output from said pending register when said second detecting circuit judges that a second request is left in said pending register, and wherein said selector selects a first request newly-supplied from said processor when said second detecting circuit judges that no second request is left in said pending register.
4. The multi-processor system as in claim 3, wherein said second detecting circuit includes a single "N"-input OR gate for providing an output to said selector, wherein "N" is a number of said processors.
5. The multi-processor system as in claim 2, wherein, based on a judgment by said pending circuit that a resulting request is left in the pending register, a remaining second request is directly arbitrated for a next issuance, such that no interruptions occur during processing of said plurality of requests.
6. The multi-processor system as in claim 2, wherein said first detecting circuit comprises a plurality of AND gates each for receiving said output of said fixed priority arbitrating circuit and said output of said selector.
7. The multi-processor system as in claim 6, wherein said second detecting circuit includes a single "N"-input OR gate for providing an output to said selector, wherein "N" is a number of said processors.
8. The multi-processor system as in claim 2, wherein said second detecting circuit includes a single "N"-input OR gate for providing an output to said selector, wherein "N" is a number of said processors.
9. The multi-processor system as in claim 1, wherein each of said fixed priority arbitrating circuits included in said plurality of priority arbitrators selects one of the first requests issued from said processors in accordance with such priority orders having the mutually same and fixed priorities.
10. The multi-processor system as in claim 1, wherein each of said fixed priority arbitrating circuits included in said plurality of priority arbitrators selects one of the first requests issued from said processors in accordance with such priority orders having the mutually different and fixed priorities.
11. The multi-processor system as in claim 1, wherein the first requests from any of said processors are output from one of said ports in order of time.
12. The multi-processor system as in claim 1, wherein each of said pending circuits holds only one set of second requests at a same time.
13. The multi-processor system as in claim 1, wherein said plurality of requests are processed such that no interruptions are present during processing of said plurality of requests.
14. The multi-processor system as in claim 1, wherein said plurality of requests from respective ones of said plurality of ports are substantially evenly processed, such that no interruptions are present during processing of said plurality of requests.
15. The multi-processor system as in claim 1, wherein each of said fixed priority arbitrating circuits separately define a priority from one another.
16. The multi-processor system as in claim 1, wherein said plurality of requests are processed such that no empty time slots exist during processing of said plurality of requests.
17. The multi-processor system as in claim 1, wherein each of said pending circuits holds one set of second requests at a same time, and accepts new requests only when all of said one set of second requests have been processed.
18. The multi-processor system as in claim 1, wherein said pending circuit includes a first detecting circuit comprising a plurality of AND
gates each for receiving said output of said fixed priority arbitrating circuit and said output of said selector.
gates each for receiving said output of said fixed priority arbitrating circuit and said output of said selector.
19. The multi-processor system as in claim 18, wherein said pending circuit further includes a second detecting circuit comprising a single "N"-input OR gate for providing an output to said selector, wherein "N" is a number of said processors.
20. The multi-processor system as in claim 1, wherein said pending circuit includes a detecting circuit having a single "N"-input OR gate for providing an output to said selector, wherein "N" is a number of said processors.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59696/1994 | 1994-03-30 | ||
| JP5969694 | 1994-03-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2145553A1 CA2145553A1 (en) | 1995-10-01 |
| CA2145553C true CA2145553C (en) | 1999-12-21 |
Family
ID=13120638
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002145553A Expired - Fee Related CA2145553C (en) | 1994-03-30 | 1995-03-27 | Multi-processor system including priority arbitrator for arbitrating request issued from processors |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5692136A (en) |
| EP (1) | EP0675446B1 (en) |
| BR (1) | BR9501308A (en) |
| CA (1) | CA2145553C (en) |
| DE (1) | DE69519486T2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5887146A (en) * | 1995-08-14 | 1999-03-23 | Data General Corporation | Symmetric multiprocessing computer with non-uniform memory access architecture |
| JP3667585B2 (en) * | 2000-02-23 | 2005-07-06 | エヌイーシーコンピュータテクノ株式会社 | Distributed memory type parallel computer and its data transfer completion confirmation method |
| US7120714B2 (en) * | 2003-05-27 | 2006-10-10 | Intel Corporation | High-speed starvation-free arbiter system, rotating-priority arbiter, and two stage arbitration method |
| JP2005092780A (en) * | 2003-09-19 | 2005-04-07 | Matsushita Electric Ind Co Ltd | Real time processor system and control method |
| US7788466B2 (en) * | 2003-09-19 | 2010-08-31 | Nxp B.V. | Integrated circuit with a plurality of communicating digital signal processors |
| US20060026329A1 (en) * | 2004-07-30 | 2006-02-02 | Yu James K | System and method for an arbiter rewind |
| US7890686B2 (en) * | 2005-10-17 | 2011-02-15 | Src Computers, Inc. | Dynamic priority conflict resolution in a multi-processor computer system having shared resources |
Family Cites Families (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3543242A (en) * | 1967-07-07 | 1970-11-24 | Ibm | Multiple level priority system |
| US3921145A (en) * | 1973-10-12 | 1975-11-18 | Burroughs Corp | Multirequest grouping computer interface |
| US4090238A (en) * | 1976-10-04 | 1978-05-16 | Rca Corporation | Priority vectored interrupt using direct memory access |
| US4334288A (en) * | 1979-06-18 | 1982-06-08 | Booher Robert K | Priority determining network having user arbitration circuits coupled to a multi-line bus |
| US4449183A (en) * | 1979-07-09 | 1984-05-15 | Digital Equipment Corporation | Arbitration scheme for a multiported shared functional device for use in multiprocessing systems |
| US4514728A (en) * | 1980-02-25 | 1985-04-30 | At&T Bell Laboratories | Store group bus allocation system |
| US4554628A (en) * | 1981-08-17 | 1985-11-19 | Burroughs Corporation | System in which multiple devices have a circuit that bids with a fixed priority, stores all losing bids if its bid wins, and doesn't bid again until all stored bids win |
| US4473880A (en) * | 1982-01-26 | 1984-09-25 | Intel Corporation | Arbitration means for controlling access to a bus shared by a number of modules |
| US4627018A (en) * | 1983-09-08 | 1986-12-02 | Sperry Corporation | Priority requestor accelerator |
| US4941086A (en) * | 1984-02-02 | 1990-07-10 | International Business Machines Corporation | Program controlled bus arbitration for a distributed array processing system |
| US4835672A (en) * | 1984-04-02 | 1989-05-30 | Unisys Corporation | Access lock apparatus for use with a high performance storage unit of a digital data processing system |
| US4964034A (en) * | 1984-10-30 | 1990-10-16 | Raytheon Company | Synchronized processing system with bus arbiter which samples and stores bus request signals and synchronizes bus grant signals according to clock signals |
| US5051946A (en) * | 1986-07-03 | 1991-09-24 | Unisys Corporation | Integrated scannable rotational priority network apparatus |
| US5038274A (en) * | 1987-11-23 | 1991-08-06 | Digital Equipment Corporation | Interrupt servicing and command acknowledgement system using distributed arbitration apparatus and shared bus |
| US4991084A (en) * | 1988-02-05 | 1991-02-05 | International Business Machines Corporation | N×M round robin order arbitrating switching matrix system |
| US4924380A (en) * | 1988-06-20 | 1990-05-08 | Modular Computer Systems, Inc. (Florida Corporation) | Dual rotating priority arbitration method for a multiprocessor memory bus |
| US4953081A (en) * | 1988-12-21 | 1990-08-28 | International Business Machines Corporation | Least recently used arbiter with programmable high priority mode and performance monitor |
| US5274822A (en) * | 1990-07-02 | 1993-12-28 | Ncr Corporation | Fast centralized arbitrator |
| EP0464237A1 (en) * | 1990-07-03 | 1992-01-08 | International Business Machines Corporation | Bus arbitration scheme |
| US5280591A (en) * | 1991-07-22 | 1994-01-18 | International Business Machines, Corporation | Centralized backplane bus arbiter for multiprocessor systems |
| US5341052A (en) * | 1991-12-04 | 1994-08-23 | North American Philips Corporation | Arbiter with test capability and associated testing method |
| US5371893A (en) * | 1991-12-27 | 1994-12-06 | International Business Machines Corporation | Look-ahead priority arbitration system and method |
| US5274785A (en) * | 1992-01-15 | 1993-12-28 | Alcatel Network Systems, Inc. | Round robin arbiter circuit apparatus |
-
1995
- 1995-03-27 CA CA002145553A patent/CA2145553C/en not_active Expired - Fee Related
- 1995-03-30 EP EP95104754A patent/EP0675446B1/en not_active Expired - Lifetime
- 1995-03-30 BR BR9501308A patent/BR9501308A/en not_active IP Right Cessation
- 1995-03-30 DE DE69519486T patent/DE69519486T2/en not_active Expired - Fee Related
-
1996
- 1996-07-24 US US08/685,748 patent/US5692136A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| DE69519486T2 (en) | 2001-06-21 |
| US5692136A (en) | 1997-11-25 |
| EP0675446A1 (en) | 1995-10-04 |
| DE69519486D1 (en) | 2001-01-04 |
| EP0675446B1 (en) | 2000-11-29 |
| CA2145553A1 (en) | 1995-10-01 |
| BR9501308A (en) | 1995-11-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5155854A (en) | System for arbitrating communication requests using multi-pass control unit based on availability of system resources | |
| US6671761B2 (en) | Bus system | |
| US5485586A (en) | Queue based arbitration using a FIFO data structure | |
| EP1345125B1 (en) | Dynamic random access memory system with bank conflict avoidance feature | |
| US7574573B2 (en) | Reactive placement controller for interfacing with banked memory storage | |
| US20060010279A1 (en) | Apparatus for use in a computer systems | |
| GB2216368A (en) | Bus arbitration method and apparatus | |
| US5371893A (en) | Look-ahead priority arbitration system and method | |
| US20060026596A1 (en) | Context scheduling | |
| EP0327203B1 (en) | NxM arbitrating non-blocking high bandwidth switch | |
| US6628662B1 (en) | Method and system for multilevel arbitration in a non-blocking crossbar switch | |
| CA2145553C (en) | Multi-processor system including priority arbitrator for arbitrating request issued from processors | |
| EP0118670A2 (en) | Priority system for channel subsystem | |
| JP3641347B2 (en) | Competitive arbitration processing method and information processing apparatus | |
| GB2341771A (en) | Address decoding | |
| JPH07319826A (en) | Multi-processor system | |
| GB2341765A (en) | Bus idle usage | |
| GB2341766A (en) | Bus architecture | |
| GB2341772A (en) | Primary and secondary bus architecture | |
| GB2341767A (en) | Bus arbitration | |
| GB2341768A (en) | Bus arbitration | |
| GB2341769A (en) | Data packet reordering | |
| GB2341699A (en) | Inter-module data transfer | |
| GB2341770A (en) | Modular bus topology | |
| JPH0512219A (en) | Process transferring system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |