CA2150580C - Communication data receiver - Google Patents
Communication data receiver Download PDFInfo
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- CA2150580C CA2150580C CA 2150580 CA2150580A CA2150580C CA 2150580 C CA2150580 C CA 2150580C CA 2150580 CA2150580 CA 2150580 CA 2150580 A CA2150580 A CA 2150580A CA 2150580 C CA2150580 C CA 2150580C
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- communication data
- buffer memory
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
- H04Q11/0478—Provisions for broadband connections
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5614—User Network Interface
- H04L2012/5616—Terminal equipment, e.g. codecs, synch.
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5629—Admission control
- H04L2012/563—Signalling, e.g. protocols, reference model
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
- H04L2012/5681—Buffer or queue management
Abstract
A communication data receiver comprises a counter for generating a write address for a buffer memory for communication cell data according to a write signal directing the communication cell data to be written into the buffer memory, a latch circuit for holding a write address for the start of communication cell data being written, an overflow detection circuit for detecting an overflow of the buffer memory, a circuit for prohibiting communication cell data from being written into the buffer memory according to an overflow detection signal, and a circuit for setting a write address held in the latch circuit as a writing start address for the next received communication cell data in the counter according to the overflow detection signal.
Description
COMNfUNICATION DATA RECEIVER
The present invention relates to a communication data receiver and a buffer control method, in particular to a data receivEar that transfers data from a physical layer via a buffer memory to an ATM layer, and to a buffer control method.
Fig. 12 is a block diagram indicating the configuration of a conventional communication data receiver.
In Fig. 12, a received cell 801 is entered to a cell synchronous circuit 802 which in turn generates a cell synchronizing signal 803 and a cell start signal 804.
Further, the cell synchronous circuit supplies a first-in first-out type: buffe=r memory with write data 805. The cell synchronizing signal 803 and the cell start signal 804 are entered to an AND circuit 806. An output signal 807 from the AND circuit 806 sets an SR flip flop 817.
A write stop signal 811 as the control signal used to stop progr~amminc~ FLFO buffer memory 857, an overflow detection signal 8.26 output upon the detection of an overflow, and a 52-detection signal 814 are entered to an OR
circuit 873. The SR flip flop 817 is reset by an output signal 874 from the OR circuit 873. A write restart signal used to control the restart of programming the FIFO buffer memory 857, and the output signal 807 from the AND circuit 806 may be entered to a set terminal S of the SR flip flop 817.
A write signal 818 used to control the programming of the FIFO buffer memory is output from the SR flip flop 817. A counter 820 is incremented by the write signal 818.
An output signal 821 from the counter 820 is entered to a 52-detection ~,ection. When the counter 820 reads a value of "52", the 52-detection signal 814 is output. The counter 820 is reset by the 52-detection signal 814.
A counter 855 is incremented by the write signal 818 and reset: by t:he overflow detection signal 826. A
The present invention relates to a communication data receiver and a buffer control method, in particular to a data receivEar that transfers data from a physical layer via a buffer memory to an ATM layer, and to a buffer control method.
Fig. 12 is a block diagram indicating the configuration of a conventional communication data receiver.
In Fig. 12, a received cell 801 is entered to a cell synchronous circuit 802 which in turn generates a cell synchronizing signal 803 and a cell start signal 804.
Further, the cell synchronous circuit supplies a first-in first-out type: buffe=r memory with write data 805. The cell synchronizing signal 803 and the cell start signal 804 are entered to an AND circuit 806. An output signal 807 from the AND circuit 806 sets an SR flip flop 817.
A write stop signal 811 as the control signal used to stop progr~amminc~ FLFO buffer memory 857, an overflow detection signal 8.26 output upon the detection of an overflow, and a 52-detection signal 814 are entered to an OR
circuit 873. The SR flip flop 817 is reset by an output signal 874 from the OR circuit 873. A write restart signal used to control the restart of programming the FIFO buffer memory 857, and the output signal 807 from the AND circuit 806 may be entered to a set terminal S of the SR flip flop 817.
A write signal 818 used to control the programming of the FIFO buffer memory is output from the SR flip flop 817. A counter 820 is incremented by the write signal 818.
An output signal 821 from the counter 820 is entered to a 52-detection ~,ection. When the counter 820 reads a value of "52", the 52-detection signal 814 is output. The counter 820 is reset by the 52-detection signal 814.
A counter 855 is incremented by the write signal 818 and reset: by t:he overflow detection signal 826. A
counter 853 is incremented when a read signal 819 is active, and reset by the overflow detection signal 826. Signals from the counters 8F>5 and 853 are output as a write address 856 and a read address 854 for the FIFO buffer memory 857, respectively.
A counter 823 is incremented by the write signal 818, decrement:ed by the read signal 819, and reset by the overflow detection signal 826. An overflow detection section 825 generates the overflow detection signal 826 in response to an output signal 824 from the counter 823. In the conventional data receiver shown in Fig. 12, each of the flip flop and counters is operated by a system clock clk.
Fig. 13 provides a timing chart helping understand the normal operation of the conventional data receiver.
Fig. 14 provides a. timing chart helping understand the abnormal operation of such data receiver, i.e. an overflow occurring in the FIFO buffer memory 857.
Fig~~. 12, 13 and 15 are used to explain the normal operation of the conventional data receiver. Received data 801 is composed of ATM cells, each of which comprises 53 bytes of data, 5 bytes of a header section and 48 bytes of payload section, as shown in Fig. 15.
The cell synchronous circuit 802 performs CRC
operation on five bytes of received data 801. If the result is "O", the cell synchronous circuit regards the five bytes as the header of the ATM cell. Further, the cell synchronizing signal 803, the cell start signal 804, and write data 805 are generated in the timing shown in Fig. 13.
The cell synchronizing signal can also be generated when a series of cel:Ls of the cell start signal 804 is detected.
When the cell synchronizing signal 803 and the cell start signal 804 become active, the output signal 807 from the AND
circuit 806 becomes active, with the SR flip flop 817 set and the write signa7_ 818 becoming active.
The counter 820 is incremented by a rise in the system clock c:lk whcan the write signal 818 is active. The counter 820 is. reset: by the 52-detection signal 814 when it reads a count value of "52" . The 52-detection signal 814 resets the SR flip flop 817 via the OR circuit 873. When the FIFO buffE~r memory 857 is programmed with 53 bytes of write data 805, the 52-detection signal 814 attempts to inactivate the: writs. signal 818.
In t:he example illustrated in Fig. 13, the cell start signal X304 becomes active in the same timing as the 52-detection aignal 814. Further, the output signal 807 from the AND circuit 806 providing the logical product of the cell start. signal 804 and the cell synchronizing signal 803 becomes active. In addition, as the SR flip flop 817 is set initially, the write signal 818 is held active (high in Fig. 13). This is because a series of ATM cells (input data 801) is enters:d.
The write address 856 given from the counter 855 is incremented by a rise in the system clock clk when the write signal 818 is active. The read address 854 given from the counter 853 is incremented by a rise in the system clock clk when the read signal 819 is active.
A counter 823 controls the number of bytes of data stored in the FIFO buffer memory 857. The counter 823 is incremented by a rise in the system clock clk when the write signal is active, and decremented by a rise in the system clock clk when the head signal 819 is active.
Then, Figures 12 and 14 are used to explain the abnormal operation of the conventional data receiver, i.e.
an overflow occurring in the FIFO buffer memory 857. This explanation assumes that the size of the FIFO buffer memory 857 is four cells (_= 212 bytes) and that data is written to and read from the FIFO buffer memory 857 as if the data receiver were operated normally. When the counter 823 reads a value of "212" (indicating that the FIFO buffer memory 857 is filled) , the overflow detection section 825 generates the overflow detecaion signal 826 as soon as the write signal 818 becomes acaive.
A counter 823 is incremented by the write signal 818, decrement:ed by the read signal 819, and reset by the overflow detection signal 826. An overflow detection section 825 generates the overflow detection signal 826 in response to an output signal 824 from the counter 823. In the conventional data receiver shown in Fig. 12, each of the flip flop and counters is operated by a system clock clk.
Fig. 13 provides a timing chart helping understand the normal operation of the conventional data receiver.
Fig. 14 provides a. timing chart helping understand the abnormal operation of such data receiver, i.e. an overflow occurring in the FIFO buffer memory 857.
Fig~~. 12, 13 and 15 are used to explain the normal operation of the conventional data receiver. Received data 801 is composed of ATM cells, each of which comprises 53 bytes of data, 5 bytes of a header section and 48 bytes of payload section, as shown in Fig. 15.
The cell synchronous circuit 802 performs CRC
operation on five bytes of received data 801. If the result is "O", the cell synchronous circuit regards the five bytes as the header of the ATM cell. Further, the cell synchronizing signal 803, the cell start signal 804, and write data 805 are generated in the timing shown in Fig. 13.
The cell synchronizing signal can also be generated when a series of cel:Ls of the cell start signal 804 is detected.
When the cell synchronizing signal 803 and the cell start signal 804 become active, the output signal 807 from the AND
circuit 806 becomes active, with the SR flip flop 817 set and the write signa7_ 818 becoming active.
The counter 820 is incremented by a rise in the system clock c:lk whcan the write signal 818 is active. The counter 820 is. reset: by the 52-detection signal 814 when it reads a count value of "52" . The 52-detection signal 814 resets the SR flip flop 817 via the OR circuit 873. When the FIFO buffE~r memory 857 is programmed with 53 bytes of write data 805, the 52-detection signal 814 attempts to inactivate the: writs. signal 818.
In t:he example illustrated in Fig. 13, the cell start signal X304 becomes active in the same timing as the 52-detection aignal 814. Further, the output signal 807 from the AND circuit 806 providing the logical product of the cell start. signal 804 and the cell synchronizing signal 803 becomes active. In addition, as the SR flip flop 817 is set initially, the write signal 818 is held active (high in Fig. 13). This is because a series of ATM cells (input data 801) is enters:d.
The write address 856 given from the counter 855 is incremented by a rise in the system clock clk when the write signal 818 is active. The read address 854 given from the counter 853 is incremented by a rise in the system clock clk when the read signal 819 is active.
A counter 823 controls the number of bytes of data stored in the FIFO buffer memory 857. The counter 823 is incremented by a rise in the system clock clk when the write signal is active, and decremented by a rise in the system clock clk when the head signal 819 is active.
Then, Figures 12 and 14 are used to explain the abnormal operation of the conventional data receiver, i.e.
an overflow occurring in the FIFO buffer memory 857. This explanation assumes that the size of the FIFO buffer memory 857 is four cells (_= 212 bytes) and that data is written to and read from the FIFO buffer memory 857 as if the data receiver were operated normally. When the counter 823 reads a value of "212" (indicating that the FIFO buffer memory 857 is filled) , the overflow detection section 825 generates the overflow detecaion signal 826 as soon as the write signal 818 becomes acaive.
The generation of the overflow detection signal 826 is regarded as the occurrence of a fatal error, with the counters 853, 855 and 823 and the SR flip flop 817 reset.
Thus, the write operation is stopped and the circuit is initialized. Then, a new ATM cell whose header has been detected restarts to be written into the FIFO buffer memory 857, and up to four cells of data are discarded.
The above conventional data receiver is such that, when triggered off by the occurrence of an overflow in the FIFO buffer memory 857, the circuit used to control the buffer memory including write and read addresses is reset.
This means that all the data corresponding to the size of the FIFO buffer memory 857 is discarded. The result is that high-order pr~~cessing requires the resending of a large amount of data. Thus, data transfer is adversely affected significantly.
The problem consists in the fact that new input data is discarded until the release of a detected overflow.
Hence, significant data may be discarded and insignificant data may not be di:~carded. For example, Japanese Patent Application Laid-open No. 242348/1992 comes up with countermeasures for figuring out the problem. Such countermeasures are characterized by the configuration shown in Fig. 16, ~~rovidi.ng a process for discarding excessive input data for paicket communication and other highly efficient com~r~unicat:ion.
The feature of the means revealed in Fig. 16 consists in th.e detection of the arrival of input data by a data arrival detection circuit 981. Input data that cannot be output by the next overloaded process is stored in a buffer memory 982. A loss table 986 developed by algorithm composed of :input ports, past discarded data and test patterns provides against an overflow of the buffer memory 982. The loss table is used by a loss controller 985 to control a writing counter (WCTR) 983 and a reading counter (RCTR) 984. This control allows the discard of less significant data in the buffer memory 982 and the accumulation of part discards for each input port 987.
Thus, data in an input port that has undergone less discard is discarded first.
Thus, the write operation is stopped and the circuit is initialized. Then, a new ATM cell whose header has been detected restarts to be written into the FIFO buffer memory 857, and up to four cells of data are discarded.
The above conventional data receiver is such that, when triggered off by the occurrence of an overflow in the FIFO buffer memory 857, the circuit used to control the buffer memory including write and read addresses is reset.
This means that all the data corresponding to the size of the FIFO buffer memory 857 is discarded. The result is that high-order pr~~cessing requires the resending of a large amount of data. Thus, data transfer is adversely affected significantly.
The problem consists in the fact that new input data is discarded until the release of a detected overflow.
Hence, significant data may be discarded and insignificant data may not be di:~carded. For example, Japanese Patent Application Laid-open No. 242348/1992 comes up with countermeasures for figuring out the problem. Such countermeasures are characterized by the configuration shown in Fig. 16, ~~rovidi.ng a process for discarding excessive input data for paicket communication and other highly efficient com~r~unicat:ion.
The feature of the means revealed in Fig. 16 consists in th.e detection of the arrival of input data by a data arrival detection circuit 981. Input data that cannot be output by the next overloaded process is stored in a buffer memory 982. A loss table 986 developed by algorithm composed of :input ports, past discarded data and test patterns provides against an overflow of the buffer memory 982. The loss table is used by a loss controller 985 to control a writing counter (WCTR) 983 and a reading counter (RCTR) 984. This control allows the discard of less significant data in the buffer memory 982 and the accumulation of part discards for each input port 987.
Thus, data in an input port that has undergone less discard is discarded first.
5 However, t:he data discard process shown in Fig. 16 cannot judge the importance of data before transferring data to the ATM layer processor.
Further, Japanese Laid-open Patent Application No.
58646/1992 comes up with a new buffer control means. The buffer contro:L means adds the pre-counted data length of received packed data for storage into a transmission buffer memory and uses such data length to update a reading address during an oveoflow. The addition of data indicating data length required a corresponding buffer memory, however.
It i.s an object of the present invention to solve the above problems.
It is anoither objective of the present invention to minimize the discard of received data during an overflow of a buffer mE~mory :for transferring the received data from a physical layer processor to an ATM layer processor in ATM
communication.
It is a further objective of the present invention to provide a communication data receiver and a buffer control method. which minimizes the effects of resending.
According to one aspect of the invention, a communication data receiver stores communication data received from a communication layer into a buffer memory and transfers said communication data to the other communication layer. The communication data receiver comprises in a primary form:
a cell synchronous means for generating a synchronizing signal and a start detection signal for said received communication data;
a write signal generation means for generating a write signal that directs said communication data to be l' .
Further, Japanese Laid-open Patent Application No.
58646/1992 comes up with a new buffer control means. The buffer contro:L means adds the pre-counted data length of received packed data for storage into a transmission buffer memory and uses such data length to update a reading address during an oveoflow. The addition of data indicating data length required a corresponding buffer memory, however.
It i.s an object of the present invention to solve the above problems.
It is anoither objective of the present invention to minimize the discard of received data during an overflow of a buffer mE~mory :for transferring the received data from a physical layer processor to an ATM layer processor in ATM
communication.
It is a further objective of the present invention to provide a communication data receiver and a buffer control method. which minimizes the effects of resending.
According to one aspect of the invention, a communication data receiver stores communication data received from a communication layer into a buffer memory and transfers said communication data to the other communication layer. The communication data receiver comprises in a primary form:
a cell synchronous means for generating a synchronizing signal and a start detection signal for said received communication data;
a write signal generation means for generating a write signal that directs said communication data to be l' .
written into said buffer memory according to said synchronizing signal and said start detection signal;
a mEaans for holding a write address of initial data of said communication data being written;
a mE:ans for detecting an overflow of said buffer memory;
a means for inactivating said write signal according to am overflow detection signal; and, a means for setting the write address held in said write address holding means as a writing start address for communication data received next according to said overflow detection signal.
The communication data receiver may further comprise:
a write address generation means for generating the write address in said buffer memory for said communication data according to said write signal output from said write signal generation means; and, a means for setting the write address held in said write address holding means at said write address generation means as the 'writing start address for said communication data received next according to said overflow detection.
Alternatively, the communication data receiver may further comprise:
a write address generation means for generating the write address in said buffer memory for said communication data according to said write signal output from said write signal generation means;
wherein said write address holding means includes a latch circuit for holding the write address of initial data of said communication data output from said write address generation 'means according to the start detection signal of said communication data delayed by one clock period;
said write address generation means loading said write address held in said latch circuit according to said overf low detecaion :signal .
In the alternative construction, the communication data receiver may further comprise:
a flip-flop for receiving a start detection signal of said communication data and outputting said start detection signal de:Layed by the one clock period;
wherein said latch circuit holds the write address for the initial data of said communication data output from said write address generation means by said start detection signal delayed by a clock output from said flip-flop.
The primary form of the communication data receiver may further- comprise:
a write address generation means for generating the write address in said buffer memory for said communication data according to said write signal output from said write signal generation means; and, a read address generation means for generating a read address for use in reading data from said buffer memory;
saidl overflow detection means including:
an a.ddres:~ judgment means for judging whether the value of said writes address is identical to the value of said read address;
a first flag for inverting a value every time said write address checks a set of addresses of said buffer memory;
a second flag for inverting a value every time said read address checks a set of addresses of said buffer memory;
a compari:~on means for comparing said first flag with said second flag; and, a means for outputting an overflow signal indicating an overf:Low of said buffer memory by entering a signal signifying that an address coincidence signal output from said address judgment means is not identical to said first and second flags output from said comparison means.
The primary form of the communication data receiver may alternatively further comprise:
a write address generation means for generating a write address on said buffer memory for said communication data according to said write signal output from said write signal generation means; and, a read address generation means for generating a read address for use in reading data from said buffer memory;
said overt=low detection means including:
a subtraction means for calculating the difference between said write address and said read address;
a zEaro detection means for judging whether the value calculated by said subtraction means is zero;
a first flag for inverting a value every time said write address checks a set of addresses of said buffer memory;
a ss=cord flag for inverting a value every time said read address checks a set of addresses of said buffer memory;
a cc>mpari:~on means for comparing said first flag with said second flag; and, a means for outputting an overflow signal indicating an overf:Low of said buffer memory by entering a signal signif~~ing that a zero detection signal output from said zero detection means is not identical to said first and second flags output from said comparison means.
In 'the primary form of the communication data receiver, the write signal generation means may be set by the logical pooduct of said synchronizing signal and said start detection signal, and include a flip-flop for outputting the: write signal for said buffer memory; and, said flip-flop may be reset by the overflow detection signal output from said overflow detection means to activate said wr_Lte signal.
According to another aspect of the invention, a second primary form of said communication data receiver comprises:
a cell synchronous means for generating a synchronizing signal and a start detection signal for said received communication data;
a white signal generation means for generating a write signal directing said communication data to be written into said buffer memory according to said synchronizing signal and said start detection signal;
an upper .address generation means for generating certain upper bits of a write address on said buffer memory for said communication data according to said write signal output from said write signal generation means;
a lower address generation means for generating certain lower bits of the write address on said buffer memory for sa~~d communication data according to said write signal output from raid write signal generation means;
a means for detecting an overflow of said buffer memory;
a means for inactivating said write signal according to am oven°flow detection signal; and, a means for setting an address lower than the current address at said lower address generation means according to said overflow detection signal and for setting a write addre:~s composed of an upper address generated by said upper address generation means and a lower address generated by said lower address generation means as a writing start addreas for said communication data received next.
In the second primary form of the communication data receiver,, the lower address generation means may be reset to zero according to said overflow detection signal, whereby a write address composed of an upper address generated by said upper address generation means and a lower address generated by said lower address generation means is set as the writing start address for said communication cell 5 data received next.
In i:he second primary form of the communication data receiver, it may further comprise:
a f_Lrst counter constituting said lower address generation means;
10 said first counter incremented by said read signal;
a second counter constituting said upper address generation means; and, a means for checking a value read by said first counter and for re:~etting said first counter to zero and incrementing :>aid second counter every time the read value coincides with the 7Length of said received data.
The communication data receiver may still further comprise:
a read address generation means for generating a read address for use in reading data from said buffer memory; and, a third counter incremented by said write signal and decremente:d by raid read signal;
wherein said overflow detection means outputting an overflow detection signal when the value read by said third counter coincides with the maximum address of said buffer memory.
The third counter may set the value as the result of subtracting an .address value generated by said lower address generation means from the read value coinciding with said maximum addreas value as a new count start value according to said overflow detection signal.
In t:he second primary form of the communication data receiver, they write signal generation means may comprise a flip-flap set by the logical product of said synchronizing signal and said start detection signal to output the write signal for said buffer memory; and, said flip-flop is reset by an overflow detection signal output. from said overflow detection means to inactivate said writ=a signal.
According to a still further aspect of the invention, a third ;primary form of said communication data receiver comprises:
a mE~ans for detecting an overflow of said buffer memory;
a mEaans for prohibiting said communication data from being written into said buffer memory according to said overflow detecaion; and, a mE:ans for setting a write address lower than a write address for said buffer memory being programmed as a writing start addreas for said communication data received next according to said overflow detection.
Other objects, features and advantages of the present invention will become clear from the detailed description given herebelow.
The present invention will be understood more fully from the detailed description given herebelow and from the accompanying drawings of the preferred embodiment of the invention, which, however, should not be taken to be limitative to the invention, but are for explanation and understanding only.
In the drawings Fig. 1 provides a block diagram that illustrates the configural~ion of the data receiver based on a first preferred embodiment; of the present invention;
Fig. 2 provides a block diagram that illustrates the typical configuration of an overflow detection section based on Fig. 1;
Fig. 3 provides a timing chart that shows the normal operation of the first preferred embodiment of the present invention;
Fig. 4 provides a timing chart that shows the occurrence of an overflow in the buffer memory used in the first preferred embodiment of the present invention;
Fig. 5 provides a timing chart that illustrates the operation of the overflow detection section in the first preferred embodiment: of the present invention;
Fig. 6A provides an illustration which shows the typical operation o:E write and read addresses and the flag of the buffer memory used in the first preferred embodiment of the present: invention;
Fig. 6B provides an illustration which shows the typical operation o:E write and read addresses and the flag of the buffer memory used in the first preferred embodiment of the present. invention;
Fig. 7A provides an illustration which shows a state of the FIFO buffer memory used in the first preferred embodiment of the present invention when it overflows;
Fig. 7B provides an illustration which shows a state of the FIFO buffer memory used in the first preferred embodiment of the present invention after it has overflowed;
Fig. 8 provides a block diagram that illustrates the configurai~ion of the data receiver based on a second preferred embodiment: of the present invention;
Fig. 9 provides a timing chart that illustrates the normal operation of the second preferred embodiment of the present invention;
Fig. 10 provides a timing chart that shows the occurrence of an ovE~rflow in the buffer memory used in the second preferred embodiment of the present invention;
Fig. 11A provides an illustration which shows a state of the FIFO buffer memory used in the second preferred embodiment of the present invention when it overflows;
Fig. 11B provides an illustration which shows a state of the FIFO buffer memory used in the second preferred embodiment of the present invention after it overflowed;
Fig. 12 provides a block diagram that illustrates the typical configuration of the conventional communication data receiver;
Fig. 13 provides a timing chart that illustrates the normal operation of the conventional communication data receiver shown in Fig. 12;
Fig. 14 provides a timing chart that illustrates the abnormal operation of the conventional communication data receiver shown in Fig. 12;
Fig. 15 shows the configuration of an ATM cell;
Fig. 16 provides a block diagram that illustrates the method o:E disc:arding input data overloaded in the conventional communication data receiver.
Given below is a detailed description of the preferred embodiments of the present invention based on the attached drawings.
Fig. 1 provides the block diagram that illustrates the configuration o:E the communication data receiver based on the first preferred embodiment of the present invention.
The communication data receiver based on the preferred embodiment comprise; a cell synchronous circuit 102, and AND
circuit 106, a 52-detection section 113, an OR circuit 115, an SR flip flop 11'7, counters 120, 127 and 129, a latch circuit 131, a FIFO buffer memory 133, a flip flop 158, and an overflow deaection device 159.
Received cell data S1 is entered to the cell synchronous circuit 102, with a cell synchronizing signal S2 and a cell start signal S3 generated. Further, the FIFO
(first-in fir;~t-out) buffer memory 133 is supplied with write data S4.
The cell synchronizing signal S2 and the cell start signal S3 are entered to the AND circuit 106. An output signal S5 from the AND circuit sets the SR flip flop 117. The ORed output of (i) a write restart signal for controlling t:he re;atart of programming the FIFO buffer memory 133 and (ii) the output S5 from the AND circuit may be entered to a set terminal S of the SR flip flop 117.
A write :atop signal S6, an overflow detection signal S7, and a 52~-detection signal S8 are entered to the OR circuit 115. The SR flip flop 117 is reset by an OR
signal S9 output from the OR circuit 115.
The SR flip flop 117 outputs a write signal S10 as the control signal of programming the FIFO buffer memory 133. The counter 120 is incremented by the write signal S10. An output signal S12 from the counter 120 is entered to the 52-detection section 113. The 52-detection section 113 outputs th.e 52-detection signal S8 when the counter 120 reads a value of "52". The counter 120 is reset by the 52-detection signal S1E~ .
The counter 129 is incremented by the write signal S10. The counter 129 is loaded with hold data S15 as output from the latch. circuit 131 by the overflow detection signal S7.
The cell start signal S3 is entered from the flip flop 158 to the latch circuit 131 with a delay of one system clock clk. Tree cell start signal S3 holds a write address S14 in the latch cir-cuit 131.
The counter 127 is incremented by a read signal S11. Output from the counter 129 becomes the write address of the FIFO buffer memory 133. Output from the counter 127 becomes a read. address S13 of the same.
The write address S14, the read address S13, and the write signal S10 are entered to the overflow detection device 159. Upon the detection of an overflow of the FIFO
buffer memory 133, the overflow detection device 159 outputs the overflow detecaion signal S7. In the preferred embodiment, each of the flip flops and counters is operated by the system clock clk.
Fig. 2 provides a block diagram that illustrates the typical configuration of the overflow detection device 159 shown in Fig. 1. As shown therein, the overflow .,.,,,~
detection device 1-'i9 comprises a subtracter 160, a zero detector 164, AND circuits 166 and 168, flags 169 and 170, and a comparat.or 171.
In hig. 2., the write address S14 and the read 5 address S13 are entered to the subtracter 160 which in turn issues output S20 as the result of the subtraction of the write address S14 and the read address S13. According to the output S20, the zero detector 164 generates an output signal S21 that indicates whether the result of subtraction by the 10 subtracter 16C~ is zero.
Further, i=he flag 169 corresponding to the write address S14 amd the flag 170 corresponding to the read address S13 are generated. The comparator 171 compares the flag 169 and the flag 170 with each other, generating a 15 resulting signal 522. If the two input flags 169 and 170 coincide with each other, the comparator 171 outputs a value of "O" as the sign<~1 S22. The AND circuit 166 ANDS the output S22 from the comparator 171 and the output S21 from the zero detector 1E~4. The AND circuit 168 ANDS output S23 from the AND circuit: 166 and the write signal S10, with the overflow detecaion :signal S7 output.
Fig. 3 provides a timing chart that shows the normal operation of the first preferred embodiment of the present inveni:ion. Fig. 4 provides a timing chart that shows the abnormal operation of the first preferred embodiment of the present invention. The abnormal operation means the occurrence of an overflow in the buffer memory.
Fig. 5 provides a timing chart that illustrates the operation of t:he overflow detection device 159 used in the first preferred embodiment of the present invention.
Fig. 6 shows the operation of the write and read addresses and the f:Lags of the FIFO buffer memory 133 used in the preferred embodiment of the present invention. Fig.
a mEaans for holding a write address of initial data of said communication data being written;
a mE:ans for detecting an overflow of said buffer memory;
a means for inactivating said write signal according to am overflow detection signal; and, a means for setting the write address held in said write address holding means as a writing start address for communication data received next according to said overflow detection signal.
The communication data receiver may further comprise:
a write address generation means for generating the write address in said buffer memory for said communication data according to said write signal output from said write signal generation means; and, a means for setting the write address held in said write address holding means at said write address generation means as the 'writing start address for said communication data received next according to said overflow detection.
Alternatively, the communication data receiver may further comprise:
a write address generation means for generating the write address in said buffer memory for said communication data according to said write signal output from said write signal generation means;
wherein said write address holding means includes a latch circuit for holding the write address of initial data of said communication data output from said write address generation 'means according to the start detection signal of said communication data delayed by one clock period;
said write address generation means loading said write address held in said latch circuit according to said overf low detecaion :signal .
In the alternative construction, the communication data receiver may further comprise:
a flip-flop for receiving a start detection signal of said communication data and outputting said start detection signal de:Layed by the one clock period;
wherein said latch circuit holds the write address for the initial data of said communication data output from said write address generation means by said start detection signal delayed by a clock output from said flip-flop.
The primary form of the communication data receiver may further- comprise:
a write address generation means for generating the write address in said buffer memory for said communication data according to said write signal output from said write signal generation means; and, a read address generation means for generating a read address for use in reading data from said buffer memory;
saidl overflow detection means including:
an a.ddres:~ judgment means for judging whether the value of said writes address is identical to the value of said read address;
a first flag for inverting a value every time said write address checks a set of addresses of said buffer memory;
a second flag for inverting a value every time said read address checks a set of addresses of said buffer memory;
a compari:~on means for comparing said first flag with said second flag; and, a means for outputting an overflow signal indicating an overf:Low of said buffer memory by entering a signal signifying that an address coincidence signal output from said address judgment means is not identical to said first and second flags output from said comparison means.
The primary form of the communication data receiver may alternatively further comprise:
a write address generation means for generating a write address on said buffer memory for said communication data according to said write signal output from said write signal generation means; and, a read address generation means for generating a read address for use in reading data from said buffer memory;
said overt=low detection means including:
a subtraction means for calculating the difference between said write address and said read address;
a zEaro detection means for judging whether the value calculated by said subtraction means is zero;
a first flag for inverting a value every time said write address checks a set of addresses of said buffer memory;
a ss=cord flag for inverting a value every time said read address checks a set of addresses of said buffer memory;
a cc>mpari:~on means for comparing said first flag with said second flag; and, a means for outputting an overflow signal indicating an overf:Low of said buffer memory by entering a signal signif~~ing that a zero detection signal output from said zero detection means is not identical to said first and second flags output from said comparison means.
In 'the primary form of the communication data receiver, the write signal generation means may be set by the logical pooduct of said synchronizing signal and said start detection signal, and include a flip-flop for outputting the: write signal for said buffer memory; and, said flip-flop may be reset by the overflow detection signal output from said overflow detection means to activate said wr_Lte signal.
According to another aspect of the invention, a second primary form of said communication data receiver comprises:
a cell synchronous means for generating a synchronizing signal and a start detection signal for said received communication data;
a white signal generation means for generating a write signal directing said communication data to be written into said buffer memory according to said synchronizing signal and said start detection signal;
an upper .address generation means for generating certain upper bits of a write address on said buffer memory for said communication data according to said write signal output from said write signal generation means;
a lower address generation means for generating certain lower bits of the write address on said buffer memory for sa~~d communication data according to said write signal output from raid write signal generation means;
a means for detecting an overflow of said buffer memory;
a means for inactivating said write signal according to am oven°flow detection signal; and, a means for setting an address lower than the current address at said lower address generation means according to said overflow detection signal and for setting a write addre:~s composed of an upper address generated by said upper address generation means and a lower address generated by said lower address generation means as a writing start addreas for said communication data received next.
In the second primary form of the communication data receiver,, the lower address generation means may be reset to zero according to said overflow detection signal, whereby a write address composed of an upper address generated by said upper address generation means and a lower address generated by said lower address generation means is set as the writing start address for said communication cell 5 data received next.
In i:he second primary form of the communication data receiver, it may further comprise:
a f_Lrst counter constituting said lower address generation means;
10 said first counter incremented by said read signal;
a second counter constituting said upper address generation means; and, a means for checking a value read by said first counter and for re:~etting said first counter to zero and incrementing :>aid second counter every time the read value coincides with the 7Length of said received data.
The communication data receiver may still further comprise:
a read address generation means for generating a read address for use in reading data from said buffer memory; and, a third counter incremented by said write signal and decremente:d by raid read signal;
wherein said overflow detection means outputting an overflow detection signal when the value read by said third counter coincides with the maximum address of said buffer memory.
The third counter may set the value as the result of subtracting an .address value generated by said lower address generation means from the read value coinciding with said maximum addreas value as a new count start value according to said overflow detection signal.
In t:he second primary form of the communication data receiver, they write signal generation means may comprise a flip-flap set by the logical product of said synchronizing signal and said start detection signal to output the write signal for said buffer memory; and, said flip-flop is reset by an overflow detection signal output. from said overflow detection means to inactivate said writ=a signal.
According to a still further aspect of the invention, a third ;primary form of said communication data receiver comprises:
a mE~ans for detecting an overflow of said buffer memory;
a mEaans for prohibiting said communication data from being written into said buffer memory according to said overflow detecaion; and, a mE:ans for setting a write address lower than a write address for said buffer memory being programmed as a writing start addreas for said communication data received next according to said overflow detection.
Other objects, features and advantages of the present invention will become clear from the detailed description given herebelow.
The present invention will be understood more fully from the detailed description given herebelow and from the accompanying drawings of the preferred embodiment of the invention, which, however, should not be taken to be limitative to the invention, but are for explanation and understanding only.
In the drawings Fig. 1 provides a block diagram that illustrates the configural~ion of the data receiver based on a first preferred embodiment; of the present invention;
Fig. 2 provides a block diagram that illustrates the typical configuration of an overflow detection section based on Fig. 1;
Fig. 3 provides a timing chart that shows the normal operation of the first preferred embodiment of the present invention;
Fig. 4 provides a timing chart that shows the occurrence of an overflow in the buffer memory used in the first preferred embodiment of the present invention;
Fig. 5 provides a timing chart that illustrates the operation of the overflow detection section in the first preferred embodiment: of the present invention;
Fig. 6A provides an illustration which shows the typical operation o:E write and read addresses and the flag of the buffer memory used in the first preferred embodiment of the present: invention;
Fig. 6B provides an illustration which shows the typical operation o:E write and read addresses and the flag of the buffer memory used in the first preferred embodiment of the present. invention;
Fig. 7A provides an illustration which shows a state of the FIFO buffer memory used in the first preferred embodiment of the present invention when it overflows;
Fig. 7B provides an illustration which shows a state of the FIFO buffer memory used in the first preferred embodiment of the present invention after it has overflowed;
Fig. 8 provides a block diagram that illustrates the configurai~ion of the data receiver based on a second preferred embodiment: of the present invention;
Fig. 9 provides a timing chart that illustrates the normal operation of the second preferred embodiment of the present invention;
Fig. 10 provides a timing chart that shows the occurrence of an ovE~rflow in the buffer memory used in the second preferred embodiment of the present invention;
Fig. 11A provides an illustration which shows a state of the FIFO buffer memory used in the second preferred embodiment of the present invention when it overflows;
Fig. 11B provides an illustration which shows a state of the FIFO buffer memory used in the second preferred embodiment of the present invention after it overflowed;
Fig. 12 provides a block diagram that illustrates the typical configuration of the conventional communication data receiver;
Fig. 13 provides a timing chart that illustrates the normal operation of the conventional communication data receiver shown in Fig. 12;
Fig. 14 provides a timing chart that illustrates the abnormal operation of the conventional communication data receiver shown in Fig. 12;
Fig. 15 shows the configuration of an ATM cell;
Fig. 16 provides a block diagram that illustrates the method o:E disc:arding input data overloaded in the conventional communication data receiver.
Given below is a detailed description of the preferred embodiments of the present invention based on the attached drawings.
Fig. 1 provides the block diagram that illustrates the configuration o:E the communication data receiver based on the first preferred embodiment of the present invention.
The communication data receiver based on the preferred embodiment comprise; a cell synchronous circuit 102, and AND
circuit 106, a 52-detection section 113, an OR circuit 115, an SR flip flop 11'7, counters 120, 127 and 129, a latch circuit 131, a FIFO buffer memory 133, a flip flop 158, and an overflow deaection device 159.
Received cell data S1 is entered to the cell synchronous circuit 102, with a cell synchronizing signal S2 and a cell start signal S3 generated. Further, the FIFO
(first-in fir;~t-out) buffer memory 133 is supplied with write data S4.
The cell synchronizing signal S2 and the cell start signal S3 are entered to the AND circuit 106. An output signal S5 from the AND circuit sets the SR flip flop 117. The ORed output of (i) a write restart signal for controlling t:he re;atart of programming the FIFO buffer memory 133 and (ii) the output S5 from the AND circuit may be entered to a set terminal S of the SR flip flop 117.
A write :atop signal S6, an overflow detection signal S7, and a 52~-detection signal S8 are entered to the OR circuit 115. The SR flip flop 117 is reset by an OR
signal S9 output from the OR circuit 115.
The SR flip flop 117 outputs a write signal S10 as the control signal of programming the FIFO buffer memory 133. The counter 120 is incremented by the write signal S10. An output signal S12 from the counter 120 is entered to the 52-detection section 113. The 52-detection section 113 outputs th.e 52-detection signal S8 when the counter 120 reads a value of "52". The counter 120 is reset by the 52-detection signal S1E~ .
The counter 129 is incremented by the write signal S10. The counter 129 is loaded with hold data S15 as output from the latch. circuit 131 by the overflow detection signal S7.
The cell start signal S3 is entered from the flip flop 158 to the latch circuit 131 with a delay of one system clock clk. Tree cell start signal S3 holds a write address S14 in the latch cir-cuit 131.
The counter 127 is incremented by a read signal S11. Output from the counter 129 becomes the write address of the FIFO buffer memory 133. Output from the counter 127 becomes a read. address S13 of the same.
The write address S14, the read address S13, and the write signal S10 are entered to the overflow detection device 159. Upon the detection of an overflow of the FIFO
buffer memory 133, the overflow detection device 159 outputs the overflow detecaion signal S7. In the preferred embodiment, each of the flip flops and counters is operated by the system clock clk.
Fig. 2 provides a block diagram that illustrates the typical configuration of the overflow detection device 159 shown in Fig. 1. As shown therein, the overflow .,.,,,~
detection device 1-'i9 comprises a subtracter 160, a zero detector 164, AND circuits 166 and 168, flags 169 and 170, and a comparat.or 171.
In hig. 2., the write address S14 and the read 5 address S13 are entered to the subtracter 160 which in turn issues output S20 as the result of the subtraction of the write address S14 and the read address S13. According to the output S20, the zero detector 164 generates an output signal S21 that indicates whether the result of subtraction by the 10 subtracter 16C~ is zero.
Further, i=he flag 169 corresponding to the write address S14 amd the flag 170 corresponding to the read address S13 are generated. The comparator 171 compares the flag 169 and the flag 170 with each other, generating a 15 resulting signal 522. If the two input flags 169 and 170 coincide with each other, the comparator 171 outputs a value of "O" as the sign<~1 S22. The AND circuit 166 ANDS the output S22 from the comparator 171 and the output S21 from the zero detector 1E~4. The AND circuit 168 ANDS output S23 from the AND circuit: 166 and the write signal S10, with the overflow detecaion :signal S7 output.
Fig. 3 provides a timing chart that shows the normal operation of the first preferred embodiment of the present inveni:ion. Fig. 4 provides a timing chart that shows the abnormal operation of the first preferred embodiment of the present invention. The abnormal operation means the occurrence of an overflow in the buffer memory.
Fig. 5 provides a timing chart that illustrates the operation of t:he overflow detection device 159 used in the first preferred embodiment of the present invention.
Fig. 6 shows the operation of the write and read addresses and the f:Lags of the FIFO buffer memory 133 used in the preferred embodiment of the present invention. Fig.
7 provides an illustration that shows the state of the FIFO
buffer memory when it overflows.
First, Fic~s. 1, 3 and 15 are used to explain the normal operat_Lon of the data receiver based on the first preferred embodiment: of the present invention. The received data S1 is composed of ATM cells. As shown in Fig. 15, the ATM cell is composed of a total of 53 bytes, 5 bytes of a header section and X68 bytes of payload section.
The cell synchronous circuit 102 applies CRC
operation to five bytes of received data S1. If the result of the CRC operation is "O", the cell synchronous circuit 102 identifies; the five bytes as five bytes of an ATM cell header. The ~~ell synchronizing signal S2, the cell start signal S3, and the write data S4 are generated in the timing shown in Fig. 3. The cell synchronizing signal S2 can also be generated when a series of cells of the cell start signal is detected.
When. the cell synchronizing signal S2 and the cell start signal S3 become active, the output signal S5 from the OR circuit 105 becomes active, with the SR f lip f lop 117 set. Thus, th.e write signal S10 becomes active.
With. the write signal S10 active, the counter 120 is incremented by a rise in the system clock clk. The counter 120 i~; resei~ by the 52-detection signal S8 when it reads a value ~of "52". The 52-detection signal S8 is output via the OR circuit 115 as the output signal S9, which in turn resets the SR flip flop 117. When 53 bytes of the write data S~~ are written, the 52-detection signal S9 attempts to inactivate the write signal S10.
In t:he preferred embodiment shown in Fig. 3, the cell start signal S3 becomes active in the same timing as the 52-detection signal S8. As the output signal S5 as the result of the logical product of the cell start signal S3 and the cell :synchronizing signal S2 is active and the SR
flip flop 117 is set initially, the write signal S10 is held active. This: is because the received cell data S1 is entered consecutively. As shown in Fig. 1, the write signal S10 is reset ~~y the write stop signal S6 as well.
The write address S14 of the FIFO buffer memory 133 is given by the counter 129. The write address S14 is incremented by the counter 129 on a rise in the system clock clk when the write ;signal S10 is active. The read address S13 is given by the counter 127. The read address S13 is incremented by the counter 127 on a rise in the system clock clk when the read signal S11 is active.
The overflow detection device 159 detects an overflow of the FIFO buffer memory by the write address S14, the read addreas S13 and the write signal 510.
The following explains the operation of the overflow detection device 159. The subtraction of the write address S14 and thf~ read address S13 is executed in the subtracter 1E~0 (F:igure Z). Fig. 5 illustrates the relationship between the write address S14, the read address S13 and the output ~~20 of the subtracter. In the preferred embodiment shown in Fig. 5, the subtracter 160 subtracts the read address S13 from the write address 514. When the output S20 from the subtracter 160 is "O", the zero detector 164 detects this va7Lue, with the output S21 activated.
Each. of flag 169 corresponding to the write address S14 amd the flag 170 corresponding to the read address S13 is set initially at "0". When each of the write address S14 acid the read address S13 is incremented to an address value of "211" and, then, returned to "0", the values of the corre~:ponding flags 169 and 170 are inverted.
Fig. 6A snows the state of the FIFO buffer memory 133 when the flag 169 coincides with the flag 170. Fig. 6A, shading indicates tree data stored in the FIFO buffer memory 133. The coincidence of the write address S14 with the read address S13 indicates that the FIFO buffer memory 133 stores no data. In Fig. 6A, the flag 169 and the flag 170 coincide with each other. Thus, the output S22 of the comparator 171 is "0". This means 'that the output S23 from the AND circuit 166 in Fig. 2 becomes 0 and the resulting overflow detection signal S7 becomes "0". Therefore, an overflow of the FIFO
buffer memory 133 i:~ not detected.
In :Fig. EBB, the flag 169 corresponding to the write address S14 i:~ inverted, being "1". In Fig. 6B, the shading indicates the data stored in the FIFO buffer memory 133. Thus, the coincidence of the write address S14 with the read addrEass S1:3 indicates that the FIFO buffer memory 133 is filled with data (Figure 7A). With the FIFO buffer memory filled with data, the output S21 from the zero detector 164 is "1" and the output S22 from the comparator 171 is "1". Hence, the output S23 from the AND circuit 166 becomes "1". When the write signal S10 becomes "1", the overflow detection :signal S7 as output from the AND circuit 168 becomes "1", wit:h an overflow detected.
Next., Figs. 1, 2, 4, 5, 6 and 7 are used to explain the operation of the data receiver based on the first preferred embodiment during an overflow.
It »s assumed that the size of the FIFO buffer memory 133 is four cells (= 212 bytes) and that data is written into and read from the FIFO buffer memory in the same manner as for t:he above normal operation. As shown in time (t) in Figs. 4 and 5, the overflow detection signal S7 is generated when the write signal S10 becomes "1", with the FIFO buffer memory 1.33 filled with data. Fig. 7A shows the state of the FIFO buffer memory when the overflow detection signal S7 is c~enerai~ed. Both of the write address S14 and the read address S13 indicate an address value of "40".
Therefore, the SR flip flop 117 is reset and the write signal S10 is inactivated, resulting in the stop of writing into the FII:'O buffer memory 133.
The write address S14 is latched by the latch circuit 131 according to the cell start signal S3 ((alpha) in Fig. 4) delayed by the flip flop 158 by system clock clk.
Thus, the hold data S15 in the latch circuit 131 is "0". As shown in Fig. 4, the: write address value of cell start data s during writing' is "0" when the overflow detection signal S7 becomes active:.
The couni=er 129 is loaded by the overflow detection signal S7 with the hold data S15 (= 0) as output from the latch circuit 131 on a rise in the system clock clk, with a v~~lue of "0" output as the write address S14.
Fig. 7B shows the spate of the FIFO buffer memory 133. As shown in Fig. 7B, the FIFO buffer memory is provided with an empty area of 40 bytes.
Upon the detection of the cell start on the received data S1 by the cell synchronous circuit 102 in the timing (beta) in Fig. 4, the cell start signal S3 and the output S5 from the AND circuit 106 become "1". Thus, the SR
flip flop 117 is sE~t, with the write signal S10 becoming "1". This means that cell writing is restarted from the address value (= 0) given by the write address 514.
Disc:ardinc~ cells being written during the occurrence of an overflow enables the FIFO buffer memory 133 to be programmed with the received latest cells. The following description based on Figures 8 to 11B deals with the data receiver used in the second preferred embodiment of the present invention. The data receiver used in the preferred embodiment comprises a cell synchronous circuit 202, an AND circuit 206, a 52-detection section 234, an OR
circuit 236, an SR flip flop 238, counters 240, 244, 246 and 248, an overflow detection device 242, an OR circuit 250, a FIFO buffer memory 252, and a subtracter 275.
In Fig. 8, received cell data S31 is entered to the cell synchronous circuit 202, which in turn generates a cell synchronizing :signal S32 and a cell start signal S33.
Also, the FIFO buffer memory 252 is supplied with write data 534. The cell synchronizing signal S32 and the cell start signal S33 arE: entered to the AND circuit 206. An output signal S35 from the AND circuit 206 sets the SR flip flop 238. The ORe:d output of (i) a write restart signal for controlling t:he restart of programming the FIFO buffer memory 252 and. (ii) the output S35 from the AND circuit 206 may be entered. to a set terminal S of the SR flip flop 238.
A write stop signal 536, an overflow detection signal S37, and a 52-detection signal S38 are entered to the 5 OR circuit 236. The: SR flip flop 238 is reset by an output signal S39 from the OR circuit 236. The SR flip flop 238 outputs a write signal S40 as the FIFO buffer memory 252 programming control signal.
Out~~ut 545 from the counter 246 constitutes the 10 lower six bits; of a write address 544. The counter 246 is incremented by the write signal S40 and reset to "0" by an output signal S48 from the OR circuit 250 that receives the overflow detecaion signal S37 and the 52-detection signal S38.
15 The 52-detection section 234 generates the 52-detection signal 538 when the output S45 from the counter 246 becomes a value of "52" . Output from the counter 248 constitutes the upper two bits of the write address S44.
The counter 2~~8 is incremented by the 52-detection signal 20 S38. Output from the counters 248 and 246 provides the write address S44 for the FIFO buffer memory 252. The counter 244 i.s incremented by a read signal 541. The counter 244 outputs a read address S43 for the FIFO buffer memory 252.
The counter 240 is incremented by the write signal S40 and decremented by the read signal S41. The counter 240 is loaded by the overflow detection signal S37 with the result of the subtraction of an output signal S46 from the counter 240 anal the output value S45 from the counter 246.
The overf:Low detection section 242 receives the output signal 546 from the counter 240 to generate the overflow detection signal S37. The subtracter 275 subtracts the output signal S46 and the output S45 from the counter 246. In the :preferred embodiment, the flip flops and the counters are e~peratead by a system clock clk.
Fig. 9 provides the timing chart that illustrates the normal o~~eration of the data receiver based on the second preferred embodiment of the present invention. Fig.
provides tree timing chart that illustrates the abnormal 5 operation of the data receiver based on the second preferred embodiment of the present invention when the buffer memory overflows. F:ig. 11 provides the illustration which shows the state of the FIFO buffer memory 252 built in the data receiver used in tlhe second preferred embodiment of the 10 present invention when it overflows.
First, Figs. 8, 9 and 15 are used to explain the normal operation of the data receiver based on the second preferred embodiment: of the present invention. The received data S31 is composed of ATM cells. As shown in Fig. 15, the ATM cell is made up of a total of 53 bytes, five bytes of a header section. and 48 bytes of payload section.
The cell synchronous circuit 202 applies CRC operation to five bytes of received data S31. If the result of the operation is "0", the five bytes are identified as five bytes of the headE~r of an ATM cell. Also, the cell synchronizing signal. S32, the cell start signal S33, and the write data S34 are generated in the timing shown in Fig. 9.
The cell synchronizing signal S32 can also be generated when a series of cells of the cell start signal S33 is detected.
When. the cell synchronizing signal S32 and the cell start signal S:33 become active, the output signal S35 from the OR circuit. 206 becomes active, with the SR flip flop 238 set. Thus, the write signal S40 becomes active.
The countE~r 246 is incremented by a rise in the system clock clk when the write signal S40 is active. When the output S45 from the counter 246 becomes a value of "52", the 52-detection signal S38 is developed from the 52 detection signal 234.
The counter 248 is incremented by a rise in the system clock clk when the 52-detection signal S38 is active.
The write address S44 for the FIFO buffer memory 252 is given by eight-bit data where output from the counter 248 is the upper two bits <~nd the output S45 from the counter 246 is the lower s,ix bites.
For examp7_e, as shown in Fig. 9, when the counter 248 reads a value o:E "0" (a binary number of "00") and the counter 246 reads a value of "52" (a binary number of "110100"), the value of the write address S44 is "52" (a binary number of "00110100"). Further, when the counter 248 reads a value of "1" (a binary number of "01") and the counter 246 reads a value of "52" (a binary number of "110100") , the value of the write address S44 is "116" (a binary number of "01.110100"). Furthermore, for example, if the counter 248 reads a value of "2" ("10") and the counter 246 reads a value of "2" ("000010"), the value of the write address S44 is. "130" ("10000010").
The 52-detection signal S38 resets the SR flip flop 238 via the OF: circuit 236. As soon as 53 bytes of write data S34 are written, the 52-detection signal S38 attempts to inactivate the write signal 540.
In t:he preferred embodiment, as shown in Fig. 9, the cell start signal S33 becomes active in the same timing as the 52-detection signal S38. This activates the output signal S35 as the logical product of the cell start signal S33 and the cE:ll synchronizing signal 532. As the SR flip flop 238 is sset initially, the write signal S40 is held active. This is because a series of ATM cells is entered.
The write signal S40 can also be reset by the write stop signal S36.
The following describes the counter 240 which controls data stored in the FIFO buffer memory 252. The counter 240 :is incremented by a rise in the system clock clk when the write signal S40 is active. The counter 240 is decremented by a rise in the system clock clk when the read signal S41 is active. As shown in Fig. 9, the value of the counter 240 ("53") i.s held when the read signal S41 and the write signal S~40 are activated at a time.
Next., Figs. 8 and 10 are used to explain the operation of the data receiver based on the second preferred embodiment of the present invention when the FIFO buffer memory overflows.
It :Ls assumed that the size of the FIFO buffer memory 252 is four cells (= 212 bytes) and that data is written into and read from the FIFO buffer memory 252 in the same manner as for t:he above normal operation. As shown in Fig. 10, the overflow detection signal S37 is generated when the write signal S40 becomes a value of "1" with the FIFO
buffer memory 252 filled with data (the counter 240 reading a value of "212"). Fig. 11A shows the state of the FIFO
buffer memory 252. In the preferred embodiment shown in Fig. 10, with the overflow detection signal S37 active, the value of the write address S44 is "104", the counter 246 serving the lower :six bits reads an S45 output value of "40", and the counter 248 serving the upper bits reads a value of "1".
When. the overflow detection signal S37 is activated, thE~ SR flip flop 238 is reset, with the write signal S40 inactivated. Thus, writing into the FIFO buffer memory 252 is stopped.
On the other hand, the counter 246 is reset to "0"
by the overflow detection signal S37 on a rise in the system clock clk. fig. 11B shows the state of the FIFO buffer memory 252, where t:he value of the write address S44 is "64".
The counter 240 is loaded with output from the subtracter 275. The subtracter 275 outputs a value of "172"
that is the result of the subtraction of the output value of the counter 296 (_ '''40") from the output signal S46 of the counter 240 (_ "212"). Hence, the FIFO buffer memory 252 is provided with an empty area of 40 bytes.
Upon. the detection of the start of a cell of received data S31 by the cell synchronous circuit 202, the cell start signal S33 and the output signal S35 from the AND
circuit 206 become "'1". Thus, the SR flip flop 238 is set, with the write signal S40 becoming "1". The result is that writing is restarted from the address indicated by the write address S44 (_ "64"). Discarding cells being written during the occurrence of an overflow enables the received latest cell to be written into the FIFO buffer memory 252.
As set out above, the data receiver of the present invention updates i~he write address of the FIFO buffer memory when it overflows, and the write address when the received start cel:1 data is written. This allows the discard of only the cell data being written during the occurrence of an overflow. Therefore, the FIFO buffer memory is so provided with an empty area that it may be programmed with the latest received data. The result is that received data discarded during an overflow can be minimized and that :impacts of resending can be curbed most significantly.
Further, when the FIFO buffer memory overflows, the next recs~ived cell data is written from the write address of the received start cell data where the overflow has been detecaed. In addition, only the cell data being written during' the occurrence of the overflow is discarded.
Thus, the discard of received data during the occurrence of an overf low i:~ so minimized that the latest received cell data may be written into the buffer memory. This enables a very signific<~nt suppression of the effect of resending.
Furthermore, 'the data receiver of the present invention comprises a ~~eans for storing the write address of the received start cell data being written and a means for updating the write address according to the value of the above means when the buffer memory overflows. Both the means allow minimization of the discard of received data during the occ:urrenc:e of an overflow.
Although the invention has been illustrated and described with respect to exemplary embodiment thereof, it should be understood by those skilled in the art that the E.
foregoing and various other changes, omissions and additions may be made therein and thereto, without departing from the spirit and scope of the present invention. Therefore, the present invention should not be understood as limited to the 5 specific embodiment: set out above but to include all possible emboc~iment:~ which can be embodies within a scope encompassed and equivalents thereof with respect to the feature set ou.t in t:he appended claims.
buffer memory when it overflows.
First, Fic~s. 1, 3 and 15 are used to explain the normal operat_Lon of the data receiver based on the first preferred embodiment: of the present invention. The received data S1 is composed of ATM cells. As shown in Fig. 15, the ATM cell is composed of a total of 53 bytes, 5 bytes of a header section and X68 bytes of payload section.
The cell synchronous circuit 102 applies CRC
operation to five bytes of received data S1. If the result of the CRC operation is "O", the cell synchronous circuit 102 identifies; the five bytes as five bytes of an ATM cell header. The ~~ell synchronizing signal S2, the cell start signal S3, and the write data S4 are generated in the timing shown in Fig. 3. The cell synchronizing signal S2 can also be generated when a series of cells of the cell start signal is detected.
When. the cell synchronizing signal S2 and the cell start signal S3 become active, the output signal S5 from the OR circuit 105 becomes active, with the SR f lip f lop 117 set. Thus, th.e write signal S10 becomes active.
With. the write signal S10 active, the counter 120 is incremented by a rise in the system clock clk. The counter 120 i~; resei~ by the 52-detection signal S8 when it reads a value ~of "52". The 52-detection signal S8 is output via the OR circuit 115 as the output signal S9, which in turn resets the SR flip flop 117. When 53 bytes of the write data S~~ are written, the 52-detection signal S9 attempts to inactivate the write signal S10.
In t:he preferred embodiment shown in Fig. 3, the cell start signal S3 becomes active in the same timing as the 52-detection signal S8. As the output signal S5 as the result of the logical product of the cell start signal S3 and the cell :synchronizing signal S2 is active and the SR
flip flop 117 is set initially, the write signal S10 is held active. This: is because the received cell data S1 is entered consecutively. As shown in Fig. 1, the write signal S10 is reset ~~y the write stop signal S6 as well.
The write address S14 of the FIFO buffer memory 133 is given by the counter 129. The write address S14 is incremented by the counter 129 on a rise in the system clock clk when the write ;signal S10 is active. The read address S13 is given by the counter 127. The read address S13 is incremented by the counter 127 on a rise in the system clock clk when the read signal S11 is active.
The overflow detection device 159 detects an overflow of the FIFO buffer memory by the write address S14, the read addreas S13 and the write signal 510.
The following explains the operation of the overflow detection device 159. The subtraction of the write address S14 and thf~ read address S13 is executed in the subtracter 1E~0 (F:igure Z). Fig. 5 illustrates the relationship between the write address S14, the read address S13 and the output ~~20 of the subtracter. In the preferred embodiment shown in Fig. 5, the subtracter 160 subtracts the read address S13 from the write address 514. When the output S20 from the subtracter 160 is "O", the zero detector 164 detects this va7Lue, with the output S21 activated.
Each. of flag 169 corresponding to the write address S14 amd the flag 170 corresponding to the read address S13 is set initially at "0". When each of the write address S14 acid the read address S13 is incremented to an address value of "211" and, then, returned to "0", the values of the corre~:ponding flags 169 and 170 are inverted.
Fig. 6A snows the state of the FIFO buffer memory 133 when the flag 169 coincides with the flag 170. Fig. 6A, shading indicates tree data stored in the FIFO buffer memory 133. The coincidence of the write address S14 with the read address S13 indicates that the FIFO buffer memory 133 stores no data. In Fig. 6A, the flag 169 and the flag 170 coincide with each other. Thus, the output S22 of the comparator 171 is "0". This means 'that the output S23 from the AND circuit 166 in Fig. 2 becomes 0 and the resulting overflow detection signal S7 becomes "0". Therefore, an overflow of the FIFO
buffer memory 133 i:~ not detected.
In :Fig. EBB, the flag 169 corresponding to the write address S14 i:~ inverted, being "1". In Fig. 6B, the shading indicates the data stored in the FIFO buffer memory 133. Thus, the coincidence of the write address S14 with the read addrEass S1:3 indicates that the FIFO buffer memory 133 is filled with data (Figure 7A). With the FIFO buffer memory filled with data, the output S21 from the zero detector 164 is "1" and the output S22 from the comparator 171 is "1". Hence, the output S23 from the AND circuit 166 becomes "1". When the write signal S10 becomes "1", the overflow detection :signal S7 as output from the AND circuit 168 becomes "1", wit:h an overflow detected.
Next., Figs. 1, 2, 4, 5, 6 and 7 are used to explain the operation of the data receiver based on the first preferred embodiment during an overflow.
It »s assumed that the size of the FIFO buffer memory 133 is four cells (= 212 bytes) and that data is written into and read from the FIFO buffer memory in the same manner as for t:he above normal operation. As shown in time (t) in Figs. 4 and 5, the overflow detection signal S7 is generated when the write signal S10 becomes "1", with the FIFO buffer memory 1.33 filled with data. Fig. 7A shows the state of the FIFO buffer memory when the overflow detection signal S7 is c~enerai~ed. Both of the write address S14 and the read address S13 indicate an address value of "40".
Therefore, the SR flip flop 117 is reset and the write signal S10 is inactivated, resulting in the stop of writing into the FII:'O buffer memory 133.
The write address S14 is latched by the latch circuit 131 according to the cell start signal S3 ((alpha) in Fig. 4) delayed by the flip flop 158 by system clock clk.
Thus, the hold data S15 in the latch circuit 131 is "0". As shown in Fig. 4, the: write address value of cell start data s during writing' is "0" when the overflow detection signal S7 becomes active:.
The couni=er 129 is loaded by the overflow detection signal S7 with the hold data S15 (= 0) as output from the latch circuit 131 on a rise in the system clock clk, with a v~~lue of "0" output as the write address S14.
Fig. 7B shows the spate of the FIFO buffer memory 133. As shown in Fig. 7B, the FIFO buffer memory is provided with an empty area of 40 bytes.
Upon the detection of the cell start on the received data S1 by the cell synchronous circuit 102 in the timing (beta) in Fig. 4, the cell start signal S3 and the output S5 from the AND circuit 106 become "1". Thus, the SR
flip flop 117 is sE~t, with the write signal S10 becoming "1". This means that cell writing is restarted from the address value (= 0) given by the write address 514.
Disc:ardinc~ cells being written during the occurrence of an overflow enables the FIFO buffer memory 133 to be programmed with the received latest cells. The following description based on Figures 8 to 11B deals with the data receiver used in the second preferred embodiment of the present invention. The data receiver used in the preferred embodiment comprises a cell synchronous circuit 202, an AND circuit 206, a 52-detection section 234, an OR
circuit 236, an SR flip flop 238, counters 240, 244, 246 and 248, an overflow detection device 242, an OR circuit 250, a FIFO buffer memory 252, and a subtracter 275.
In Fig. 8, received cell data S31 is entered to the cell synchronous circuit 202, which in turn generates a cell synchronizing :signal S32 and a cell start signal S33.
Also, the FIFO buffer memory 252 is supplied with write data 534. The cell synchronizing signal S32 and the cell start signal S33 arE: entered to the AND circuit 206. An output signal S35 from the AND circuit 206 sets the SR flip flop 238. The ORe:d output of (i) a write restart signal for controlling t:he restart of programming the FIFO buffer memory 252 and. (ii) the output S35 from the AND circuit 206 may be entered. to a set terminal S of the SR flip flop 238.
A write stop signal 536, an overflow detection signal S37, and a 52-detection signal S38 are entered to the 5 OR circuit 236. The: SR flip flop 238 is reset by an output signal S39 from the OR circuit 236. The SR flip flop 238 outputs a write signal S40 as the FIFO buffer memory 252 programming control signal.
Out~~ut 545 from the counter 246 constitutes the 10 lower six bits; of a write address 544. The counter 246 is incremented by the write signal S40 and reset to "0" by an output signal S48 from the OR circuit 250 that receives the overflow detecaion signal S37 and the 52-detection signal S38.
15 The 52-detection section 234 generates the 52-detection signal 538 when the output S45 from the counter 246 becomes a value of "52" . Output from the counter 248 constitutes the upper two bits of the write address S44.
The counter 2~~8 is incremented by the 52-detection signal 20 S38. Output from the counters 248 and 246 provides the write address S44 for the FIFO buffer memory 252. The counter 244 i.s incremented by a read signal 541. The counter 244 outputs a read address S43 for the FIFO buffer memory 252.
The counter 240 is incremented by the write signal S40 and decremented by the read signal S41. The counter 240 is loaded by the overflow detection signal S37 with the result of the subtraction of an output signal S46 from the counter 240 anal the output value S45 from the counter 246.
The overf:Low detection section 242 receives the output signal 546 from the counter 240 to generate the overflow detection signal S37. The subtracter 275 subtracts the output signal S46 and the output S45 from the counter 246. In the :preferred embodiment, the flip flops and the counters are e~peratead by a system clock clk.
Fig. 9 provides the timing chart that illustrates the normal o~~eration of the data receiver based on the second preferred embodiment of the present invention. Fig.
provides tree timing chart that illustrates the abnormal 5 operation of the data receiver based on the second preferred embodiment of the present invention when the buffer memory overflows. F:ig. 11 provides the illustration which shows the state of the FIFO buffer memory 252 built in the data receiver used in tlhe second preferred embodiment of the 10 present invention when it overflows.
First, Figs. 8, 9 and 15 are used to explain the normal operation of the data receiver based on the second preferred embodiment: of the present invention. The received data S31 is composed of ATM cells. As shown in Fig. 15, the ATM cell is made up of a total of 53 bytes, five bytes of a header section. and 48 bytes of payload section.
The cell synchronous circuit 202 applies CRC operation to five bytes of received data S31. If the result of the operation is "0", the five bytes are identified as five bytes of the headE~r of an ATM cell. Also, the cell synchronizing signal. S32, the cell start signal S33, and the write data S34 are generated in the timing shown in Fig. 9.
The cell synchronizing signal S32 can also be generated when a series of cells of the cell start signal S33 is detected.
When. the cell synchronizing signal S32 and the cell start signal S:33 become active, the output signal S35 from the OR circuit. 206 becomes active, with the SR flip flop 238 set. Thus, the write signal S40 becomes active.
The countE~r 246 is incremented by a rise in the system clock clk when the write signal S40 is active. When the output S45 from the counter 246 becomes a value of "52", the 52-detection signal S38 is developed from the 52 detection signal 234.
The counter 248 is incremented by a rise in the system clock clk when the 52-detection signal S38 is active.
The write address S44 for the FIFO buffer memory 252 is given by eight-bit data where output from the counter 248 is the upper two bits <~nd the output S45 from the counter 246 is the lower s,ix bites.
For examp7_e, as shown in Fig. 9, when the counter 248 reads a value o:E "0" (a binary number of "00") and the counter 246 reads a value of "52" (a binary number of "110100"), the value of the write address S44 is "52" (a binary number of "00110100"). Further, when the counter 248 reads a value of "1" (a binary number of "01") and the counter 246 reads a value of "52" (a binary number of "110100") , the value of the write address S44 is "116" (a binary number of "01.110100"). Furthermore, for example, if the counter 248 reads a value of "2" ("10") and the counter 246 reads a value of "2" ("000010"), the value of the write address S44 is. "130" ("10000010").
The 52-detection signal S38 resets the SR flip flop 238 via the OF: circuit 236. As soon as 53 bytes of write data S34 are written, the 52-detection signal S38 attempts to inactivate the write signal 540.
In t:he preferred embodiment, as shown in Fig. 9, the cell start signal S33 becomes active in the same timing as the 52-detection signal S38. This activates the output signal S35 as the logical product of the cell start signal S33 and the cE:ll synchronizing signal 532. As the SR flip flop 238 is sset initially, the write signal S40 is held active. This is because a series of ATM cells is entered.
The write signal S40 can also be reset by the write stop signal S36.
The following describes the counter 240 which controls data stored in the FIFO buffer memory 252. The counter 240 :is incremented by a rise in the system clock clk when the write signal S40 is active. The counter 240 is decremented by a rise in the system clock clk when the read signal S41 is active. As shown in Fig. 9, the value of the counter 240 ("53") i.s held when the read signal S41 and the write signal S~40 are activated at a time.
Next., Figs. 8 and 10 are used to explain the operation of the data receiver based on the second preferred embodiment of the present invention when the FIFO buffer memory overflows.
It :Ls assumed that the size of the FIFO buffer memory 252 is four cells (= 212 bytes) and that data is written into and read from the FIFO buffer memory 252 in the same manner as for t:he above normal operation. As shown in Fig. 10, the overflow detection signal S37 is generated when the write signal S40 becomes a value of "1" with the FIFO
buffer memory 252 filled with data (the counter 240 reading a value of "212"). Fig. 11A shows the state of the FIFO
buffer memory 252. In the preferred embodiment shown in Fig. 10, with the overflow detection signal S37 active, the value of the write address S44 is "104", the counter 246 serving the lower :six bits reads an S45 output value of "40", and the counter 248 serving the upper bits reads a value of "1".
When. the overflow detection signal S37 is activated, thE~ SR flip flop 238 is reset, with the write signal S40 inactivated. Thus, writing into the FIFO buffer memory 252 is stopped.
On the other hand, the counter 246 is reset to "0"
by the overflow detection signal S37 on a rise in the system clock clk. fig. 11B shows the state of the FIFO buffer memory 252, where t:he value of the write address S44 is "64".
The counter 240 is loaded with output from the subtracter 275. The subtracter 275 outputs a value of "172"
that is the result of the subtraction of the output value of the counter 296 (_ '''40") from the output signal S46 of the counter 240 (_ "212"). Hence, the FIFO buffer memory 252 is provided with an empty area of 40 bytes.
Upon. the detection of the start of a cell of received data S31 by the cell synchronous circuit 202, the cell start signal S33 and the output signal S35 from the AND
circuit 206 become "'1". Thus, the SR flip flop 238 is set, with the write signal S40 becoming "1". The result is that writing is restarted from the address indicated by the write address S44 (_ "64"). Discarding cells being written during the occurrence of an overflow enables the received latest cell to be written into the FIFO buffer memory 252.
As set out above, the data receiver of the present invention updates i~he write address of the FIFO buffer memory when it overflows, and the write address when the received start cel:1 data is written. This allows the discard of only the cell data being written during the occurrence of an overflow. Therefore, the FIFO buffer memory is so provided with an empty area that it may be programmed with the latest received data. The result is that received data discarded during an overflow can be minimized and that :impacts of resending can be curbed most significantly.
Further, when the FIFO buffer memory overflows, the next recs~ived cell data is written from the write address of the received start cell data where the overflow has been detecaed. In addition, only the cell data being written during' the occurrence of the overflow is discarded.
Thus, the discard of received data during the occurrence of an overf low i:~ so minimized that the latest received cell data may be written into the buffer memory. This enables a very signific<~nt suppression of the effect of resending.
Furthermore, 'the data receiver of the present invention comprises a ~~eans for storing the write address of the received start cell data being written and a means for updating the write address according to the value of the above means when the buffer memory overflows. Both the means allow minimization of the discard of received data during the occ:urrenc:e of an overflow.
Although the invention has been illustrated and described with respect to exemplary embodiment thereof, it should be understood by those skilled in the art that the E.
foregoing and various other changes, omissions and additions may be made therein and thereto, without departing from the spirit and scope of the present invention. Therefore, the present invention should not be understood as limited to the 5 specific embodiment: set out above but to include all possible emboc~iment:~ which can be embodies within a scope encompassed and equivalents thereof with respect to the feature set ou.t in t:he appended claims.
Claims (14)
1. A communication data receiver for storing communication data received from a communication layer into a buffer memory and transferring said communication data to another communication layer, said communication data receiver comprising:
a cell synchronous means for generating a synchronizing signal and a start detection signal for said received communication data;
a write signal generation means for generating a write signal that directs said communication data to be written into said buffer memory according to said synchronizing signal and said start detection signal;
a means for holding a write address of initial data of said communication data being written;
a means for detecting an overflow of said buffer memory;
a means for inactivating said write signal according to an overflow detection signal; and, a means for setting the write address held in said write address holding means as a writing start address for communication data received next according to said overflow detection signal.
a cell synchronous means for generating a synchronizing signal and a start detection signal for said received communication data;
a write signal generation means for generating a write signal that directs said communication data to be written into said buffer memory according to said synchronizing signal and said start detection signal;
a means for holding a write address of initial data of said communication data being written;
a means for detecting an overflow of said buffer memory;
a means for inactivating said write signal according to an overflow detection signal; and, a means for setting the write address held in said write address holding means as a writing start address for communication data received next according to said overflow detection signal.
2. A communication data receiver as set forth in Claim 1, which further comprises:
a write address generation means for generating the write address in said buffer memory for said communication data according to said write signal output from said write signal generation means; and, a means for setting the write address held in said write address holding means at said write address generation means as the writing start address for said communication data received next according to said overflow detection.
a write address generation means for generating the write address in said buffer memory for said communication data according to said write signal output from said write signal generation means; and, a means for setting the write address held in said write address holding means at said write address generation means as the writing start address for said communication data received next according to said overflow detection.
3. A communication data receiver as set forth in Claim 1, which further comprises:
a write address generation means for generating the write address in said buffer memory for said communication data according to said write signal output from said write signal generation means;
wherein said write address holding means includes a latch circuit for holding the write address of initial data of said communication data output from said write address generation means according to the start detection signal of said communication data delayed by one clock period;
said write address generation means loading said write address held in said latch circuit according to said overflow detection signal.
a write address generation means for generating the write address in said buffer memory for said communication data according to said write signal output from said write signal generation means;
wherein said write address holding means includes a latch circuit for holding the write address of initial data of said communication data output from said write address generation means according to the start detection signal of said communication data delayed by one clock period;
said write address generation means loading said write address held in said latch circuit according to said overflow detection signal.
4. A communication data receiver as set forth in Claim 3, which further comprises:
a flip-flop for receiving a start detection signal of said communication data and outputting said start detection signal delayed by the one clock period;
wherein said latch circuit holds the write address for the initial data of said communication data output from said write address generation means by said start detection signal delayed by a clock output from said flip-flop.
a flip-flop for receiving a start detection signal of said communication data and outputting said start detection signal delayed by the one clock period;
wherein said latch circuit holds the write address for the initial data of said communication data output from said write address generation means by said start detection signal delayed by a clock output from said flip-flop.
5. A communication data receiver as set forth in Claim 1, which further comprises:
a write address generation means for generating the write address in said buffer memory for said communication data according to said write signal output from said write signal generation means; and, a read address generation means for generating a read address for use in reading data from said buffer memory;
said overflow detection means including:
an address judgment means for judging whether the value of said write address is identical to the value of said read address;
a first flag for inverting a value every time said write address checks a set of addresses of said buffer memory;
a second flag for inverting a value every time said read address checks a set of addresses of said buffer memory;
a comparison means for comparing said first flag with said second flag; and, a means for outputting an overflow signal indicating an overflow of said buffer memory by entering a signal signifying that an address coincidence signal output from said address judgment means is not identical to said first and second flags output from said comparison means.
a write address generation means for generating the write address in said buffer memory for said communication data according to said write signal output from said write signal generation means; and, a read address generation means for generating a read address for use in reading data from said buffer memory;
said overflow detection means including:
an address judgment means for judging whether the value of said write address is identical to the value of said read address;
a first flag for inverting a value every time said write address checks a set of addresses of said buffer memory;
a second flag for inverting a value every time said read address checks a set of addresses of said buffer memory;
a comparison means for comparing said first flag with said second flag; and, a means for outputting an overflow signal indicating an overflow of said buffer memory by entering a signal signifying that an address coincidence signal output from said address judgment means is not identical to said first and second flags output from said comparison means.
6. A communication data receiver as set forth in Claim 1, which further comprises:
a write address generation means for generating a write address on said buffer memory for said communication data according to said write signal output from said write signal generation means; and, a read address generation means for generating a read address for use in reading data from said buffer memory;
said overflow detection means comprising:
a subtraction means for calculating the difference between said write address and said read address;
a zero detection means for judging whether the value calculated by said subtraction means is zero;
a first flag for inverting a value every time said write address checks a set of addresses of said buffer memory;
a second flag for inverting a value every time said read address checks a set of addresses of said buffer memory;
a comparison means for comparing said first flag with said second flag; and, a means for outputting an overflow signal indicating an overflow of said buffer memory by entering a signal signifying that a zero detection signal output from said zero detection means is not identical to said first and second flags output from said comparison means.
a write address generation means for generating a write address on said buffer memory for said communication data according to said write signal output from said write signal generation means; and, a read address generation means for generating a read address for use in reading data from said buffer memory;
said overflow detection means comprising:
a subtraction means for calculating the difference between said write address and said read address;
a zero detection means for judging whether the value calculated by said subtraction means is zero;
a first flag for inverting a value every time said write address checks a set of addresses of said buffer memory;
a second flag for inverting a value every time said read address checks a set of addresses of said buffer memory;
a comparison means for comparing said first flag with said second flag; and, a means for outputting an overflow signal indicating an overflow of said buffer memory by entering a signal signifying that a zero detection signal output from said zero detection means is not identical to said first and second flags output from said comparison means.
7. A communication data receiver as set forth in Claim 1, wherein:
said write signal generation means is set by the logical product of said synchronizing signal and said start detection signal, and includes a flip-flop for outputting the write signal for said buffer memory; and, said flip-flop is reset by the overflow detection signal output from said overflow detection means to activate said write signal.
said write signal generation means is set by the logical product of said synchronizing signal and said start detection signal, and includes a flip-flop for outputting the write signal for said buffer memory; and, said flip-flop is reset by the overflow detection signal output from said overflow detection means to activate said write signal.
8. A communication data receiver for storing communication data received from a communication layer into a buffer memory and transferring said communication data to another communication layer, said communication data receiver comprising:
a cell synchronous means for generating a synchronizing signal and a start detection signal for said received communication data;
a write signal generation means for generating a write signal directing said communication data to be written into said buffer memory according to said synchronizing signal and said start detection signal;
an upper address generation means for generating certain upper bits of a write address on said buffer memory for said communication data according to said write signal output from said write signal generation means;
a lower address generation means for generating certain lower bits of the write address on said buffer memory for said communication data according to said write signal output from said write signal generation means;
a means for detecting an overflow of said buffer memory;
a means for inactivating said write signal according to an overflow detection signal; and, a means for setting an address lower than the current address at said lower address generation means according to said overflow detection signal and for setting a write address composed of an upper address generated by said upper address generation means and a lower address generated by said lower address generation means as a writing start address for said communication data received next.
a cell synchronous means for generating a synchronizing signal and a start detection signal for said received communication data;
a write signal generation means for generating a write signal directing said communication data to be written into said buffer memory according to said synchronizing signal and said start detection signal;
an upper address generation means for generating certain upper bits of a write address on said buffer memory for said communication data according to said write signal output from said write signal generation means;
a lower address generation means for generating certain lower bits of the write address on said buffer memory for said communication data according to said write signal output from said write signal generation means;
a means for detecting an overflow of said buffer memory;
a means for inactivating said write signal according to an overflow detection signal; and, a means for setting an address lower than the current address at said lower address generation means according to said overflow detection signal and for setting a write address composed of an upper address generated by said upper address generation means and a lower address generated by said lower address generation means as a writing start address for said communication data received next.
9. A communication data receiver as set forth in Claim 8, wherein:
said lower address generation means is reset to zero according to said overflow detection signal, whereby a write address composed of an upper address generated by said upper address generation means and a lower address generated by said lower address generation means is set as the writing start address for said communication data received next.
said lower address generation means is reset to zero according to said overflow detection signal, whereby a write address composed of an upper address generated by said upper address generation means and a lower address generated by said lower address generation means is set as the writing start address for said communication data received next.
10. A communication data receiver as set forth in Claim 8, which further comprises:
a first counter constituting said lower address generation means;
said first counter incremented by said write signal;
a second counter constituting said upper address generation means; and, a means for checking a value read by said first counter and for resetting said first counter to zero and incrementing said second counter every time the read value coincides with the length of said received data.
a first counter constituting said lower address generation means;
said first counter incremented by said write signal;
a second counter constituting said upper address generation means; and, a means for checking a value read by said first counter and for resetting said first counter to zero and incrementing said second counter every time the read value coincides with the length of said received data.
11. A communication data receiver as set forth in Claim 10, which further comprises:
a read address generation means for generating a read address for use in reading data from said buffer memory; and, a third counter incremented by said write signal and decremented by said read signal;
wherein said overflow detection means outputting an overflow detection signal when the value read by said third counter coincides with the maximum address of said buffer memory.
a read address generation means for generating a read address for use in reading data from said buffer memory; and, a third counter incremented by said write signal and decremented by said read signal;
wherein said overflow detection means outputting an overflow detection signal when the value read by said third counter coincides with the maximum address of said buffer memory.
12. A communication data receiver as set forth in Claim 11, wherein:
said third counter sets the value as the result of subtracting an address value generated by said lower address generation means from the read value coinciding with said maximum address value as a new count start value according to said overflow detection signal.
said third counter sets the value as the result of subtracting an address value generated by said lower address generation means from the read value coinciding with said maximum address value as a new count start value according to said overflow detection signal.
13. A communication data receiver as set forth in Claim 8, wherein:
said write signal generation means comprises a flip-flop set by the logical product of said synchronizing signal and said start detection signal to output the write signal for said buffer memory; and, said flip-flop is reset by the overflow detection signal output from said overflow detection means to inactivate said write signal.
said write signal generation means comprises a flip-flop set by the logical product of said synchronizing signal and said start detection signal to output the write signal for said buffer memory; and, said flip-flop is reset by the overflow detection signal output from said overflow detection means to inactivate said write signal.
14. A communication data receiver for storing communication data received from a communication layer into a buffer memory and transferring said communication data to another communication layer, said communication data receiver comprising:
a means for detecting an overflow of said buffer memory;
a means for prohibiting said communication data from being written into said buffer memory according to said overflow detection; and, a means for setting a write address lower than a write address of said communication data being written in said buffer memory as a writing start address for said communication data received next according to said overflow detection.
a means for detecting an overflow of said buffer memory;
a means for prohibiting said communication data from being written into said buffer memory according to said overflow detection; and, a means for setting a write address lower than a write address of said communication data being written in said buffer memory as a writing start address for said communication data received next according to said overflow detection.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14074194A JP2699872B2 (en) | 1994-06-01 | 1994-06-01 | Data receiving device and buffer management method |
| JP6-140741 | 1994-06-01 |
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| Publication Number | Publication Date |
|---|---|
| CA2150580A1 CA2150580A1 (en) | 1995-12-02 |
| CA2150580C true CA2150580C (en) | 2000-05-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CA 2150580 Expired - Fee Related CA2150580C (en) | 1994-06-01 | 1995-05-31 | Communication data receiver |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5663948A (en) |
| EP (1) | EP0685976A3 (en) |
| JP (1) | JP2699872B2 (en) |
| CA (1) | CA2150580C (en) |
Families Citing this family (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT1277692B1 (en) * | 1995-12-22 | 1997-11-11 | Italtel Spa | FIFO STORAGE AND SHARED BUFFER SWITCHING DEVICE FOR ATM CONNECTION NETWORKS |
| GB9605425D0 (en) * | 1996-03-15 | 1996-05-15 | Newbridge Networks Corp | Congestion management in managed packet-switched networks |
| US5838661A (en) * | 1996-03-27 | 1998-11-17 | Cirrus Logic, Inc. | Method and arrangement for shutting off a receive channel in a data communications system |
| US5946347A (en) * | 1996-05-31 | 1999-08-31 | Diamond Multimedia Systems Inc. | Low latency transport of signals in an error correcting data modem |
| US5931915A (en) * | 1997-05-13 | 1999-08-03 | International Business Machines Corporation | Method for processing early arrival messages within a multinode asynchronous data communications system |
| US6112268A (en) * | 1997-06-16 | 2000-08-29 | Matsushita Electric Industrial Co., Ltd. | System for indicating status of a buffer based on a write address of the buffer and generating an abort signal before buffer overflows |
| US6327249B1 (en) * | 1999-08-04 | 2001-12-04 | Ess Technology, Inc | Data communication device |
| US6907488B1 (en) * | 1999-09-14 | 2005-06-14 | Siemens Aktiengesellschaft | Serial data transmission via a bus system |
| US20020126673A1 (en) * | 2001-01-12 | 2002-09-12 | Nirav Dagli | Shared memory |
| US7051131B1 (en) * | 2002-12-27 | 2006-05-23 | Unisys Corporation | Method and apparatus for recording and monitoring bus activity in a multi-processor environment |
| US7623515B2 (en) | 2005-07-14 | 2009-11-24 | Yahoo! Inc. | Content router notification |
| US7631045B2 (en) | 2005-07-14 | 2009-12-08 | Yahoo! Inc. | Content router asynchronous exchange |
| US7849199B2 (en) | 2005-07-14 | 2010-12-07 | Yahoo ! Inc. | Content router |
| US8024290B2 (en) | 2005-11-14 | 2011-09-20 | Yahoo! Inc. | Data synchronization and device handling |
| US8065680B2 (en) | 2005-11-15 | 2011-11-22 | Yahoo! Inc. | Data gateway for jobs management based on a persistent job table and a server table |
| US9367832B2 (en) * | 2006-01-04 | 2016-06-14 | Yahoo! Inc. | Synchronizing image data among applications and devices |
| EP2036003B1 (en) * | 2006-06-30 | 2017-05-03 | Leica Biosystems Imaging, Inc. | Method for storing and retrieving large images via dicom |
| US8010555B2 (en) * | 2006-06-30 | 2011-08-30 | Aperio Technologies, Inc. | System and method for managing images over a network |
| US9137160B2 (en) * | 2009-01-29 | 2015-09-15 | Qualcomm Incorporated | Method and apparatus for accomodating a receiver buffer to prevent data overflow |
| US8250243B2 (en) * | 2010-06-24 | 2012-08-21 | International Business Machines Corporation | Diagnostic data collection and storage put-away station in a multiprocessor system |
| US10680957B2 (en) | 2014-05-28 | 2020-06-09 | Cavium International | Method and apparatus for analytics in a network switch |
| US20150365339A1 (en) * | 2014-06-11 | 2015-12-17 | Xpliant, Inc. | Counter with overflow fifo and a method thereof |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2538976A1 (en) * | 1982-12-29 | 1984-07-06 | Servel Michel | SYSTEM FOR SWITCHING SYNCHRONOUS PACKETS OF FIXED LENGTH |
| JP2667868B2 (en) * | 1988-04-06 | 1997-10-27 | 株式会社日立製作所 | Cell switching system |
| JPH0458646A (en) * | 1990-06-28 | 1992-02-25 | Toshiba Corp | Buffer management system |
| JPH0495431A (en) * | 1990-08-13 | 1992-03-27 | Oki Electric Ind Co Ltd | Cell receiver |
| JP2794953B2 (en) | 1991-01-17 | 1998-09-10 | 日本電気株式会社 | Data discard method |
| JP2947628B2 (en) * | 1991-03-11 | 1999-09-13 | 富士通株式会社 | Switch control device |
| JPH04360091A (en) * | 1991-06-06 | 1992-12-14 | Matsushita Electric Ind Co Ltd | Memory control circuit |
| JPH05260076A (en) * | 1992-03-13 | 1993-10-08 | Oki Electric Ind Co Ltd | Atm/stm interface circuit |
-
1994
- 1994-06-01 JP JP14074194A patent/JP2699872B2/en not_active Expired - Lifetime
-
1995
- 1995-05-31 EP EP19950108330 patent/EP0685976A3/en not_active Withdrawn
- 1995-05-31 CA CA 2150580 patent/CA2150580C/en not_active Expired - Fee Related
- 1995-06-01 US US08/456,691 patent/US5663948A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US5663948A (en) | 1997-09-02 |
| CA2150580A1 (en) | 1995-12-02 |
| EP0685976A2 (en) | 1995-12-06 |
| EP0685976A3 (en) | 1998-07-01 |
| JPH07327038A (en) | 1995-12-12 |
| JP2699872B2 (en) | 1998-01-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |